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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-block.git] / drivers / video / pxafb.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
1da177e4
LT		 25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/errno.h>
30#include <linux/string.h>
31#include <linux/interrupt.h>
32#include <linux/slab.h>
33#include <linux/fb.h>
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/ioport.h>
37#include <linux/cpufreq.h>
d052d1be 38#include <linux/platform_device.h>
1da177e4 39#include <linux/dma-mapping.h>
72e3524c
RK		 40#include <linux/clk.h>
41#include <linux/err.h>
2ba162b9 42#include <linux/completion.h>
3c42a449
EM		 43#include <linux/kthread.h>
44#include <linux/freezer.h>
1da177e4
LT		 45
46#include <asm/hardware.h>
47#include <asm/io.h>
48#include <asm/irq.h>
bf1b8ab6 49#include <asm/div64.h>
1da177e4 50#include <asm/arch/pxa-regs.h>
a683b14d 51#include <asm/arch/pxa2xx-gpio.h>
1da177e4
LT		 52#include <asm/arch/bitfield.h>
53#include <asm/arch/pxafb.h>
54
55/*
56 * Complain if VAR is out of range.
57 */
58#define DEBUG_VAR 1
59
60#include "pxafb.h"
61
62/* Bits which should not be set in machine configuration structures */
b0086efb 63#define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
64 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
65 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
66
67#define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
68 LCCR3_PCD | LCCR3_BPP)
1da177e4
LT		 69
70static void (*pxafb_backlight_power)(int);
d14b272b 71static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
1da177e4 72
b0086efb 73static int pxafb_activate_var(struct fb_var_screeninfo *var,
74 struct pxafb_info *);
1da177e4
LT		 75static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
76
a7535ba7
EM		 77static inline unsigned long
78lcd_readl(struct pxafb_info *fbi, unsigned int off)
79{
80 return __raw_readl(fbi->mmio_base + off);
81}
82
83static inline void
84lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
85{
86 __raw_writel(val, fbi->mmio_base + off);
87}
88
1da177e4
LT		 89static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
90{
91 unsigned long flags;
92
93 local_irq_save(flags);
94 /*
95 * We need to handle two requests being made at the same time.
96 * There are two important cases:
b0086efb 97 * 1. When we are changing VT (C_REENABLE) while unblanking
98 * (C_ENABLE) We must perform the unblanking, which will
99 * do our REENABLE for us.
100 * 2. When we are blanking, but immediately unblank before
101 * we have blanked. We do the "REENABLE" thing here as
102 * well, just to be sure.
1da177e4
LT		 103 */
104 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
105 state = (u_int) -1;
106 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
107 state = C_REENABLE;
108
109 if (state != (u_int)-1) {
110 fbi->task_state = state;
111 schedule_work(&fbi->task);
112 }
113 local_irq_restore(flags);
114}
115
116static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
117{
118 chan &= 0xffff;
119 chan >>= 16 - bf->length;
120 return chan << bf->offset;
121}
122
123static int
124pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
125 u_int trans, struct fb_info *info)
126{
127 struct pxafb_info *fbi = (struct pxafb_info *)info;
9ffa7396
HK		 128 u_int val;
129
130 if (regno >= fbi->palette_size)
131 return 1;
132
133 if (fbi->fb.var.grayscale) {
134 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
135 return 0;
136 }
137
138 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
139 case LCCR4_PAL_FOR_0:
140 val = ((red >> 0) & 0xf800);
141 val |= ((green >> 5) & 0x07e0);
142 val |= ((blue >> 11) & 0x001f);
1da177e4 143 fbi->palette_cpu[regno] = val;
9ffa7396
HK		 144 break;
145 case LCCR4_PAL_FOR_1:
146 val = ((red << 8) & 0x00f80000);
147 val |= ((green >> 0) & 0x0000fc00);
148 val |= ((blue >> 8) & 0x000000f8);
b0086efb 149 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396
HK		 150 break;
151 case LCCR4_PAL_FOR_2:
152 val = ((red << 8) & 0x00fc0000);
153 val |= ((green >> 0) & 0x0000fc00);
154 val |= ((blue >> 8) & 0x000000fc);
b0086efb 155 ((u32 *)(fbi->palette_cpu))[regno] = val;
9ffa7396 156 break;
1da177e4 157 }
9ffa7396
HK		 158
159 return 0;
1da177e4
LT		 160}
161
162static int
163pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
164 u_int trans, struct fb_info *info)
165{
166 struct pxafb_info *fbi = (struct pxafb_info *)info;
167 unsigned int val;
168 int ret = 1;
169
170 /*
171 * If inverse mode was selected, invert all the colours
172 * rather than the register number. The register number
173 * is what you poke into the framebuffer to produce the
174 * colour you requested.
175 */
176 if (fbi->cmap_inverse) {
177 red = 0xffff - red;
178 green = 0xffff - green;
179 blue = 0xffff - blue;
180 }
181
182 /*
183 * If greyscale is true, then we convert the RGB value
184 * to greyscale no matter what visual we are using.
185 */
186 if (fbi->fb.var.grayscale)
187 red = green = blue = (19595 * red + 38470 * green +
188 7471 * blue) >> 16;
189
190 switch (fbi->fb.fix.visual) {
191 case FB_VISUAL_TRUECOLOR:
192 /*
193 * 16-bit True Colour. We encode the RGB value
194 * according to the RGB bitfield information.
195 */
196 if (regno < 16) {
197 u32 *pal = fbi->fb.pseudo_palette;
198
199 val = chan_to_field(red, &fbi->fb.var.red);
200 val |= chan_to_field(green, &fbi->fb.var.green);
201 val |= chan_to_field(blue, &fbi->fb.var.blue);
202
203 pal[regno] = val;
204 ret = 0;
205 }
206 break;
207
208 case FB_VISUAL_STATIC_PSEUDOCOLOR:
209 case FB_VISUAL_PSEUDOCOLOR:
210 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
211 break;
212 }
213
214 return ret;
215}
216
217/*
218 * pxafb_bpp_to_lccr3():
219 * Convert a bits per pixel value to the correct bit pattern for LCCR3
220 */
221static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
222{
b0086efb 223 int ret = 0;
224 switch (var->bits_per_pixel) {
225 case 1: ret = LCCR3_1BPP; break;
226 case 2: ret = LCCR3_2BPP; break;
227 case 4: ret = LCCR3_4BPP; break;
228 case 8: ret = LCCR3_8BPP; break;
229 case 16: ret = LCCR3_16BPP; break;
230 }
231 return ret;
1da177e4
LT		 232}
233
234#ifdef CONFIG_CPU_FREQ
235/*
236 * pxafb_display_dma_period()
237 * Calculate the minimum period (in picoseconds) between two DMA
238 * requests for the LCD controller. If we hit this, it means we're
239 * doing nothing but LCD DMA.
240 */
241static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
242{
b0086efb 243 /*
244 * Period = pixclock * bits_per_byte * bytes_per_transfer
245 * / memory_bits_per_pixel;
246 */
247 return var->pixclock * 8 * 16 / var->bits_per_pixel;
1da177e4 248}
1da177e4
LT		 249#endif
250
d14b272b
RP		 251/*
252 * Select the smallest mode that allows the desired resolution to be
253 * displayed. If desired parameters can be rounded up.
254 */
b0086efb 255static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
256 struct fb_var_screeninfo *var)
d14b272b
RP		 257{
258 struct pxafb_mode_info *mode = NULL;
259 struct pxafb_mode_info *modelist = mach->modes;
260 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
261 unsigned int i;
262
b0086efb 263 for (i = 0; i < mach->num_modes; i++) {
264 if (modelist[i].xres >= var->xres &&
265 modelist[i].yres >= var->yres &&
266 modelist[i].xres < best_x &&
267 modelist[i].yres < best_y &&
268 modelist[i].bpp >= var->bits_per_pixel) {
d14b272b
RP		 269 best_x = modelist[i].xres;
270 best_y = modelist[i].yres;
271 mode = &modelist[i];
272 }
273 }
274
275 return mode;
276}
277
b0086efb 278static void pxafb_setmode(struct fb_var_screeninfo *var,
279 struct pxafb_mode_info *mode)
d14b272b
RP		 280{
281 var->xres = mode->xres;
282 var->yres = mode->yres;
283 var->bits_per_pixel = mode->bpp;
284 var->pixclock = mode->pixclock;
285 var->hsync_len = mode->hsync_len;
286 var->left_margin = mode->left_margin;
287 var->right_margin = mode->right_margin;
288 var->vsync_len = mode->vsync_len;
289 var->upper_margin = mode->upper_margin;
290 var->lower_margin = mode->lower_margin;
291 var->sync = mode->sync;
292 var->grayscale = mode->cmap_greyscale;
293 var->xres_virtual = var->xres;
294 var->yres_virtual = var->yres;
295}
296
1da177e4
LT		 297/*
298 * pxafb_check_var():
299 * Get the video params out of 'var'. If a value doesn't fit, round it up,
300 * if it's too big, return -EINVAL.
301 *
302 * Round up in the following order: bits_per_pixel, xres,
303 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
304 * bitfields, horizontal timing, vertical timing.
305 */
306static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
307{
308 struct pxafb_info *fbi = (struct pxafb_info *)info;
d14b272b 309 struct pxafb_mach_info *inf = fbi->dev->platform_data;
1da177e4
LT		 310
311 if (var->xres < MIN_XRES)
312 var->xres = MIN_XRES;
313 if (var->yres < MIN_YRES)
314 var->yres = MIN_YRES;
d14b272b
RP		 315
316 if (inf->fixed_modes) {
317 struct pxafb_mode_info *mode;
318
319 mode = pxafb_getmode(inf, var);
320 if (!mode)
321 return -EINVAL;
322 pxafb_setmode(var, mode);
323 } else {
324 if (var->xres > inf->modes->xres)
325 return -EINVAL;
326 if (var->yres > inf->modes->yres)
327 return -EINVAL;
328 if (var->bits_per_pixel > inf->modes->bpp)
329 return -EINVAL;
330 }
331
1da177e4
LT		 332 var->xres_virtual =
333 max(var->xres_virtual, var->xres);
334 var->yres_virtual =
335 max(var->yres_virtual, var->yres);
336
b0086efb 337 /*
1da177e4
LT		 338 * Setup the RGB parameters for this display.
339 *
340 * The pixel packing format is described on page 7-11 of the
341 * PXA2XX Developer's Manual.
b0086efb 342 */
1da177e4
LT		 343 if (var->bits_per_pixel == 16) {
344 var->red.offset = 11; var->red.length = 5;
345 var->green.offset = 5; var->green.length = 6;
346 var->blue.offset = 0; var->blue.length = 5;
347 var->transp.offset = var->transp.length = 0;
348 } else {
b0086efb 349 var->red.offset = var->green.offset = 0;
350 var->blue.offset = var->transp.offset = 0;
1da177e4
LT		 351 var->red.length = 8;
352 var->green.length = 8;
353 var->blue.length = 8;
354 var->transp.length = 0;
355 }
356
357#ifdef CONFIG_CPU_FREQ
ca5da710
RK		 358 pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
359 pxafb_display_dma_period(var),
360 get_clk_frequency_khz(0));
1da177e4
LT		 361#endif
362
363 return 0;
364}
365
366static inline void pxafb_set_truecolor(u_int is_true_color)
367{
b0086efb 368 /* do your machine-specific setup if needed */
1da177e4
LT		 369}
370
371/*
372 * pxafb_set_par():
373 * Set the user defined part of the display for the specified console
374 */
375static int pxafb_set_par(struct fb_info *info)
376{
377 struct pxafb_info *fbi = (struct pxafb_info *)info;
378 struct fb_var_screeninfo *var = &info->var;
1da177e4 379
1da177e4
LT		 380 if (var->bits_per_pixel == 16)
381 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
382 else if (!fbi->cmap_static)
383 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
384 else {
385 /*
386 * Some people have weird ideas about wanting static
387 * pseudocolor maps. I suspect their user space
388 * applications are broken.
389 */
390 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
391 }
392
393 fbi->fb.fix.line_length = var->xres_virtual *
394 var->bits_per_pixel / 8;
395 if (var->bits_per_pixel == 16)
396 fbi->palette_size = 0;
397 else
b0086efb 398 fbi->palette_size = var->bits_per_pixel == 1 ?
399 4 : 1 << var->bits_per_pixel;
1da177e4 400
2c42dd8e 401 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
1da177e4
LT		 402
403 /*
404 * Set (any) board control register to handle new color depth
405 */
406 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
407
408 if (fbi->fb.var.bits_per_pixel == 16)
409 fb_dealloc_cmap(&fbi->fb.cmap);
410 else
411 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
412
413 pxafb_activate_var(var, fbi);
414
415 return 0;
416}
417
1da177e4
LT		 418/*
419 * pxafb_blank():
420 * Blank the display by setting all palette values to zero. Note, the
421 * 16 bpp mode does not really use the palette, so this will not
422 * blank the display in all modes.
423 */
424static int pxafb_blank(int blank, struct fb_info *info)
425{
426 struct pxafb_info *fbi = (struct pxafb_info *)info;
427 int i;
428
1da177e4
LT		 429 switch (blank) {
430 case FB_BLANK_POWERDOWN:
431 case FB_BLANK_VSYNC_SUSPEND:
432 case FB_BLANK_HSYNC_SUSPEND:
433 case FB_BLANK_NORMAL:
434 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
435 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
436 for (i = 0; i < fbi->palette_size; i++)
437 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
438
439 pxafb_schedule_work(fbi, C_DISABLE);
b0086efb 440 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 441 break;
442
443 case FB_BLANK_UNBLANK:
b0086efb 444 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
1da177e4
LT		 445 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
446 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
447 fb_set_cmap(&fbi->fb.cmap, info);
448 pxafb_schedule_work(fbi, C_ENABLE);
449 }
450 return 0;
451}
452
216d526c 453static int pxafb_mmap(struct fb_info *info,
1da177e4
LT		 454 struct vm_area_struct *vma)
455{
456 struct pxafb_info *fbi = (struct pxafb_info *)info;
457 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
458
459 if (off < info->fix.smem_len) {
3c42a449 460 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
1da177e4
LT		 461 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
462 fbi->map_dma, fbi->map_size);
463 }
464 return -EINVAL;
465}
466
467static struct fb_ops pxafb_ops = {
468 .owner = THIS_MODULE,
469 .fb_check_var = pxafb_check_var,
470 .fb_set_par = pxafb_set_par,
471 .fb_setcolreg = pxafb_setcolreg,
472 .fb_fillrect = cfb_fillrect,
473 .fb_copyarea = cfb_copyarea,
474 .fb_imageblit = cfb_imageblit,
475 .fb_blank = pxafb_blank,
1da177e4
LT		 476 .fb_mmap = pxafb_mmap,
477};
478
479/*
480 * Calculate the PCD value from the clock rate (in picoseconds).
481 * We take account of the PPCR clock setting.
482 * From PXA Developer's Manual:
483 *
484 * PixelClock = LCLK
485 * -------------
486 * 2 ( PCD + 1 )
487 *
488 * PCD = LCLK
489 * ------------- - 1
490 * 2(PixelClock)
491 *
492 * Where:
493 * LCLK = LCD/Memory Clock
494 * PCD = LCCR3[7:0]
495 *
496 * PixelClock here is in Hz while the pixclock argument given is the
497 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
498 *
499 * The function get_lclk_frequency_10khz returns LCLK in units of
500 * 10khz. Calling the result of this function lclk gives us the
501 * following
502 *
503 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
504 * -------------------------------------- - 1
505 * 2
506 *
507 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
508 */
b0086efb 509static inline unsigned int get_pcd(struct pxafb_info *fbi,
510 unsigned int pixclock)
1da177e4
LT		 511{
512 unsigned long long pcd;
513
514 /* FIXME: Need to take into account Double Pixel Clock mode
72e3524c
RK		 515 * (DPC) bit? or perhaps set it based on the various clock
516 * speeds */
517 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
518 pcd *= pixclock;
bf1b8ab6 519 do_div(pcd, 100000000 * 2);
1da177e4
LT		 520 /* no need for this, since we should subtract 1 anyway. they cancel */
521 /* pcd += 1; */ /* make up for integer math truncations */
522 return (unsigned int)pcd;
523}
524
ba44cd2d
RP		 525/*
526 * Some touchscreens need hsync information from the video driver to
72e3524c
RK		 527 * function correctly. We export it here. Note that 'hsync_time' and
528 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
529 * of the hsync period in seconds.
ba44cd2d
RP		 530 */
531static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
532{
72e3524c 533 unsigned long htime;
ba44cd2d
RP		 534
535 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
b0086efb 536 fbi->hsync_time = 0;
ba44cd2d
RP		 537 return;
538 }
539
72e3524c
RK		 540 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
541
ba44cd2d
RP		 542 fbi->hsync_time = htime;
543}
544
545unsigned long pxafb_get_hsync_time(struct device *dev)
546{
547 struct pxafb_info *fbi = dev_get_drvdata(dev);
548
549 /* If display is blanked/suspended, hsync isn't active */
550 if (!fbi || (fbi->state != C_ENABLE))
551 return 0;
552
553 return fbi->hsync_time;
554}
555EXPORT_SYMBOL(pxafb_get_hsync_time);
556
2c42dd8e 557static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
558 unsigned int offset, size_t size)
559{
560 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
561 unsigned int dma_desc_off, pal_desc_off;
562
563 if (dma < 0 || dma >= DMA_MAX)
564 return -EINVAL;
565
566 dma_desc = &fbi->dma_buff->dma_desc[dma];
567 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
568
569 dma_desc->fsadr = fbi->screen_dma + offset;
570 dma_desc->fidr = 0;
571 dma_desc->ldcmd = size;
572
573 if (pal < 0 || pal >= PAL_MAX) {
574 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
575 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
576 } else {
577 pal_desc = &fbi->dma_buff->pal_desc[dma];
578 pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]);
579
580 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
581 pal_desc->fidr = 0;
582
583 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
584 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
585 else
586 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
587
588 pal_desc->ldcmd |= LDCMD_PAL;
589
590 /* flip back and forth between palette and frame buffer */
591 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
592 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
593 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
594 }
595
596 return 0;
597}
598
3c42a449
EM		 599#ifdef CONFIG_FB_PXA_SMARTPANEL
600static int setup_smart_dma(struct pxafb_info *fbi)
601{
602 struct pxafb_dma_descriptor *dma_desc;
603 unsigned long dma_desc_off, cmd_buff_off;
604
605 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
606 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
607 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
608
609 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
610 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
611 dma_desc->fidr = 0;
612 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
613
614 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
615 return 0;
616}
617
618int pxafb_smart_flush(struct fb_info *info)
619{
620 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
621 uint32_t prsr;
622 int ret = 0;
623
624 /* disable controller until all registers are set up */
625 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
626
627 /* 1. make it an even number of commands to align on 32-bit boundary
628 * 2. add the interrupt command to the end of the chain so we can
629 * keep track of the end of the transfer
630 */
631
632 while (fbi->n_smart_cmds & 1)
633 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
634
635 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
636 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
637 setup_smart_dma(fbi);
638
639 /* continue to execute next command */
640 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
641 lcd_writel(fbi, PRSR, prsr);
642
643 /* stop the processor in case it executed "wait for sync" cmd */
644 lcd_writel(fbi, CMDCR, 0x0001);
645
646 /* don't send interrupts for fifo underruns on channel 6 */
647 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
648
649 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
650 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
651 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
652 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
653 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
654
655 /* begin sending */
656 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
657
658 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
659 pr_warning("%s: timeout waiting for command done\n",
660 __func__);
661 ret = -ETIMEDOUT;
662 }
663
664 /* quick disable */
665 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
666 lcd_writel(fbi, PRSR, prsr);
667 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
668 lcd_writel(fbi, FDADR6, 0);
669 fbi->n_smart_cmds = 0;
670 return ret;
671}
672
673int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
674{
675 int i;
676 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
677
678 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
679 for (i = 0; i < n_cmds; i++) {
680 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
681 pxafb_smart_flush(info);
682
683 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
684 }
685
686 return 0;
687}
688
689static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
690{
691 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
692 return (t == 0) ? 1 : t;
693}
694
695static void setup_smart_timing(struct pxafb_info *fbi,
696 struct fb_var_screeninfo *var)
697{
698 struct pxafb_mach_info *inf = fbi->dev->platform_data;
699 struct pxafb_mode_info *mode = &inf->modes[0];
700 unsigned long lclk = clk_get_rate(fbi->clk);
701 unsigned t1, t2, t3, t4;
702
703 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
704 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
705 t3 = mode->op_hold_time;
706 t4 = mode->cmd_inh_time;
707
708 fbi->reg_lccr1 =
709 LCCR1_DisWdth(var->xres) |
710 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
711 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
712 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
713
714 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
715 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
716
717 /* FIXME: make this configurable */
718 fbi->reg_cmdcr = 1;
719}
720
721static int pxafb_smart_thread(void *arg)
722{
7f1133cb 723 struct pxafb_info *fbi = arg;
3c42a449
EM		 724 struct pxafb_mach_info *inf = fbi->dev->platform_data;
725
726 if (!fbi || !inf->smart_update) {
727 pr_err("%s: not properly initialized, thread terminated\n",
728 __func__);
729 return -EINVAL;
730 }
731
732 pr_debug("%s(): task starting\n", __func__);
733
734 set_freezable();
735 while (!kthread_should_stop()) {
736
737 if (try_to_freeze())
738 continue;
739
740 if (fbi->state == C_ENABLE) {
741 inf->smart_update(&fbi->fb);
742 complete(&fbi->refresh_done);
743 }
744
745 set_current_state(TASK_INTERRUPTIBLE);
746 schedule_timeout(30 * HZ / 1000);
747 }
748
749 pr_debug("%s(): task ending\n", __func__);
750 return 0;
751}
752
753static int pxafb_smart_init(struct pxafb_info *fbi)
754{
755 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
756 "lcd_refresh");
757 if (IS_ERR(fbi->smart_thread)) {
758 printk(KERN_ERR "%s: unable to create kernel thread\n",
759 __func__);
760 return PTR_ERR(fbi->smart_thread);
761 }
762 return 0;
763}
764#else
765int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
766{
767 return 0;
768}
769
770int pxafb_smart_flush(struct fb_info *info)
771{
772 return 0;
773}
774#endif /* CONFIG_FB_SMART_PANEL */
775
90eabbf0
EM		 776static void setup_parallel_timing(struct pxafb_info *fbi,
777 struct fb_var_screeninfo *var)
778{
779 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
780
781 fbi->reg_lccr1 =
782 LCCR1_DisWdth(var->xres) +
783 LCCR1_HorSnchWdth(var->hsync_len) +
784 LCCR1_BegLnDel(var->left_margin) +
785 LCCR1_EndLnDel(var->right_margin);
786
787 /*
788 * If we have a dual scan LCD, we need to halve
789 * the YRES parameter.
790 */
791 lines_per_panel = var->yres;
792 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
793 lines_per_panel /= 2;
794
795 fbi->reg_lccr2 =
796 LCCR2_DisHght(lines_per_panel) +
797 LCCR2_VrtSnchWdth(var->vsync_len) +
798 LCCR2_BegFrmDel(var->upper_margin) +
799 LCCR2_EndFrmDel(var->lower_margin);
800
801 fbi->reg_lccr3 = fbi->lccr3 |
802 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
803 LCCR3_HorSnchH : LCCR3_HorSnchL) |
804 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
805 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
806
807 if (pcd) {
808 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
809 set_hsync_time(fbi, pcd);
810 }
811}
812
1da177e4
LT		 813/*
814 * pxafb_activate_var():
b0086efb 815 * Configures LCD Controller based on entries in var parameter.
816 * Settings are only written to the controller if changes were made.
1da177e4 817 */
b0086efb 818static int pxafb_activate_var(struct fb_var_screeninfo *var,
819 struct pxafb_info *fbi)
1da177e4 820{
1da177e4 821 u_long flags;
2c42dd8e 822 size_t nbytes;
1da177e4 823
1da177e4 824#if DEBUG_VAR
3c42a449
EM		 825 if (!(fbi->lccr0 & LCCR0_LCDT)) {
826 if (var->xres < 16 || var->xres > 1024)
827 printk(KERN_ERR "%s: invalid xres %d\n",
828 fbi->fb.fix.id, var->xres);
829 switch (var->bits_per_pixel) {
830 case 1:
831 case 2:
832 case 4:
833 case 8:
834 case 16:
835 break;
836 default:
837 printk(KERN_ERR "%s: invalid bit depth %d\n",
838 fbi->fb.fix.id, var->bits_per_pixel);
839 break;
840 }
841
842 if (var->hsync_len < 1 || var->hsync_len > 64)
843 printk(KERN_ERR "%s: invalid hsync_len %d\n",
844 fbi->fb.fix.id, var->hsync_len);
845 if (var->left_margin < 1 || var->left_margin > 255)
846 printk(KERN_ERR "%s: invalid left_margin %d\n",
847 fbi->fb.fix.id, var->left_margin);
848 if (var->right_margin < 1 || var->right_margin > 255)
849 printk(KERN_ERR "%s: invalid right_margin %d\n",
850 fbi->fb.fix.id, var->right_margin);
851 if (var->yres < 1 || var->yres > 1024)
852 printk(KERN_ERR "%s: invalid yres %d\n",
853 fbi->fb.fix.id, var->yres);
854 if (var->vsync_len < 1 || var->vsync_len > 64)
855 printk(KERN_ERR "%s: invalid vsync_len %d\n",
856 fbi->fb.fix.id, var->vsync_len);
857 if (var->upper_margin < 0 || var->upper_margin > 255)
858 printk(KERN_ERR "%s: invalid upper_margin %d\n",
859 fbi->fb.fix.id, var->upper_margin);
860 if (var->lower_margin < 0 || var->lower_margin > 255)
861 printk(KERN_ERR "%s: invalid lower_margin %d\n",
862 fbi->fb.fix.id, var->lower_margin);
1da177e4 863 }
1da177e4 864#endif
90eabbf0
EM		 865 /* Update shadow copy atomically */
866 local_irq_save(flags);
1da177e4 867
3c42a449
EM		 868#ifdef CONFIG_FB_PXA_SMARTPANEL
869 if (fbi->lccr0 & LCCR0_LCDT)
870 setup_smart_timing(fbi, var);
871 else
872#endif
873 setup_parallel_timing(fbi, var);
90eabbf0
EM		 874
875 fbi->reg_lccr0 = fbi->lccr0 |
1da177e4 876 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
b0086efb 877 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
1da177e4 878
90eabbf0 879 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
1da177e4 880
90eabbf0 881 nbytes = var->yres * fbi->fb.fix.line_length;
1da177e4 882
90eabbf0
EM		 883 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
884 nbytes = nbytes / 2;
2c42dd8e 885 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
90eabbf0 886 }
2c42dd8e 887
3c42a449 888 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
2c42dd8e 889 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
890 else
891 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
1da177e4 892
a7535ba7 893 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
9ffa7396 894 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1da177e4
LT		 895 local_irq_restore(flags);
896
897 /*
898 * Only update the registers if the controller is enabled
899 * and something has changed.
900 */
a7535ba7
EM		 901 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
902 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
903 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
904 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
905 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
906 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1da177e4
LT		 907 pxafb_schedule_work(fbi, C_REENABLE);
908
909 return 0;
910}
911
912/*
913 * NOTE! The following functions are purely helpers for set_ctrlr_state.
914 * Do not call them directly; set_ctrlr_state does the correct serialisation
915 * to ensure that things happen in the right way 100% of time time.
916 * -- rmk
917 */
918static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
919{
ca5da710 920 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1da177e4 921
b0086efb 922 if (pxafb_backlight_power)
923 pxafb_backlight_power(on);
1da177e4
LT		 924}
925
926static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
927{
ca5da710 928 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1da177e4
LT		 929
930 if (pxafb_lcd_power)
d14b272b 931 pxafb_lcd_power(on, &fbi->fb.var);
1da177e4
LT		 932}
933
934static void pxafb_setup_gpio(struct pxafb_info *fbi)
935{
936 int gpio, ldd_bits;
b0086efb 937 unsigned int lccr0 = fbi->lccr0;
1da177e4
LT		 938
939 /*
940 * setup is based on type of panel supported
b0086efb 941 */
1da177e4
LT		 942
943 /* 4 bit interface */
944 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
945 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
946 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
947 ldd_bits = 4;
948
949 /* 8 bit interface */
b0086efb 950 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
951 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
952 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
953 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
954 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
955 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1da177e4
LT		 956 ldd_bits = 8;
957
958 /* 16 bit interface */
959 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
b0086efb 960 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
961 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1da177e4
LT		 962 ldd_bits = 16;
963
964 else {
b0086efb 965 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
966 "bits per pixel\n");
1da177e4 967 return;
b0086efb 968 }
1da177e4
LT		 969
970 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
971 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
972 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
973 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
974 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
975 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
976}
977
978static void pxafb_enable_controller(struct pxafb_info *fbi)
979{
ca5da710 980 pr_debug("pxafb: Enabling LCD controller\n");
2c42dd8e 981 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
982 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
ca5da710
RK		 983 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
984 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
985 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
986 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1da177e4 987
8d372266 988 /* enable LCD controller clock */
72e3524c 989 clk_enable(fbi->clk);
8d372266 990
3c42a449
EM		 991 if (fbi->lccr0 & LCCR0_LCDT)
992 return;
993
1da177e4 994 /* Sequence from 11.7.10 */
a7535ba7
EM		 995 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
996 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
997 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
998 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
999
1000 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1001 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1002 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1da177e4
LT		 1003}
1004
1005static void pxafb_disable_controller(struct pxafb_info *fbi)
1006{
ce4fb7b8 1007 uint32_t lccr0;
1008
3c42a449
EM		 1009#ifdef CONFIG_FB_PXA_SMARTPANEL
1010 if (fbi->lccr0 & LCCR0_LCDT) {
1011 wait_for_completion_timeout(&fbi->refresh_done,
1012 200 * HZ / 1000);
1013 return;
1014 }
1015#endif
1016
ce4fb7b8 1017 /* Clear LCD Status Register */
a7535ba7 1018 lcd_writel(fbi, LCSR, 0xffffffff);
ce4fb7b8 1019
a7535ba7
EM		 1020 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1021 lcd_writel(fbi, LCCR0, lccr0);
1022 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1da177e4 1023
2ba162b9 1024 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
8d372266
NP		 1025
1026 /* disable LCD controller clock */
72e3524c 1027 clk_disable(fbi->clk);
1da177e4
LT		 1028}
1029
1030/*
1031 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1032 */
7d12e780 1033static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1da177e4
LT		 1034{
1035 struct pxafb_info *fbi = dev_id;
a7535ba7 1036 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1da177e4
LT		 1037
1038 if (lcsr & LCSR_LDD) {
a7535ba7
EM		 1039 lccr0 = lcd_readl(fbi, LCCR0);
1040 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
2ba162b9 1041 complete(&fbi->disable_done);
1da177e4
LT		 1042 }
1043
3c42a449
EM		 1044#ifdef CONFIG_FB_PXA_SMARTPANEL
1045 if (lcsr & LCSR_CMD_INT)
1046 complete(&fbi->command_done);
1047#endif
1048
a7535ba7 1049 lcd_writel(fbi, LCSR, lcsr);
1da177e4
LT		 1050 return IRQ_HANDLED;
1051}
1052
1053/*
1054 * This function must be called from task context only, since it will
1055 * sleep when disabling the LCD controller, or if we get two contending
1056 * processes trying to alter state.
1057 */
1058static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1059{
1060 u_int old_state;
1061
1062 down(&fbi->ctrlr_sem);
1063
1064 old_state = fbi->state;
1065
1066 /*
1067 * Hack around fbcon initialisation.
1068 */
1069 if (old_state == C_STARTUP && state == C_REENABLE)
1070 state = C_ENABLE;
1071
1072 switch (state) {
1073 case C_DISABLE_CLKCHANGE:
1074 /*
1075 * Disable controller for clock change. If the
1076 * controller is already disabled, then do nothing.
1077 */
1078 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1079 fbi->state = state;
b0086efb 1080 /* TODO __pxafb_lcd_power(fbi, 0); */
1da177e4
LT		 1081 pxafb_disable_controller(fbi);
1082 }
1083 break;
1084
1085 case C_DISABLE_PM:
1086 case C_DISABLE:
1087 /*
1088 * Disable controller
1089 */
1090 if (old_state != C_DISABLE) {
1091 fbi->state = state;
1092 __pxafb_backlight_power(fbi, 0);
1093 __pxafb_lcd_power(fbi, 0);
1094 if (old_state != C_DISABLE_CLKCHANGE)
1095 pxafb_disable_controller(fbi);
1096 }
1097 break;
1098
1099 case C_ENABLE_CLKCHANGE:
1100 /*
1101 * Enable the controller after clock change. Only
1102 * do this if we were disabled for the clock change.
1103 */
1104 if (old_state == C_DISABLE_CLKCHANGE) {
1105 fbi->state = C_ENABLE;
1106 pxafb_enable_controller(fbi);
b0086efb 1107 /* TODO __pxafb_lcd_power(fbi, 1); */
1da177e4
LT		 1108 }
1109 break;
1110
1111 case C_REENABLE:
1112 /*
1113 * Re-enable the controller only if it was already
1114 * enabled. This is so we reprogram the control
1115 * registers.
1116 */
1117 if (old_state == C_ENABLE) {
d14b272b 1118 __pxafb_lcd_power(fbi, 0);
1da177e4
LT		 1119 pxafb_disable_controller(fbi);
1120 pxafb_setup_gpio(fbi);
1121 pxafb_enable_controller(fbi);
d14b272b 1122 __pxafb_lcd_power(fbi, 1);
1da177e4
LT		 1123 }
1124 break;
1125
1126 case C_ENABLE_PM:
1127 /*
1128 * Re-enable the controller after PM. This is not
1129 * perfect - think about the case where we were doing
1130 * a clock change, and we suspended half-way through.
1131 */
1132 if (old_state != C_DISABLE_PM)
1133 break;
1134 /* fall through */
1135
1136 case C_ENABLE:
1137 /*
1138 * Power up the LCD screen, enable controller, and
1139 * turn on the backlight.
1140 */
1141 if (old_state != C_ENABLE) {
1142 fbi->state = C_ENABLE;
1143 pxafb_setup_gpio(fbi);
1144 pxafb_enable_controller(fbi);
1145 __pxafb_lcd_power(fbi, 1);
1146 __pxafb_backlight_power(fbi, 1);
1147 }
1148 break;
1149 }
1150 up(&fbi->ctrlr_sem);
1151}
1152
1153/*
1154 * Our LCD controller task (which is called when we blank or unblank)
1155 * via keventd.
1156 */
6d5aefb8 1157static void pxafb_task(struct work_struct *work)
1da177e4 1158{
6d5aefb8
DH		 1159 struct pxafb_info *fbi =
1160 container_of(work, struct pxafb_info, task);
1da177e4
LT		 1161 u_int state = xchg(&fbi->task_state, -1);
1162
1163 set_ctrlr_state(fbi, state);
1164}
1165
1166#ifdef CONFIG_CPU_FREQ
1167/*
1168 * CPU clock speed change handler. We need to adjust the LCD timing
1169 * parameters when the CPU clock is adjusted by the power management
1170 * subsystem.
1171 *
1172 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1173 */
1174static int
1175pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1176{
1177 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
b0086efb 1178 /* TODO struct cpufreq_freqs *f = data; */
1da177e4
LT		 1179 u_int pcd;
1180
1181 switch (val) {
1182 case CPUFREQ_PRECHANGE:
1183 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1184 break;
1185
1186 case CPUFREQ_POSTCHANGE:
72e3524c 1187 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
ba44cd2d 1188 set_hsync_time(fbi, pcd);
b0086efb 1189 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1190 LCCR3_PixClkDiv(pcd);
1da177e4
LT		 1191 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1192 break;
1193 }
1194 return 0;
1195}
1196
1197static int
1198pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1199{
1200 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1201 struct fb_var_screeninfo *var = &fbi->fb.var;
1202 struct cpufreq_policy *policy = data;
1203
1204 switch (val) {
1205 case CPUFREQ_ADJUST:
1206 case CPUFREQ_INCOMPATIBLE:
ac2bf5bd 1207 pr_debug("min dma period: %d ps, "
1da177e4
LT		 1208 "new clock %d kHz\n", pxafb_display_dma_period(var),
1209 policy->max);
b0086efb 1210 /* TODO: fill in min/max values */
1da177e4 1211 break;
1da177e4
LT		 1212 }
1213 return 0;
1214}
1215#endif
1216
1217#ifdef CONFIG_PM
1218/*
1219 * Power management hooks. Note that we won't be called from IRQ context,
1220 * unlike the blank functions above, so we may sleep.
1221 */
3ae5eaec 1222static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1223{
3ae5eaec 1224 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1225
9480e307 1226 set_ctrlr_state(fbi, C_DISABLE_PM);
1da177e4
LT		 1227 return 0;
1228}
1229
3ae5eaec 1230static int pxafb_resume(struct platform_device *dev)
1da177e4 1231{
3ae5eaec 1232 struct pxafb_info *fbi = platform_get_drvdata(dev);
1da177e4 1233
9480e307 1234 set_ctrlr_state(fbi, C_ENABLE_PM);
1da177e4
LT		 1235 return 0;
1236}
1237#else
1238#define pxafb_suspend NULL
1239#define pxafb_resume NULL
1240#endif
1241
1242/*
1243 * pxafb_map_video_memory():
1244 * Allocates the DRAM memory for the frame buffer. This buffer is
1245 * remapped into a non-cached, non-buffered, memory region to
1246 * allow palette and pixel writes to occur without flushing the
1247 * cache. Once this area is remapped, all virtual memory
1248 * access to the video memory should occur at the new region.
1249 */
1250static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
1251{
1da177e4
LT		 1252 /*
1253 * We reserve one page for the palette, plus the size
1254 * of the framebuffer.
1255 */
3c42a449
EM		 1256 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1257 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1da177e4
LT		 1258 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1259 &fbi->map_dma, GFP_KERNEL);
1260
1261 if (fbi->map_cpu) {
1262 /* prevent initial garbage on screen */
1263 memset(fbi->map_cpu, 0, fbi->map_size);
3c42a449
EM		 1264 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1265 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1266
1da177e4
LT		 1267 /*
1268 * FIXME: this is actually the wrong thing to place in
1269 * smem_start. But fbdev suffers from the problem that
1270 * it needs an API which doesn't exist (in this case,
1271 * dma_writecombine_mmap)
1272 */
1273 fbi->fb.fix.smem_start = fbi->screen_dma;
1da177e4
LT		 1274 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1275
3c42a449 1276 fbi->dma_buff = (void *) fbi->map_cpu;
2c42dd8e 1277 fbi->dma_buff_phys = fbi->map_dma;
3c42a449
EM		 1278 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1279
1280#ifdef CONFIG_FB_PXA_SMARTPANEL
1281 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1282 fbi->n_smart_cmds = 0;
1283#endif
1da177e4
LT		 1284 }
1285
1286 return fbi->map_cpu ? 0 : -ENOMEM;
1287}
1288
84f43c30 1289static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1290 struct pxafb_mode_info *modes,
1291 unsigned int num_modes)
1292{
1293 unsigned int i, smemlen;
1294
1295 pxafb_setmode(&fbi->fb.var, &modes[0]);
1296
1297 for (i = 0; i < num_modes; i++) {
1298 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1299 if (smemlen > fbi->fb.fix.smem_len)
1300 fbi->fb.fix.smem_len = smemlen;
1301 }
1302}
1303
1304static int pxafb_decode_mach_info(struct pxafb_info *fbi,
1305 struct pxafb_mach_info *inf)
1306{
1307 unsigned int lcd_conn = inf->lcd_conn;
1308
1309 fbi->cmap_inverse = inf->cmap_inverse;
1310 fbi->cmap_static = inf->cmap_static;
1311
1312 switch (lcd_conn & 0xf) {
1313 case LCD_TYPE_MONO_STN:
1314 fbi->lccr0 = LCCR0_CMS;
1315 break;
1316 case LCD_TYPE_MONO_DSTN:
1317 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1318 break;
1319 case LCD_TYPE_COLOR_STN:
1320 fbi->lccr0 = 0;
1321 break;
1322 case LCD_TYPE_COLOR_DSTN:
1323 fbi->lccr0 = LCCR0_SDS;
1324 break;
1325 case LCD_TYPE_COLOR_TFT:
1326 fbi->lccr0 = LCCR0_PAS;
1327 break;
1328 case LCD_TYPE_SMART_PANEL:
1329 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1330 break;
1331 default:
1332 /* fall back to backward compatibility way */
1333 fbi->lccr0 = inf->lccr0;
1334 fbi->lccr3 = inf->lccr3;
1335 fbi->lccr4 = inf->lccr4;
1336 return -EINVAL;
1337 }
1338
1339 if (lcd_conn == LCD_MONO_STN_8BPP)
1340 fbi->lccr0 |= LCCR0_DPD;
1341
1342 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1343 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1344 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1345
1346 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1347 return 0;
1348}
1349
1da177e4
LT		 1350static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1351{
1352 struct pxafb_info *fbi;
1353 void *addr;
1354 struct pxafb_mach_info *inf = dev->platform_data;
d14b272b 1355 struct pxafb_mode_info *mode = inf->modes;
1da177e4
LT		 1356
1357 /* Alloc the pxafb_info and pseudo_palette in one step */
1358 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1359 if (!fbi)
1360 return NULL;
1361
1362 memset(fbi, 0, sizeof(struct pxafb_info));
1363 fbi->dev = dev;
1364
72e3524c
RK		 1365 fbi->clk = clk_get(dev, "LCDCLK");
1366 if (IS_ERR(fbi->clk)) {
1367 kfree(fbi);
1368 return NULL;
1369 }
1370
1da177e4
LT		 1371 strcpy(fbi->fb.fix.id, PXA_NAME);
1372
1373 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1374 fbi->fb.fix.type_aux = 0;
1375 fbi->fb.fix.xpanstep = 0;
1376 fbi->fb.fix.ypanstep = 0;
1377 fbi->fb.fix.ywrapstep = 0;
1378 fbi->fb.fix.accel = FB_ACCEL_NONE;
1379
1380 fbi->fb.var.nonstd = 0;
1381 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1382 fbi->fb.var.height = -1;
1383 fbi->fb.var.width = -1;
1384 fbi->fb.var.accel_flags = 0;
1385 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1386
1387 fbi->fb.fbops = &pxafb_ops;
1388 fbi->fb.flags = FBINFO_DEFAULT;
1389 fbi->fb.node = -1;
1390
1391 addr = fbi;
1392 addr = addr + sizeof(struct pxafb_info);
1393 fbi->fb.pseudo_palette = addr;
1394
b0086efb 1395 fbi->state = C_STARTUP;
1396 fbi->task_state = (u_char)-1;
d14b272b 1397
84f43c30 1398 pxafb_decode_mach_info(fbi, inf);
1da177e4
LT		 1399
1400 init_waitqueue_head(&fbi->ctrlr_wait);
6d5aefb8 1401 INIT_WORK(&fbi->task, pxafb_task);
1da177e4 1402 init_MUTEX(&fbi->ctrlr_sem);
2ba162b9 1403 init_completion(&fbi->disable_done);
3c42a449
EM		 1404#ifdef CONFIG_FB_PXA_SMARTPANEL
1405 init_completion(&fbi->command_done);
1406 init_completion(&fbi->refresh_done);
1407#endif
1da177e4
LT		 1408
1409 return fbi;
1410}
1411
1412#ifdef CONFIG_FB_PXA_PARAMETERS
b0086efb 1413static int __init parse_opt_mode(struct device *dev, const char *this_opt)
1da177e4
LT		 1414{
1415 struct pxafb_mach_info *inf = dev->platform_data;
817daf14 1416
1417 const char *name = this_opt+5;
1418 unsigned int namelen = strlen(name);
1419 int res_specified = 0, bpp_specified = 0;
1420 unsigned int xres = 0, yres = 0, bpp = 0;
1421 int yres_specified = 0;
1422 int i;
1423 for (i = namelen-1; i >= 0; i--) {
1424 switch (name[i]) {
1425 case '-':
1426 namelen = i;
1427 if (!bpp_specified && !yres_specified) {
1428 bpp = simple_strtoul(&name[i+1], NULL, 0);
1429 bpp_specified = 1;
1430 } else
1431 goto done;
1432 break;
1433 case 'x':
1434 if (!yres_specified) {
1435 yres = simple_strtoul(&name[i+1], NULL, 0);
1436 yres_specified = 1;
1437 } else
1438 goto done;
1439 break;
1440 case '0' ... '9':
1441 break;
1442 default:
1443 goto done;
1444 }
1445 }
1446 if (i < 0 && yres_specified) {
1447 xres = simple_strtoul(name, NULL, 0);
1448 res_specified = 1;
1449 }
1450done:
1451 if (res_specified) {
1452 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1453 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1454 }
1455 if (bpp_specified)
1456 switch (bpp) {
1457 case 1:
1458 case 2:
1459 case 4:
1460 case 8:
1461 case 16:
1462 inf->modes[0].bpp = bpp;
1463 dev_info(dev, "overriding bit depth: %d\n", bpp);
1464 break;
1465 default:
1466 dev_err(dev, "Depth %d is not valid\n", bpp);
1467 return -EINVAL;
1468 }
1469 return 0;
1470}
1471
b0086efb 1472static int __init parse_opt(struct device *dev, char *this_opt)
817daf14 1473{
1474 struct pxafb_mach_info *inf = dev->platform_data;
1475 struct pxafb_mode_info *mode = &inf->modes[0];
1476 char s[64];
1477
1478 s[0] = '\0';
1479
1480 if (!strncmp(this_opt, "mode:", 5)) {
1481 return parse_opt_mode(dev, this_opt);
1482 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1483 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1484 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1485 } else if (!strncmp(this_opt, "left:", 5)) {
1486 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1487 sprintf(s, "left: %u\n", mode->left_margin);
1488 } else if (!strncmp(this_opt, "right:", 6)) {
1489 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1490 sprintf(s, "right: %u\n", mode->right_margin);
1491 } else if (!strncmp(this_opt, "upper:", 6)) {
1492 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1493 sprintf(s, "upper: %u\n", mode->upper_margin);
1494 } else if (!strncmp(this_opt, "lower:", 6)) {
1495 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1496 sprintf(s, "lower: %u\n", mode->lower_margin);
1497 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1498 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1499 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1500 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1501 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1502 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1503 } else if (!strncmp(this_opt, "hsync:", 6)) {
1504 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1505 sprintf(s, "hsync: Active Low\n");
1506 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1507 } else {
1508 sprintf(s, "hsync: Active High\n");
1509 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1510 }
1511 } else if (!strncmp(this_opt, "vsync:", 6)) {
1512 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1513 sprintf(s, "vsync: Active Low\n");
1514 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1515 } else {
1516 sprintf(s, "vsync: Active High\n");
1517 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1518 }
1519 } else if (!strncmp(this_opt, "dpc:", 4)) {
1520 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1521 sprintf(s, "double pixel clock: false\n");
1522 inf->lccr3 &= ~LCCR3_DPC;
1523 } else {
1524 sprintf(s, "double pixel clock: true\n");
1525 inf->lccr3 |= LCCR3_DPC;
1526 }
1527 } else if (!strncmp(this_opt, "outputen:", 9)) {
1528 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1529 sprintf(s, "output enable: active low\n");
1530 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1531 } else {
1532 sprintf(s, "output enable: active high\n");
1533 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1534 }
1535 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1536 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1537 sprintf(s, "pixel clock polarity: falling edge\n");
1538 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1539 } else {
1540 sprintf(s, "pixel clock polarity: rising edge\n");
1541 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1542 }
1543 } else if (!strncmp(this_opt, "color", 5)) {
1544 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1545 } else if (!strncmp(this_opt, "mono", 4)) {
1546 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1547 } else if (!strncmp(this_opt, "active", 6)) {
1548 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1549 } else if (!strncmp(this_opt, "passive", 7)) {
1550 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1551 } else if (!strncmp(this_opt, "single", 6)) {
1552 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1553 } else if (!strncmp(this_opt, "dual", 4)) {
1554 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1555 } else if (!strncmp(this_opt, "4pix", 4)) {
1556 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1557 } else if (!strncmp(this_opt, "8pix", 4)) {
1558 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1559 } else {
1560 dev_err(dev, "unknown option: %s\n", this_opt);
1561 return -EINVAL;
1562 }
1563
1564 if (s[0] != '\0')
1565 dev_info(dev, "override %s", s);
1566
1567 return 0;
1568}
1569
1570static int __init pxafb_parse_options(struct device *dev, char *options)
1571{
1da177e4 1572 char *this_opt;
817daf14 1573 int ret;
1da177e4 1574
817daf14 1575 if (!options || !*options)
1576 return 0;
1da177e4
LT		 1577
1578 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1579
1580 /* could be made table driven or similar?... */
817daf14 1581 while ((this_opt = strsep(&options, ",")) != NULL) {
1582 ret = parse_opt(dev, this_opt);
1583 if (ret)
1584 return ret;
1585 }
1586 return 0;
1da177e4 1587}
92ac73c1 1588
1589static char g_options[256] __devinitdata = "";
1590
1591#ifndef CONFIG_MODULES
1592static int __devinit pxafb_setup_options(void)
1593{
1594 char *options = NULL;
1595
1596 if (fb_get_options("pxafb", &options))
1597 return -ENODEV;
1598
1599 if (options)
1600 strlcpy(g_options, options, sizeof(g_options));
1601
1602 return 0;
1603}
1604#else
1605#define pxafb_setup_options() (0)
1606
1607module_param_string(options, g_options, sizeof(g_options), 0);
1608MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1609#endif
1610
1611#else
1612#define pxafb_parse_options(...) (0)
1613#define pxafb_setup_options() (0)
1da177e4
LT		 1614#endif
1615
ac2bf5bd 1616static int __init pxafb_probe(struct platform_device *dev)
1da177e4
LT		 1617{
1618 struct pxafb_info *fbi;
1619 struct pxafb_mach_info *inf;
ce4fb7b8 1620 struct resource *r;
1621 int irq, ret;
1da177e4 1622
2cbbb3b5 1623 dev_dbg(&dev->dev, "pxafb_probe\n");
1da177e4 1624
3ae5eaec 1625 inf = dev->dev.platform_data;
1da177e4
LT		 1626 ret = -ENOMEM;
1627 fbi = NULL;
1628 if (!inf)
1629 goto failed;
1630
3ae5eaec 1631 ret = pxafb_parse_options(&dev->dev, g_options);
1da177e4
LT		 1632 if (ret < 0)
1633 goto failed;
1da177e4
LT		 1634
1635#ifdef DEBUG_VAR
b0086efb 1636 /* Check for various illegal bit-combinations. Currently only
1da177e4
LT		 1637 * a warning is given. */
1638
b0086efb 1639 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1640 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1641 "illegal bits: %08x\n",
1642 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1643 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1644 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1645 "illegal bits: %08x\n",
1646 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1647 if (inf->lccr0 & LCCR0_DPD &&
1da177e4
LT		 1648 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1649 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1650 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
b0086efb 1651 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1652 "only valid in passive mono"
1653 " single panel mode\n");
1654 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1da177e4 1655 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
b0086efb 1656 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1657 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1658 (inf->modes->upper_margin || inf->modes->lower_margin))
1659 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1660 "passive mode\n");
1da177e4
LT		 1661#endif
1662
b0086efb 1663 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1664 inf->modes->xres,
1665 inf->modes->yres,
1666 inf->modes->bpp);
1667 if (inf->modes->xres == 0 ||
1668 inf->modes->yres == 0 ||
1669 inf->modes->bpp == 0) {
3ae5eaec 1670 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1da177e4
LT		 1671 ret = -EINVAL;
1672 goto failed;
1673 }
1674 pxafb_backlight_power = inf->pxafb_backlight_power;
1675 pxafb_lcd_power = inf->pxafb_lcd_power;
3ae5eaec 1676 fbi = pxafb_init_fbinfo(&dev->dev);
1da177e4 1677 if (!fbi) {
b0086efb 1678 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
3ae5eaec 1679 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
b0086efb 1680 ret = -ENOMEM;
1da177e4
LT		 1681 goto failed;
1682 }
1683
ce4fb7b8 1684 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1685 if (r == NULL) {
1686 dev_err(&dev->dev, "no I/O memory resource defined\n");
1687 ret = -ENODEV;
1688 goto failed;
1689 }
1690
1691 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1692 if (r == NULL) {
1693 dev_err(&dev->dev, "failed to request I/O memory\n");
1694 ret = -EBUSY;
1695 goto failed;
1696 }
1697
1698 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1699 if (fbi->mmio_base == NULL) {
1700 dev_err(&dev->dev, "failed to map I/O memory\n");
1701 ret = -EBUSY;
1702 goto failed_free_res;
1703 }
1704
1da177e4
LT		 1705 /* Initialize video memory */
1706 ret = pxafb_map_video_memory(fbi);
1707 if (ret) {
3ae5eaec 1708 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1da177e4 1709 ret = -ENOMEM;
ce4fb7b8 1710 goto failed_free_io;
1da177e4 1711 }
1da177e4 1712
ce4fb7b8 1713 irq = platform_get_irq(dev, 0);
1714 if (irq < 0) {
1715 dev_err(&dev->dev, "no IRQ defined\n");
1716 ret = -ENODEV;
1717 goto failed_free_mem;
1718 }
1719
1720 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1da177e4 1721 if (ret) {
3ae5eaec 1722 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1da177e4 1723 ret = -EBUSY;
ce4fb7b8 1724 goto failed_free_mem;
1da177e4
LT		 1725 }
1726
3c42a449
EM		 1727#ifdef CONFIG_FB_PXA_SMARTPANEL
1728 ret = pxafb_smart_init(fbi);
1729 if (ret) {
1730 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1731 goto failed_free_irq;
1732 }
1733#endif
1da177e4
LT		 1734 /*
1735 * This makes sure that our colour bitfield
1736 * descriptors are correctly initialised.
1737 */
1738 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1739 pxafb_set_par(&fbi->fb);
1740
3ae5eaec 1741 platform_set_drvdata(dev, fbi);
1da177e4
LT		 1742
1743 ret = register_framebuffer(&fbi->fb);
1744 if (ret < 0) {
b0086efb 1745 dev_err(&dev->dev,
1746 "Failed to register framebuffer device: %d\n", ret);
ce4fb7b8 1747 goto failed_free_irq;
1da177e4
LT		 1748 }
1749
1da177e4
LT		 1750#ifdef CONFIG_CPU_FREQ
1751 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1752 fbi->freq_policy.notifier_call = pxafb_freq_policy;
b0086efb 1753 cpufreq_register_notifier(&fbi->freq_transition,
1754 CPUFREQ_TRANSITION_NOTIFIER);
1755 cpufreq_register_notifier(&fbi->freq_policy,
1756 CPUFREQ_POLICY_NOTIFIER);
1da177e4
LT		 1757#endif
1758
1759 /*
1760 * Ok, now enable the LCD controller
1761 */
1762 set_ctrlr_state(fbi, C_ENABLE);
1763
1764 return 0;
1765
ce4fb7b8 1766failed_free_irq:
1767 free_irq(irq, fbi);
1768failed_free_res:
1769 release_mem_region(r->start, r->end - r->start + 1);
1770failed_free_io:
1771 iounmap(fbi->mmio_base);
1772failed_free_mem:
1773 dma_free_writecombine(&dev->dev, fbi->map_size,
1774 fbi->map_cpu, fbi->map_dma);
1da177e4 1775failed:
3ae5eaec 1776 platform_set_drvdata(dev, NULL);
1da177e4
LT		 1777 kfree(fbi);
1778 return ret;
1779}
1780
3ae5eaec 1781static struct platform_driver pxafb_driver = {
1da177e4 1782 .probe = pxafb_probe,
1da177e4
LT		 1783 .suspend = pxafb_suspend,
1784 .resume = pxafb_resume,
3ae5eaec
RK		 1785 .driver = {
1786 .name = "pxa2xx-fb",
1787 },
1da177e4
LT		 1788};
1789
ac2bf5bd 1790static int __devinit pxafb_init(void)
1da177e4 1791{
92ac73c1 1792 if (pxafb_setup_options())
1793 return -EINVAL;
1da177e4 1794
3ae5eaec 1795 return platform_driver_register(&pxafb_driver);
1da177e4
LT		 1796}
1797
1798module_init(pxafb_init);
1799
1800MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1801MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)