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36c9366e VW |
1 | /* |
2 | * Copyright (C) 2005 Philips Semiconductors | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2, or (at your option) | |
7 | * any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; see the file COPYING. If not, write to | |
16 | * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, | |
17 | * Boston, MA 02111-1307, USA, or http://www.gnu.org/licenses/gpl.html | |
18 | */ | |
19 | ||
20 | #define MAX_DUM_CHANNELS 64 | |
21 | ||
22 | #define RGB_MEM_WINDOW(x) (0x10000000 + (x)*0x00100000) | |
23 | ||
24 | #define QCIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x30000: -1) | |
25 | #define CIF_OFFSET(x) (((x) == 0) ? 0x00000: ((x) == 1) ? 0x60000: -1) | |
26 | ||
27 | #define CTRL_SETDIRTY (0x00000001) | |
28 | #define CONF_DIRTYENABLE (0x00000020) | |
29 | #define CONF_SYNCENABLE (0x00000004) | |
30 | ||
31 | #define DIRTY_ENABLED(conf) ((conf) & 0x0020) | |
32 | #define SYNC_ENABLED(conf) ((conf) & 0x0004) | |
33 | ||
34 | /* Display 1 & 2 Write Timing Configuration */ | |
35 | #define PNX4008_DUM_WT_CFG 0x00372000 | |
36 | ||
37 | /* Display 1 & 2 Read Timing Configuration */ | |
38 | #define PNX4008_DUM_RT_CFG 0x00003A47 | |
39 | ||
40 | /* DUM Transit State Timing Configuration */ | |
41 | #define PNX4008_DUM_T_CFG 0x1D /* 29 HCLK cycles */ | |
42 | ||
43 | /* DUM Sync count clock divider */ | |
44 | #define PNX4008_DUM_CLK_DIV 0x02DD | |
45 | ||
46 | /* Memory size for framebuffer, allocated through dma_alloc_writecombine(). | |
47 | * Must be PAGE aligned | |
48 | */ | |
49 | #define FB_DMA_SIZE (PAGE_ALIGN(SZ_1M + PAGE_SIZE)) | |
50 | ||
51 | #define OFFSET_RGBBUFFER (0xB0000) | |
52 | #define OFFSET_YUVBUFFER (0x00000) | |
53 | ||
54 | #define YUVBUFFER (lcd_video_start + OFFSET_YUVBUFFER) | |
55 | #define RGBBUFFER (lcd_video_start + OFFSET_RGBBUFFER) | |
56 | ||
57 | #define CMDSTRING_BASEADDR (0x00C000) /* iram */ | |
58 | #define BYTES_PER_CMDSTRING (0x80) | |
59 | #define NR_OF_CMDSTRINGS (64) | |
60 | ||
61 | #define MAX_NR_PRESTRINGS (0x40) | |
62 | #define MAX_NR_POSTSTRINGS (0x40) | |
63 | ||
64 | /* various mask definitions */ | |
65 | #define DUM_CLK_ENABLE 0x01 | |
66 | #define DUM_CLK_DISABLE 0 | |
67 | #define DUM_DECODE_MASK 0x1FFFFFFF | |
68 | #define DUM_CHANNEL_CFG_MASK 0x01FF | |
69 | #define DUM_CHANNEL_CFG_SYNC_MASK 0xFFFE00FF | |
70 | #define DUM_CHANNEL_CFG_SYNC_MASK_SET 0x0CA00 | |
71 | ||
72 | #define SDUM_RETURNVAL_BASE (0x500) | |
73 | ||
74 | #define CONF_SYNC_OFF (0x602) | |
75 | #define CONF_SYNC_ON (0x603) | |
76 | ||
77 | #define CONF_DIRTYDETECTION_OFF (0x600) | |
78 | #define CONF_DIRTYDETECTION_ON (0x601) | |
79 | ||
36c9366e VW |
80 | struct dumchannel_uf { |
81 | int channelnr; | |
82 | u32 *dirty; | |
83 | u32 *source; | |
84 | u32 x_offset; | |
85 | u32 y_offset; | |
86 | u32 width; | |
87 | u32 height; | |
88 | }; | |
89 | ||
90 | enum { | |
91 | FB_TYPE_YUV, | |
92 | FB_TYPE_RGB | |
93 | }; | |
94 | ||
95 | struct cmdstring { | |
96 | int channelnr; | |
97 | uint16_t prestringlen; | |
98 | uint16_t poststringlen; | |
99 | uint16_t format; | |
100 | uint16_t reserved; | |
101 | uint16_t startaddr_low; | |
102 | uint16_t startaddr_high; | |
103 | uint16_t pixdatlen_low; | |
104 | uint16_t pixdatlen_high; | |
105 | u32 precmd[MAX_NR_PRESTRINGS]; | |
106 | u32 postcmd[MAX_NR_POSTSTRINGS]; | |
107 | ||
108 | }; | |
109 | ||
110 | struct dumchannel { | |
111 | int channelnr; | |
112 | int dum_ch_min; | |
113 | int dum_ch_max; | |
114 | int dum_ch_conf; | |
115 | int dum_ch_stat; | |
116 | int dum_ch_ctrl; | |
117 | }; | |
118 | ||
119 | int pnx4008_alloc_dum_channel(int dev_id); | |
120 | int pnx4008_free_dum_channel(int channr, int dev_id); | |
121 | ||
122 | int pnx4008_get_dum_channel_uf(struct dumchannel_uf *pChan_uf, int dev_id); | |
123 | int pnx4008_put_dum_channel_uf(struct dumchannel_uf chan_uf, int dev_id); | |
124 | ||
125 | int pnx4008_set_dum_channel_sync(int channr, int val, int dev_id); | |
126 | int pnx4008_set_dum_channel_dirty_detect(int channr, int val, int dev_id); | |
127 | ||
128 | int pnx4008_force_dum_update_channel(int channr, int dev_id); | |
129 | ||
130 | int pnx4008_get_dum_channel_config(int channr, int dev_id); | |
131 | ||
132 | int pnx4008_sdum_mmap(struct fb_info *info, struct vm_area_struct *vma, struct device *dev); | |
133 | int pnx4008_set_dum_exit_notification(int dev_id); | |
134 | ||
135 | int pnx4008_get_fb_addresses(int fb_type, void **virt_addr, | |
136 | dma_addr_t * phys_addr, int *fb_length); |