Merge remote-tracking branches 'regulator/topic/tps65218', 'regulator/topic/tps6524x...
[linux-2.6-block.git] / drivers / video / omap2 / dss / sdi.c
CommitLineData
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1/*
2 * linux/drivers/video/omap2/dss/sdi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "SDI"
21
22#include <linux/kernel.h>
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23#include <linux/delay.h>
24#include <linux/err.h>
508886cf 25#include <linux/regulator/consumer.h>
a8a35931 26#include <linux/export.h>
a57dd4fe 27#include <linux/platform_device.h>
13b1ba7d 28#include <linux/string.h>
23c0a7a6 29
a0b38cc4 30#include <video/omapdss.h>
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31#include "dss.h"
32
33static struct {
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34 struct platform_device *pdev;
35
23c0a7a6 36 bool update_enabled;
508886cf 37 struct regulator *vdds_sdi_reg;
23c0a7a6 38
37a57990 39 struct dss_lcd_mgr_config mgr_config;
9b4a5716 40 struct omap_video_timings timings;
889b4fd7 41 int datapairs;
81b87f51 42
1f68d9c4 43 struct omap_dss_device output;
37a57990 44} sdi;
64ba4f74 45
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46struct sdi_clk_calc_ctx {
47 unsigned long pck_min, pck_max;
48
c56812fc 49 unsigned long fck;
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50 struct dispc_clock_info dispc_cinfo;
51};
52
53static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
54 unsigned long pck, void *data)
55{
56 struct sdi_clk_calc_ctx *ctx = data;
57
58 ctx->dispc_cinfo.lck_div = lckd;
59 ctx->dispc_cinfo.pck_div = pckd;
60 ctx->dispc_cinfo.lck = lck;
61 ctx->dispc_cinfo.pck = pck;
62
63 return true;
64}
65
d0f58bd3 66static bool dpi_calc_dss_cb(unsigned long fck, void *data)
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67{
68 struct sdi_clk_calc_ctx *ctx = data;
69
d0f58bd3 70 ctx->fck = fck;
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71
72 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
73 dpi_calc_dispc_cb, ctx);
74}
75
76static int sdi_calc_clock_div(unsigned long pclk,
d0f58bd3 77 unsigned long *fck,
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78 struct dispc_clock_info *dispc_cinfo)
79{
80 int i;
81 struct sdi_clk_calc_ctx ctx;
82
83 /*
84 * DSS fclk gives us very few possibilities, so finding a good pixel
85 * clock may not be possible. We try multiple times to find the clock,
86 * each time widening the pixel clock range we look for, up to
87 * +/- 1MHz.
88 */
89
90 for (i = 0; i < 10; ++i) {
91 bool ok;
92
93 memset(&ctx, 0, sizeof(ctx));
94 if (pclk > 1000 * i * i * i)
95 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
96 else
97 ctx.pck_min = 0;
98 ctx.pck_max = pclk + 1000 * i * i * i;
99
688af02d 100 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx);
36816faa 101 if (ok) {
d0f58bd3 102 *fck = ctx.fck;
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103 *dispc_cinfo = ctx.dispc_cinfo;
104 return 0;
105 }
106 }
107
108 return -EINVAL;
109}
110
37a57990 111static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
23c0a7a6 112{
7ae9a71e 113 struct omap_overlay_manager *mgr = sdi.output.manager;
7d6069e5 114
37a57990 115 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
64ba4f74 116
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117 sdi.mgr_config.stallmode = false;
118 sdi.mgr_config.fifohandcheck = false;
119
120 sdi.mgr_config.video_port_width = 24;
121 sdi.mgr_config.lcden_sig_polarity = 1;
122
7d6069e5 123 dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
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124}
125
cd6e915b 126static int sdi_display_enable(struct omap_dss_device *dssdev)
23c0a7a6 127{
1f68d9c4 128 struct omap_dss_device *out = &sdi.output;
9b4a5716 129 struct omap_video_timings *t = &sdi.timings;
d0f58bd3 130 unsigned long fck;
23c0a7a6 131 struct dispc_clock_info dispc_cinfo;
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132 unsigned long pck;
133 int r;
134
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135 if (out == NULL || out->manager == NULL) {
136 DSSERR("failed to enable display: no output/manager\n");
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137 return -ENODEV;
138 }
139
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140 r = regulator_enable(sdi.vdds_sdi_reg);
141 if (r)
4fbafaf3 142 goto err_reg_enable;
508886cf 143
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144 r = dispc_runtime_get();
145 if (r)
146 goto err_get_dispc;
23c0a7a6 147
23c0a7a6 148 /* 15.5.9.1.2 */
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149 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
150 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
a8d5e41c 151
d0f58bd3 152 r = sdi_calc_clock_div(t->pixel_clock * 1000, &fck, &dispc_cinfo);
23c0a7a6 153 if (r)
4fbafaf3 154 goto err_calc_clock_div;
23c0a7a6 155
37a57990 156 sdi.mgr_config.clock_info = dispc_cinfo;
23c0a7a6 157
d0f58bd3 158 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
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159
160 if (pck != t->pixel_clock) {
161 DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
162 "got %lu kHz\n",
163 t->pixel_clock, pck);
164
165 t->pixel_clock = pck;
166 }
167
168
7d6069e5 169 dss_mgr_set_timings(out->manager, t);
23c0a7a6 170
d0f58bd3 171 r = dss_set_fck_rate(fck);
23c0a7a6 172 if (r)
4fbafaf3 173 goto err_set_dss_clock_div;
23c0a7a6 174
37a57990 175 sdi_config_lcd_manager(dssdev);
23c0a7a6 176
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177 /*
178 * LCLK and PCLK divisors are located in shadow registers, and we
179 * normally write them to DISPC registers when enabling the output.
180 * However, SDI uses pck-free as source clock for its PLL, and pck-free
181 * is affected by the divisors. And as we need the PLL before enabling
182 * the output, we need to write the divisors early.
183 *
184 * It seems just writing to the DISPC register is enough, and we don't
185 * need to care about the shadow register mechanism for pck-free. The
186 * exact reason for this is unknown.
187 */
7d6069e5 188 dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
889b4fd7 189
66591457 190 dss_sdi_init(sdi.datapairs);
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191 r = dss_sdi_enable();
192 if (r)
4fbafaf3 193 goto err_sdi_enable;
42c9dee8 194 mdelay(2);
23c0a7a6 195
7d6069e5 196 r = dss_mgr_enable(out->manager);
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197 if (r)
198 goto err_mgr_enable;
23c0a7a6 199
23c0a7a6 200 return 0;
4fbafaf3 201
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202err_mgr_enable:
203 dss_sdi_disable();
4fbafaf3 204err_sdi_enable:
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205err_set_dss_clock_div:
206err_calc_clock_div:
207 dispc_runtime_put();
208err_get_dispc:
508886cf 209 regulator_disable(sdi.vdds_sdi_reg);
4fbafaf3 210err_reg_enable:
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211 return r;
212}
213
cd6e915b 214static void sdi_display_disable(struct omap_dss_device *dssdev)
23c0a7a6 215{
7ae9a71e 216 struct omap_overlay_manager *mgr = sdi.output.manager;
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217
218 dss_mgr_disable(mgr);
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219
220 dss_sdi_disable();
221
4fbafaf3 222 dispc_runtime_put();
23c0a7a6 223
508886cf 224 regulator_disable(sdi.vdds_sdi_reg);
23c0a7a6 225}
23c0a7a6 226
cd6e915b 227static void sdi_set_timings(struct omap_dss_device *dssdev,
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228 struct omap_video_timings *timings)
229{
9b4a5716 230 sdi.timings = *timings;
c7833f7b 231}
c7833f7b 232
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233static void sdi_get_timings(struct omap_dss_device *dssdev,
234 struct omap_video_timings *timings)
235{
236 *timings = sdi.timings;
237}
238
239static int sdi_check_timings(struct omap_dss_device *dssdev,
240 struct omap_video_timings *timings)
241{
242 struct omap_overlay_manager *mgr = sdi.output.manager;
243
244 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
245 return -EINVAL;
246
247 if (timings->pixel_clock == 0)
248 return -EINVAL;
249
250 return 0;
251}
252
cd6e915b 253static void sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
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AT
254{
255 sdi.datapairs = datapairs;
256}
889b4fd7 257
d37801b3 258static int sdi_init_regulator(void)
23c0a7a6 259{
d37801b3 260 struct regulator *vdds_sdi;
23c0a7a6 261
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262 if (sdi.vdds_sdi_reg)
263 return 0;
5f42f2ce 264
349c3d95 265 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
d37801b3 266 if (IS_ERR(vdds_sdi)) {
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267 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
268 DSSERR("can't get VDDS_SDI regulator\n");
349c3d95 269 return PTR_ERR(vdds_sdi);
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270 }
271
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272 sdi.vdds_sdi_reg = vdds_sdi;
273
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274 return 0;
275}
276
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277static int sdi_connect(struct omap_dss_device *dssdev,
278 struct omap_dss_device *dst)
279{
280 struct omap_overlay_manager *mgr;
281 int r;
282
283 r = sdi_init_regulator();
284 if (r)
285 return r;
286
287 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
288 if (!mgr)
289 return -ENODEV;
290
291 r = dss_mgr_connect(mgr, dssdev);
292 if (r)
293 return r;
294
295 r = omapdss_output_set_device(dssdev, dst);
296 if (r) {
297 DSSERR("failed to connect output to new device: %s\n",
298 dst->name);
299 dss_mgr_disconnect(mgr, dssdev);
300 return r;
301 }
302
303 return 0;
304}
305
306static void sdi_disconnect(struct omap_dss_device *dssdev,
307 struct omap_dss_device *dst)
308{
9560dc10 309 WARN_ON(dst != dssdev->dst);
b1082dfd 310
9560dc10 311 if (dst != dssdev->dst)
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312 return;
313
314 omapdss_output_unset_device(dssdev);
315
316 if (dssdev->manager)
317 dss_mgr_disconnect(dssdev->manager, dssdev);
318}
319
320static const struct omapdss_sdi_ops sdi_ops = {
321 .connect = sdi_connect,
322 .disconnect = sdi_disconnect,
323
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324 .enable = sdi_display_enable,
325 .disable = sdi_display_disable,
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326
327 .check_timings = sdi_check_timings,
cd6e915b 328 .set_timings = sdi_set_timings,
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329 .get_timings = sdi_get_timings,
330
cd6e915b 331 .set_datapairs = sdi_set_datapairs,
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332};
333
d23b3357 334static void sdi_init_output(struct platform_device *pdev)
81b87f51 335{
1f68d9c4 336 struct omap_dss_device *out = &sdi.output;
81b87f51 337
1f68d9c4 338 out->dev = &pdev->dev;
81b87f51 339 out->id = OMAP_DSS_OUTPUT_SDI;
1f68d9c4 340 out->output_type = OMAP_DISPLAY_TYPE_SDI;
7286a08f 341 out->name = "sdi.0";
2eea5ae6 342 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
b1082dfd 343 out->ops.sdi = &sdi_ops;
b7328e14 344 out->owner = THIS_MODULE;
81b87f51 345
5d47dbc8 346 omapdss_register_output(out);
81b87f51
AT
347}
348
349static void __exit sdi_uninit_output(struct platform_device *pdev)
350{
1f68d9c4 351 struct omap_dss_device *out = &sdi.output;
81b87f51 352
5d47dbc8 353 omapdss_unregister_output(out);
81b87f51
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354}
355
d23b3357 356static int omap_sdi_probe(struct platform_device *pdev)
38f3daf6 357{
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358 sdi.pdev = pdev;
359
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360 sdi_init_output(pdev);
361
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362 return 0;
363}
364
6e7e8f06 365static int __exit omap_sdi_remove(struct platform_device *pdev)
23c0a7a6 366{
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367 sdi_uninit_output(pdev);
368
a57dd4fe
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369 return 0;
370}
371
372static struct platform_driver omap_sdi_driver = {
d23b3357 373 .probe = omap_sdi_probe,
6e7e8f06 374 .remove = __exit_p(omap_sdi_remove),
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375 .driver = {
376 .name = "omapdss_sdi",
377 .owner = THIS_MODULE,
378 },
379};
380
6e7e8f06 381int __init sdi_init_platform_driver(void)
a57dd4fe 382{
d23b3357 383 return platform_driver_register(&omap_sdi_driver);
a57dd4fe
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384}
385
6e7e8f06 386void __exit sdi_uninit_platform_driver(void)
a57dd4fe
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387{
388 platform_driver_unregister(&omap_sdi_driver);
23c0a7a6 389}