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5c18adb3 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/rfbi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "RFBI" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/kfifo.h> | |
32 | #include <linux/ktime.h> | |
33 | #include <linux/hrtimer.h> | |
34 | #include <linux/seq_file.h> | |
35 | ||
36 | #include <plat/display.h> | |
37 | #include "dss.h" | |
38 | ||
39 | /*#define MEASURE_PERF*/ | |
40 | ||
41 | #define RFBI_BASE 0x48050800 | |
42 | ||
43 | struct rfbi_reg { u16 idx; }; | |
44 | ||
45 | #define RFBI_REG(idx) ((const struct rfbi_reg) { idx }) | |
46 | ||
47 | #define RFBI_REVISION RFBI_REG(0x0000) | |
48 | #define RFBI_SYSCONFIG RFBI_REG(0x0010) | |
49 | #define RFBI_SYSSTATUS RFBI_REG(0x0014) | |
50 | #define RFBI_CONTROL RFBI_REG(0x0040) | |
51 | #define RFBI_PIXEL_CNT RFBI_REG(0x0044) | |
52 | #define RFBI_LINE_NUMBER RFBI_REG(0x0048) | |
53 | #define RFBI_CMD RFBI_REG(0x004c) | |
54 | #define RFBI_PARAM RFBI_REG(0x0050) | |
55 | #define RFBI_DATA RFBI_REG(0x0054) | |
56 | #define RFBI_READ RFBI_REG(0x0058) | |
57 | #define RFBI_STATUS RFBI_REG(0x005c) | |
58 | ||
59 | #define RFBI_CONFIG(n) RFBI_REG(0x0060 + (n)*0x18) | |
60 | #define RFBI_ONOFF_TIME(n) RFBI_REG(0x0064 + (n)*0x18) | |
61 | #define RFBI_CYCLE_TIME(n) RFBI_REG(0x0068 + (n)*0x18) | |
62 | #define RFBI_DATA_CYCLE1(n) RFBI_REG(0x006c + (n)*0x18) | |
63 | #define RFBI_DATA_CYCLE2(n) RFBI_REG(0x0070 + (n)*0x18) | |
64 | #define RFBI_DATA_CYCLE3(n) RFBI_REG(0x0074 + (n)*0x18) | |
65 | ||
66 | #define RFBI_VSYNC_WIDTH RFBI_REG(0x0090) | |
67 | #define RFBI_HSYNC_WIDTH RFBI_REG(0x0094) | |
68 | ||
69 | #define RFBI_CMD_FIFO_LEN_BYTES (16 * sizeof(struct update_param)) | |
70 | ||
71 | #define REG_FLD_MOD(idx, val, start, end) \ | |
72 | rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end)) | |
73 | ||
74 | /* To work around an RFBI transfer rate limitation */ | |
75 | #define OMAP_RFBI_RATE_LIMIT 1 | |
76 | ||
77 | enum omap_rfbi_cycleformat { | |
78 | OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0, | |
79 | OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1, | |
80 | OMAP_DSS_RFBI_CYCLEFORMAT_3_1 = 2, | |
81 | OMAP_DSS_RFBI_CYCLEFORMAT_3_2 = 3, | |
82 | }; | |
83 | ||
84 | enum omap_rfbi_datatype { | |
85 | OMAP_DSS_RFBI_DATATYPE_12 = 0, | |
86 | OMAP_DSS_RFBI_DATATYPE_16 = 1, | |
87 | OMAP_DSS_RFBI_DATATYPE_18 = 2, | |
88 | OMAP_DSS_RFBI_DATATYPE_24 = 3, | |
89 | }; | |
90 | ||
91 | enum omap_rfbi_parallelmode { | |
92 | OMAP_DSS_RFBI_PARALLELMODE_8 = 0, | |
93 | OMAP_DSS_RFBI_PARALLELMODE_9 = 1, | |
94 | OMAP_DSS_RFBI_PARALLELMODE_12 = 2, | |
95 | OMAP_DSS_RFBI_PARALLELMODE_16 = 3, | |
96 | }; | |
97 | ||
98 | enum update_cmd { | |
99 | RFBI_CMD_UPDATE = 0, | |
100 | RFBI_CMD_SYNC = 1, | |
101 | }; | |
102 | ||
103 | static int rfbi_convert_timings(struct rfbi_timings *t); | |
104 | static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div); | |
105 | static void process_cmd_fifo(void); | |
106 | ||
107 | static struct { | |
108 | void __iomem *base; | |
109 | ||
110 | unsigned long l4_khz; | |
111 | ||
112 | enum omap_rfbi_datatype datatype; | |
113 | enum omap_rfbi_parallelmode parallelmode; | |
114 | ||
115 | enum omap_rfbi_te_mode te_mode; | |
116 | int te_enabled; | |
117 | ||
118 | void (*framedone_callback)(void *data); | |
119 | void *framedone_callback_data; | |
120 | ||
121 | struct omap_dss_device *dssdev[2]; | |
122 | ||
fc248a49 | 123 | struct kfifo cmd_fifo; |
5c18adb3 TV |
124 | spinlock_t cmd_lock; |
125 | struct completion cmd_done; | |
126 | atomic_t cmd_fifo_full; | |
127 | atomic_t cmd_pending; | |
128 | #ifdef MEASURE_PERF | |
129 | unsigned perf_bytes; | |
130 | ktime_t perf_setup_time; | |
131 | ktime_t perf_start_time; | |
132 | #endif | |
133 | } rfbi; | |
134 | ||
135 | struct update_region { | |
136 | u16 x; | |
137 | u16 y; | |
138 | u16 w; | |
139 | u16 h; | |
140 | }; | |
141 | ||
142 | struct update_param { | |
143 | u8 rfbi_module; | |
144 | u8 cmd; | |
145 | ||
146 | union { | |
147 | struct update_region r; | |
148 | struct completion *sync; | |
149 | } par; | |
150 | }; | |
151 | ||
152 | static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val) | |
153 | { | |
154 | __raw_writel(val, rfbi.base + idx.idx); | |
155 | } | |
156 | ||
157 | static inline u32 rfbi_read_reg(const struct rfbi_reg idx) | |
158 | { | |
159 | return __raw_readl(rfbi.base + idx.idx); | |
160 | } | |
161 | ||
162 | static void rfbi_enable_clocks(bool enable) | |
163 | { | |
164 | if (enable) | |
165 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); | |
166 | else | |
167 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); | |
168 | } | |
169 | ||
170 | void omap_rfbi_write_command(const void *buf, u32 len) | |
171 | { | |
172 | rfbi_enable_clocks(1); | |
173 | switch (rfbi.parallelmode) { | |
174 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
175 | { | |
176 | const u8 *b = buf; | |
177 | for (; len; len--) | |
178 | rfbi_write_reg(RFBI_CMD, *b++); | |
179 | break; | |
180 | } | |
181 | ||
182 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
183 | { | |
184 | const u16 *w = buf; | |
185 | BUG_ON(len & 1); | |
186 | for (; len; len -= 2) | |
187 | rfbi_write_reg(RFBI_CMD, *w++); | |
188 | break; | |
189 | } | |
190 | ||
191 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
192 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
193 | default: | |
194 | BUG(); | |
195 | } | |
196 | rfbi_enable_clocks(0); | |
197 | } | |
198 | EXPORT_SYMBOL(omap_rfbi_write_command); | |
199 | ||
200 | void omap_rfbi_read_data(void *buf, u32 len) | |
201 | { | |
202 | rfbi_enable_clocks(1); | |
203 | switch (rfbi.parallelmode) { | |
204 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
205 | { | |
206 | u8 *b = buf; | |
207 | for (; len; len--) { | |
208 | rfbi_write_reg(RFBI_READ, 0); | |
209 | *b++ = rfbi_read_reg(RFBI_READ); | |
210 | } | |
211 | break; | |
212 | } | |
213 | ||
214 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
215 | { | |
216 | u16 *w = buf; | |
217 | BUG_ON(len & ~1); | |
218 | for (; len; len -= 2) { | |
219 | rfbi_write_reg(RFBI_READ, 0); | |
220 | *w++ = rfbi_read_reg(RFBI_READ); | |
221 | } | |
222 | break; | |
223 | } | |
224 | ||
225 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
226 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
227 | default: | |
228 | BUG(); | |
229 | } | |
230 | rfbi_enable_clocks(0); | |
231 | } | |
232 | EXPORT_SYMBOL(omap_rfbi_read_data); | |
233 | ||
234 | void omap_rfbi_write_data(const void *buf, u32 len) | |
235 | { | |
236 | rfbi_enable_clocks(1); | |
237 | switch (rfbi.parallelmode) { | |
238 | case OMAP_DSS_RFBI_PARALLELMODE_8: | |
239 | { | |
240 | const u8 *b = buf; | |
241 | for (; len; len--) | |
242 | rfbi_write_reg(RFBI_PARAM, *b++); | |
243 | break; | |
244 | } | |
245 | ||
246 | case OMAP_DSS_RFBI_PARALLELMODE_16: | |
247 | { | |
248 | const u16 *w = buf; | |
249 | BUG_ON(len & 1); | |
250 | for (; len; len -= 2) | |
251 | rfbi_write_reg(RFBI_PARAM, *w++); | |
252 | break; | |
253 | } | |
254 | ||
255 | case OMAP_DSS_RFBI_PARALLELMODE_9: | |
256 | case OMAP_DSS_RFBI_PARALLELMODE_12: | |
257 | default: | |
258 | BUG(); | |
259 | ||
260 | } | |
261 | rfbi_enable_clocks(0); | |
262 | } | |
263 | EXPORT_SYMBOL(omap_rfbi_write_data); | |
264 | ||
265 | void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width, | |
266 | u16 x, u16 y, | |
267 | u16 w, u16 h) | |
268 | { | |
269 | int start_offset = scr_width * y + x; | |
270 | int horiz_offset = scr_width - w; | |
271 | int i; | |
272 | ||
273 | rfbi_enable_clocks(1); | |
274 | ||
275 | if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && | |
276 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { | |
277 | const u16 __iomem *pd = buf; | |
278 | pd += start_offset; | |
279 | ||
280 | for (; h; --h) { | |
281 | for (i = 0; i < w; ++i) { | |
282 | const u8 __iomem *b = (const u8 __iomem *)pd; | |
283 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); | |
284 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); | |
285 | ++pd; | |
286 | } | |
287 | pd += horiz_offset; | |
288 | } | |
289 | } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_24 && | |
290 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) { | |
291 | const u32 __iomem *pd = buf; | |
292 | pd += start_offset; | |
293 | ||
294 | for (; h; --h) { | |
295 | for (i = 0; i < w; ++i) { | |
296 | const u8 __iomem *b = (const u8 __iomem *)pd; | |
297 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+2)); | |
298 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+1)); | |
299 | rfbi_write_reg(RFBI_PARAM, __raw_readb(b+0)); | |
300 | ++pd; | |
301 | } | |
302 | pd += horiz_offset; | |
303 | } | |
304 | } else if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 && | |
305 | rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_16) { | |
306 | const u16 __iomem *pd = buf; | |
307 | pd += start_offset; | |
308 | ||
309 | for (; h; --h) { | |
310 | for (i = 0; i < w; ++i) { | |
311 | rfbi_write_reg(RFBI_PARAM, __raw_readw(pd)); | |
312 | ++pd; | |
313 | } | |
314 | pd += horiz_offset; | |
315 | } | |
316 | } else { | |
317 | BUG(); | |
318 | } | |
319 | ||
320 | rfbi_enable_clocks(0); | |
321 | } | |
322 | EXPORT_SYMBOL(omap_rfbi_write_pixels); | |
323 | ||
324 | #ifdef MEASURE_PERF | |
325 | static void perf_mark_setup(void) | |
326 | { | |
327 | rfbi.perf_setup_time = ktime_get(); | |
328 | } | |
329 | ||
330 | static void perf_mark_start(void) | |
331 | { | |
332 | rfbi.perf_start_time = ktime_get(); | |
333 | } | |
334 | ||
335 | static void perf_show(const char *name) | |
336 | { | |
337 | ktime_t t, setup_time, trans_time; | |
338 | u32 total_bytes; | |
339 | u32 setup_us, trans_us, total_us; | |
340 | ||
341 | t = ktime_get(); | |
342 | ||
343 | setup_time = ktime_sub(rfbi.perf_start_time, rfbi.perf_setup_time); | |
344 | setup_us = (u32)ktime_to_us(setup_time); | |
345 | if (setup_us == 0) | |
346 | setup_us = 1; | |
347 | ||
348 | trans_time = ktime_sub(t, rfbi.perf_start_time); | |
349 | trans_us = (u32)ktime_to_us(trans_time); | |
350 | if (trans_us == 0) | |
351 | trans_us = 1; | |
352 | ||
353 | total_us = setup_us + trans_us; | |
354 | ||
355 | total_bytes = rfbi.perf_bytes; | |
356 | ||
357 | DSSINFO("%s update %u us + %u us = %u us (%uHz), %u bytes, " | |
358 | "%u kbytes/sec\n", | |
359 | name, | |
360 | setup_us, | |
361 | trans_us, | |
362 | total_us, | |
363 | 1000*1000 / total_us, | |
364 | total_bytes, | |
365 | total_bytes * 1000 / total_us); | |
366 | } | |
367 | #else | |
368 | #define perf_mark_setup() | |
369 | #define perf_mark_start() | |
370 | #define perf_show(x) | |
371 | #endif | |
372 | ||
373 | void rfbi_transfer_area(u16 width, u16 height, | |
374 | void (callback)(void *data), void *data) | |
375 | { | |
376 | u32 l; | |
377 | ||
378 | /*BUG_ON(callback == 0);*/ | |
379 | BUG_ON(rfbi.framedone_callback != NULL); | |
380 | ||
381 | DSSDBG("rfbi_transfer_area %dx%d\n", width, height); | |
382 | ||
383 | dispc_set_lcd_size(width, height); | |
384 | ||
385 | dispc_enable_lcd_out(1); | |
386 | ||
387 | rfbi.framedone_callback = callback; | |
388 | rfbi.framedone_callback_data = data; | |
389 | ||
390 | rfbi_enable_clocks(1); | |
391 | ||
392 | rfbi_write_reg(RFBI_PIXEL_CNT, width * height); | |
393 | ||
394 | l = rfbi_read_reg(RFBI_CONTROL); | |
395 | l = FLD_MOD(l, 1, 0, 0); /* enable */ | |
396 | if (!rfbi.te_enabled) | |
397 | l = FLD_MOD(l, 1, 4, 4); /* ITE */ | |
398 | ||
399 | perf_mark_start(); | |
400 | ||
401 | rfbi_write_reg(RFBI_CONTROL, l); | |
402 | } | |
403 | ||
404 | static void framedone_callback(void *data, u32 mask) | |
405 | { | |
406 | void (*callback)(void *data); | |
407 | ||
408 | DSSDBG("FRAMEDONE\n"); | |
409 | ||
410 | perf_show("DISPC"); | |
411 | ||
412 | REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); | |
413 | ||
414 | rfbi_enable_clocks(0); | |
415 | ||
416 | callback = rfbi.framedone_callback; | |
417 | rfbi.framedone_callback = NULL; | |
418 | ||
419 | /*callback(rfbi.framedone_callback_data);*/ | |
420 | ||
421 | atomic_set(&rfbi.cmd_pending, 0); | |
422 | ||
423 | process_cmd_fifo(); | |
424 | } | |
425 | ||
426 | #if 1 /* VERBOSE */ | |
427 | static void rfbi_print_timings(void) | |
428 | { | |
429 | u32 l; | |
430 | u32 time; | |
431 | ||
432 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
433 | time = 1000000000 / rfbi.l4_khz; | |
434 | if (l & (1 << 4)) | |
435 | time *= 2; | |
436 | ||
437 | DSSDBG("Tick time %u ps\n", time); | |
438 | l = rfbi_read_reg(RFBI_ONOFF_TIME(0)); | |
439 | DSSDBG("CSONTIME %d, CSOFFTIME %d, WEONTIME %d, WEOFFTIME %d, " | |
440 | "REONTIME %d, REOFFTIME %d\n", | |
441 | l & 0x0f, (l >> 4) & 0x3f, (l >> 10) & 0x0f, (l >> 14) & 0x3f, | |
442 | (l >> 20) & 0x0f, (l >> 24) & 0x3f); | |
443 | ||
444 | l = rfbi_read_reg(RFBI_CYCLE_TIME(0)); | |
445 | DSSDBG("WECYCLETIME %d, RECYCLETIME %d, CSPULSEWIDTH %d, " | |
446 | "ACCESSTIME %d\n", | |
447 | (l & 0x3f), (l >> 6) & 0x3f, (l >> 12) & 0x3f, | |
448 | (l >> 22) & 0x3f); | |
449 | } | |
450 | #else | |
451 | static void rfbi_print_timings(void) {} | |
452 | #endif | |
453 | ||
454 | ||
455 | ||
456 | ||
457 | static u32 extif_clk_period; | |
458 | ||
459 | static inline unsigned long round_to_extif_ticks(unsigned long ps, int div) | |
460 | { | |
461 | int bus_tick = extif_clk_period * div; | |
462 | return (ps + bus_tick - 1) / bus_tick * bus_tick; | |
463 | } | |
464 | ||
465 | static int calc_reg_timing(struct rfbi_timings *t, int div) | |
466 | { | |
467 | t->clk_div = div; | |
468 | ||
469 | t->cs_on_time = round_to_extif_ticks(t->cs_on_time, div); | |
470 | ||
471 | t->we_on_time = round_to_extif_ticks(t->we_on_time, div); | |
472 | t->we_off_time = round_to_extif_ticks(t->we_off_time, div); | |
473 | t->we_cycle_time = round_to_extif_ticks(t->we_cycle_time, div); | |
474 | ||
475 | t->re_on_time = round_to_extif_ticks(t->re_on_time, div); | |
476 | t->re_off_time = round_to_extif_ticks(t->re_off_time, div); | |
477 | t->re_cycle_time = round_to_extif_ticks(t->re_cycle_time, div); | |
478 | ||
479 | t->access_time = round_to_extif_ticks(t->access_time, div); | |
480 | t->cs_off_time = round_to_extif_ticks(t->cs_off_time, div); | |
481 | t->cs_pulse_width = round_to_extif_ticks(t->cs_pulse_width, div); | |
482 | ||
483 | DSSDBG("[reg]cson %d csoff %d reon %d reoff %d\n", | |
484 | t->cs_on_time, t->cs_off_time, t->re_on_time, t->re_off_time); | |
485 | DSSDBG("[reg]weon %d weoff %d recyc %d wecyc %d\n", | |
486 | t->we_on_time, t->we_off_time, t->re_cycle_time, | |
487 | t->we_cycle_time); | |
488 | DSSDBG("[reg]rdaccess %d cspulse %d\n", | |
489 | t->access_time, t->cs_pulse_width); | |
490 | ||
491 | return rfbi_convert_timings(t); | |
492 | } | |
493 | ||
494 | static int calc_extif_timings(struct rfbi_timings *t) | |
495 | { | |
496 | u32 max_clk_div; | |
497 | int div; | |
498 | ||
499 | rfbi_get_clk_info(&extif_clk_period, &max_clk_div); | |
500 | for (div = 1; div <= max_clk_div; div++) { | |
501 | if (calc_reg_timing(t, div) == 0) | |
502 | break; | |
503 | } | |
504 | ||
505 | if (div <= max_clk_div) | |
506 | return 0; | |
507 | ||
508 | DSSERR("can't setup timings\n"); | |
509 | return -1; | |
510 | } | |
511 | ||
512 | ||
513 | void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t) | |
514 | { | |
515 | int r; | |
516 | ||
517 | if (!t->converted) { | |
518 | r = calc_extif_timings(t); | |
519 | if (r < 0) | |
520 | DSSERR("Failed to calc timings\n"); | |
521 | } | |
522 | ||
523 | BUG_ON(!t->converted); | |
524 | ||
525 | rfbi_enable_clocks(1); | |
526 | rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]); | |
527 | rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]); | |
528 | ||
529 | /* TIMEGRANULARITY */ | |
530 | REG_FLD_MOD(RFBI_CONFIG(rfbi_module), | |
531 | (t->tim[2] ? 1 : 0), 4, 4); | |
532 | ||
533 | rfbi_print_timings(); | |
534 | rfbi_enable_clocks(0); | |
535 | } | |
536 | ||
537 | static int ps_to_rfbi_ticks(int time, int div) | |
538 | { | |
539 | unsigned long tick_ps; | |
540 | int ret; | |
541 | ||
542 | /* Calculate in picosecs to yield more exact results */ | |
543 | tick_ps = 1000000000 / (rfbi.l4_khz) * div; | |
544 | ||
545 | ret = (time + tick_ps - 1) / tick_ps; | |
546 | ||
547 | return ret; | |
548 | } | |
549 | ||
550 | #ifdef OMAP_RFBI_RATE_LIMIT | |
551 | unsigned long rfbi_get_max_tx_rate(void) | |
552 | { | |
553 | unsigned long l4_rate, dss1_rate; | |
554 | int min_l4_ticks = 0; | |
555 | int i; | |
556 | ||
557 | /* According to TI this can't be calculated so make the | |
558 | * adjustments for a couple of known frequencies and warn for | |
559 | * others. | |
560 | */ | |
561 | static const struct { | |
562 | unsigned long l4_clk; /* HZ */ | |
563 | unsigned long dss1_clk; /* HZ */ | |
564 | unsigned long min_l4_ticks; | |
565 | } ftab[] = { | |
566 | { 55, 132, 7, }, /* 7.86 MPix/s */ | |
567 | { 110, 110, 12, }, /* 9.16 MPix/s */ | |
568 | { 110, 132, 10, }, /* 11 Mpix/s */ | |
569 | { 120, 120, 10, }, /* 12 Mpix/s */ | |
570 | { 133, 133, 10, }, /* 13.3 Mpix/s */ | |
571 | }; | |
572 | ||
573 | l4_rate = rfbi.l4_khz / 1000; | |
574 | dss1_rate = dss_clk_get_rate(DSS_CLK_FCK1) / 1000000; | |
575 | ||
576 | for (i = 0; i < ARRAY_SIZE(ftab); i++) { | |
577 | /* Use a window instead of an exact match, to account | |
578 | * for different DPLL multiplier / divider pairs. | |
579 | */ | |
580 | if (abs(ftab[i].l4_clk - l4_rate) < 3 && | |
581 | abs(ftab[i].dss1_clk - dss1_rate) < 3) { | |
582 | min_l4_ticks = ftab[i].min_l4_ticks; | |
583 | break; | |
584 | } | |
585 | } | |
586 | if (i == ARRAY_SIZE(ftab)) { | |
587 | /* Can't be sure, return anyway the maximum not | |
588 | * rate-limited. This might cause a problem only for the | |
589 | * tearing synchronisation. | |
590 | */ | |
591 | DSSERR("can't determine maximum RFBI transfer rate\n"); | |
592 | return rfbi.l4_khz * 1000; | |
593 | } | |
594 | return rfbi.l4_khz * 1000 / min_l4_ticks; | |
595 | } | |
596 | #else | |
597 | int rfbi_get_max_tx_rate(void) | |
598 | { | |
599 | return rfbi.l4_khz * 1000; | |
600 | } | |
601 | #endif | |
602 | ||
603 | static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div) | |
604 | { | |
605 | *clk_period = 1000000000 / rfbi.l4_khz; | |
606 | *max_clk_div = 2; | |
607 | } | |
608 | ||
609 | static int rfbi_convert_timings(struct rfbi_timings *t) | |
610 | { | |
611 | u32 l; | |
612 | int reon, reoff, weon, weoff, cson, csoff, cs_pulse; | |
613 | int actim, recyc, wecyc; | |
614 | int div = t->clk_div; | |
615 | ||
616 | if (div <= 0 || div > 2) | |
617 | return -1; | |
618 | ||
619 | /* Make sure that after conversion it still holds that: | |
620 | * weoff > weon, reoff > reon, recyc >= reoff, wecyc >= weoff, | |
621 | * csoff > cson, csoff >= max(weoff, reoff), actim > reon | |
622 | */ | |
623 | weon = ps_to_rfbi_ticks(t->we_on_time, div); | |
624 | weoff = ps_to_rfbi_ticks(t->we_off_time, div); | |
625 | if (weoff <= weon) | |
626 | weoff = weon + 1; | |
627 | if (weon > 0x0f) | |
628 | return -1; | |
629 | if (weoff > 0x3f) | |
630 | return -1; | |
631 | ||
632 | reon = ps_to_rfbi_ticks(t->re_on_time, div); | |
633 | reoff = ps_to_rfbi_ticks(t->re_off_time, div); | |
634 | if (reoff <= reon) | |
635 | reoff = reon + 1; | |
636 | if (reon > 0x0f) | |
637 | return -1; | |
638 | if (reoff > 0x3f) | |
639 | return -1; | |
640 | ||
641 | cson = ps_to_rfbi_ticks(t->cs_on_time, div); | |
642 | csoff = ps_to_rfbi_ticks(t->cs_off_time, div); | |
643 | if (csoff <= cson) | |
644 | csoff = cson + 1; | |
645 | if (csoff < max(weoff, reoff)) | |
646 | csoff = max(weoff, reoff); | |
647 | if (cson > 0x0f) | |
648 | return -1; | |
649 | if (csoff > 0x3f) | |
650 | return -1; | |
651 | ||
652 | l = cson; | |
653 | l |= csoff << 4; | |
654 | l |= weon << 10; | |
655 | l |= weoff << 14; | |
656 | l |= reon << 20; | |
657 | l |= reoff << 24; | |
658 | ||
659 | t->tim[0] = l; | |
660 | ||
661 | actim = ps_to_rfbi_ticks(t->access_time, div); | |
662 | if (actim <= reon) | |
663 | actim = reon + 1; | |
664 | if (actim > 0x3f) | |
665 | return -1; | |
666 | ||
667 | wecyc = ps_to_rfbi_ticks(t->we_cycle_time, div); | |
668 | if (wecyc < weoff) | |
669 | wecyc = weoff; | |
670 | if (wecyc > 0x3f) | |
671 | return -1; | |
672 | ||
673 | recyc = ps_to_rfbi_ticks(t->re_cycle_time, div); | |
674 | if (recyc < reoff) | |
675 | recyc = reoff; | |
676 | if (recyc > 0x3f) | |
677 | return -1; | |
678 | ||
679 | cs_pulse = ps_to_rfbi_ticks(t->cs_pulse_width, div); | |
680 | if (cs_pulse > 0x3f) | |
681 | return -1; | |
682 | ||
683 | l = wecyc; | |
684 | l |= recyc << 6; | |
685 | l |= cs_pulse << 12; | |
686 | l |= actim << 22; | |
687 | ||
688 | t->tim[1] = l; | |
689 | ||
690 | t->tim[2] = div - 1; | |
691 | ||
692 | t->converted = 1; | |
693 | ||
694 | return 0; | |
695 | } | |
696 | ||
697 | /* xxx FIX module selection missing */ | |
698 | int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode, | |
699 | unsigned hs_pulse_time, unsigned vs_pulse_time, | |
700 | int hs_pol_inv, int vs_pol_inv, int extif_div) | |
701 | { | |
702 | int hs, vs; | |
703 | int min; | |
704 | u32 l; | |
705 | ||
706 | hs = ps_to_rfbi_ticks(hs_pulse_time, 1); | |
707 | vs = ps_to_rfbi_ticks(vs_pulse_time, 1); | |
708 | if (hs < 2) | |
709 | return -EDOM; | |
710 | if (mode == OMAP_DSS_RFBI_TE_MODE_2) | |
711 | min = 2; | |
712 | else /* OMAP_DSS_RFBI_TE_MODE_1 */ | |
713 | min = 4; | |
714 | if (vs < min) | |
715 | return -EDOM; | |
716 | if (vs == hs) | |
717 | return -EINVAL; | |
718 | rfbi.te_mode = mode; | |
719 | DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n", | |
720 | mode, hs, vs, hs_pol_inv, vs_pol_inv); | |
721 | ||
722 | rfbi_enable_clocks(1); | |
723 | rfbi_write_reg(RFBI_HSYNC_WIDTH, hs); | |
724 | rfbi_write_reg(RFBI_VSYNC_WIDTH, vs); | |
725 | ||
726 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
727 | if (hs_pol_inv) | |
728 | l &= ~(1 << 21); | |
729 | else | |
730 | l |= 1 << 21; | |
731 | if (vs_pol_inv) | |
732 | l &= ~(1 << 20); | |
733 | else | |
734 | l |= 1 << 20; | |
735 | rfbi_enable_clocks(0); | |
736 | ||
737 | return 0; | |
738 | } | |
739 | EXPORT_SYMBOL(omap_rfbi_setup_te); | |
740 | ||
741 | /* xxx FIX module selection missing */ | |
742 | int omap_rfbi_enable_te(bool enable, unsigned line) | |
743 | { | |
744 | u32 l; | |
745 | ||
746 | DSSDBG("te %d line %d mode %d\n", enable, line, rfbi.te_mode); | |
747 | if (line > (1 << 11) - 1) | |
748 | return -EINVAL; | |
749 | ||
750 | rfbi_enable_clocks(1); | |
751 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
752 | l &= ~(0x3 << 2); | |
753 | if (enable) { | |
754 | rfbi.te_enabled = 1; | |
755 | l |= rfbi.te_mode << 2; | |
756 | } else | |
757 | rfbi.te_enabled = 0; | |
758 | rfbi_write_reg(RFBI_CONFIG(0), l); | |
759 | rfbi_write_reg(RFBI_LINE_NUMBER, line); | |
760 | rfbi_enable_clocks(0); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | EXPORT_SYMBOL(omap_rfbi_enable_te); | |
765 | ||
766 | #if 0 | |
767 | static void rfbi_enable_config(int enable1, int enable2) | |
768 | { | |
769 | u32 l; | |
770 | int cs = 0; | |
771 | ||
772 | if (enable1) | |
773 | cs |= 1<<0; | |
774 | if (enable2) | |
775 | cs |= 1<<1; | |
776 | ||
777 | rfbi_enable_clocks(1); | |
778 | ||
779 | l = rfbi_read_reg(RFBI_CONTROL); | |
780 | ||
781 | l = FLD_MOD(l, cs, 3, 2); | |
782 | l = FLD_MOD(l, 0, 1, 1); | |
783 | ||
784 | rfbi_write_reg(RFBI_CONTROL, l); | |
785 | ||
786 | ||
787 | l = rfbi_read_reg(RFBI_CONFIG(0)); | |
788 | l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */ | |
789 | /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ | |
790 | /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */ | |
791 | ||
792 | l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */ | |
793 | l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */ | |
794 | l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */ | |
795 | ||
796 | l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0); | |
797 | rfbi_write_reg(RFBI_CONFIG(0), l); | |
798 | ||
799 | rfbi_enable_clocks(0); | |
800 | } | |
801 | #endif | |
802 | ||
803 | int rfbi_configure(int rfbi_module, int bpp, int lines) | |
804 | { | |
805 | u32 l; | |
806 | int cycle1 = 0, cycle2 = 0, cycle3 = 0; | |
807 | enum omap_rfbi_cycleformat cycleformat; | |
808 | enum omap_rfbi_datatype datatype; | |
809 | enum omap_rfbi_parallelmode parallelmode; | |
810 | ||
811 | switch (bpp) { | |
812 | case 12: | |
813 | datatype = OMAP_DSS_RFBI_DATATYPE_12; | |
814 | break; | |
815 | case 16: | |
816 | datatype = OMAP_DSS_RFBI_DATATYPE_16; | |
817 | break; | |
818 | case 18: | |
819 | datatype = OMAP_DSS_RFBI_DATATYPE_18; | |
820 | break; | |
821 | case 24: | |
822 | datatype = OMAP_DSS_RFBI_DATATYPE_24; | |
823 | break; | |
824 | default: | |
825 | BUG(); | |
826 | return 1; | |
827 | } | |
828 | rfbi.datatype = datatype; | |
829 | ||
830 | switch (lines) { | |
831 | case 8: | |
832 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_8; | |
833 | break; | |
834 | case 9: | |
835 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_9; | |
836 | break; | |
837 | case 12: | |
838 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_12; | |
839 | break; | |
840 | case 16: | |
841 | parallelmode = OMAP_DSS_RFBI_PARALLELMODE_16; | |
842 | break; | |
843 | default: | |
844 | BUG(); | |
845 | return 1; | |
846 | } | |
847 | rfbi.parallelmode = parallelmode; | |
848 | ||
849 | if ((bpp % lines) == 0) { | |
850 | switch (bpp / lines) { | |
851 | case 1: | |
852 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_1_1; | |
853 | break; | |
854 | case 2: | |
855 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_2_1; | |
856 | break; | |
857 | case 3: | |
858 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_1; | |
859 | break; | |
860 | default: | |
861 | BUG(); | |
862 | return 1; | |
863 | } | |
864 | } else if ((2 * bpp % lines) == 0) { | |
865 | if ((2 * bpp / lines) == 3) | |
866 | cycleformat = OMAP_DSS_RFBI_CYCLEFORMAT_3_2; | |
867 | else { | |
868 | BUG(); | |
869 | return 1; | |
870 | } | |
871 | } else { | |
872 | BUG(); | |
873 | return 1; | |
874 | } | |
875 | ||
876 | switch (cycleformat) { | |
877 | case OMAP_DSS_RFBI_CYCLEFORMAT_1_1: | |
878 | cycle1 = lines; | |
879 | break; | |
880 | ||
881 | case OMAP_DSS_RFBI_CYCLEFORMAT_2_1: | |
882 | cycle1 = lines; | |
883 | cycle2 = lines; | |
884 | break; | |
885 | ||
886 | case OMAP_DSS_RFBI_CYCLEFORMAT_3_1: | |
887 | cycle1 = lines; | |
888 | cycle2 = lines; | |
889 | cycle3 = lines; | |
890 | break; | |
891 | ||
892 | case OMAP_DSS_RFBI_CYCLEFORMAT_3_2: | |
893 | cycle1 = lines; | |
894 | cycle2 = (lines / 2) | ((lines / 2) << 16); | |
895 | cycle3 = (lines << 16); | |
896 | break; | |
897 | } | |
898 | ||
899 | rfbi_enable_clocks(1); | |
900 | ||
901 | REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ | |
902 | ||
903 | l = 0; | |
904 | l |= FLD_VAL(parallelmode, 1, 0); | |
905 | l |= FLD_VAL(0, 3, 2); /* TRIGGERMODE: ITE */ | |
906 | l |= FLD_VAL(0, 4, 4); /* TIMEGRANULARITY */ | |
907 | l |= FLD_VAL(datatype, 6, 5); | |
908 | /* l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */ | |
909 | l |= FLD_VAL(0, 8, 7); /* L4FORMAT, 1pix/L4 */ | |
910 | l |= FLD_VAL(cycleformat, 10, 9); | |
911 | l |= FLD_VAL(0, 12, 11); /* UNUSEDBITS */ | |
912 | l |= FLD_VAL(0, 16, 16); /* A0POLARITY */ | |
913 | l |= FLD_VAL(0, 17, 17); /* REPOLARITY */ | |
914 | l |= FLD_VAL(0, 18, 18); /* WEPOLARITY */ | |
915 | l |= FLD_VAL(0, 19, 19); /* CSPOLARITY */ | |
916 | l |= FLD_VAL(1, 20, 20); /* TE_VSYNC_POLARITY */ | |
917 | l |= FLD_VAL(1, 21, 21); /* HSYNCPOLARITY */ | |
918 | rfbi_write_reg(RFBI_CONFIG(rfbi_module), l); | |
919 | ||
920 | rfbi_write_reg(RFBI_DATA_CYCLE1(rfbi_module), cycle1); | |
921 | rfbi_write_reg(RFBI_DATA_CYCLE2(rfbi_module), cycle2); | |
922 | rfbi_write_reg(RFBI_DATA_CYCLE3(rfbi_module), cycle3); | |
923 | ||
924 | ||
925 | l = rfbi_read_reg(RFBI_CONTROL); | |
926 | l = FLD_MOD(l, rfbi_module+1, 3, 2); /* Select CSx */ | |
927 | l = FLD_MOD(l, 0, 1, 1); /* clear bypass */ | |
928 | rfbi_write_reg(RFBI_CONTROL, l); | |
929 | ||
930 | ||
931 | DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", | |
932 | bpp, lines, cycle1, cycle2, cycle3); | |
933 | ||
934 | rfbi_enable_clocks(0); | |
935 | ||
936 | return 0; | |
937 | } | |
938 | EXPORT_SYMBOL(rfbi_configure); | |
939 | ||
940 | static int rfbi_find_display(struct omap_dss_device *dssdev) | |
941 | { | |
942 | if (dssdev == rfbi.dssdev[0]) | |
943 | return 0; | |
944 | ||
945 | if (dssdev == rfbi.dssdev[1]) | |
946 | return 1; | |
947 | ||
948 | BUG(); | |
949 | return -1; | |
950 | } | |
951 | ||
952 | ||
953 | static void signal_fifo_waiters(void) | |
954 | { | |
955 | if (atomic_read(&rfbi.cmd_fifo_full) > 0) { | |
956 | /* DSSDBG("SIGNALING: Fifo not full for waiter!\n"); */ | |
957 | complete(&rfbi.cmd_done); | |
958 | atomic_dec(&rfbi.cmd_fifo_full); | |
959 | } | |
960 | } | |
961 | ||
962 | /* returns 1 for async op, and 0 for sync op */ | |
963 | static int do_update(struct omap_dss_device *dssdev, struct update_region *upd) | |
964 | { | |
965 | u16 x = upd->x; | |
966 | u16 y = upd->y; | |
967 | u16 w = upd->w; | |
968 | u16 h = upd->h; | |
969 | ||
970 | perf_mark_setup(); | |
971 | ||
972 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { | |
973 | /*dssdev->driver->enable_te(dssdev, 1); */ | |
974 | dss_setup_partial_planes(dssdev, &x, &y, &w, &h); | |
975 | } | |
976 | ||
977 | #ifdef MEASURE_PERF | |
978 | rfbi.perf_bytes = w * h * 2; /* XXX always 16bit */ | |
979 | #endif | |
980 | ||
981 | dssdev->driver->setup_update(dssdev, x, y, w, h); | |
982 | ||
983 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { | |
984 | rfbi_transfer_area(w, h, NULL, NULL); | |
985 | return 1; | |
986 | } else { | |
987 | struct omap_overlay *ovl; | |
988 | void __iomem *addr; | |
989 | int scr_width; | |
990 | ||
991 | ovl = dssdev->manager->overlays[0]; | |
992 | scr_width = ovl->info.screen_width; | |
993 | addr = ovl->info.vaddr; | |
994 | ||
995 | omap_rfbi_write_pixels(addr, scr_width, x, y, w, h); | |
996 | ||
997 | perf_show("L4"); | |
998 | ||
999 | return 0; | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | static void process_cmd_fifo(void) | |
1004 | { | |
1005 | int len; | |
1006 | struct update_param p; | |
1007 | struct omap_dss_device *dssdev; | |
1008 | unsigned long flags; | |
1009 | ||
1010 | if (atomic_inc_return(&rfbi.cmd_pending) != 1) | |
1011 | return; | |
1012 | ||
1013 | while (true) { | |
fc248a49 | 1014 | spin_lock_irqsave(&rfbi.cmd_lock, flags); |
5c18adb3 | 1015 | |
fc248a49 | 1016 | len = kfifo_out(&rfbi.cmd_fifo, (unsigned char *)&p, |
5c18adb3 TV |
1017 | sizeof(struct update_param)); |
1018 | if (len == 0) { | |
1019 | DSSDBG("nothing more in fifo\n"); | |
1020 | atomic_set(&rfbi.cmd_pending, 0); | |
fc248a49 | 1021 | spin_unlock_irqrestore(&rfbi.cmd_lock, flags); |
5c18adb3 TV |
1022 | break; |
1023 | } | |
1024 | ||
1025 | /* DSSDBG("fifo full %d\n", rfbi.cmd_fifo_full.counter);*/ | |
1026 | ||
fc248a49 | 1027 | spin_unlock_irqrestore(&rfbi.cmd_lock, flags); |
5c18adb3 TV |
1028 | |
1029 | BUG_ON(len != sizeof(struct update_param)); | |
1030 | BUG_ON(p.rfbi_module > 1); | |
1031 | ||
1032 | dssdev = rfbi.dssdev[p.rfbi_module]; | |
1033 | ||
1034 | if (p.cmd == RFBI_CMD_UPDATE) { | |
1035 | if (do_update(dssdev, &p.par.r)) | |
1036 | break; /* async op */ | |
1037 | } else if (p.cmd == RFBI_CMD_SYNC) { | |
1038 | DSSDBG("Signaling SYNC done!\n"); | |
1039 | complete(p.par.sync); | |
1040 | } else | |
1041 | BUG(); | |
1042 | } | |
1043 | ||
1044 | signal_fifo_waiters(); | |
1045 | } | |
1046 | ||
1047 | static void rfbi_push_cmd(struct update_param *p) | |
1048 | { | |
1049 | int ret; | |
1050 | ||
1051 | while (1) { | |
1052 | unsigned long flags; | |
1053 | int available; | |
1054 | ||
fc248a49 | 1055 | spin_lock_irqsave(&rfbi.cmd_lock, flags); |
5c18adb3 | 1056 | available = RFBI_CMD_FIFO_LEN_BYTES - |
fc248a49 | 1057 | kfifo_len(&rfbi.cmd_fifo); |
5c18adb3 TV |
1058 | |
1059 | /* DSSDBG("%d bytes left in fifo\n", available); */ | |
1060 | if (available < sizeof(struct update_param)) { | |
1061 | DSSDBG("Going to wait because FIFO FULL..\n"); | |
fc248a49 | 1062 | spin_unlock_irqrestore(&rfbi.cmd_lock, flags); |
5c18adb3 TV |
1063 | atomic_inc(&rfbi.cmd_fifo_full); |
1064 | wait_for_completion(&rfbi.cmd_done); | |
1065 | /*DSSDBG("Woke up because fifo not full anymore\n");*/ | |
1066 | continue; | |
1067 | } | |
1068 | ||
fc248a49 | 1069 | ret = kfifo_in(&rfbi.cmd_fifo, (unsigned char *)p, |
5c18adb3 TV |
1070 | sizeof(struct update_param)); |
1071 | /* DSSDBG("pushed %d bytes\n", ret);*/ | |
1072 | ||
fc248a49 | 1073 | spin_unlock_irqrestore(&rfbi.cmd_lock, flags); |
5c18adb3 TV |
1074 | |
1075 | BUG_ON(ret != sizeof(struct update_param)); | |
1076 | ||
1077 | break; | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | static void rfbi_push_update(int rfbi_module, int x, int y, int w, int h) | |
1082 | { | |
1083 | struct update_param p; | |
1084 | ||
1085 | p.rfbi_module = rfbi_module; | |
1086 | p.cmd = RFBI_CMD_UPDATE; | |
1087 | ||
1088 | p.par.r.x = x; | |
1089 | p.par.r.y = y; | |
1090 | p.par.r.w = w; | |
1091 | p.par.r.h = h; | |
1092 | ||
1093 | DSSDBG("RFBI pushed %d,%d %dx%d\n", x, y, w, h); | |
1094 | ||
1095 | rfbi_push_cmd(&p); | |
1096 | ||
1097 | process_cmd_fifo(); | |
1098 | } | |
1099 | ||
1100 | static void rfbi_push_sync(int rfbi_module, struct completion *sync_comp) | |
1101 | { | |
1102 | struct update_param p; | |
1103 | ||
1104 | p.rfbi_module = rfbi_module; | |
1105 | p.cmd = RFBI_CMD_SYNC; | |
1106 | p.par.sync = sync_comp; | |
1107 | ||
1108 | rfbi_push_cmd(&p); | |
1109 | ||
1110 | DSSDBG("RFBI sync pushed to cmd fifo\n"); | |
1111 | ||
1112 | process_cmd_fifo(); | |
1113 | } | |
1114 | ||
1115 | void rfbi_dump_regs(struct seq_file *s) | |
1116 | { | |
1117 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) | |
1118 | ||
1119 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1); | |
1120 | ||
1121 | DUMPREG(RFBI_REVISION); | |
1122 | DUMPREG(RFBI_SYSCONFIG); | |
1123 | DUMPREG(RFBI_SYSSTATUS); | |
1124 | DUMPREG(RFBI_CONTROL); | |
1125 | DUMPREG(RFBI_PIXEL_CNT); | |
1126 | DUMPREG(RFBI_LINE_NUMBER); | |
1127 | DUMPREG(RFBI_CMD); | |
1128 | DUMPREG(RFBI_PARAM); | |
1129 | DUMPREG(RFBI_DATA); | |
1130 | DUMPREG(RFBI_READ); | |
1131 | DUMPREG(RFBI_STATUS); | |
1132 | ||
1133 | DUMPREG(RFBI_CONFIG(0)); | |
1134 | DUMPREG(RFBI_ONOFF_TIME(0)); | |
1135 | DUMPREG(RFBI_CYCLE_TIME(0)); | |
1136 | DUMPREG(RFBI_DATA_CYCLE1(0)); | |
1137 | DUMPREG(RFBI_DATA_CYCLE2(0)); | |
1138 | DUMPREG(RFBI_DATA_CYCLE3(0)); | |
1139 | ||
1140 | DUMPREG(RFBI_CONFIG(1)); | |
1141 | DUMPREG(RFBI_ONOFF_TIME(1)); | |
1142 | DUMPREG(RFBI_CYCLE_TIME(1)); | |
1143 | DUMPREG(RFBI_DATA_CYCLE1(1)); | |
1144 | DUMPREG(RFBI_DATA_CYCLE2(1)); | |
1145 | DUMPREG(RFBI_DATA_CYCLE3(1)); | |
1146 | ||
1147 | DUMPREG(RFBI_VSYNC_WIDTH); | |
1148 | DUMPREG(RFBI_HSYNC_WIDTH); | |
1149 | ||
1150 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1); | |
1151 | #undef DUMPREG | |
1152 | } | |
1153 | ||
1154 | int rfbi_init(void) | |
1155 | { | |
1156 | u32 rev; | |
1157 | u32 l; | |
fc248a49 | 1158 | int r; |
5c18adb3 TV |
1159 | |
1160 | spin_lock_init(&rfbi.cmd_lock); | |
fc248a49 TV |
1161 | r = kfifo_alloc(&rfbi.cmd_fifo, RFBI_CMD_FIFO_LEN_BYTES, GFP_KERNEL); |
1162 | if (r) | |
1163 | return r; | |
5c18adb3 TV |
1164 | |
1165 | init_completion(&rfbi.cmd_done); | |
1166 | atomic_set(&rfbi.cmd_fifo_full, 0); | |
1167 | atomic_set(&rfbi.cmd_pending, 0); | |
1168 | ||
1169 | rfbi.base = ioremap(RFBI_BASE, SZ_256); | |
1170 | if (!rfbi.base) { | |
1171 | DSSERR("can't ioremap RFBI\n"); | |
1172 | return -ENOMEM; | |
1173 | } | |
1174 | ||
1175 | rfbi_enable_clocks(1); | |
1176 | ||
1177 | msleep(10); | |
1178 | ||
1179 | rfbi.l4_khz = dss_clk_get_rate(DSS_CLK_ICK) / 1000; | |
1180 | ||
1181 | /* Enable autoidle and smart-idle */ | |
1182 | l = rfbi_read_reg(RFBI_SYSCONFIG); | |
1183 | l |= (1 << 0) | (2 << 3); | |
1184 | rfbi_write_reg(RFBI_SYSCONFIG, l); | |
1185 | ||
1186 | rev = rfbi_read_reg(RFBI_REVISION); | |
1187 | printk(KERN_INFO "OMAP RFBI rev %d.%d\n", | |
1188 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
1189 | ||
1190 | rfbi_enable_clocks(0); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | void rfbi_exit(void) | |
1196 | { | |
1197 | DSSDBG("rfbi_exit\n"); | |
1198 | ||
fc248a49 | 1199 | kfifo_free(&rfbi.cmd_fifo); |
5c18adb3 TV |
1200 | |
1201 | iounmap(rfbi.base); | |
1202 | } | |
1203 | ||
1204 | /* struct omap_display support */ | |
1205 | static int rfbi_display_update(struct omap_dss_device *dssdev, | |
1206 | u16 x, u16 y, u16 w, u16 h) | |
1207 | { | |
1208 | int rfbi_module; | |
1209 | ||
1210 | if (w == 0 || h == 0) | |
1211 | return 0; | |
1212 | ||
1213 | rfbi_module = rfbi_find_display(dssdev); | |
1214 | ||
1215 | rfbi_push_update(rfbi_module, x, y, w, h); | |
1216 | ||
1217 | return 0; | |
1218 | } | |
1219 | ||
1220 | static int rfbi_display_sync(struct omap_dss_device *dssdev) | |
1221 | { | |
1222 | struct completion sync_comp; | |
1223 | int rfbi_module; | |
1224 | ||
1225 | rfbi_module = rfbi_find_display(dssdev); | |
1226 | ||
1227 | init_completion(&sync_comp); | |
1228 | rfbi_push_sync(rfbi_module, &sync_comp); | |
1229 | DSSDBG("Waiting for SYNC to happen...\n"); | |
1230 | wait_for_completion(&sync_comp); | |
1231 | DSSDBG("Released from SYNC\n"); | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | static int rfbi_display_enable_te(struct omap_dss_device *dssdev, bool enable) | |
1236 | { | |
1237 | dssdev->driver->enable_te(dssdev, enable); | |
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | static int rfbi_display_enable(struct omap_dss_device *dssdev) | |
1242 | { | |
1243 | int r; | |
1244 | ||
1245 | r = omap_dss_start_device(dssdev); | |
1246 | if (r) { | |
1247 | DSSERR("failed to start device\n"); | |
1248 | goto err0; | |
1249 | } | |
1250 | ||
1251 | r = omap_dispc_register_isr(framedone_callback, NULL, | |
1252 | DISPC_IRQ_FRAMEDONE); | |
1253 | if (r) { | |
1254 | DSSERR("can't get FRAMEDONE irq\n"); | |
1255 | goto err1; | |
1256 | } | |
1257 | ||
1258 | dispc_set_lcd_display_type(OMAP_DSS_LCD_DISPLAY_TFT); | |
1259 | ||
1260 | dispc_set_parallel_interface_mode(OMAP_DSS_PARALLELMODE_RFBI); | |
1261 | ||
1262 | dispc_set_tft_data_lines(dssdev->ctrl.pixel_size); | |
1263 | ||
1264 | rfbi_configure(dssdev->phy.rfbi.channel, | |
1265 | dssdev->ctrl.pixel_size, | |
1266 | dssdev->phy.rfbi.data_lines); | |
1267 | ||
1268 | rfbi_set_timings(dssdev->phy.rfbi.channel, | |
1269 | &dssdev->ctrl.rfbi_timings); | |
1270 | ||
1271 | ||
1272 | if (dssdev->driver->enable) { | |
1273 | r = dssdev->driver->enable(dssdev); | |
1274 | if (r) | |
1275 | goto err2; | |
1276 | } | |
1277 | ||
1278 | return 0; | |
1279 | err2: | |
1280 | omap_dispc_unregister_isr(framedone_callback, NULL, | |
1281 | DISPC_IRQ_FRAMEDONE); | |
1282 | err1: | |
1283 | omap_dss_stop_device(dssdev); | |
1284 | err0: | |
1285 | return r; | |
1286 | } | |
1287 | ||
1288 | static void rfbi_display_disable(struct omap_dss_device *dssdev) | |
1289 | { | |
1290 | dssdev->driver->disable(dssdev); | |
1291 | omap_dispc_unregister_isr(framedone_callback, NULL, | |
1292 | DISPC_IRQ_FRAMEDONE); | |
1293 | omap_dss_stop_device(dssdev); | |
1294 | } | |
1295 | ||
1296 | int rfbi_init_display(struct omap_dss_device *dssdev) | |
1297 | { | |
1298 | dssdev->enable = rfbi_display_enable; | |
1299 | dssdev->disable = rfbi_display_disable; | |
1300 | dssdev->update = rfbi_display_update; | |
1301 | dssdev->sync = rfbi_display_sync; | |
1302 | dssdev->enable_te = rfbi_display_enable_te; | |
1303 | ||
1304 | rfbi.dssdev[dssdev->phy.rfbi.channel] = dssdev; | |
1305 | ||
1306 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE; | |
1307 | ||
1308 | return 0; | |
1309 | } |