projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: HDMI: Rename resource variable at probe.
[linux-2.6-block.git] / drivers / video / omap2 / dss / hdmi.c
CommitLineData
c3198a5e
M		 1/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
24e6289c 32#include <linux/platform_device.h>
4fbafaf3
TV		 33#include <linux/pm_runtime.h>
34#include <linux/clk.h>
cca35017 35#include <linux/gpio.h>
17486943 36#include <linux/regulator/consumer.h>
a0b38cc4 37#include <video/omapdss.h>
c3198a5e 38
94c52987 39#include "ti_hdmi.h"
c3198a5e 40#include "dss.h"
ad44cc32 41#include "dss_features.h"
c3198a5e 42
95a8aeb6
M		 43#define HDMI_WP 0x0
44#define HDMI_CORE_SYS 0x400
45#define HDMI_CORE_AV 0x900
46#define HDMI_PLLCTRL 0x200
47#define HDMI_PHY 0x300
48
7c1f1eca
M		 49/* HDMI EDID Length move this */
50#define HDMI_EDID_MAX_LENGTH 256
51#define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
56
b44e4582 57#define HDMI_DEFAULT_REGN 16
8d88767a
TV		 58#define HDMI_DEFAULT_REGM2 1
59
c3198a5e
M		 60static struct {
61 struct mutex lock;
c3198a5e 62 struct platform_device *pdev;
95a8aeb6 63 struct hdmi_ip_data ip_data;
4fbafaf3
TV		 64
65 struct clk *sys_clk;
17486943 66 struct regulator *vdda_hdmi_dac_reg;
cca35017
TV		 67
68 int ct_cp_hpd_gpio;
69 int ls_oe_gpio;
70 int hpd_gpio;
81b87f51
AT		 71
72 struct omap_dss_output output;
c3198a5e
M		 73} hdmi;
74
75/*
76 * Logic for the below structure :
77 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
78 * There is a correspondence between CEA/VESA timing and code, please
79 * refer to section 6.3 in HDMI 1.3 specification for timing code.
80 *
81 * In the below structure, cea_vesa_timings corresponds to all OMAP4
82 * supported CEA and VESA timing values.code_cea corresponds to the CEA
83 * code, It is used to get the timing from cea_vesa_timing array.Similarly
84 * with code_vesa. Code_index is used for back mapping, that is once EDID
85 * is read from the TV, EDID is parsed to find the timing values and then
86 * map it to corresponding CEA or VESA index.
87 */
88
46095b2d 89static const struct hdmi_config cea_timings[] = {
cc937e5e
AT		 90 {
91 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
92 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
93 false, },
94 { 1, HDMI_HDMI },
95 },
96 {
97 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
98 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
99 false, },
100 { 2, HDMI_HDMI },
101 },
102 {
103 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
104 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
105 false, },
106 { 4, HDMI_HDMI },
107 },
108 {
109 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
110 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
111 true, },
112 { 5, HDMI_HDMI },
113 },
114 {
115 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
116 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
117 true, },
118 { 6, HDMI_HDMI },
119 },
120 {
121 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
122 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
123 false, },
124 { 16, HDMI_HDMI },
125 },
126 {
127 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
128 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
129 false, },
130 { 17, HDMI_HDMI },
131 },
132 {
133 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
134 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
135 false, },
136 { 19, HDMI_HDMI },
137 },
138 {
139 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
140 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
141 true, },
142 { 20, HDMI_HDMI },
143 },
144 {
145 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
146 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
147 true, },
148 { 21, HDMI_HDMI },
149 },
150 {
151 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
152 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
153 false, },
154 { 29, HDMI_HDMI },
155 },
156 {
157 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
158 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
159 false, },
160 { 31, HDMI_HDMI },
161 },
162 {
163 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
164 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
165 false, },
166 { 32, HDMI_HDMI },
167 },
168 {
169 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
170 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
171 false, },
172 { 35, HDMI_HDMI },
173 },
174 {
175 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
176 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
177 false, },
178 { 37, HDMI_HDMI },
179 },
46095b2d 180};
cc937e5e 181
46095b2d 182static const struct hdmi_config vesa_timings[] = {
a05ce78f 183/* VESA From Here */
cc937e5e
AT		 184 {
185 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
186 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
187 false, },
188 { 4, HDMI_DVI },
189 },
190 {
191 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
192 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
193 false, },
194 { 9, HDMI_DVI },
195 },
196 {
197 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
198 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
199 false, },
200 { 0xE, HDMI_DVI },
201 },
202 {
203 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
204 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
205 false, },
206 { 0x17, HDMI_DVI },
207 },
208 {
209 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
210 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
211 false, },
212 { 0x1C, HDMI_DVI },
213 },
214 {
215 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
216 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
217 false, },
218 { 0x27, HDMI_DVI },
219 },
220 {
221 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
222 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
223 false, },
224 { 0x20, HDMI_DVI },
225 },
226 {
227 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
228 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
229 false, },
230 { 0x23, HDMI_DVI },
231 },
232 {
233 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
234 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
235 false, },
236 { 0x10, HDMI_DVI },
237 },
238 {
239 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
240 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
241 false, },
242 { 0x2A, HDMI_DVI },
243 },
244 {
245 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
246 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
247 false, },
248 { 0x2F, HDMI_DVI },
249 },
250 {
251 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
252 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
253 false, },
254 { 0x3A, HDMI_DVI },
255 },
256 {
257 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
258 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
259 false, },
260 { 0x51, HDMI_DVI },
261 },
262 {
263 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
264 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
265 false, },
266 { 0x52, HDMI_DVI },
267 },
268 {
269 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
270 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
271 false, },
272 { 0x16, HDMI_DVI },
273 },
274 {
275 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
276 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
277 false, },
278 { 0x29, HDMI_DVI },
279 },
280 {
281 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
282 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
283 false, },
284 { 0x39, HDMI_DVI },
285 },
286 {
287 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
288 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
289 false, },
290 { 0x1B, HDMI_DVI },
291 },
292 {
293 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
294 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
295 false, },
296 { 0x55, HDMI_DVI },
297 },
7a7ce2c7
TV		 298 {
299 { 1920, 1200, 154000, 32, 48, 80, 6, 3, 26,
300 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
301 false, },
302 { 0x44, HDMI_DVI },
303 },
c3198a5e
M		 304};
305
4fbafaf3
TV		 306static int hdmi_runtime_get(void)
307{
308 int r;
309
310 DSSDBG("hdmi_runtime_get\n");
311
312 r = pm_runtime_get_sync(&hdmi.pdev->dev);
313 WARN_ON(r < 0);
a247ce78 314 if (r < 0)
852f0838 315 return r;
a247ce78
AT		 316
317 return 0;
4fbafaf3
TV		 318}
319
320static void hdmi_runtime_put(void)
321{
322 int r;
323
324 DSSDBG("hdmi_runtime_put\n");
325
0eaf9f52 326 r = pm_runtime_put_sync(&hdmi.pdev->dev);
5be3aebd 327 WARN_ON(r < 0 && r != -ENOSYS);
4fbafaf3
TV		 328}
329
9d8232a7 330static int __init hdmi_init_display(struct omap_dss_device *dssdev)
c3198a5e 331{
cca35017
TV		 332 int r;
333
334 struct gpio gpios[] = {
335 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
336 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
337 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
338 };
339
c3198a5e
M		 340 DSSDBG("init_display\n");
341
b2c7d54f 342 dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version());
cca35017 343
17486943
TV		 344 if (hdmi.vdda_hdmi_dac_reg == NULL) {
345 struct regulator *reg;
346
347 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
348
349 if (IS_ERR(reg)) {
350 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
351 return PTR_ERR(reg);
352 }
353
354 hdmi.vdda_hdmi_dac_reg = reg;
355 }
356
cca35017
TV		 357 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
358 if (r)
359 return r;
360
c3198a5e
M		 361 return 0;
362}
363
cca35017
TV		 364static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
365{
366 DSSDBG("uninit_display\n");
367
368 gpio_free(hdmi.ct_cp_hpd_gpio);
369 gpio_free(hdmi.ls_oe_gpio);
370 gpio_free(hdmi.hpd_gpio);
371}
372
46095b2d
M		 373static const struct hdmi_config *hdmi_find_timing(
374 const struct hdmi_config *timings_arr,
375 int len)
c3198a5e 376{
46095b2d 377 int i;
c3198a5e 378
46095b2d 379 for (i = 0; i < len; i++) {
9e4ed603 380 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
46095b2d
M		 381 return &timings_arr[i];
382 }
383 return NULL;
384}
c3198a5e 385
46095b2d
M		 386static const struct hdmi_config *hdmi_get_timings(void)
387{
388 const struct hdmi_config *arr;
389 int len;
390
9e4ed603 391 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
46095b2d
M		 392 arr = vesa_timings;
393 len = ARRAY_SIZE(vesa_timings);
394 } else {
395 arr = cea_timings;
396 len = ARRAY_SIZE(cea_timings);
397 }
398
399 return hdmi_find_timing(arr, len);
400}
401
402static bool hdmi_timings_compare(struct omap_video_timings *timing1,
cc937e5e 403 const struct omap_video_timings *timing2)
46095b2d
M		 404{
405 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
406
f236b892
TV		 407 if ((DIV_ROUND_CLOSEST(timing2->pixel_clock, 1000) ==
408 DIV_ROUND_CLOSEST(timing1->pixel_clock, 1000)) &&
46095b2d
M		 409 (timing2->x_res == timing1->x_res) &&
410 (timing2->y_res == timing1->y_res)) {
c3198a5e 411
46095b2d
M		 412 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
413 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
414 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
415 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
416
417 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
418 "timing2_hsync = %d timing2_vsync = %d\n",
419 timing1_hsync, timing1_vsync,
420 timing2_hsync, timing2_vsync);
421
422 if ((timing1_hsync == timing2_hsync) &&
423 (timing1_vsync == timing2_vsync)) {
424 return true;
425 }
c3198a5e 426 }
46095b2d 427 return false;
c3198a5e
M		 428}
429
430static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
431{
46095b2d 432 int i;
c3198a5e
M		 433 struct hdmi_cm cm = {-1};
434 DSSDBG("hdmi_get_code\n");
435
46095b2d
M		 436 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
437 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
438 cm = cea_timings[i].cm;
439 goto end;
440 }
441 }
442 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
443 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
444 cm = vesa_timings[i].cm;
445 goto end;
c3198a5e
M		 446 }
447 }
448
46095b2d 449end: return cm;
c3198a5e 450
c3198a5e
M		 451}
452
c3dc6a7a
AT		 453unsigned long hdmi_get_pixel_clock(void)
454{
455 /* HDMI Pixel Clock in Mhz */
a05ce78f 456 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
c3dc6a7a
AT		 457}
458
6cb07b25
AT		 459static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
460 struct hdmi_pll_info *pi)
c3198a5e 461{
6cb07b25 462 unsigned long clkin, refclk;
c3198a5e
M		 463 u32 mf;
464
4fbafaf3 465 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
c3198a5e
M		 466 /*
467 * Input clock is predivided by N + 1
468 * out put of which is reference clk
469 */
8d88767a
TV		 470 if (dssdev->clocks.hdmi.regn == 0)
471 pi->regn = HDMI_DEFAULT_REGN;
472 else
473 pi->regn = dssdev->clocks.hdmi.regn;
474
b44e4582 475 refclk = clkin / pi->regn;
c3198a5e 476
8d88767a
TV		 477 if (dssdev->clocks.hdmi.regm2 == 0)
478 pi->regm2 = HDMI_DEFAULT_REGM2;
479 else
480 pi->regm2 = dssdev->clocks.hdmi.regm2;
c3198a5e 481
dd2116a3
M		 482 /*
483 * multiplier is pixel_clk/ref_clk
484 * Multiplying by 100 to avoid fractional part removal
485 */
486 pi->regm = phy * pi->regm2 / refclk;
487
c3198a5e
M		 488 /*
489 * fractional multiplier is remainder of the difference between
490 * multiplier and actual phy(required pixel clock thus should be
491 * multiplied by 2^18(262144) divided by the reference clock
492 */
dd2116a3
M		 493 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
494 pi->regmf = pi->regm2 * mf / refclk;
c3198a5e
M		 495
496 /*
497 * Dcofreq should be set to 1 if required pixel clock
498 * is greater than 1000MHz
499 */
500 pi->dcofreq = phy > 1000 * 100;
b44e4582 501 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
c3198a5e 502
7b27da54
M		 503 /* Set the reference clock to sysclk reference */
504 pi->refsel = HDMI_REFSEL_SYSCLK;
505
c3198a5e
M		 506 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
507 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
508}
509
bb426fc9 510static int hdmi_power_on_core(struct omap_dss_device *dssdev)
c3198a5e 511{
46095b2d 512 int r;
c3198a5e 513
cca35017
TV		 514 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
515 gpio_set_value(hdmi.ls_oe_gpio, 1);
516
a84b2065
TV		 517 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
518 udelay(300);
519
17486943
TV		 520 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
521 if (r)
522 goto err_vdac_enable;
523
4fbafaf3
TV		 524 r = hdmi_runtime_get();
525 if (r)
cca35017 526 goto err_runtime_get;
c3198a5e 527
bb426fc9
TV		 528 /* Make selection of HDMI in DSS */
529 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
530
bb426fc9
TV		 531 return 0;
532
533err_runtime_get:
534 regulator_disable(hdmi.vdda_hdmi_dac_reg);
535err_vdac_enable:
536 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
537 gpio_set_value(hdmi.ls_oe_gpio, 0);
538 return r;
539}
540
541static void hdmi_power_off_core(struct omap_dss_device *dssdev)
542{
543 hdmi_runtime_put();
544 regulator_disable(hdmi.vdda_hdmi_dac_reg);
545 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
546 gpio_set_value(hdmi.ls_oe_gpio, 0);
547}
548
549static int hdmi_power_on_full(struct omap_dss_device *dssdev)
550{
551 int r;
552 struct omap_video_timings *p;
553 struct omap_overlay_manager *mgr = dssdev->output->manager;
554 unsigned long phy;
555
556 r = hdmi_power_on_core(dssdev);
557 if (r)
558 return r;
559
cea87b92 560 dss_mgr_disable(mgr);
c3198a5e 561
7849398f 562 p = &hdmi.ip_data.cfg.timings;
c3198a5e 563
7849398f 564 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
c3198a5e 565
c3198a5e
M		 566 phy = p->pixel_clock;
567
7b27da54 568 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
c3198a5e 569
c0456be3 570 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
c3198a5e 571
95a8aeb6 572 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
60634a28 573 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
c3198a5e
M		 574 if (r) {
575 DSSDBG("Failed to lock PLL\n");
cca35017 576 goto err_pll_enable;
c3198a5e
M		 577 }
578
60634a28 579 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
c3198a5e
M		 580 if (r) {
581 DSSDBG("Failed to start PHY\n");
d3b4aa51 582 goto err_phy_enable;
c3198a5e
M		 583 }
584
60634a28 585 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
c3198a5e 586
c3198a5e
M		 587 /* bypass TV gamma table */
588 dispc_enable_gamma_table(0);
589
590 /* tv size */
cea87b92 591 dss_mgr_set_timings(mgr, p);
c3198a5e 592
c0456be3
RN		 593 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
594 if (r)
595 goto err_vid_enable;
c3198a5e 596
cea87b92 597 r = dss_mgr_enable(mgr);
33ca237f
TV		 598 if (r)
599 goto err_mgr_enable;
3870c909 600
c3198a5e 601 return 0;
33ca237f
TV		 602
603err_mgr_enable:
c0456be3
RN		 604 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
605err_vid_enable:
33ca237f 606 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
d3b4aa51 607err_phy_enable:
33ca237f 608 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
cca35017 609err_pll_enable:
bb426fc9 610 hdmi_power_off_core(dssdev);
c3198a5e
M		 611 return -EIO;
612}
613
bb426fc9 614static void hdmi_power_off_full(struct omap_dss_device *dssdev)
c3198a5e 615{
cea87b92
AT		 616 struct omap_overlay_manager *mgr = dssdev->output->manager;
617
618 dss_mgr_disable(mgr);
c3198a5e 619
c0456be3 620 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
60634a28
M		 621 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
622 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
17486943 623
bb426fc9 624 hdmi_power_off_core(dssdev);
c3198a5e
M		 625}
626
627int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
628 struct omap_video_timings *timings)
629{
630 struct hdmi_cm cm;
631
632 cm = hdmi_get_code(timings);
633 if (cm.code == -1) {
c3198a5e
M		 634 return -EINVAL;
635 }
636
637 return 0;
638
639}
640
7849398f
AT		 641void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
642 struct omap_video_timings *timings)
c3198a5e
M		 643{
644 struct hdmi_cm cm;
7849398f 645 const struct hdmi_config *t;
c3198a5e 646
ed1aa900
AT		 647 mutex_lock(&hdmi.lock);
648
7849398f
AT		 649 cm = hdmi_get_code(timings);
650 hdmi.ip_data.cfg.cm = cm;
651
652 t = hdmi_get_timings();
653 if (t != NULL)
654 hdmi.ip_data.cfg = *t;
fa70dc5f 655
ed1aa900 656 mutex_unlock(&hdmi.lock);
c3198a5e
M		 657}
658
e40402cf 659static void hdmi_dump_regs(struct seq_file *s)
162874d5
M		 660{
661 mutex_lock(&hdmi.lock);
662
f8fb7d7b
WY		 663 if (hdmi_runtime_get()) {
664 mutex_unlock(&hdmi.lock);
162874d5 665 return;
f8fb7d7b 666 }
162874d5
M		 667
668 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
669 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
670 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
671 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
672
673 hdmi_runtime_put();
674 mutex_unlock(&hdmi.lock);
675}
676
47024565
TV		 677int omapdss_hdmi_read_edid(u8 *buf, int len)
678{
679 int r;
680
681 mutex_lock(&hdmi.lock);
682
683 r = hdmi_runtime_get();
684 BUG_ON(r);
685
686 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
687
688 hdmi_runtime_put();
689 mutex_unlock(&hdmi.lock);
690
691 return r;
692}
693
759593ff
TV		 694bool omapdss_hdmi_detect(void)
695{
696 int r;
697
698 mutex_lock(&hdmi.lock);
699
700 r = hdmi_runtime_get();
701 BUG_ON(r);
702
703 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
704
705 hdmi_runtime_put();
706 mutex_unlock(&hdmi.lock);
707
708 return r == 1;
709}
710
c3198a5e
M		 711int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
712{
cea87b92 713 struct omap_dss_output *out = dssdev->output;
c3198a5e
M		 714 int r = 0;
715
716 DSSDBG("ENTER hdmi_display_enable\n");
717
718 mutex_lock(&hdmi.lock);
719
cea87b92
AT		 720 if (out == NULL || out->manager == NULL) {
721 DSSERR("failed to enable display: no output/manager\n");
05e1d606
TV		 722 r = -ENODEV;
723 goto err0;
724 }
725
cca35017 726 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
c49d005b 727
c3198a5e
M		 728 r = omap_dss_start_device(dssdev);
729 if (r) {
730 DSSERR("failed to start device\n");
731 goto err0;
732 }
733
bb426fc9 734 r = hdmi_power_on_full(dssdev);
c3198a5e
M		 735 if (r) {
736 DSSERR("failed to power on device\n");
cca35017 737 goto err1;
c3198a5e
M		 738 }
739
740 mutex_unlock(&hdmi.lock);
741 return 0;
742
c3198a5e
M		 743err1:
744 omap_dss_stop_device(dssdev);
745err0:
746 mutex_unlock(&hdmi.lock);
747 return r;
748}
749
750void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
751{
752 DSSDBG("Enter hdmi_display_disable\n");
753
754 mutex_lock(&hdmi.lock);
755
bb426fc9 756 hdmi_power_off_full(dssdev);
c3198a5e 757
c3198a5e
M		 758 omap_dss_stop_device(dssdev);
759
760 mutex_unlock(&hdmi.lock);
761}
762
4489823c
TV		 763int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev)
764{
765 int r = 0;
766
767 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
768
769 mutex_lock(&hdmi.lock);
770
771 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
772
773 r = hdmi_power_on_core(dssdev);
774 if (r) {
775 DSSERR("failed to power on device\n");
776 goto err0;
777 }
778
779 mutex_unlock(&hdmi.lock);
780 return 0;
781
782err0:
783 mutex_unlock(&hdmi.lock);
784 return r;
785}
786
787void omapdss_hdmi_core_disable(struct omap_dss_device *dssdev)
788{
789 DSSDBG("Enter omapdss_hdmi_core_disable\n");
790
791 mutex_lock(&hdmi.lock);
792
793 hdmi_power_off_core(dssdev);
794
795 mutex_unlock(&hdmi.lock);
796}
797
4fbafaf3
TV		 798static int hdmi_get_clocks(struct platform_device *pdev)
799{
800 struct clk *clk;
801
802 clk = clk_get(&pdev->dev, "sys_clk");
803 if (IS_ERR(clk)) {
804 DSSERR("can't get sys_clk\n");
805 return PTR_ERR(clk);
806 }
807
808 hdmi.sys_clk = clk;
809
4fbafaf3
TV		 810 return 0;
811}
812
813static void hdmi_put_clocks(void)
814{
815 if (hdmi.sys_clk)
816 clk_put(hdmi.sys_clk);
4fbafaf3
TV		 817}
818
35547626
RN		 819#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
820int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
821{
822 u32 deep_color;
25a65359 823 bool deep_color_correct = false;
35547626
RN		 824 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
825
826 if (n == NULL || cts == NULL)
827 return -EINVAL;
828
829 /* TODO: When implemented, query deep color mode here. */
830 deep_color = 100;
831
25a65359
RN		 832 /*
833 * When using deep color, the default N value (as in the HDMI
834 * specification) yields to an non-integer CTS. Hence, we
835 * modify it while keeping the restrictions described in
836 * section 7.2.1 of the HDMI 1.4a specification.
837 */
35547626
RN		 838 switch (sample_freq) {
839 case 32000:
25a65359
RN		 840 case 48000:
841 case 96000:
842 case 192000:
843 if (deep_color == 125)
844 if (pclk == 27027 || pclk == 74250)
845 deep_color_correct = true;
846 if (deep_color == 150)
847 if (pclk == 27027)
848 deep_color_correct = true;
35547626
RN		 849 break;
850 case 44100:
25a65359
RN		 851 case 88200:
852 case 176400:
853 if (deep_color == 125)
854 if (pclk == 27027)
855 deep_color_correct = true;
35547626
RN		 856 break;
857 default:
35547626
RN		 858 return -EINVAL;
859 }
860
25a65359
RN		 861 if (deep_color_correct) {
862 switch (sample_freq) {
863 case 32000:
864 *n = 8192;
865 break;
866 case 44100:
867 *n = 12544;
868 break;
869 case 48000:
870 *n = 8192;
871 break;
872 case 88200:
873 *n = 25088;
874 break;
875 case 96000:
876 *n = 16384;
877 break;
878 case 176400:
879 *n = 50176;
880 break;
881 case 192000:
882 *n = 32768;
883 break;
884 default:
885 return -EINVAL;
886 }
887 } else {
888 switch (sample_freq) {
889 case 32000:
890 *n = 4096;
891 break;
892 case 44100:
893 *n = 6272;
894 break;
895 case 48000:
896 *n = 6144;
897 break;
898 case 88200:
899 *n = 12544;
900 break;
901 case 96000:
902 *n = 12288;
903 break;
904 case 176400:
905 *n = 25088;
906 break;
907 case 192000:
908 *n = 24576;
909 break;
910 default:
911 return -EINVAL;
912 }
913 }
35547626
RN		 914 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
915 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
916
917 return 0;
918}
f3a97491
RN		 919
920int hdmi_audio_enable(void)
921{
922 DSSDBG("audio_enable\n");
923
924 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
925}
926
927void hdmi_audio_disable(void)
928{
929 DSSDBG("audio_disable\n");
930
931 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
932}
933
934int hdmi_audio_start(void)
935{
936 DSSDBG("audio_start\n");
937
938 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
939}
940
941void hdmi_audio_stop(void)
942{
943 DSSDBG("audio_stop\n");
944
945 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
946}
947
948bool hdmi_mode_has_audio(void)
949{
950 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
951 return true;
952 else
953 return false;
954}
955
956int hdmi_audio_config(struct omap_dss_audio *audio)
957{
958 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
959}
960
35547626
RN		 961#endif
962
1521653c 963static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
38f3daf6
TV		 964{
965 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
2bbcce5e 966 const char *def_disp_name = omapdss_get_default_display_name();
1521653c
TV		 967 struct omap_dss_device *def_dssdev;
968 int i;
969
970 def_dssdev = NULL;
38f3daf6
TV		 971
972 for (i = 0; i < pdata->num_devices; ++i) {
973 struct omap_dss_device *dssdev = pdata->devices[i];
974
975 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
976 continue;
977
1521653c
TV		 978 if (def_dssdev == NULL)
979 def_dssdev = dssdev;
cca35017 980
1521653c
TV		 981 if (def_disp_name != NULL &&
982 strcmp(dssdev->name, def_disp_name) == 0) {
983 def_dssdev = dssdev;
984 break;
38f3daf6 985 }
1521653c
TV		 986 }
987
988 return def_dssdev;
989}
990
991static void __init hdmi_probe_pdata(struct platform_device *pdev)
992{
5274484b 993 struct omap_dss_device *plat_dssdev;
1521653c
TV		 994 struct omap_dss_device *dssdev;
995 struct omap_dss_hdmi_data *priv;
996 int r;
38f3daf6 997
5274484b 998 plat_dssdev = hdmi_find_dssdev(pdev);
1521653c 999
5274484b
TV		 1000 if (!plat_dssdev)
1001 return;
1002
1003 dssdev = dss_alloc_and_init_device(&pdev->dev);
1521653c
TV		 1004 if (!dssdev)
1005 return;
1006
5274484b
TV		 1007 dss_copy_device_pdata(dssdev, plat_dssdev);
1008
1521653c
TV		 1009 priv = dssdev->data;
1010
1011 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
1012 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
1013 hdmi.hpd_gpio = priv->hpd_gpio;
1014
bcb226a9
TV		 1015 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
1016
1521653c
TV		 1017 r = hdmi_init_display(dssdev);
1018 if (r) {
1019 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5274484b 1020 dss_put_device(dssdev);
1521653c
TV		 1021 return;
1022 }
1023
5274484b 1024 r = dss_add_device(dssdev);
1521653c
TV		 1025 if (r) {
1026 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5274484b 1027 dss_put_device(dssdev);
1521653c 1028 return;
38f3daf6
TV		 1029 }
1030}
1031
81b87f51
AT		 1032static void __init hdmi_init_output(struct platform_device *pdev)
1033{
1034 struct omap_dss_output *out = &hdmi.output;
1035
1036 out->pdev = pdev;
1037 out->id = OMAP_DSS_OUTPUT_HDMI;
1038 out->type = OMAP_DISPLAY_TYPE_HDMI;
1039
1040 dss_register_output(out);
1041}
1042
1043static void __exit hdmi_uninit_output(struct platform_device *pdev)
1044{
1045 struct omap_dss_output *out = &hdmi.output;
1046
1047 dss_unregister_output(out);
1048}
1049
c3198a5e 1050/* HDMI HW IP initialisation */
6e7e8f06 1051static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
c3198a5e 1052{
af23cb35 1053 struct resource *res;
38f3daf6 1054 int r;
c3198a5e 1055
c3198a5e
M		 1056 hdmi.pdev = pdev;
1057
1058 mutex_init(&hdmi.lock);
1059
af23cb35
RN		 1060 res = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1061 if (!res) {
c3198a5e
M		 1062 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1063 return -EINVAL;
1064 }
1065
1066 /* Base address taken from platform */
af23cb35 1067 hdmi.ip_data.base_wp = ioremap(res->start, resource_size(res));
95a8aeb6 1068 if (!hdmi.ip_data.base_wp) {
c3198a5e
M		 1069 DSSERR("can't ioremap WP\n");
1070 return -ENOMEM;
1071 }
1072
4fbafaf3
TV		 1073 r = hdmi_get_clocks(pdev);
1074 if (r) {
95a8aeb6 1075 iounmap(hdmi.ip_data.base_wp);
4fbafaf3
TV		 1076 return r;
1077 }
1078
1079 pm_runtime_enable(&pdev->dev);
1080
95a8aeb6
M		 1081 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1082 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1083 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1084 hdmi.ip_data.phy_offset = HDMI_PHY;
7849398f 1085
3a5383a2 1086 mutex_init(&hdmi.ip_data.lock);
95a8aeb6 1087
c3198a5e
M		 1088 hdmi_panel_init();
1089
e40402cf
TV		 1090 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1091
81b87f51
AT		 1092 hdmi_init_output(pdev);
1093
38f3daf6 1094 hdmi_probe_pdata(pdev);
35deca3d 1095
c3198a5e
M		 1096 return 0;
1097}
1098
cca35017
TV		 1099static int __exit hdmi_remove_child(struct device *dev, void *data)
1100{
1101 struct omap_dss_device *dssdev = to_dss_device(dev);
1102 hdmi_uninit_display(dssdev);
1103 return 0;
1104}
1105
6e7e8f06 1106static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
c3198a5e 1107{
cca35017
TV		 1108 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1109
5274484b 1110 dss_unregister_child_devices(&pdev->dev);
35deca3d 1111
c3198a5e
M		 1112 hdmi_panel_exit();
1113
81b87f51
AT		 1114 hdmi_uninit_output(pdev);
1115
4fbafaf3
TV		 1116 pm_runtime_disable(&pdev->dev);
1117
1118 hdmi_put_clocks();
1119
95a8aeb6 1120 iounmap(hdmi.ip_data.base_wp);
c3198a5e
M		 1121
1122 return 0;
1123}
1124
4fbafaf3
TV		 1125static int hdmi_runtime_suspend(struct device *dev)
1126{
f11766d1 1127 clk_disable_unprepare(hdmi.sys_clk);
4fbafaf3
TV		 1128
1129 dispc_runtime_put();
4fbafaf3
TV		 1130
1131 return 0;
1132}
1133
1134static int hdmi_runtime_resume(struct device *dev)
1135{
1136 int r;
1137
4fbafaf3
TV		 1138 r = dispc_runtime_get();
1139 if (r < 0)
852f0838 1140 return r;
4fbafaf3 1141
f11766d1 1142 clk_prepare_enable(hdmi.sys_clk);
4fbafaf3
TV		 1143
1144 return 0;
4fbafaf3
TV		 1145}
1146
1147static const struct dev_pm_ops hdmi_pm_ops = {
1148 .runtime_suspend = hdmi_runtime_suspend,
1149 .runtime_resume = hdmi_runtime_resume,
1150};
1151
c3198a5e 1152static struct platform_driver omapdss_hdmihw_driver = {
6e7e8f06 1153 .remove = __exit_p(omapdss_hdmihw_remove),
c3198a5e
M		 1154 .driver = {
1155 .name = "omapdss_hdmi",
1156 .owner = THIS_MODULE,
4fbafaf3 1157 .pm = &hdmi_pm_ops,
c3198a5e
M		 1158 },
1159};
1160
6e7e8f06 1161int __init hdmi_init_platform_driver(void)
c3198a5e 1162{
61055d4b 1163 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
c3198a5e
M		 1164}
1165
6e7e8f06 1166void __exit hdmi_uninit_platform_driver(void)
c3198a5e 1167{
04c742c3 1168 platform_driver_unregister(&omapdss_hdmihw_driver);
c3198a5e 1169}
Linux 6.x block layer and io_uring tree(s)