Commit | Line | Data |
---|---|---|
c3198a5e M |
1 | /* |
2 | * hdmi.c | |
3 | * | |
4 | * HDMI interface DSS driver setting for TI's OMAP4 family of processor. | |
5 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * Authors: Yong Zhi | |
7 | * Mythri pk <mythripk@ti.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License version 2 as published by | |
11 | * the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #define DSS_SUBSYS_NAME "HDMI" | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/mutex.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/string.h> | |
24e6289c | 32 | #include <linux/platform_device.h> |
4fbafaf3 TV |
33 | #include <linux/pm_runtime.h> |
34 | #include <linux/clk.h> | |
cca35017 | 35 | #include <linux/gpio.h> |
17486943 | 36 | #include <linux/regulator/consumer.h> |
a0b38cc4 | 37 | #include <video/omapdss.h> |
c3198a5e | 38 | |
94c52987 | 39 | #include "ti_hdmi.h" |
c3198a5e | 40 | #include "dss.h" |
ad44cc32 | 41 | #include "dss_features.h" |
c3198a5e | 42 | |
95a8aeb6 M |
43 | #define HDMI_WP 0x0 |
44 | #define HDMI_CORE_SYS 0x400 | |
45 | #define HDMI_CORE_AV 0x900 | |
46 | #define HDMI_PLLCTRL 0x200 | |
47 | #define HDMI_PHY 0x300 | |
48 | ||
7c1f1eca M |
49 | /* HDMI EDID Length move this */ |
50 | #define HDMI_EDID_MAX_LENGTH 256 | |
51 | #define EDID_TIMING_DESCRIPTOR_SIZE 0x12 | |
52 | #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 | |
53 | #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 | |
54 | #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 | |
55 | #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 | |
56 | ||
b44e4582 | 57 | #define HDMI_DEFAULT_REGN 16 |
8d88767a TV |
58 | #define HDMI_DEFAULT_REGM2 1 |
59 | ||
c3198a5e M |
60 | static struct { |
61 | struct mutex lock; | |
c3198a5e | 62 | struct platform_device *pdev; |
95a8aeb6 | 63 | struct hdmi_ip_data ip_data; |
4fbafaf3 TV |
64 | |
65 | struct clk *sys_clk; | |
17486943 | 66 | struct regulator *vdda_hdmi_dac_reg; |
cca35017 TV |
67 | |
68 | int ct_cp_hpd_gpio; | |
69 | int ls_oe_gpio; | |
70 | int hpd_gpio; | |
81b87f51 AT |
71 | |
72 | struct omap_dss_output output; | |
c3198a5e M |
73 | } hdmi; |
74 | ||
75 | /* | |
76 | * Logic for the below structure : | |
77 | * user enters the CEA or VESA timings by specifying the HDMI/DVI code. | |
78 | * There is a correspondence between CEA/VESA timing and code, please | |
79 | * refer to section 6.3 in HDMI 1.3 specification for timing code. | |
80 | * | |
81 | * In the below structure, cea_vesa_timings corresponds to all OMAP4 | |
82 | * supported CEA and VESA timing values.code_cea corresponds to the CEA | |
83 | * code, It is used to get the timing from cea_vesa_timing array.Similarly | |
84 | * with code_vesa. Code_index is used for back mapping, that is once EDID | |
85 | * is read from the TV, EDID is parsed to find the timing values and then | |
86 | * map it to corresponding CEA or VESA index. | |
87 | */ | |
88 | ||
46095b2d | 89 | static const struct hdmi_config cea_timings[] = { |
cc937e5e AT |
90 | { |
91 | { 640, 480, 25200, 96, 16, 48, 2, 10, 33, | |
92 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
93 | false, }, | |
94 | { 1, HDMI_HDMI }, | |
95 | }, | |
96 | { | |
97 | { 720, 480, 27027, 62, 16, 60, 6, 9, 30, | |
98 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
99 | false, }, | |
100 | { 2, HDMI_HDMI }, | |
101 | }, | |
102 | { | |
103 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
104 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
105 | false, }, | |
106 | { 4, HDMI_HDMI }, | |
107 | }, | |
108 | { | |
109 | { 1920, 540, 74250, 44, 88, 148, 5, 2, 15, | |
110 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
111 | true, }, | |
112 | { 5, HDMI_HDMI }, | |
113 | }, | |
114 | { | |
115 | { 1440, 240, 27027, 124, 38, 114, 3, 4, 15, | |
116 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
117 | true, }, | |
118 | { 6, HDMI_HDMI }, | |
119 | }, | |
120 | { | |
121 | { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36, | |
122 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
123 | false, }, | |
124 | { 16, HDMI_HDMI }, | |
125 | }, | |
126 | { | |
127 | { 720, 576, 27000, 64, 12, 68, 5, 5, 39, | |
128 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
129 | false, }, | |
130 | { 17, HDMI_HDMI }, | |
131 | }, | |
132 | { | |
133 | { 1280, 720, 74250, 40, 440, 220, 5, 5, 20, | |
134 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
135 | false, }, | |
136 | { 19, HDMI_HDMI }, | |
137 | }, | |
138 | { | |
139 | { 1920, 540, 74250, 44, 528, 148, 5, 2, 15, | |
140 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
141 | true, }, | |
142 | { 20, HDMI_HDMI }, | |
143 | }, | |
144 | { | |
145 | { 1440, 288, 27000, 126, 24, 138, 3, 2, 19, | |
146 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
147 | true, }, | |
148 | { 21, HDMI_HDMI }, | |
149 | }, | |
150 | { | |
151 | { 1440, 576, 54000, 128, 24, 136, 5, 5, 39, | |
152 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
153 | false, }, | |
154 | { 29, HDMI_HDMI }, | |
155 | }, | |
156 | { | |
157 | { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36, | |
158 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
159 | false, }, | |
160 | { 31, HDMI_HDMI }, | |
161 | }, | |
162 | { | |
163 | { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36, | |
164 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
165 | false, }, | |
166 | { 32, HDMI_HDMI }, | |
167 | }, | |
168 | { | |
169 | { 2880, 480, 108108, 248, 64, 240, 6, 9, 30, | |
170 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
171 | false, }, | |
172 | { 35, HDMI_HDMI }, | |
173 | }, | |
174 | { | |
175 | { 2880, 576, 108000, 256, 48, 272, 5, 5, 39, | |
176 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
177 | false, }, | |
178 | { 37, HDMI_HDMI }, | |
179 | }, | |
46095b2d | 180 | }; |
cc937e5e | 181 | |
46095b2d | 182 | static const struct hdmi_config vesa_timings[] = { |
a05ce78f | 183 | /* VESA From Here */ |
cc937e5e AT |
184 | { |
185 | { 640, 480, 25175, 96, 16, 48, 2, 11, 31, | |
186 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
187 | false, }, | |
188 | { 4, HDMI_DVI }, | |
189 | }, | |
190 | { | |
191 | { 800, 600, 40000, 128, 40, 88, 4, 1, 23, | |
192 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
193 | false, }, | |
194 | { 9, HDMI_DVI }, | |
195 | }, | |
196 | { | |
197 | { 848, 480, 33750, 112, 16, 112, 8, 6, 23, | |
198 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
199 | false, }, | |
200 | { 0xE, HDMI_DVI }, | |
201 | }, | |
202 | { | |
203 | { 1280, 768, 79500, 128, 64, 192, 7, 3, 20, | |
204 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
205 | false, }, | |
206 | { 0x17, HDMI_DVI }, | |
207 | }, | |
208 | { | |
209 | { 1280, 800, 83500, 128, 72, 200, 6, 3, 22, | |
210 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
211 | false, }, | |
212 | { 0x1C, HDMI_DVI }, | |
213 | }, | |
214 | { | |
215 | { 1360, 768, 85500, 112, 64, 256, 6, 3, 18, | |
216 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
217 | false, }, | |
218 | { 0x27, HDMI_DVI }, | |
219 | }, | |
220 | { | |
221 | { 1280, 960, 108000, 112, 96, 312, 3, 1, 36, | |
222 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
223 | false, }, | |
224 | { 0x20, HDMI_DVI }, | |
225 | }, | |
226 | { | |
227 | { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38, | |
228 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
229 | false, }, | |
230 | { 0x23, HDMI_DVI }, | |
231 | }, | |
232 | { | |
233 | { 1024, 768, 65000, 136, 24, 160, 6, 3, 29, | |
234 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW, | |
235 | false, }, | |
236 | { 0x10, HDMI_DVI }, | |
237 | }, | |
238 | { | |
239 | { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32, | |
240 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
241 | false, }, | |
242 | { 0x2A, HDMI_DVI }, | |
243 | }, | |
244 | { | |
245 | { 1440, 900, 106500, 152, 80, 232, 6, 3, 25, | |
246 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
247 | false, }, | |
248 | { 0x2F, HDMI_DVI }, | |
249 | }, | |
250 | { | |
251 | { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30, | |
252 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW, | |
253 | false, }, | |
254 | { 0x3A, HDMI_DVI }, | |
255 | }, | |
256 | { | |
257 | { 1366, 768, 85500, 143, 70, 213, 3, 3, 24, | |
258 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
259 | false, }, | |
260 | { 0x51, HDMI_DVI }, | |
261 | }, | |
262 | { | |
263 | { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36, | |
264 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
265 | false, }, | |
266 | { 0x52, HDMI_DVI }, | |
267 | }, | |
268 | { | |
269 | { 1280, 768, 68250, 32, 48, 80, 7, 3, 12, | |
270 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
271 | false, }, | |
272 | { 0x16, HDMI_DVI }, | |
273 | }, | |
274 | { | |
275 | { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23, | |
276 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
277 | false, }, | |
278 | { 0x29, HDMI_DVI }, | |
279 | }, | |
280 | { | |
281 | { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21, | |
282 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
283 | false, }, | |
284 | { 0x39, HDMI_DVI }, | |
285 | }, | |
286 | { | |
287 | { 1280, 800, 79500, 32, 48, 80, 6, 3, 14, | |
288 | OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH, | |
289 | false, }, | |
290 | { 0x1B, HDMI_DVI }, | |
291 | }, | |
292 | { | |
293 | { 1280, 720, 74250, 40, 110, 220, 5, 5, 20, | |
294 | OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH, | |
295 | false, }, | |
296 | { 0x55, HDMI_DVI }, | |
297 | }, | |
c3198a5e M |
298 | }; |
299 | ||
4fbafaf3 TV |
300 | static int hdmi_runtime_get(void) |
301 | { | |
302 | int r; | |
303 | ||
304 | DSSDBG("hdmi_runtime_get\n"); | |
305 | ||
306 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
307 | WARN_ON(r < 0); | |
a247ce78 | 308 | if (r < 0) |
852f0838 | 309 | return r; |
a247ce78 AT |
310 | |
311 | return 0; | |
4fbafaf3 TV |
312 | } |
313 | ||
314 | static void hdmi_runtime_put(void) | |
315 | { | |
316 | int r; | |
317 | ||
318 | DSSDBG("hdmi_runtime_put\n"); | |
319 | ||
0eaf9f52 | 320 | r = pm_runtime_put_sync(&hdmi.pdev->dev); |
5be3aebd | 321 | WARN_ON(r < 0 && r != -ENOSYS); |
4fbafaf3 TV |
322 | } |
323 | ||
9d8232a7 | 324 | static int __init hdmi_init_display(struct omap_dss_device *dssdev) |
c3198a5e | 325 | { |
cca35017 TV |
326 | int r; |
327 | ||
328 | struct gpio gpios[] = { | |
329 | { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" }, | |
330 | { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" }, | |
331 | { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" }, | |
332 | }; | |
333 | ||
c3198a5e M |
334 | DSSDBG("init_display\n"); |
335 | ||
b2c7d54f | 336 | dss_init_hdmi_ip_ops(&hdmi.ip_data, omapdss_get_version()); |
cca35017 | 337 | |
17486943 TV |
338 | if (hdmi.vdda_hdmi_dac_reg == NULL) { |
339 | struct regulator *reg; | |
340 | ||
341 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac"); | |
342 | ||
343 | if (IS_ERR(reg)) { | |
344 | DSSERR("can't get VDDA_HDMI_DAC regulator\n"); | |
345 | return PTR_ERR(reg); | |
346 | } | |
347 | ||
348 | hdmi.vdda_hdmi_dac_reg = reg; | |
349 | } | |
350 | ||
cca35017 TV |
351 | r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); |
352 | if (r) | |
353 | return r; | |
354 | ||
c3198a5e M |
355 | return 0; |
356 | } | |
357 | ||
cca35017 TV |
358 | static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev) |
359 | { | |
360 | DSSDBG("uninit_display\n"); | |
361 | ||
362 | gpio_free(hdmi.ct_cp_hpd_gpio); | |
363 | gpio_free(hdmi.ls_oe_gpio); | |
364 | gpio_free(hdmi.hpd_gpio); | |
365 | } | |
366 | ||
46095b2d M |
367 | static const struct hdmi_config *hdmi_find_timing( |
368 | const struct hdmi_config *timings_arr, | |
369 | int len) | |
c3198a5e | 370 | { |
46095b2d | 371 | int i; |
c3198a5e | 372 | |
46095b2d | 373 | for (i = 0; i < len; i++) { |
9e4ed603 | 374 | if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code) |
46095b2d M |
375 | return &timings_arr[i]; |
376 | } | |
377 | return NULL; | |
378 | } | |
c3198a5e | 379 | |
46095b2d M |
380 | static const struct hdmi_config *hdmi_get_timings(void) |
381 | { | |
382 | const struct hdmi_config *arr; | |
383 | int len; | |
384 | ||
9e4ed603 | 385 | if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) { |
46095b2d M |
386 | arr = vesa_timings; |
387 | len = ARRAY_SIZE(vesa_timings); | |
388 | } else { | |
389 | arr = cea_timings; | |
390 | len = ARRAY_SIZE(cea_timings); | |
391 | } | |
392 | ||
393 | return hdmi_find_timing(arr, len); | |
394 | } | |
395 | ||
396 | static bool hdmi_timings_compare(struct omap_video_timings *timing1, | |
cc937e5e | 397 | const struct omap_video_timings *timing2) |
46095b2d M |
398 | { |
399 | int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync; | |
400 | ||
401 | if ((timing2->pixel_clock == timing1->pixel_clock) && | |
402 | (timing2->x_res == timing1->x_res) && | |
403 | (timing2->y_res == timing1->y_res)) { | |
c3198a5e | 404 | |
46095b2d M |
405 | timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp; |
406 | timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp; | |
407 | timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
408 | timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp; | |
409 | ||
410 | DSSDBG("timing1_hsync = %d timing1_vsync = %d"\ | |
411 | "timing2_hsync = %d timing2_vsync = %d\n", | |
412 | timing1_hsync, timing1_vsync, | |
413 | timing2_hsync, timing2_vsync); | |
414 | ||
415 | if ((timing1_hsync == timing2_hsync) && | |
416 | (timing1_vsync == timing2_vsync)) { | |
417 | return true; | |
418 | } | |
c3198a5e | 419 | } |
46095b2d | 420 | return false; |
c3198a5e M |
421 | } |
422 | ||
423 | static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing) | |
424 | { | |
46095b2d | 425 | int i; |
c3198a5e M |
426 | struct hdmi_cm cm = {-1}; |
427 | DSSDBG("hdmi_get_code\n"); | |
428 | ||
46095b2d M |
429 | for (i = 0; i < ARRAY_SIZE(cea_timings); i++) { |
430 | if (hdmi_timings_compare(timing, &cea_timings[i].timings)) { | |
431 | cm = cea_timings[i].cm; | |
432 | goto end; | |
433 | } | |
434 | } | |
435 | for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) { | |
436 | if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) { | |
437 | cm = vesa_timings[i].cm; | |
438 | goto end; | |
c3198a5e M |
439 | } |
440 | } | |
441 | ||
46095b2d | 442 | end: return cm; |
c3198a5e | 443 | |
c3198a5e M |
444 | } |
445 | ||
c3dc6a7a AT |
446 | unsigned long hdmi_get_pixel_clock(void) |
447 | { | |
448 | /* HDMI Pixel Clock in Mhz */ | |
a05ce78f | 449 | return hdmi.ip_data.cfg.timings.pixel_clock * 1000; |
c3dc6a7a AT |
450 | } |
451 | ||
6cb07b25 AT |
452 | static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy, |
453 | struct hdmi_pll_info *pi) | |
c3198a5e | 454 | { |
6cb07b25 | 455 | unsigned long clkin, refclk; |
c3198a5e M |
456 | u32 mf; |
457 | ||
4fbafaf3 | 458 | clkin = clk_get_rate(hdmi.sys_clk) / 10000; |
c3198a5e M |
459 | /* |
460 | * Input clock is predivided by N + 1 | |
461 | * out put of which is reference clk | |
462 | */ | |
8d88767a TV |
463 | if (dssdev->clocks.hdmi.regn == 0) |
464 | pi->regn = HDMI_DEFAULT_REGN; | |
465 | else | |
466 | pi->regn = dssdev->clocks.hdmi.regn; | |
467 | ||
b44e4582 | 468 | refclk = clkin / pi->regn; |
c3198a5e | 469 | |
8d88767a TV |
470 | if (dssdev->clocks.hdmi.regm2 == 0) |
471 | pi->regm2 = HDMI_DEFAULT_REGM2; | |
472 | else | |
473 | pi->regm2 = dssdev->clocks.hdmi.regm2; | |
c3198a5e | 474 | |
dd2116a3 M |
475 | /* |
476 | * multiplier is pixel_clk/ref_clk | |
477 | * Multiplying by 100 to avoid fractional part removal | |
478 | */ | |
479 | pi->regm = phy * pi->regm2 / refclk; | |
480 | ||
c3198a5e M |
481 | /* |
482 | * fractional multiplier is remainder of the difference between | |
483 | * multiplier and actual phy(required pixel clock thus should be | |
484 | * multiplied by 2^18(262144) divided by the reference clock | |
485 | */ | |
dd2116a3 M |
486 | mf = (phy - pi->regm / pi->regm2 * refclk) * 262144; |
487 | pi->regmf = pi->regm2 * mf / refclk; | |
c3198a5e M |
488 | |
489 | /* | |
490 | * Dcofreq should be set to 1 if required pixel clock | |
491 | * is greater than 1000MHz | |
492 | */ | |
493 | pi->dcofreq = phy > 1000 * 100; | |
b44e4582 | 494 | pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10; |
c3198a5e | 495 | |
7b27da54 M |
496 | /* Set the reference clock to sysclk reference */ |
497 | pi->refsel = HDMI_REFSEL_SYSCLK; | |
498 | ||
c3198a5e M |
499 | DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf); |
500 | DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd); | |
501 | } | |
502 | ||
c3198a5e M |
503 | static int hdmi_power_on(struct omap_dss_device *dssdev) |
504 | { | |
46095b2d | 505 | int r; |
c3198a5e | 506 | struct omap_video_timings *p; |
cea87b92 | 507 | struct omap_overlay_manager *mgr = dssdev->output->manager; |
6cb07b25 | 508 | unsigned long phy; |
c3198a5e | 509 | |
cca35017 TV |
510 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 1); |
511 | gpio_set_value(hdmi.ls_oe_gpio, 1); | |
512 | ||
a84b2065 TV |
513 | /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */ |
514 | udelay(300); | |
515 | ||
17486943 TV |
516 | r = regulator_enable(hdmi.vdda_hdmi_dac_reg); |
517 | if (r) | |
518 | goto err_vdac_enable; | |
519 | ||
4fbafaf3 TV |
520 | r = hdmi_runtime_get(); |
521 | if (r) | |
cca35017 | 522 | goto err_runtime_get; |
c3198a5e | 523 | |
cea87b92 | 524 | dss_mgr_disable(mgr); |
c3198a5e | 525 | |
7849398f | 526 | p = &hdmi.ip_data.cfg.timings; |
c3198a5e | 527 | |
7849398f | 528 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); |
c3198a5e | 529 | |
c3198a5e M |
530 | phy = p->pixel_clock; |
531 | ||
7b27da54 | 532 | hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data); |
c3198a5e | 533 | |
c0456be3 | 534 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
c3198a5e | 535 | |
95a8aeb6 | 536 | /* config the PLL and PHY hdmi_set_pll_pwrfirst */ |
60634a28 | 537 | r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data); |
c3198a5e M |
538 | if (r) { |
539 | DSSDBG("Failed to lock PLL\n"); | |
cca35017 | 540 | goto err_pll_enable; |
c3198a5e M |
541 | } |
542 | ||
60634a28 | 543 | r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data); |
c3198a5e M |
544 | if (r) { |
545 | DSSDBG("Failed to start PHY\n"); | |
d3b4aa51 | 546 | goto err_phy_enable; |
c3198a5e M |
547 | } |
548 | ||
60634a28 | 549 | hdmi.ip_data.ops->video_configure(&hdmi.ip_data); |
c3198a5e M |
550 | |
551 | /* Make selection of HDMI in DSS */ | |
552 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
553 | ||
554 | /* Select the dispc clock source as PRCM clock, to ensure that it is not | |
555 | * DSI PLL source as the clock selected by DSI PLL might not be | |
556 | * sufficient for the resolution selected / that can be changed | |
557 | * dynamically by user. This can be moved to single location , say | |
558 | * Boardfile. | |
559 | */ | |
6cb07b25 | 560 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
c3198a5e M |
561 | |
562 | /* bypass TV gamma table */ | |
563 | dispc_enable_gamma_table(0); | |
564 | ||
565 | /* tv size */ | |
cea87b92 | 566 | dss_mgr_set_timings(mgr, p); |
c3198a5e | 567 | |
c0456be3 RN |
568 | r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data); |
569 | if (r) | |
570 | goto err_vid_enable; | |
c3198a5e | 571 | |
cea87b92 | 572 | r = dss_mgr_enable(mgr); |
33ca237f TV |
573 | if (r) |
574 | goto err_mgr_enable; | |
3870c909 | 575 | |
c3198a5e | 576 | return 0; |
33ca237f TV |
577 | |
578 | err_mgr_enable: | |
c0456be3 RN |
579 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
580 | err_vid_enable: | |
33ca237f | 581 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
d3b4aa51 | 582 | err_phy_enable: |
33ca237f | 583 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); |
cca35017 | 584 | err_pll_enable: |
4fbafaf3 | 585 | hdmi_runtime_put(); |
cca35017 | 586 | err_runtime_get: |
17486943 TV |
587 | regulator_disable(hdmi.vdda_hdmi_dac_reg); |
588 | err_vdac_enable: | |
cca35017 TV |
589 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 0); |
590 | gpio_set_value(hdmi.ls_oe_gpio, 0); | |
c3198a5e M |
591 | return -EIO; |
592 | } | |
593 | ||
594 | static void hdmi_power_off(struct omap_dss_device *dssdev) | |
595 | { | |
cea87b92 AT |
596 | struct omap_overlay_manager *mgr = dssdev->output->manager; |
597 | ||
598 | dss_mgr_disable(mgr); | |
c3198a5e | 599 | |
c0456be3 | 600 | hdmi.ip_data.ops->video_disable(&hdmi.ip_data); |
60634a28 M |
601 | hdmi.ip_data.ops->phy_disable(&hdmi.ip_data); |
602 | hdmi.ip_data.ops->pll_disable(&hdmi.ip_data); | |
4fbafaf3 | 603 | hdmi_runtime_put(); |
cca35017 | 604 | |
17486943 TV |
605 | regulator_disable(hdmi.vdda_hdmi_dac_reg); |
606 | ||
cca35017 TV |
607 | gpio_set_value(hdmi.ct_cp_hpd_gpio, 0); |
608 | gpio_set_value(hdmi.ls_oe_gpio, 0); | |
c3198a5e M |
609 | } |
610 | ||
611 | int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
612 | struct omap_video_timings *timings) | |
613 | { | |
614 | struct hdmi_cm cm; | |
615 | ||
616 | cm = hdmi_get_code(timings); | |
617 | if (cm.code == -1) { | |
c3198a5e M |
618 | return -EINVAL; |
619 | } | |
620 | ||
621 | return 0; | |
622 | ||
623 | } | |
624 | ||
7849398f AT |
625 | void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev, |
626 | struct omap_video_timings *timings) | |
c3198a5e M |
627 | { |
628 | struct hdmi_cm cm; | |
7849398f | 629 | const struct hdmi_config *t; |
c3198a5e | 630 | |
ed1aa900 AT |
631 | mutex_lock(&hdmi.lock); |
632 | ||
7849398f AT |
633 | cm = hdmi_get_code(timings); |
634 | hdmi.ip_data.cfg.cm = cm; | |
635 | ||
636 | t = hdmi_get_timings(); | |
637 | if (t != NULL) | |
638 | hdmi.ip_data.cfg = *t; | |
fa70dc5f | 639 | |
ed1aa900 | 640 | mutex_unlock(&hdmi.lock); |
c3198a5e M |
641 | } |
642 | ||
e40402cf | 643 | static void hdmi_dump_regs(struct seq_file *s) |
162874d5 M |
644 | { |
645 | mutex_lock(&hdmi.lock); | |
646 | ||
647 | if (hdmi_runtime_get()) | |
648 | return; | |
649 | ||
650 | hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s); | |
651 | hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s); | |
652 | hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s); | |
653 | hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s); | |
654 | ||
655 | hdmi_runtime_put(); | |
656 | mutex_unlock(&hdmi.lock); | |
657 | } | |
658 | ||
47024565 TV |
659 | int omapdss_hdmi_read_edid(u8 *buf, int len) |
660 | { | |
661 | int r; | |
662 | ||
663 | mutex_lock(&hdmi.lock); | |
664 | ||
665 | r = hdmi_runtime_get(); | |
666 | BUG_ON(r); | |
667 | ||
668 | r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len); | |
669 | ||
670 | hdmi_runtime_put(); | |
671 | mutex_unlock(&hdmi.lock); | |
672 | ||
673 | return r; | |
674 | } | |
675 | ||
759593ff TV |
676 | bool omapdss_hdmi_detect(void) |
677 | { | |
678 | int r; | |
679 | ||
680 | mutex_lock(&hdmi.lock); | |
681 | ||
682 | r = hdmi_runtime_get(); | |
683 | BUG_ON(r); | |
684 | ||
685 | r = hdmi.ip_data.ops->detect(&hdmi.ip_data); | |
686 | ||
687 | hdmi_runtime_put(); | |
688 | mutex_unlock(&hdmi.lock); | |
689 | ||
690 | return r == 1; | |
691 | } | |
692 | ||
c3198a5e M |
693 | int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev) |
694 | { | |
cea87b92 | 695 | struct omap_dss_output *out = dssdev->output; |
c3198a5e M |
696 | int r = 0; |
697 | ||
698 | DSSDBG("ENTER hdmi_display_enable\n"); | |
699 | ||
700 | mutex_lock(&hdmi.lock); | |
701 | ||
cea87b92 AT |
702 | if (out == NULL || out->manager == NULL) { |
703 | DSSERR("failed to enable display: no output/manager\n"); | |
05e1d606 TV |
704 | r = -ENODEV; |
705 | goto err0; | |
706 | } | |
707 | ||
cca35017 | 708 | hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio; |
c49d005b | 709 | |
c3198a5e M |
710 | r = omap_dss_start_device(dssdev); |
711 | if (r) { | |
712 | DSSERR("failed to start device\n"); | |
713 | goto err0; | |
714 | } | |
715 | ||
c3198a5e M |
716 | r = hdmi_power_on(dssdev); |
717 | if (r) { | |
718 | DSSERR("failed to power on device\n"); | |
cca35017 | 719 | goto err1; |
c3198a5e M |
720 | } |
721 | ||
722 | mutex_unlock(&hdmi.lock); | |
723 | return 0; | |
724 | ||
c3198a5e M |
725 | err1: |
726 | omap_dss_stop_device(dssdev); | |
727 | err0: | |
728 | mutex_unlock(&hdmi.lock); | |
729 | return r; | |
730 | } | |
731 | ||
732 | void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev) | |
733 | { | |
734 | DSSDBG("Enter hdmi_display_disable\n"); | |
735 | ||
736 | mutex_lock(&hdmi.lock); | |
737 | ||
738 | hdmi_power_off(dssdev); | |
739 | ||
c3198a5e M |
740 | omap_dss_stop_device(dssdev); |
741 | ||
742 | mutex_unlock(&hdmi.lock); | |
743 | } | |
744 | ||
4fbafaf3 TV |
745 | static int hdmi_get_clocks(struct platform_device *pdev) |
746 | { | |
747 | struct clk *clk; | |
748 | ||
749 | clk = clk_get(&pdev->dev, "sys_clk"); | |
750 | if (IS_ERR(clk)) { | |
751 | DSSERR("can't get sys_clk\n"); | |
752 | return PTR_ERR(clk); | |
753 | } | |
754 | ||
755 | hdmi.sys_clk = clk; | |
756 | ||
4fbafaf3 TV |
757 | return 0; |
758 | } | |
759 | ||
760 | static void hdmi_put_clocks(void) | |
761 | { | |
762 | if (hdmi.sys_clk) | |
763 | clk_put(hdmi.sys_clk); | |
4fbafaf3 TV |
764 | } |
765 | ||
35547626 RN |
766 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
767 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts) | |
768 | { | |
769 | u32 deep_color; | |
25a65359 | 770 | bool deep_color_correct = false; |
35547626 RN |
771 | u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock; |
772 | ||
773 | if (n == NULL || cts == NULL) | |
774 | return -EINVAL; | |
775 | ||
776 | /* TODO: When implemented, query deep color mode here. */ | |
777 | deep_color = 100; | |
778 | ||
25a65359 RN |
779 | /* |
780 | * When using deep color, the default N value (as in the HDMI | |
781 | * specification) yields to an non-integer CTS. Hence, we | |
782 | * modify it while keeping the restrictions described in | |
783 | * section 7.2.1 of the HDMI 1.4a specification. | |
784 | */ | |
35547626 RN |
785 | switch (sample_freq) { |
786 | case 32000: | |
25a65359 RN |
787 | case 48000: |
788 | case 96000: | |
789 | case 192000: | |
790 | if (deep_color == 125) | |
791 | if (pclk == 27027 || pclk == 74250) | |
792 | deep_color_correct = true; | |
793 | if (deep_color == 150) | |
794 | if (pclk == 27027) | |
795 | deep_color_correct = true; | |
35547626 RN |
796 | break; |
797 | case 44100: | |
25a65359 RN |
798 | case 88200: |
799 | case 176400: | |
800 | if (deep_color == 125) | |
801 | if (pclk == 27027) | |
802 | deep_color_correct = true; | |
35547626 RN |
803 | break; |
804 | default: | |
35547626 RN |
805 | return -EINVAL; |
806 | } | |
807 | ||
25a65359 RN |
808 | if (deep_color_correct) { |
809 | switch (sample_freq) { | |
810 | case 32000: | |
811 | *n = 8192; | |
812 | break; | |
813 | case 44100: | |
814 | *n = 12544; | |
815 | break; | |
816 | case 48000: | |
817 | *n = 8192; | |
818 | break; | |
819 | case 88200: | |
820 | *n = 25088; | |
821 | break; | |
822 | case 96000: | |
823 | *n = 16384; | |
824 | break; | |
825 | case 176400: | |
826 | *n = 50176; | |
827 | break; | |
828 | case 192000: | |
829 | *n = 32768; | |
830 | break; | |
831 | default: | |
832 | return -EINVAL; | |
833 | } | |
834 | } else { | |
835 | switch (sample_freq) { | |
836 | case 32000: | |
837 | *n = 4096; | |
838 | break; | |
839 | case 44100: | |
840 | *n = 6272; | |
841 | break; | |
842 | case 48000: | |
843 | *n = 6144; | |
844 | break; | |
845 | case 88200: | |
846 | *n = 12544; | |
847 | break; | |
848 | case 96000: | |
849 | *n = 12288; | |
850 | break; | |
851 | case 176400: | |
852 | *n = 25088; | |
853 | break; | |
854 | case 192000: | |
855 | *n = 24576; | |
856 | break; | |
857 | default: | |
858 | return -EINVAL; | |
859 | } | |
860 | } | |
35547626 RN |
861 | /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */ |
862 | *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10); | |
863 | ||
864 | return 0; | |
865 | } | |
f3a97491 RN |
866 | |
867 | int hdmi_audio_enable(void) | |
868 | { | |
869 | DSSDBG("audio_enable\n"); | |
870 | ||
871 | return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data); | |
872 | } | |
873 | ||
874 | void hdmi_audio_disable(void) | |
875 | { | |
876 | DSSDBG("audio_disable\n"); | |
877 | ||
878 | hdmi.ip_data.ops->audio_disable(&hdmi.ip_data); | |
879 | } | |
880 | ||
881 | int hdmi_audio_start(void) | |
882 | { | |
883 | DSSDBG("audio_start\n"); | |
884 | ||
885 | return hdmi.ip_data.ops->audio_start(&hdmi.ip_data); | |
886 | } | |
887 | ||
888 | void hdmi_audio_stop(void) | |
889 | { | |
890 | DSSDBG("audio_stop\n"); | |
891 | ||
892 | hdmi.ip_data.ops->audio_stop(&hdmi.ip_data); | |
893 | } | |
894 | ||
895 | bool hdmi_mode_has_audio(void) | |
896 | { | |
897 | if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI) | |
898 | return true; | |
899 | else | |
900 | return false; | |
901 | } | |
902 | ||
903 | int hdmi_audio_config(struct omap_dss_audio *audio) | |
904 | { | |
905 | return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio); | |
906 | } | |
907 | ||
35547626 RN |
908 | #endif |
909 | ||
1521653c | 910 | static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev) |
38f3daf6 TV |
911 | { |
912 | struct omap_dss_board_info *pdata = pdev->dev.platform_data; | |
2bbcce5e | 913 | const char *def_disp_name = omapdss_get_default_display_name(); |
1521653c TV |
914 | struct omap_dss_device *def_dssdev; |
915 | int i; | |
916 | ||
917 | def_dssdev = NULL; | |
38f3daf6 TV |
918 | |
919 | for (i = 0; i < pdata->num_devices; ++i) { | |
920 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
921 | ||
922 | if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI) | |
923 | continue; | |
924 | ||
1521653c TV |
925 | if (def_dssdev == NULL) |
926 | def_dssdev = dssdev; | |
cca35017 | 927 | |
1521653c TV |
928 | if (def_disp_name != NULL && |
929 | strcmp(dssdev->name, def_disp_name) == 0) { | |
930 | def_dssdev = dssdev; | |
931 | break; | |
38f3daf6 | 932 | } |
1521653c TV |
933 | } |
934 | ||
935 | return def_dssdev; | |
936 | } | |
937 | ||
938 | static void __init hdmi_probe_pdata(struct platform_device *pdev) | |
939 | { | |
5274484b | 940 | struct omap_dss_device *plat_dssdev; |
1521653c TV |
941 | struct omap_dss_device *dssdev; |
942 | struct omap_dss_hdmi_data *priv; | |
943 | int r; | |
38f3daf6 | 944 | |
5274484b | 945 | plat_dssdev = hdmi_find_dssdev(pdev); |
1521653c | 946 | |
5274484b TV |
947 | if (!plat_dssdev) |
948 | return; | |
949 | ||
950 | dssdev = dss_alloc_and_init_device(&pdev->dev); | |
1521653c TV |
951 | if (!dssdev) |
952 | return; | |
953 | ||
5274484b TV |
954 | dss_copy_device_pdata(dssdev, plat_dssdev); |
955 | ||
1521653c TV |
956 | priv = dssdev->data; |
957 | ||
958 | hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio; | |
959 | hdmi.ls_oe_gpio = priv->ls_oe_gpio; | |
960 | hdmi.hpd_gpio = priv->hpd_gpio; | |
961 | ||
bcb226a9 TV |
962 | dssdev->channel = OMAP_DSS_CHANNEL_DIGIT; |
963 | ||
1521653c TV |
964 | r = hdmi_init_display(dssdev); |
965 | if (r) { | |
966 | DSSERR("device %s init failed: %d\n", dssdev->name, r); | |
5274484b | 967 | dss_put_device(dssdev); |
1521653c TV |
968 | return; |
969 | } | |
970 | ||
5274484b | 971 | r = dss_add_device(dssdev); |
1521653c TV |
972 | if (r) { |
973 | DSSERR("device %s register failed: %d\n", dssdev->name, r); | |
5274484b | 974 | dss_put_device(dssdev); |
1521653c | 975 | return; |
38f3daf6 TV |
976 | } |
977 | } | |
978 | ||
81b87f51 AT |
979 | static void __init hdmi_init_output(struct platform_device *pdev) |
980 | { | |
981 | struct omap_dss_output *out = &hdmi.output; | |
982 | ||
983 | out->pdev = pdev; | |
984 | out->id = OMAP_DSS_OUTPUT_HDMI; | |
985 | out->type = OMAP_DISPLAY_TYPE_HDMI; | |
986 | ||
987 | dss_register_output(out); | |
988 | } | |
989 | ||
990 | static void __exit hdmi_uninit_output(struct platform_device *pdev) | |
991 | { | |
992 | struct omap_dss_output *out = &hdmi.output; | |
993 | ||
994 | dss_unregister_output(out); | |
995 | } | |
996 | ||
c3198a5e | 997 | /* HDMI HW IP initialisation */ |
6e7e8f06 | 998 | static int __init omapdss_hdmihw_probe(struct platform_device *pdev) |
c3198a5e M |
999 | { |
1000 | struct resource *hdmi_mem; | |
38f3daf6 | 1001 | int r; |
c3198a5e | 1002 | |
c3198a5e M |
1003 | hdmi.pdev = pdev; |
1004 | ||
1005 | mutex_init(&hdmi.lock); | |
1006 | ||
1007 | hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0); | |
1008 | if (!hdmi_mem) { | |
1009 | DSSERR("can't get IORESOURCE_MEM HDMI\n"); | |
1010 | return -EINVAL; | |
1011 | } | |
1012 | ||
1013 | /* Base address taken from platform */ | |
95a8aeb6 M |
1014 | hdmi.ip_data.base_wp = ioremap(hdmi_mem->start, |
1015 | resource_size(hdmi_mem)); | |
1016 | if (!hdmi.ip_data.base_wp) { | |
c3198a5e M |
1017 | DSSERR("can't ioremap WP\n"); |
1018 | return -ENOMEM; | |
1019 | } | |
1020 | ||
4fbafaf3 TV |
1021 | r = hdmi_get_clocks(pdev); |
1022 | if (r) { | |
95a8aeb6 | 1023 | iounmap(hdmi.ip_data.base_wp); |
4fbafaf3 TV |
1024 | return r; |
1025 | } | |
1026 | ||
1027 | pm_runtime_enable(&pdev->dev); | |
1028 | ||
95a8aeb6 M |
1029 | hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS; |
1030 | hdmi.ip_data.core_av_offset = HDMI_CORE_AV; | |
1031 | hdmi.ip_data.pll_offset = HDMI_PLLCTRL; | |
1032 | hdmi.ip_data.phy_offset = HDMI_PHY; | |
7849398f | 1033 | |
3a5383a2 | 1034 | mutex_init(&hdmi.ip_data.lock); |
95a8aeb6 | 1035 | |
c3198a5e M |
1036 | hdmi_panel_init(); |
1037 | ||
e40402cf TV |
1038 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
1039 | ||
81b87f51 AT |
1040 | hdmi_init_output(pdev); |
1041 | ||
38f3daf6 | 1042 | hdmi_probe_pdata(pdev); |
35deca3d | 1043 | |
c3198a5e M |
1044 | return 0; |
1045 | } | |
1046 | ||
cca35017 TV |
1047 | static int __exit hdmi_remove_child(struct device *dev, void *data) |
1048 | { | |
1049 | struct omap_dss_device *dssdev = to_dss_device(dev); | |
1050 | hdmi_uninit_display(dssdev); | |
1051 | return 0; | |
1052 | } | |
1053 | ||
6e7e8f06 | 1054 | static int __exit omapdss_hdmihw_remove(struct platform_device *pdev) |
c3198a5e | 1055 | { |
cca35017 TV |
1056 | device_for_each_child(&pdev->dev, NULL, hdmi_remove_child); |
1057 | ||
5274484b | 1058 | dss_unregister_child_devices(&pdev->dev); |
35deca3d | 1059 | |
c3198a5e M |
1060 | hdmi_panel_exit(); |
1061 | ||
81b87f51 AT |
1062 | hdmi_uninit_output(pdev); |
1063 | ||
4fbafaf3 TV |
1064 | pm_runtime_disable(&pdev->dev); |
1065 | ||
1066 | hdmi_put_clocks(); | |
1067 | ||
95a8aeb6 | 1068 | iounmap(hdmi.ip_data.base_wp); |
c3198a5e M |
1069 | |
1070 | return 0; | |
1071 | } | |
1072 | ||
4fbafaf3 TV |
1073 | static int hdmi_runtime_suspend(struct device *dev) |
1074 | { | |
f11766d1 | 1075 | clk_disable_unprepare(hdmi.sys_clk); |
4fbafaf3 TV |
1076 | |
1077 | dispc_runtime_put(); | |
4fbafaf3 TV |
1078 | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static int hdmi_runtime_resume(struct device *dev) | |
1083 | { | |
1084 | int r; | |
1085 | ||
4fbafaf3 TV |
1086 | r = dispc_runtime_get(); |
1087 | if (r < 0) | |
852f0838 | 1088 | return r; |
4fbafaf3 | 1089 | |
f11766d1 | 1090 | clk_prepare_enable(hdmi.sys_clk); |
4fbafaf3 TV |
1091 | |
1092 | return 0; | |
4fbafaf3 TV |
1093 | } |
1094 | ||
1095 | static const struct dev_pm_ops hdmi_pm_ops = { | |
1096 | .runtime_suspend = hdmi_runtime_suspend, | |
1097 | .runtime_resume = hdmi_runtime_resume, | |
1098 | }; | |
1099 | ||
c3198a5e | 1100 | static struct platform_driver omapdss_hdmihw_driver = { |
6e7e8f06 | 1101 | .remove = __exit_p(omapdss_hdmihw_remove), |
c3198a5e M |
1102 | .driver = { |
1103 | .name = "omapdss_hdmi", | |
1104 | .owner = THIS_MODULE, | |
4fbafaf3 | 1105 | .pm = &hdmi_pm_ops, |
c3198a5e M |
1106 | }, |
1107 | }; | |
1108 | ||
6e7e8f06 | 1109 | int __init hdmi_init_platform_driver(void) |
c3198a5e | 1110 | { |
61055d4b | 1111 | return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe); |
c3198a5e M |
1112 | } |
1113 | ||
6e7e8f06 | 1114 | void __exit hdmi_uninit_platform_driver(void) |
c3198a5e | 1115 | { |
04c742c3 | 1116 | platform_driver_unregister(&omapdss_hdmihw_driver); |
c3198a5e | 1117 | } |