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OMAP: DSS2: Have separate irq handlers for DISPC and DSI
[linux-2.6-block.git] / drivers / video / omap2 / dss / dsi.c
CommitLineData
3de7a1dc
TV		 1/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
b9eb5d7d 30#include <linux/semaphore.h>
3de7a1dc
TV		 31#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
3de7a1dc 34#include <linux/wait.h>
18946f62 35#include <linux/workqueue.h>
3de7a1dc
TV		 36
37#include <plat/display.h>
38#include <plat/clock.h>
39
40#include "dss.h"
41
42/*#define VERBOSE_IRQ*/
43#define DSI_CATCH_MISSING_TE
44
3de7a1dc
TV		 45struct dsi_reg { u16 idx; };
46
47#define DSI_REG(idx) ((const struct dsi_reg) { idx })
48
49#define DSI_SZ_REGS SZ_1K
50/* DSI Protocol Engine */
51
52#define DSI_REVISION DSI_REG(0x0000)
53#define DSI_SYSCONFIG DSI_REG(0x0010)
54#define DSI_SYSSTATUS DSI_REG(0x0014)
55#define DSI_IRQSTATUS DSI_REG(0x0018)
56#define DSI_IRQENABLE DSI_REG(0x001C)
57#define DSI_CTRL DSI_REG(0x0040)
58#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
59#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
60#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
61#define DSI_CLK_CTRL DSI_REG(0x0054)
62#define DSI_TIMING1 DSI_REG(0x0058)
63#define DSI_TIMING2 DSI_REG(0x005C)
64#define DSI_VM_TIMING1 DSI_REG(0x0060)
65#define DSI_VM_TIMING2 DSI_REG(0x0064)
66#define DSI_VM_TIMING3 DSI_REG(0x0068)
67#define DSI_CLK_TIMING DSI_REG(0x006C)
68#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
69#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
70#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
71#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
72#define DSI_VM_TIMING4 DSI_REG(0x0080)
73#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
74#define DSI_VM_TIMING5 DSI_REG(0x0088)
75#define DSI_VM_TIMING6 DSI_REG(0x008C)
76#define DSI_VM_TIMING7 DSI_REG(0x0090)
77#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
78#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
79#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
80#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
81#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
82#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
83#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
84#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
85
86/* DSIPHY_SCP */
87
88#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
89#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
90#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
91#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
92
93/* DSI_PLL_CTRL_SCP */
94
95#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
96#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
97#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
98#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
99#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
100
101#define REG_GET(idx, start, end) \
102 FLD_GET(dsi_read_reg(idx), start, end)
103
104#define REG_FLD_MOD(idx, val, start, end) \
105 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
106
107/* Global interrupts */
108#define DSI_IRQ_VC0 (1 << 0)
109#define DSI_IRQ_VC1 (1 << 1)
110#define DSI_IRQ_VC2 (1 << 2)
111#define DSI_IRQ_VC3 (1 << 3)
112#define DSI_IRQ_WAKEUP (1 << 4)
113#define DSI_IRQ_RESYNC (1 << 5)
114#define DSI_IRQ_PLL_LOCK (1 << 7)
115#define DSI_IRQ_PLL_UNLOCK (1 << 8)
116#define DSI_IRQ_PLL_RECALL (1 << 9)
117#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
118#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
119#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
120#define DSI_IRQ_TE_TRIGGER (1 << 16)
121#define DSI_IRQ_ACK_TRIGGER (1 << 17)
122#define DSI_IRQ_SYNC_LOST (1 << 18)
123#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
124#define DSI_IRQ_TA_TIMEOUT (1 << 20)
125#define DSI_IRQ_ERROR_MASK \
126 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
127 DSI_IRQ_TA_TIMEOUT)
128#define DSI_IRQ_CHANNEL_MASK 0xf
129
130/* Virtual channel interrupts */
131#define DSI_VC_IRQ_CS (1 << 0)
132#define DSI_VC_IRQ_ECC_CORR (1 << 1)
133#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
134#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
135#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
136#define DSI_VC_IRQ_BTA (1 << 5)
137#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
138#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
139#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
140#define DSI_VC_IRQ_ERROR_MASK \
141 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
142 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
143 DSI_VC_IRQ_FIFO_TX_UDF)
144
145/* ComplexIO interrupts */
146#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
147#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
148#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
149#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
150#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
151#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
152#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
153#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
154#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
155#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
156#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
157#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
158#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
159#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
164#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
165#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
bbecb50b
TV		 166#define DSI_CIO_IRQ_ERROR_MASK \
167 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
168 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
169 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
170 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
171 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
3de7a1dc
TV		 174
175#define DSI_DT_DCS_SHORT_WRITE_0 0x05
176#define DSI_DT_DCS_SHORT_WRITE_1 0x15
177#define DSI_DT_DCS_READ 0x06
178#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
179#define DSI_DT_NULL_PACKET 0x09
180#define DSI_DT_DCS_LONG_WRITE 0x39
181
182#define DSI_DT_RX_ACK_WITH_ERR 0x02
183#define DSI_DT_RX_DCS_LONG_READ 0x1c
184#define DSI_DT_RX_SHORT_READ_1 0x21
185#define DSI_DT_RX_SHORT_READ_2 0x22
186
187#define FINT_MAX 2100000
188#define FINT_MIN 750000
189#define REGN_MAX (1 << 7)
190#define REGM_MAX ((1 << 11) - 1)
191#define REGM3_MAX (1 << 4)
192#define REGM4_MAX (1 << 4)
193#define LP_DIV_MAX ((1 << 13) - 1)
194
195enum fifo_size {
196 DSI_FIFO_SIZE_0 = 0,
197 DSI_FIFO_SIZE_32 = 1,
198 DSI_FIFO_SIZE_64 = 2,
199 DSI_FIFO_SIZE_96 = 3,
200 DSI_FIFO_SIZE_128 = 4,
201};
202
203enum dsi_vc_mode {
204 DSI_VC_MODE_L4 = 0,
205 DSI_VC_MODE_VP,
206};
207
208struct dsi_update_region {
3de7a1dc
TV		 209 u16 x, y, w, h;
210 struct omap_dss_device *device;
211};
212
dfc0fd8d
TV		 213struct dsi_irq_stats {
214 unsigned long last_reset;
215 unsigned irq_count;
216 unsigned dsi_irqs[32];
217 unsigned vc_irqs[4][32];
218 unsigned cio_irqs[32];
219};
220
3de7a1dc
TV		 221static struct
222{
c8aac01b 223 struct platform_device *pdev;
3de7a1dc 224 void __iomem *base;
affe360d 225 int irq;
3de7a1dc
TV		 226
227 struct dsi_clock_info current_cinfo;
228
229 struct regulator *vdds_dsi_reg;
230
231 struct {
232 enum dsi_vc_mode mode;
233 struct omap_dss_device *dssdev;
234 enum fifo_size fifo_size;
3de7a1dc
TV		 235 } vc[4];
236
237 struct mutex lock;
b9eb5d7d 238 struct semaphore bus_lock;
3de7a1dc
TV		 239
240 unsigned pll_locked;
241
242 struct completion bta_completion;
ab83b14c 243 void (*bta_callback)(void);
3de7a1dc 244
18946f62 245 int update_channel;
3de7a1dc 246 struct dsi_update_region update_region;
3de7a1dc 247
3de7a1dc 248 bool te_enabled;
3de7a1dc 249
0f16aa0a
TV		 250 struct workqueue_struct *workqueue;
251
18946f62
TV		 252 void (*framedone_callback)(int, void *);
253 void *framedone_data;
254
255 struct delayed_work framedone_timeout_work;
256
3de7a1dc
TV		 257#ifdef DSI_CATCH_MISSING_TE
258 struct timer_list te_timer;
259#endif
260
261 unsigned long cache_req_pck;
262 unsigned long cache_clk_freq;
263 struct dsi_clock_info cache_cinfo;
264
265 u32 errors;
266 spinlock_t errors_lock;
267#ifdef DEBUG
268 ktime_t perf_setup_time;
269 ktime_t perf_start_time;
3de7a1dc
TV		 270#endif
271 int debug_read;
272 int debug_write;
dfc0fd8d
TV		 273
274#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
275 spinlock_t irq_stats_lock;
276 struct dsi_irq_stats irq_stats;
277#endif
3de7a1dc
TV		 278} dsi;
279
280#ifdef DEBUG
281static unsigned int dsi_perf;
282module_param_named(dsi_perf, dsi_perf, bool, 0644);
283#endif
284
285static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
286{
287 __raw_writel(val, dsi.base + idx.idx);
288}
289
290static inline u32 dsi_read_reg(const struct dsi_reg idx)
291{
292 return __raw_readl(dsi.base + idx.idx);
293}
294
295
296void dsi_save_context(void)
297{
298}
299
300void dsi_restore_context(void)
301{
302}
303
304void dsi_bus_lock(void)
305{
b9eb5d7d 306 down(&dsi.bus_lock);
3de7a1dc
TV		 307}
308EXPORT_SYMBOL(dsi_bus_lock);
309
310void dsi_bus_unlock(void)
311{
b9eb5d7d 312 up(&dsi.bus_lock);
3de7a1dc
TV		 313}
314EXPORT_SYMBOL(dsi_bus_unlock);
315
4f765023
TV		 316static bool dsi_bus_is_locked(void)
317{
b9eb5d7d 318 return dsi.bus_lock.count == 0;
4f765023
TV		 319}
320
3de7a1dc
TV		 321static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
322 int value)
323{
324 int t = 100000;
325
326 while (REG_GET(idx, bitnum, bitnum) != value) {
327 if (--t == 0)
328 return !value;
329 }
330
331 return value;
332}
333
334#ifdef DEBUG
335static void dsi_perf_mark_setup(void)
336{
337 dsi.perf_setup_time = ktime_get();
338}
339
340static void dsi_perf_mark_start(void)
341{
342 dsi.perf_start_time = ktime_get();
343}
344
3de7a1dc
TV		 345static void dsi_perf_show(const char *name)
346{
347 ktime_t t, setup_time, trans_time;
348 u32 total_bytes;
349 u32 setup_us, trans_us, total_us;
350
351 if (!dsi_perf)
352 return;
353
3de7a1dc
TV		 354 t = ktime_get();
355
356 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
357 setup_us = (u32)ktime_to_us(setup_time);
358 if (setup_us == 0)
359 setup_us = 1;
360
361 trans_time = ktime_sub(t, dsi.perf_start_time);
362 trans_us = (u32)ktime_to_us(trans_time);
363 if (trans_us == 0)
364 trans_us = 1;
365
366 total_us = setup_us + trans_us;
367
18946f62
TV		 368 total_bytes = dsi.update_region.w *
369 dsi.update_region.h *
370 dsi.update_region.device->ctrl.pixel_size / 8;
3de7a1dc 371
1bbb275e
TV		 372 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
373 "%u bytes, %u kbytes/sec\n",
374 name,
375 setup_us,
376 trans_us,
377 total_us,
378 1000*1000 / total_us,
379 total_bytes,
380 total_bytes * 1000 / total_us);
3de7a1dc
TV		 381}
382#else
383#define dsi_perf_mark_setup()
384#define dsi_perf_mark_start()
3de7a1dc
TV		 385#define dsi_perf_show(x)
386#endif
387
388static void print_irq_status(u32 status)
389{
390#ifndef VERBOSE_IRQ
391 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
392 return;
393#endif
394 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
395
396#define PIS(x) \
397 if (status & DSI_IRQ_##x) \
398 printk(#x " ");
399#ifdef VERBOSE_IRQ
400 PIS(VC0);
401 PIS(VC1);
402 PIS(VC2);
403 PIS(VC3);
404#endif
405 PIS(WAKEUP);
406 PIS(RESYNC);
407 PIS(PLL_LOCK);
408 PIS(PLL_UNLOCK);
409 PIS(PLL_RECALL);
410 PIS(COMPLEXIO_ERR);
411 PIS(HS_TX_TIMEOUT);
412 PIS(LP_RX_TIMEOUT);
413 PIS(TE_TRIGGER);
414 PIS(ACK_TRIGGER);
415 PIS(SYNC_LOST);
416 PIS(LDO_POWER_GOOD);
417 PIS(TA_TIMEOUT);
418#undef PIS
419
420 printk("\n");
421}
422
423static void print_irq_status_vc(int channel, u32 status)
424{
425#ifndef VERBOSE_IRQ
426 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
427 return;
428#endif
429 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
430
431#define PIS(x) \
432 if (status & DSI_VC_IRQ_##x) \
433 printk(#x " ");
434 PIS(CS);
435 PIS(ECC_CORR);
436#ifdef VERBOSE_IRQ
437 PIS(PACKET_SENT);
438#endif
439 PIS(FIFO_TX_OVF);
440 PIS(FIFO_RX_OVF);
441 PIS(BTA);
442 PIS(ECC_NO_CORR);
443 PIS(FIFO_TX_UDF);
444 PIS(PP_BUSY_CHANGE);
445#undef PIS
446 printk("\n");
447}
448
449static void print_irq_status_cio(u32 status)
450{
451 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
452
453#define PIS(x) \
454 if (status & DSI_CIO_IRQ_##x) \
455 printk(#x " ");
456 PIS(ERRSYNCESC1);
457 PIS(ERRSYNCESC2);
458 PIS(ERRSYNCESC3);
459 PIS(ERRESC1);
460 PIS(ERRESC2);
461 PIS(ERRESC3);
462 PIS(ERRCONTROL1);
463 PIS(ERRCONTROL2);
464 PIS(ERRCONTROL3);
465 PIS(STATEULPS1);
466 PIS(STATEULPS2);
467 PIS(STATEULPS3);
468 PIS(ERRCONTENTIONLP0_1);
469 PIS(ERRCONTENTIONLP1_1);
470 PIS(ERRCONTENTIONLP0_2);
471 PIS(ERRCONTENTIONLP1_2);
472 PIS(ERRCONTENTIONLP0_3);
473 PIS(ERRCONTENTIONLP1_3);
474 PIS(ULPSACTIVENOT_ALL0);
475 PIS(ULPSACTIVENOT_ALL1);
476#undef PIS
477
478 printk("\n");
479}
480
481static int debug_irq;
482
483/* called from dss */
affe360d 484static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
3de7a1dc
TV		 485{
486 u32 irqstatus, vcstatus, ciostatus;
487 int i;
488
489 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
490
affe360d 491 /* IRQ is not for us */
492 if (!irqstatus)
493 return IRQ_NONE;
494
dfc0fd8d
TV		 495#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
496 spin_lock(&dsi.irq_stats_lock);
497 dsi.irq_stats.irq_count++;
498 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
499#endif
500
3de7a1dc
TV		 501 if (irqstatus & DSI_IRQ_ERROR_MASK) {
502 DSSERR("DSI error, irqstatus %x\n", irqstatus);
503 print_irq_status(irqstatus);
504 spin_lock(&dsi.errors_lock);
505 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
506 spin_unlock(&dsi.errors_lock);
507 } else if (debug_irq) {
508 print_irq_status(irqstatus);
509 }
510
511#ifdef DSI_CATCH_MISSING_TE
512 if (irqstatus & DSI_IRQ_TE_TRIGGER)
513 del_timer(&dsi.te_timer);
514#endif
515
516 for (i = 0; i < 4; ++i) {
517 if ((irqstatus & (1<<i)) == 0)
518 continue;
519
520 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
521
dfc0fd8d
TV		 522#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
523 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
524#endif
525
ab83b14c 526 if (vcstatus & DSI_VC_IRQ_BTA) {
3de7a1dc
TV		 527 complete(&dsi.bta_completion);
528
ab83b14c
TV		 529 if (dsi.bta_callback)
530 dsi.bta_callback();
531 }
532
3de7a1dc
TV		 533 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
534 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
535 i, vcstatus);
536 print_irq_status_vc(i, vcstatus);
537 } else if (debug_irq) {
538 print_irq_status_vc(i, vcstatus);
539 }
540
541 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
542 /* flush posted write */
543 dsi_read_reg(DSI_VC_IRQSTATUS(i));
544 }
545
546 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
547 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
548
dfc0fd8d
TV		 549#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
550 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
551#endif
552
3de7a1dc
TV		 553 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
554 /* flush posted write */
555 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
556
bbecb50b
TV		 557 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
558 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
559 print_irq_status_cio(ciostatus);
560 } else if (debug_irq) {
561 print_irq_status_cio(ciostatus);
562 }
3de7a1dc
TV		 563 }
564
565 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
566 /* flush posted write */
567 dsi_read_reg(DSI_IRQSTATUS);
dfc0fd8d
TV		 568
569#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
570 spin_unlock(&dsi.irq_stats_lock);
571#endif
affe360d 572 return IRQ_HANDLED;
3de7a1dc
TV		 573}
574
3de7a1dc
TV		 575static void _dsi_initialize_irq(void)
576{
577 u32 l;
578 int i;
579
580 /* disable all interrupts */
581 dsi_write_reg(DSI_IRQENABLE, 0);
582 for (i = 0; i < 4; ++i)
583 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
584 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
585
586 /* clear interrupt status */
587 l = dsi_read_reg(DSI_IRQSTATUS);
588 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
589
590 for (i = 0; i < 4; ++i) {
591 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
592 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
593 }
594
595 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
596 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
597
598 /* enable error irqs */
599 l = DSI_IRQ_ERROR_MASK;
600#ifdef DSI_CATCH_MISSING_TE
601 l |= DSI_IRQ_TE_TRIGGER;
602#endif
603 dsi_write_reg(DSI_IRQENABLE, l);
604
605 l = DSI_VC_IRQ_ERROR_MASK;
606 for (i = 0; i < 4; ++i)
607 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
608
bbecb50b
TV		 609 l = DSI_CIO_IRQ_ERROR_MASK;
610 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
3de7a1dc
TV		 611}
612
613static u32 dsi_get_errors(void)
614{
615 unsigned long flags;
616 u32 e;
617 spin_lock_irqsave(&dsi.errors_lock, flags);
618 e = dsi.errors;
619 dsi.errors = 0;
620 spin_unlock_irqrestore(&dsi.errors_lock, flags);
621 return e;
622}
623
624static void dsi_vc_enable_bta_irq(int channel)
625{
626 u32 l;
627
628 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
629
630 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
631 l |= DSI_VC_IRQ_BTA;
632 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
633}
634
635static void dsi_vc_disable_bta_irq(int channel)
636{
637 u32 l;
638
639 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
640 l &= ~DSI_VC_IRQ_BTA;
641 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
642}
643
644/* DSI func clock. this could also be DSI2_PLL_FCLK */
645static inline void enable_clocks(bool enable)
646{
647 if (enable)
6af9cd14 648 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc 649 else
6af9cd14 650 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 651}
652
653/* source clock for DSI PLL. this could also be PCLKFREE */
654static inline void dsi_enable_pll_clock(bool enable)
655{
656 if (enable)
6af9cd14 657 dss_clk_enable(DSS_CLK_SYSCK);
3de7a1dc 658 else
6af9cd14 659 dss_clk_disable(DSS_CLK_SYSCK);
3de7a1dc
TV		 660
661 if (enable && dsi.pll_locked) {
662 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
663 DSSERR("cannot lock PLL when enabling clocks\n");
664 }
665}
666
667#ifdef DEBUG
668static void _dsi_print_reset_status(void)
669{
670 u32 l;
671
672 if (!dss_debug)
673 return;
674
675 /* A dummy read using the SCP interface to any DSIPHY register is
676 * required after DSIPHY reset to complete the reset of the DSI complex
677 * I/O. */
678 l = dsi_read_reg(DSI_DSIPHY_CFG5);
679
680 printk(KERN_DEBUG "DSI resets: ");
681
682 l = dsi_read_reg(DSI_PLL_STATUS);
683 printk("PLL (%d) ", FLD_GET(l, 0, 0));
684
685 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
686 printk("CIO (%d) ", FLD_GET(l, 29, 29));
687
688 l = dsi_read_reg(DSI_DSIPHY_CFG5);
689 printk("PHY (%x, %d, %d, %d)\n",
690 FLD_GET(l, 28, 26),
691 FLD_GET(l, 29, 29),
692 FLD_GET(l, 30, 30),
693 FLD_GET(l, 31, 31));
694}
695#else
696#define _dsi_print_reset_status()
697#endif
698
699static inline int dsi_if_enable(bool enable)
700{
701 DSSDBG("dsi_if_enable(%d)\n", enable);
702
703 enable = enable ? 1 : 0;
704 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
705
706 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
707 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
708 return -EIO;
709 }
710
711 return 0;
712}
713
714unsigned long dsi_get_dsi1_pll_rate(void)
715{
716 return dsi.current_cinfo.dsi1_pll_fclk;
717}
718
719static unsigned long dsi_get_dsi2_pll_rate(void)
720{
721 return dsi.current_cinfo.dsi2_pll_fclk;
722}
723
724static unsigned long dsi_get_txbyteclkhs(void)
725{
726 return dsi.current_cinfo.clkin4ddr / 16;
727}
728
729static unsigned long dsi_fclk_rate(void)
730{
731 unsigned long r;
732
63cf28ac 733 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
3de7a1dc 734 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
6af9cd14 735 r = dss_clk_get_rate(DSS_CLK_FCK);
3de7a1dc
TV		 736 } else {
737 /* DSI FCLK source is DSI2_PLL_FCLK */
738 r = dsi_get_dsi2_pll_rate();
739 }
740
741 return r;
742}
743
744static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
745{
746 unsigned long dsi_fclk;
747 unsigned lp_clk_div;
748 unsigned long lp_clk;
749
750 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
751
752 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
753 return -EINVAL;
754
755 dsi_fclk = dsi_fclk_rate();
756
757 lp_clk = dsi_fclk / 2 / lp_clk_div;
758
759 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
760 dsi.current_cinfo.lp_clk = lp_clk;
761 dsi.current_cinfo.lp_clk_div = lp_clk_div;
762
763 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
764
765 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
766 21, 21); /* LP_RX_SYNCHRO_ENABLE */
767
768 return 0;
769}
770
771
772enum dsi_pll_power_state {
773 DSI_PLL_POWER_OFF = 0x0,
774 DSI_PLL_POWER_ON_HSCLK = 0x1,
775 DSI_PLL_POWER_ON_ALL = 0x2,
776 DSI_PLL_POWER_ON_DIV = 0x3,
777};
778
779static int dsi_pll_power(enum dsi_pll_power_state state)
780{
781 int t = 0;
782
783 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
784
785 /* PLL_PWR_STATUS */
786 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
24be78b3 787 if (++t > 1000) {
3de7a1dc
TV		 788 DSSERR("Failed to set DSI PLL power mode to %d\n",
789 state);
790 return -ENODEV;
791 }
24be78b3 792 udelay(1);
3de7a1dc
TV		 793 }
794
795 return 0;
796}
797
798/* calculate clock rates using dividers in cinfo */
ff1b2cde
SS		 799static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
800 struct dsi_clock_info *cinfo)
3de7a1dc
TV		 801{
802 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
803 return -EINVAL;
804
805 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
806 return -EINVAL;
807
808 if (cinfo->regm3 > REGM3_MAX)
809 return -EINVAL;
810
811 if (cinfo->regm4 > REGM4_MAX)
812 return -EINVAL;
813
814 if (cinfo->use_dss2_fck) {
6af9cd14 815 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
3de7a1dc
TV		 816 /* XXX it is unclear if highfreq should be used
817 * with DSS2_FCK source also */
818 cinfo->highfreq = 0;
819 } else {
ff1b2cde 820 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
3de7a1dc
TV		 821
822 if (cinfo->clkin < 32000000)
823 cinfo->highfreq = 0;
824 else
825 cinfo->highfreq = 1;
826 }
827
828 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
829
830 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
831 return -EINVAL;
832
833 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
834
835 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
836 return -EINVAL;
837
838 if (cinfo->regm3 > 0)
839 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
840 else
841 cinfo->dsi1_pll_fclk = 0;
842
843 if (cinfo->regm4 > 0)
844 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
845 else
846 cinfo->dsi2_pll_fclk = 0;
847
848 return 0;
849}
850
851int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
852 struct dsi_clock_info *dsi_cinfo,
853 struct dispc_clock_info *dispc_cinfo)
854{
855 struct dsi_clock_info cur, best;
856 struct dispc_clock_info best_dispc;
857 int min_fck_per_pck;
858 int match = 0;
859 unsigned long dss_clk_fck2;
860
6af9cd14 861 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
3de7a1dc
TV		 862
863 if (req_pck == dsi.cache_req_pck &&
864 dsi.cache_cinfo.clkin == dss_clk_fck2) {
865 DSSDBG("DSI clock info found from cache\n");
866 *dsi_cinfo = dsi.cache_cinfo;
867 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
868 dispc_cinfo);
869 return 0;
870 }
871
872 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
873
874 if (min_fck_per_pck &&
875 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
876 DSSERR("Requested pixel clock not possible with the current "
877 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
878 "the constraint off.\n");
879 min_fck_per_pck = 0;
880 }
881
882 DSSDBG("dsi_pll_calc\n");
883
884retry:
885 memset(&best, 0, sizeof(best));
886 memset(&best_dispc, 0, sizeof(best_dispc));
887
888 memset(&cur, 0, sizeof(cur));
889 cur.clkin = dss_clk_fck2;
890 cur.use_dss2_fck = 1;
891 cur.highfreq = 0;
892
893 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
894 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
895 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
896 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
897 if (cur.highfreq == 0)
898 cur.fint = cur.clkin / cur.regn;
899 else
900 cur.fint = cur.clkin / (2 * cur.regn);
901
902 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
903 continue;
904
905 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
906 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
907 unsigned long a, b;
908
909 a = 2 * cur.regm * (cur.clkin/1000);
910 b = cur.regn * (cur.highfreq + 1);
911 cur.clkin4ddr = a / b * 1000;
912
913 if (cur.clkin4ddr > 1800 * 1000 * 1000)
914 break;
915
916 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
917 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
918 ++cur.regm3) {
919 struct dispc_clock_info cur_dispc;
920 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
921
922 /* this will narrow down the search a bit,
923 * but still give pixclocks below what was
924 * requested */
925 if (cur.dsi1_pll_fclk < req_pck)
926 break;
927
928 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
929 continue;
930
931 if (min_fck_per_pck &&
932 cur.dsi1_pll_fclk <
933 req_pck * min_fck_per_pck)
934 continue;
935
936 match = 1;
937
938 dispc_find_clk_divs(is_tft, req_pck,
939 cur.dsi1_pll_fclk,
940 &cur_dispc);
941
942 if (abs(cur_dispc.pck - req_pck) <
943 abs(best_dispc.pck - req_pck)) {
944 best = cur;
945 best_dispc = cur_dispc;
946
947 if (cur_dispc.pck == req_pck)
948 goto found;
949 }
950 }
951 }
952 }
953found:
954 if (!match) {
955 if (min_fck_per_pck) {
956 DSSERR("Could not find suitable clock settings.\n"
957 "Turning FCK/PCK constraint off and"
958 "trying again.\n");
959 min_fck_per_pck = 0;
960 goto retry;
961 }
962
963 DSSERR("Could not find suitable clock settings.\n");
964
965 return -EINVAL;
966 }
967
968 /* DSI2_PLL_FCLK (regm4) is not used */
969 best.regm4 = 0;
970 best.dsi2_pll_fclk = 0;
971
972 if (dsi_cinfo)
973 *dsi_cinfo = best;
974 if (dispc_cinfo)
975 *dispc_cinfo = best_dispc;
976
977 dsi.cache_req_pck = req_pck;
978 dsi.cache_clk_freq = 0;
979 dsi.cache_cinfo = best;
980
981 return 0;
982}
983
984int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
985{
986 int r = 0;
987 u32 l;
988 int f;
989
990 DSSDBGF();
991
992 dsi.current_cinfo.fint = cinfo->fint;
993 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
994 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
995 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
996
997 dsi.current_cinfo.regn = cinfo->regn;
998 dsi.current_cinfo.regm = cinfo->regm;
999 dsi.current_cinfo.regm3 = cinfo->regm3;
1000 dsi.current_cinfo.regm4 = cinfo->regm4;
1001
1002 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1003
1004 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1005 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1006 cinfo->clkin,
1007 cinfo->highfreq);
1008
1009 /* DSIPHY == CLKIN4DDR */
1010 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1011 cinfo->regm,
1012 cinfo->regn,
1013 cinfo->clkin,
1014 cinfo->highfreq + 1,
1015 cinfo->clkin4ddr);
1016
1017 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1018 cinfo->clkin4ddr / 1000 / 1000 / 2);
1019
1020 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1021
1022 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1023 cinfo->regm3, cinfo->dsi1_pll_fclk);
1024 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1025 cinfo->regm4, cinfo->dsi2_pll_fclk);
1026
1027 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1028
1029 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1030 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1031 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1032 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1033 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1034 22, 19); /* DSI_CLOCK_DIV */
1035 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1036 26, 23); /* DSIPROTO_CLOCK_DIV */
1037 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1038
1039 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1040 if (cinfo->fint < 1000000)
1041 f = 0x3;
1042 else if (cinfo->fint < 1250000)
1043 f = 0x4;
1044 else if (cinfo->fint < 1500000)
1045 f = 0x5;
1046 else if (cinfo->fint < 1750000)
1047 f = 0x6;
1048 else
1049 f = 0x7;
1050
1051 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1052 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1053 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1054 11, 11); /* DSI_PLL_CLKSEL */
1055 l = FLD_MOD(l, cinfo->highfreq,
1056 12, 12); /* DSI_PLL_HIGHFREQ */
1057 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1058 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1059 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1060 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1061
1062 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1063
1064 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1065 DSSERR("dsi pll go bit not going down.\n");
1066 r = -EIO;
1067 goto err;
1068 }
1069
1070 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1071 DSSERR("cannot lock PLL\n");
1072 r = -EIO;
1073 goto err;
1074 }
1075
1076 dsi.pll_locked = 1;
1077
1078 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1079 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1080 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1081 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1082 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1083 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1084 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1085 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1086 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1087 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1088 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1089 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1090 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1091 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1092 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1093 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1094
1095 DSSDBG("PLL config done\n");
1096err:
1097 return r;
1098}
1099
1100int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1101 bool enable_hsdiv)
1102{
1103 int r = 0;
1104 enum dsi_pll_power_state pwstate;
1105
1106 DSSDBG("PLL init\n");
1107
1108 enable_clocks(1);
1109 dsi_enable_pll_clock(1);
1110
1111 r = regulator_enable(dsi.vdds_dsi_reg);
1112 if (r)
1113 goto err0;
1114
1115 /* XXX PLL does not come out of reset without this... */
1116 dispc_pck_free_enable(1);
1117
1118 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1119 DSSERR("PLL not coming out of reset.\n");
1120 r = -ENODEV;
481dfa0e 1121 dispc_pck_free_enable(0);
3de7a1dc
TV		 1122 goto err1;
1123 }
1124
1125 /* XXX ... but if left on, we get problems when planes do not
1126 * fill the whole display. No idea about this */
1127 dispc_pck_free_enable(0);
1128
1129 if (enable_hsclk && enable_hsdiv)
1130 pwstate = DSI_PLL_POWER_ON_ALL;
1131 else if (enable_hsclk)
1132 pwstate = DSI_PLL_POWER_ON_HSCLK;
1133 else if (enable_hsdiv)
1134 pwstate = DSI_PLL_POWER_ON_DIV;
1135 else
1136 pwstate = DSI_PLL_POWER_OFF;
1137
1138 r = dsi_pll_power(pwstate);
1139
1140 if (r)
1141 goto err1;
1142
1143 DSSDBG("PLL init done\n");
1144
1145 return 0;
1146err1:
1147 regulator_disable(dsi.vdds_dsi_reg);
1148err0:
1149 enable_clocks(0);
1150 dsi_enable_pll_clock(0);
1151 return r;
1152}
1153
1154void dsi_pll_uninit(void)
1155{
1156 enable_clocks(0);
1157 dsi_enable_pll_clock(0);
1158
1159 dsi.pll_locked = 0;
1160 dsi_pll_power(DSI_PLL_POWER_OFF);
1161 regulator_disable(dsi.vdds_dsi_reg);
1162 DSSDBG("PLL uninit done\n");
1163}
1164
1165void dsi_dump_clocks(struct seq_file *s)
1166{
1167 int clksel;
1168 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1169
1170 enable_clocks(1);
1171
1172 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1173
1174 seq_printf(s, "- DSI PLL -\n");
1175
1176 seq_printf(s, "dsi pll source = %s\n",
1177 clksel == 0 ?
1178 "dss2_alwon_fclk" : "pclkfree");
1179
1180 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1181
1182 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1183 cinfo->clkin4ddr, cinfo->regm);
1184
1185 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1186 cinfo->dsi1_pll_fclk,
1187 cinfo->regm3,
63cf28ac
TV		 1188 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1189 "off" : "on");
3de7a1dc
TV		 1190
1191 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1192 cinfo->dsi2_pll_fclk,
1193 cinfo->regm4,
63cf28ac
TV		 1194 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1195 "off" : "on");
3de7a1dc
TV		 1196
1197 seq_printf(s, "- DSI -\n");
1198
1199 seq_printf(s, "dsi fclk source = %s\n",
63cf28ac 1200 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
3de7a1dc
TV		 1201 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1202
1203 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1204
1205 seq_printf(s, "DDR_CLK\t\t%lu\n",
1206 cinfo->clkin4ddr / 4);
1207
1208 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1209
1210 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1211
1212 seq_printf(s, "VP_CLK\t\t%lu\n"
1213 "VP_PCLK\t\t%lu\n",
ff1b2cde
SS		 1214 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1215 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
3de7a1dc
TV		 1216
1217 enable_clocks(0);
1218}
1219
dfc0fd8d
TV		 1220#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1221void dsi_dump_irqs(struct seq_file *s)
1222{
1223 unsigned long flags;
1224 struct dsi_irq_stats stats;
1225
1226 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1227
1228 stats = dsi.irq_stats;
1229 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1230 dsi.irq_stats.last_reset = jiffies;
1231
1232 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1233
1234 seq_printf(s, "period %u ms\n",
1235 jiffies_to_msecs(jiffies - stats.last_reset));
1236
1237 seq_printf(s, "irqs %d\n", stats.irq_count);
1238#define PIS(x) \
1239 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1240
1241 seq_printf(s, "-- DSI interrupts --\n");
1242 PIS(VC0);
1243 PIS(VC1);
1244 PIS(VC2);
1245 PIS(VC3);
1246 PIS(WAKEUP);
1247 PIS(RESYNC);
1248 PIS(PLL_LOCK);
1249 PIS(PLL_UNLOCK);
1250 PIS(PLL_RECALL);
1251 PIS(COMPLEXIO_ERR);
1252 PIS(HS_TX_TIMEOUT);
1253 PIS(LP_RX_TIMEOUT);
1254 PIS(TE_TRIGGER);
1255 PIS(ACK_TRIGGER);
1256 PIS(SYNC_LOST);
1257 PIS(LDO_POWER_GOOD);
1258 PIS(TA_TIMEOUT);
1259#undef PIS
1260
1261#define PIS(x) \
1262 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1263 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1264 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1265 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1266 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1267
1268 seq_printf(s, "-- VC interrupts --\n");
1269 PIS(CS);
1270 PIS(ECC_CORR);
1271 PIS(PACKET_SENT);
1272 PIS(FIFO_TX_OVF);
1273 PIS(FIFO_RX_OVF);
1274 PIS(BTA);
1275 PIS(ECC_NO_CORR);
1276 PIS(FIFO_TX_UDF);
1277 PIS(PP_BUSY_CHANGE);
1278#undef PIS
1279
1280#define PIS(x) \
1281 seq_printf(s, "%-20s %10d\n", #x, \
1282 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1283
1284 seq_printf(s, "-- CIO interrupts --\n");
1285 PIS(ERRSYNCESC1);
1286 PIS(ERRSYNCESC2);
1287 PIS(ERRSYNCESC3);
1288 PIS(ERRESC1);
1289 PIS(ERRESC2);
1290 PIS(ERRESC3);
1291 PIS(ERRCONTROL1);
1292 PIS(ERRCONTROL2);
1293 PIS(ERRCONTROL3);
1294 PIS(STATEULPS1);
1295 PIS(STATEULPS2);
1296 PIS(STATEULPS3);
1297 PIS(ERRCONTENTIONLP0_1);
1298 PIS(ERRCONTENTIONLP1_1);
1299 PIS(ERRCONTENTIONLP0_2);
1300 PIS(ERRCONTENTIONLP1_2);
1301 PIS(ERRCONTENTIONLP0_3);
1302 PIS(ERRCONTENTIONLP1_3);
1303 PIS(ULPSACTIVENOT_ALL0);
1304 PIS(ULPSACTIVENOT_ALL1);
1305#undef PIS
1306}
1307#endif
1308
3de7a1dc
TV		 1309void dsi_dump_regs(struct seq_file *s)
1310{
1311#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1312
6af9cd14 1313 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 1314
1315 DUMPREG(DSI_REVISION);
1316 DUMPREG(DSI_SYSCONFIG);
1317 DUMPREG(DSI_SYSSTATUS);
1318 DUMPREG(DSI_IRQSTATUS);
1319 DUMPREG(DSI_IRQENABLE);
1320 DUMPREG(DSI_CTRL);
1321 DUMPREG(DSI_COMPLEXIO_CFG1);
1322 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1323 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1324 DUMPREG(DSI_CLK_CTRL);
1325 DUMPREG(DSI_TIMING1);
1326 DUMPREG(DSI_TIMING2);
1327 DUMPREG(DSI_VM_TIMING1);
1328 DUMPREG(DSI_VM_TIMING2);
1329 DUMPREG(DSI_VM_TIMING3);
1330 DUMPREG(DSI_CLK_TIMING);
1331 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1332 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1333 DUMPREG(DSI_COMPLEXIO_CFG2);
1334 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1335 DUMPREG(DSI_VM_TIMING4);
1336 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1337 DUMPREG(DSI_VM_TIMING5);
1338 DUMPREG(DSI_VM_TIMING6);
1339 DUMPREG(DSI_VM_TIMING7);
1340 DUMPREG(DSI_STOPCLK_TIMING);
1341
1342 DUMPREG(DSI_VC_CTRL(0));
1343 DUMPREG(DSI_VC_TE(0));
1344 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1345 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1346 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1347 DUMPREG(DSI_VC_IRQSTATUS(0));
1348 DUMPREG(DSI_VC_IRQENABLE(0));
1349
1350 DUMPREG(DSI_VC_CTRL(1));
1351 DUMPREG(DSI_VC_TE(1));
1352 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1353 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1354 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1355 DUMPREG(DSI_VC_IRQSTATUS(1));
1356 DUMPREG(DSI_VC_IRQENABLE(1));
1357
1358 DUMPREG(DSI_VC_CTRL(2));
1359 DUMPREG(DSI_VC_TE(2));
1360 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1361 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1362 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1363 DUMPREG(DSI_VC_IRQSTATUS(2));
1364 DUMPREG(DSI_VC_IRQENABLE(2));
1365
1366 DUMPREG(DSI_VC_CTRL(3));
1367 DUMPREG(DSI_VC_TE(3));
1368 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1369 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1370 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1371 DUMPREG(DSI_VC_IRQSTATUS(3));
1372 DUMPREG(DSI_VC_IRQENABLE(3));
1373
1374 DUMPREG(DSI_DSIPHY_CFG0);
1375 DUMPREG(DSI_DSIPHY_CFG1);
1376 DUMPREG(DSI_DSIPHY_CFG2);
1377 DUMPREG(DSI_DSIPHY_CFG5);
1378
1379 DUMPREG(DSI_PLL_CONTROL);
1380 DUMPREG(DSI_PLL_STATUS);
1381 DUMPREG(DSI_PLL_GO);
1382 DUMPREG(DSI_PLL_CONFIGURATION1);
1383 DUMPREG(DSI_PLL_CONFIGURATION2);
1384
6af9cd14 1385 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 1386#undef DUMPREG
1387}
1388
1389enum dsi_complexio_power_state {
1390 DSI_COMPLEXIO_POWER_OFF = 0x0,
1391 DSI_COMPLEXIO_POWER_ON = 0x1,
1392 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1393};
1394
1395static int dsi_complexio_power(enum dsi_complexio_power_state state)
1396{
1397 int t = 0;
1398
1399 /* PWR_CMD */
1400 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1401
1402 /* PWR_STATUS */
1403 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
24be78b3 1404 if (++t > 1000) {
3de7a1dc
TV		 1405 DSSERR("failed to set complexio power state to "
1406 "%d\n", state);
1407 return -ENODEV;
1408 }
24be78b3 1409 udelay(1);
3de7a1dc
TV		 1410 }
1411
1412 return 0;
1413}
1414
1415static void dsi_complexio_config(struct omap_dss_device *dssdev)
1416{
1417 u32 r;
1418
1419 int clk_lane = dssdev->phy.dsi.clk_lane;
1420 int data1_lane = dssdev->phy.dsi.data1_lane;
1421 int data2_lane = dssdev->phy.dsi.data2_lane;
1422 int clk_pol = dssdev->phy.dsi.clk_pol;
1423 int data1_pol = dssdev->phy.dsi.data1_pol;
1424 int data2_pol = dssdev->phy.dsi.data2_pol;
1425
1426 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1427 r = FLD_MOD(r, clk_lane, 2, 0);
1428 r = FLD_MOD(r, clk_pol, 3, 3);
1429 r = FLD_MOD(r, data1_lane, 6, 4);
1430 r = FLD_MOD(r, data1_pol, 7, 7);
1431 r = FLD_MOD(r, data2_lane, 10, 8);
1432 r = FLD_MOD(r, data2_pol, 11, 11);
1433 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1434
1435 /* The configuration of the DSI complex I/O (number of data lanes,
1436 position, differential order) should not be changed while
1437 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1438 the hardware to take into account a new configuration of the complex
1439 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1440 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1441 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1442 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1443 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1444 DSI complex I/O configuration is unknown. */
1445
1446 /*
1447 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1448 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1449 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1450 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1451 */
1452}
1453
1454static inline unsigned ns2ddr(unsigned ns)
1455{
1456 /* convert time in ns to ddr ticks, rounding up */
1457 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1458 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1459}
1460
1461static inline unsigned ddr2ns(unsigned ddr)
1462{
1463 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1464 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1465}
1466
1467static void dsi_complexio_timings(void)
1468{
1469 u32 r;
1470 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1471 u32 tlpx_half, tclk_trail, tclk_zero;
1472 u32 tclk_prepare;
1473
1474 /* calculate timings */
1475
1476 /* 1 * DDR_CLK = 2 * UI */
1477
1478 /* min 40ns + 4*UI max 85ns + 6*UI */
1479 ths_prepare = ns2ddr(70) + 2;
1480
1481 /* min 145ns + 10*UI */
1482 ths_prepare_ths_zero = ns2ddr(175) + 2;
1483
1484 /* min max(8*UI, 60ns+4*UI) */
1485 ths_trail = ns2ddr(60) + 5;
1486
1487 /* min 100ns */
1488 ths_exit = ns2ddr(145);
1489
1490 /* tlpx min 50n */
1491 tlpx_half = ns2ddr(25);
1492
1493 /* min 60ns */
1494 tclk_trail = ns2ddr(60) + 2;
1495
1496 /* min 38ns, max 95ns */
1497 tclk_prepare = ns2ddr(65);
1498
1499 /* min tclk-prepare + tclk-zero = 300ns */
1500 tclk_zero = ns2ddr(260);
1501
1502 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1503 ths_prepare, ddr2ns(ths_prepare),
1504 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1505 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1506 ths_trail, ddr2ns(ths_trail),
1507 ths_exit, ddr2ns(ths_exit));
1508
1509 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1510 "tclk_zero %u (%uns)\n",
1511 tlpx_half, ddr2ns(tlpx_half),
1512 tclk_trail, ddr2ns(tclk_trail),
1513 tclk_zero, ddr2ns(tclk_zero));
1514 DSSDBG("tclk_prepare %u (%uns)\n",
1515 tclk_prepare, ddr2ns(tclk_prepare));
1516
1517 /* program timings */
1518
1519 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1520 r = FLD_MOD(r, ths_prepare, 31, 24);
1521 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1522 r = FLD_MOD(r, ths_trail, 15, 8);
1523 r = FLD_MOD(r, ths_exit, 7, 0);
1524 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1525
1526 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1527 r = FLD_MOD(r, tlpx_half, 22, 16);
1528 r = FLD_MOD(r, tclk_trail, 15, 8);
1529 r = FLD_MOD(r, tclk_zero, 7, 0);
1530 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1531
1532 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1533 r = FLD_MOD(r, tclk_prepare, 7, 0);
1534 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1535}
1536
1537
1538static int dsi_complexio_init(struct omap_dss_device *dssdev)
1539{
1540 int r = 0;
1541
1542 DSSDBG("dsi_complexio_init\n");
1543
1544 /* CIO_CLK_ICG, enable L3 clk to CIO */
1545 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1546
1547 /* A dummy read using the SCP interface to any DSIPHY register is
1548 * required after DSIPHY reset to complete the reset of the DSI complex
1549 * I/O. */
1550 dsi_read_reg(DSI_DSIPHY_CFG5);
1551
1552 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1553 DSSERR("ComplexIO PHY not coming out of reset.\n");
1554 r = -ENODEV;
1555 goto err;
1556 }
1557
1558 dsi_complexio_config(dssdev);
1559
1560 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1561
1562 if (r)
1563 goto err;
1564
1565 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1566 DSSERR("ComplexIO not coming out of reset.\n");
1567 r = -ENODEV;
1568 goto err;
1569 }
1570
1571 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1572 DSSERR("ComplexIO LDO power down.\n");
1573 r = -ENODEV;
1574 goto err;
1575 }
1576
1577 dsi_complexio_timings();
1578
1579 /*
1580 The configuration of the DSI complex I/O (number of data lanes,
1581 position, differential order) should not be changed while
1582 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1583 hardware to recognize a new configuration of the complex I/O (done
1584 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1585 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1586 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1587 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1588 bit to 1. If the sequence is not followed, the DSi complex I/O
1589 configuration is undetermined.
1590 */
1591 dsi_if_enable(1);
1592 dsi_if_enable(0);
1593 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1594 dsi_if_enable(1);
1595 dsi_if_enable(0);
1596
1597 DSSDBG("CIO init done\n");
1598err:
1599 return r;
1600}
1601
1602static void dsi_complexio_uninit(void)
1603{
1604 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1605}
1606
1607static int _dsi_wait_reset(void)
1608{
24be78b3 1609 int t = 0;
3de7a1dc
TV		 1610
1611 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
24be78b3 1612 if (++t > 5) {
3de7a1dc
TV		 1613 DSSERR("soft reset failed\n");
1614 return -ENODEV;
1615 }
1616 udelay(1);
1617 }
1618
1619 return 0;
1620}
1621
1622static int _dsi_reset(void)
1623{
1624 /* Soft reset */
1625 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1626 return _dsi_wait_reset();
1627}
1628
1629static void dsi_reset_tx_fifo(int channel)
1630{
1631 u32 mask;
1632 u32 l;
1633
1634 /* set fifosize of the channel to 0, then return the old size */
1635 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1636
1637 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1638 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1639
1640 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1641}
1642
1643static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1644 enum fifo_size size3, enum fifo_size size4)
1645{
1646 u32 r = 0;
1647 int add = 0;
1648 int i;
1649
1650 dsi.vc[0].fifo_size = size1;
1651 dsi.vc[1].fifo_size = size2;
1652 dsi.vc[2].fifo_size = size3;
1653 dsi.vc[3].fifo_size = size4;
1654
1655 for (i = 0; i < 4; i++) {
1656 u8 v;
1657 int size = dsi.vc[i].fifo_size;
1658
1659 if (add + size > 4) {
1660 DSSERR("Illegal FIFO configuration\n");
1661 BUG();
1662 }
1663
1664 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1665 r |= v << (8 * i);
1666 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1667 add += size;
1668 }
1669
1670 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1671}
1672
1673static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1674 enum fifo_size size3, enum fifo_size size4)
1675{
1676 u32 r = 0;
1677 int add = 0;
1678 int i;
1679
1680 dsi.vc[0].fifo_size = size1;
1681 dsi.vc[1].fifo_size = size2;
1682 dsi.vc[2].fifo_size = size3;
1683 dsi.vc[3].fifo_size = size4;
1684
1685 for (i = 0; i < 4; i++) {
1686 u8 v;
1687 int size = dsi.vc[i].fifo_size;
1688
1689 if (add + size > 4) {
1690 DSSERR("Illegal FIFO configuration\n");
1691 BUG();
1692 }
1693
1694 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1695 r |= v << (8 * i);
1696 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1697 add += size;
1698 }
1699
1700 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1701}
1702
1703static int dsi_force_tx_stop_mode_io(void)
1704{
1705 u32 r;
1706
1707 r = dsi_read_reg(DSI_TIMING1);
1708 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1709 dsi_write_reg(DSI_TIMING1, r);
1710
1711 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1712 DSSERR("TX_STOP bit not going down\n");
1713 return -EIO;
1714 }
1715
1716 return 0;
1717}
1718
3de7a1dc
TV		 1719static int dsi_vc_enable(int channel, bool enable)
1720{
446f7bff
TV		 1721 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1722 channel, enable);
3de7a1dc
TV		 1723
1724 enable = enable ? 1 : 0;
1725
1726 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1727
1728 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1729 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1730 return -EIO;
1731 }
1732
1733 return 0;
1734}
1735
1736static void dsi_vc_initial_config(int channel)
1737{
1738 u32 r;
1739
1740 DSSDBGF("%d", channel);
1741
1742 r = dsi_read_reg(DSI_VC_CTRL(channel));
1743
1744 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1745 DSSERR("VC(%d) busy when trying to configure it!\n",
1746 channel);
1747
1748 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1749 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1750 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1751 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1752 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1753 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1754 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1755
1756 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1757 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1758
1759 dsi_write_reg(DSI_VC_CTRL(channel), r);
1760
1761 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1762}
1763
9ecd9684 1764static int dsi_vc_config_l4(int channel)
3de7a1dc
TV		 1765{
1766 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
9ecd9684 1767 return 0;
3de7a1dc
TV		 1768
1769 DSSDBGF("%d", channel);
1770
1771 dsi_vc_enable(channel, 0);
1772
9ecd9684
TV		 1773 /* VC_BUSY */
1774 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1775 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
9ecd9684
TV		 1776 return -EIO;
1777 }
3de7a1dc
TV		 1778
1779 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1780
1781 dsi_vc_enable(channel, 1);
1782
1783 dsi.vc[channel].mode = DSI_VC_MODE_L4;
9ecd9684
TV		 1784
1785 return 0;
3de7a1dc
TV		 1786}
1787
9ecd9684 1788static int dsi_vc_config_vp(int channel)
3de7a1dc
TV		 1789{
1790 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
9ecd9684 1791 return 0;
3de7a1dc
TV		 1792
1793 DSSDBGF("%d", channel);
1794
1795 dsi_vc_enable(channel, 0);
1796
9ecd9684
TV		 1797 /* VC_BUSY */
1798 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1799 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
9ecd9684
TV		 1800 return -EIO;
1801 }
3de7a1dc
TV		 1802
1803 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1804
1805 dsi_vc_enable(channel, 1);
1806
1807 dsi.vc[channel].mode = DSI_VC_MODE_VP;
9ecd9684
TV		 1808
1809 return 0;
3de7a1dc
TV		 1810}
1811
1812
61140c9a 1813void omapdss_dsi_vc_enable_hs(int channel, bool enable)
3de7a1dc
TV		 1814{
1815 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1816
61140c9a
TV		 1817 WARN_ON(!dsi_bus_is_locked());
1818
3de7a1dc
TV		 1819 dsi_vc_enable(channel, 0);
1820 dsi_if_enable(0);
1821
1822 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1823
1824 dsi_vc_enable(channel, 1);
1825 dsi_if_enable(1);
1826
1827 dsi_force_tx_stop_mode_io();
1828}
61140c9a 1829EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
3de7a1dc
TV		 1830
1831static void dsi_vc_flush_long_data(int channel)
1832{
1833 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1834 u32 val;
1835 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1836 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1837 (val >> 0) & 0xff,
1838 (val >> 8) & 0xff,
1839 (val >> 16) & 0xff,
1840 (val >> 24) & 0xff);
1841 }
1842}
1843
1844static void dsi_show_rx_ack_with_err(u16 err)
1845{
1846 DSSERR("\tACK with ERROR (%#x):\n", err);
1847 if (err & (1 << 0))
1848 DSSERR("\t\tSoT Error\n");
1849 if (err & (1 << 1))
1850 DSSERR("\t\tSoT Sync Error\n");
1851 if (err & (1 << 2))
1852 DSSERR("\t\tEoT Sync Error\n");
1853 if (err & (1 << 3))
1854 DSSERR("\t\tEscape Mode Entry Command Error\n");
1855 if (err & (1 << 4))
1856 DSSERR("\t\tLP Transmit Sync Error\n");
1857 if (err & (1 << 5))
1858 DSSERR("\t\tHS Receive Timeout Error\n");
1859 if (err & (1 << 6))
1860 DSSERR("\t\tFalse Control Error\n");
1861 if (err & (1 << 7))
1862 DSSERR("\t\t(reserved7)\n");
1863 if (err & (1 << 8))
1864 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1865 if (err & (1 << 9))
1866 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1867 if (err & (1 << 10))
1868 DSSERR("\t\tChecksum Error\n");
1869 if (err & (1 << 11))
1870 DSSERR("\t\tData type not recognized\n");
1871 if (err & (1 << 12))
1872 DSSERR("\t\tInvalid VC ID\n");
1873 if (err & (1 << 13))
1874 DSSERR("\t\tInvalid Transmission Length\n");
1875 if (err & (1 << 14))
1876 DSSERR("\t\t(reserved14)\n");
1877 if (err & (1 << 15))
1878 DSSERR("\t\tDSI Protocol Violation\n");
1879}
1880
1881static u16 dsi_vc_flush_receive_data(int channel)
1882{
1883 /* RX_FIFO_NOT_EMPTY */
1884 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1885 u32 val;
1886 u8 dt;
1887 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
86a7867e 1888 DSSERR("\trawval %#08x\n", val);
3de7a1dc
TV		 1889 dt = FLD_GET(val, 5, 0);
1890 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1891 u16 err = FLD_GET(val, 23, 8);
1892 dsi_show_rx_ack_with_err(err);
1893 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
86a7867e 1894 DSSERR("\tDCS short response, 1 byte: %#x\n",
3de7a1dc
TV		 1895 FLD_GET(val, 23, 8));
1896 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
86a7867e 1897 DSSERR("\tDCS short response, 2 byte: %#x\n",
3de7a1dc
TV		 1898 FLD_GET(val, 23, 8));
1899 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
86a7867e 1900 DSSERR("\tDCS long response, len %d\n",
3de7a1dc
TV		 1901 FLD_GET(val, 23, 8));
1902 dsi_vc_flush_long_data(channel);
1903 } else {
1904 DSSERR("\tunknown datatype 0x%02x\n", dt);
1905 }
1906 }
1907 return 0;
1908}
1909
1910static int dsi_vc_send_bta(int channel)
1911{
446f7bff 1912 if (dsi.debug_write || dsi.debug_read)
3de7a1dc
TV		 1913 DSSDBG("dsi_vc_send_bta %d\n", channel);
1914
4f765023 1915 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 1916
1917 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1918 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1919 dsi_vc_flush_receive_data(channel);
1920 }
1921
1922 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1923
1924 return 0;
1925}
1926
1927int dsi_vc_send_bta_sync(int channel)
1928{
1929 int r = 0;
1930 u32 err;
1931
1932 INIT_COMPLETION(dsi.bta_completion);
1933
1934 dsi_vc_enable_bta_irq(channel);
1935
1936 r = dsi_vc_send_bta(channel);
1937 if (r)
1938 goto err;
1939
1940 if (wait_for_completion_timeout(&dsi.bta_completion,
1941 msecs_to_jiffies(500)) == 0) {
1942 DSSERR("Failed to receive BTA\n");
1943 r = -EIO;
1944 goto err;
1945 }
1946
1947 err = dsi_get_errors();
1948 if (err) {
1949 DSSERR("Error while sending BTA: %x\n", err);
1950 r = -EIO;
1951 goto err;
1952 }
1953err:
1954 dsi_vc_disable_bta_irq(channel);
1955
1956 return r;
1957}
1958EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1959
1960static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1961 u16 len, u8 ecc)
1962{
1963 u32 val;
1964 u8 data_id;
1965
4f765023 1966 WARN_ON(!dsi_bus_is_locked());
3de7a1dc 1967
dd8079d6 1968 data_id = data_type | channel << 6;
3de7a1dc
TV		 1969
1970 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1971 FLD_VAL(ecc, 31, 24);
1972
1973 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1974}
1975
1976static inline void dsi_vc_write_long_payload(int channel,
1977 u8 b1, u8 b2, u8 b3, u8 b4)
1978{
1979 u32 val;
1980
1981 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1982
1983/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1984 b1, b2, b3, b4, val); */
1985
1986 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1987}
1988
1989static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1990 u8 ecc)
1991{
1992 /*u32 val; */
1993 int i;
1994 u8 *p;
1995 int r = 0;
1996 u8 b1, b2, b3, b4;
1997
1998 if (dsi.debug_write)
1999 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2000
2001 /* len + header */
2002 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2003 DSSERR("unable to send long packet: packet too long.\n");
2004 return -EINVAL;
2005 }
2006
2007 dsi_vc_config_l4(channel);
2008
2009 dsi_vc_write_long_header(channel, data_type, len, ecc);
2010
3de7a1dc
TV		 2011 p = data;
2012 for (i = 0; i < len >> 2; i++) {
2013 if (dsi.debug_write)
2014 DSSDBG("\tsending full packet %d\n", i);
3de7a1dc
TV		 2015
2016 b1 = *p++;
2017 b2 = *p++;
2018 b3 = *p++;
2019 b4 = *p++;
2020
2021 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2022 }
2023
2024 i = len % 4;
2025 if (i) {
2026 b1 = 0; b2 = 0; b3 = 0;
2027
2028 if (dsi.debug_write)
2029 DSSDBG("\tsending remainder bytes %d\n", i);
2030
2031 switch (i) {
2032 case 3:
2033 b1 = *p++;
2034 b2 = *p++;
2035 b3 = *p++;
2036 break;
2037 case 2:
2038 b1 = *p++;
2039 b2 = *p++;
2040 break;
2041 case 1:
2042 b1 = *p++;
2043 break;
2044 }
2045
2046 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2047 }
2048
2049 return r;
2050}
2051
2052static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2053{
2054 u32 r;
2055 u8 data_id;
2056
4f765023 2057 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 2058
2059 if (dsi.debug_write)
2060 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2061 channel,
2062 data_type, data & 0xff, (data >> 8) & 0xff);
2063
2064 dsi_vc_config_l4(channel);
2065
2066 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2067 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2068 return -EINVAL;
2069 }
2070
dd8079d6 2071 data_id = data_type | channel << 6;
3de7a1dc
TV		 2072
2073 r = (data_id << 0) | (data << 8) | (ecc << 24);
2074
2075 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2076
2077 return 0;
2078}
2079
2080int dsi_vc_send_null(int channel)
2081{
2082 u8 nullpkg[] = {0, 0, 0, 0};
397bb3c2 2083 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
3de7a1dc
TV		 2084}
2085EXPORT_SYMBOL(dsi_vc_send_null);
2086
2087int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2088{
2089 int r;
2090
2091 BUG_ON(len == 0);
2092
2093 if (len == 1) {
2094 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2095 data[0], 0);
2096 } else if (len == 2) {
2097 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2098 data[0] | (data[1] << 8), 0);
2099 } else {
2100 /* 0x39 = DCS Long Write */
2101 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2102 data, len, 0);
2103 }
2104
2105 return r;
2106}
2107EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2108
2109int dsi_vc_dcs_write(int channel, u8 *data, int len)
2110{
2111 int r;
2112
2113 r = dsi_vc_dcs_write_nosync(channel, data, len);
2114 if (r)
5d68e032 2115 goto err;
3de7a1dc
TV		 2116
2117 r = dsi_vc_send_bta_sync(channel);
5d68e032
TV		 2118 if (r)
2119 goto err;
3de7a1dc 2120
b63ac1e3
TV		 2121 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2122 DSSERR("rx fifo not empty after write, dumping data:\n");
2123 dsi_vc_flush_receive_data(channel);
2124 r = -EIO;
2125 goto err;
2126 }
2127
5d68e032
TV		 2128 return 0;
2129err:
2130 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2131 channel, data[0], len);
3de7a1dc
TV		 2132 return r;
2133}
2134EXPORT_SYMBOL(dsi_vc_dcs_write);
2135
828c48f8
TV		 2136int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2137{
2138 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2139}
2140EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2141
2142int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2143{
2144 u8 buf[2];
2145 buf[0] = dcs_cmd;
2146 buf[1] = param;
2147 return dsi_vc_dcs_write(channel, buf, 2);
2148}
2149EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2150
3de7a1dc
TV		 2151int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2152{
2153 u32 val;
2154 u8 dt;
2155 int r;
2156
2157 if (dsi.debug_read)
ff90a348 2158 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3de7a1dc
TV		 2159
2160 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2161 if (r)
5d68e032 2162 goto err;
3de7a1dc
TV		 2163
2164 r = dsi_vc_send_bta_sync(channel);
2165 if (r)
5d68e032 2166 goto err;
3de7a1dc
TV		 2167
2168 /* RX_FIFO_NOT_EMPTY */
2169 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2170 DSSERR("RX fifo empty when trying to read.\n");
5d68e032
TV		 2171 r = -EIO;
2172 goto err;
3de7a1dc
TV		 2173 }
2174
2175 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2176 if (dsi.debug_read)
2177 DSSDBG("\theader: %08x\n", val);
2178 dt = FLD_GET(val, 5, 0);
2179 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2180 u16 err = FLD_GET(val, 23, 8);
2181 dsi_show_rx_ack_with_err(err);
5d68e032
TV		 2182 r = -EIO;
2183 goto err;
3de7a1dc
TV		 2184
2185 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2186 u8 data = FLD_GET(val, 15, 8);
2187 if (dsi.debug_read)
2188 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2189
5d68e032
TV		 2190 if (buflen < 1) {
2191 r = -EIO;
2192 goto err;
2193 }
3de7a1dc
TV		 2194
2195 buf[0] = data;
2196
2197 return 1;
2198 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2199 u16 data = FLD_GET(val, 23, 8);
2200 if (dsi.debug_read)
2201 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2202
5d68e032
TV		 2203 if (buflen < 2) {
2204 r = -EIO;
2205 goto err;
2206 }
3de7a1dc
TV		 2207
2208 buf[0] = data & 0xff;
2209 buf[1] = (data >> 8) & 0xff;
2210
2211 return 2;
2212 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2213 int w;
2214 int len = FLD_GET(val, 23, 8);
2215 if (dsi.debug_read)
2216 DSSDBG("\tDCS long response, len %d\n", len);
2217
5d68e032
TV		 2218 if (len > buflen) {
2219 r = -EIO;
2220 goto err;
2221 }
3de7a1dc
TV		 2222
2223 /* two byte checksum ends the packet, not included in len */
2224 for (w = 0; w < len + 2;) {
2225 int b;
2226 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2227 if (dsi.debug_read)
2228 DSSDBG("\t\t%02x %02x %02x %02x\n",
2229 (val >> 0) & 0xff,
2230 (val >> 8) & 0xff,
2231 (val >> 16) & 0xff,
2232 (val >> 24) & 0xff);
2233
2234 for (b = 0; b < 4; ++b) {
2235 if (w < len)
2236 buf[w] = (val >> (b * 8)) & 0xff;
2237 /* we discard the 2 byte checksum */
2238 ++w;
2239 }
2240 }
2241
2242 return len;
3de7a1dc
TV		 2243 } else {
2244 DSSERR("\tunknown datatype 0x%02x\n", dt);
5d68e032
TV		 2245 r = -EIO;
2246 goto err;
3de7a1dc 2247 }
5d68e032
TV		 2248
2249 BUG();
2250err:
2251 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2252 channel, dcs_cmd);
2253 return r;
2254
3de7a1dc
TV		 2255}
2256EXPORT_SYMBOL(dsi_vc_dcs_read);
2257
828c48f8
TV		 2258int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2259{
2260 int r;
2261
2262 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2263
2264 if (r < 0)
2265 return r;
2266
2267 if (r != 1)
2268 return -EIO;
2269
2270 return 0;
2271}
2272EXPORT_SYMBOL(dsi_vc_dcs_read_1);
3de7a1dc 2273
0c244f77 2274int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
53055aae 2275{
0c244f77 2276 u8 buf[2];
53055aae
TV		 2277 int r;
2278
0c244f77 2279 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
53055aae
TV		 2280
2281 if (r < 0)
2282 return r;
2283
2284 if (r != 2)
2285 return -EIO;
2286
0c244f77
TV		 2287 *data1 = buf[0];
2288 *data2 = buf[1];
2289
53055aae
TV		 2290 return 0;
2291}
2292EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2293
3de7a1dc
TV		 2294int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2295{
fa15c79b 2296 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
3de7a1dc 2297 len, 0);
3de7a1dc
TV		 2298}
2299EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2300
4ffa3571 2301static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2302{
3de7a1dc 2303 unsigned long fck;
4ffa3571
TV		 2304 unsigned long total_ticks;
2305 u32 r;
3de7a1dc 2306
4ffa3571 2307 BUG_ON(ticks > 0x1fff);
3de7a1dc 2308
4ffa3571 2309 /* ticks in DSI_FCK */
3de7a1dc 2310 fck = dsi_fclk_rate();
3de7a1dc
TV		 2311
2312 r = dsi_read_reg(DSI_TIMING2);
2313 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
4ffa3571
TV		 2314 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2315 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3de7a1dc
TV		 2316 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2317 dsi_write_reg(DSI_TIMING2, r);
2318
4ffa3571
TV		 2319 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2320
2321 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2322 total_ticks,
2323 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2324 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2325}
2326
4ffa3571 2327static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
3de7a1dc 2328{
3de7a1dc 2329 unsigned long fck;
4ffa3571
TV		 2330 unsigned long total_ticks;
2331 u32 r;
2332
2333 BUG_ON(ticks > 0x1fff);
3de7a1dc
TV		 2334
2335 /* ticks in DSI_FCK */
2336 fck = dsi_fclk_rate();
3de7a1dc
TV		 2337
2338 r = dsi_read_reg(DSI_TIMING1);
2339 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
4ffa3571
TV		 2340 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2341 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3de7a1dc
TV		 2342 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2343 dsi_write_reg(DSI_TIMING1, r);
2344
4ffa3571
TV		 2345 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2346
2347 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2348 total_ticks,
2349 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2350 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2351}
2352
4ffa3571 2353static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
3de7a1dc 2354{
3de7a1dc 2355 unsigned long fck;
4ffa3571
TV		 2356 unsigned long total_ticks;
2357 u32 r;
3de7a1dc 2358
4ffa3571 2359 BUG_ON(ticks > 0x1fff);
3de7a1dc 2360
4ffa3571 2361 /* ticks in DSI_FCK */
3de7a1dc 2362 fck = dsi_fclk_rate();
3de7a1dc
TV		 2363
2364 r = dsi_read_reg(DSI_TIMING1);
2365 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
4ffa3571
TV		 2366 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2367 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3de7a1dc
TV		 2368 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2369 dsi_write_reg(DSI_TIMING1, r);
2370
4ffa3571
TV		 2371 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2372
2373 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2374 total_ticks,
2375 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2376 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2377}
2378
4ffa3571 2379static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2380{
3de7a1dc 2381 unsigned long fck;
4ffa3571
TV		 2382 unsigned long total_ticks;
2383 u32 r;
3de7a1dc 2384
4ffa3571 2385 BUG_ON(ticks > 0x1fff);
3de7a1dc 2386
4ffa3571 2387 /* ticks in TxByteClkHS */
3de7a1dc 2388 fck = dsi_get_txbyteclkhs();
3de7a1dc
TV		 2389
2390 r = dsi_read_reg(DSI_TIMING2);
2391 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
4ffa3571
TV		 2392 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2393 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3de7a1dc
TV		 2394 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2395 dsi_write_reg(DSI_TIMING2, r);
2396
4ffa3571
TV		 2397 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2398
2399 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2400 total_ticks,
2401 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2402 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2403}
2404static int dsi_proto_config(struct omap_dss_device *dssdev)
2405{
2406 u32 r;
2407 int buswidth = 0;
2408
dd8079d6
TV		 2409 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2410 DSI_FIFO_SIZE_32,
2411 DSI_FIFO_SIZE_32,
2412 DSI_FIFO_SIZE_32);
3de7a1dc 2413
dd8079d6
TV		 2414 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2415 DSI_FIFO_SIZE_32,
2416 DSI_FIFO_SIZE_32,
2417 DSI_FIFO_SIZE_32);
3de7a1dc
TV		 2418
2419 /* XXX what values for the timeouts? */
4ffa3571
TV		 2420 dsi_set_stop_state_counter(0x1000, false, false);
2421 dsi_set_ta_timeout(0x1fff, true, true);
2422 dsi_set_lp_rx_timeout(0x1fff, true, true);
2423 dsi_set_hs_tx_timeout(0x1fff, true, true);
3de7a1dc
TV		 2424
2425 switch (dssdev->ctrl.pixel_size) {
2426 case 16:
2427 buswidth = 0;
2428 break;
2429 case 18:
2430 buswidth = 1;
2431 break;
2432 case 24:
2433 buswidth = 2;
2434 break;
2435 default:
2436 BUG();
2437 }
2438
2439 r = dsi_read_reg(DSI_CTRL);
2440 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2441 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2442 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2443 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2444 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2445 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2446 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2447 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2448 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2449 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2450 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2451
2452 dsi_write_reg(DSI_CTRL, r);
2453
2454 dsi_vc_initial_config(0);
dd8079d6
TV		 2455 dsi_vc_initial_config(1);
2456 dsi_vc_initial_config(2);
2457 dsi_vc_initial_config(3);
3de7a1dc
TV		 2458
2459 return 0;
2460}
2461
2462static void dsi_proto_timings(struct omap_dss_device *dssdev)
2463{
2464 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2465 unsigned tclk_pre, tclk_post;
2466 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2467 unsigned ths_trail, ths_exit;
2468 unsigned ddr_clk_pre, ddr_clk_post;
2469 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2470 unsigned ths_eot;
2471 u32 r;
2472
2473 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2474 ths_prepare = FLD_GET(r, 31, 24);
2475 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2476 ths_zero = ths_prepare_ths_zero - ths_prepare;
2477 ths_trail = FLD_GET(r, 15, 8);
2478 ths_exit = FLD_GET(r, 7, 0);
2479
2480 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2481 tlpx = FLD_GET(r, 22, 16) * 2;
2482 tclk_trail = FLD_GET(r, 15, 8);
2483 tclk_zero = FLD_GET(r, 7, 0);
2484
2485 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2486 tclk_prepare = FLD_GET(r, 7, 0);
2487
2488 /* min 8*UI */
2489 tclk_pre = 20;
2490 /* min 60ns + 52*UI */
2491 tclk_post = ns2ddr(60) + 26;
2492
2493 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2494 if (dssdev->phy.dsi.data1_lane != 0 &&
2495 dssdev->phy.dsi.data2_lane != 0)
2496 ths_eot = 2;
2497 else
2498 ths_eot = 4;
2499
2500 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2501 4);
2502 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2503
2504 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2505 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2506
2507 r = dsi_read_reg(DSI_CLK_TIMING);
2508 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2509 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2510 dsi_write_reg(DSI_CLK_TIMING, r);
2511
2512 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2513 ddr_clk_pre,
2514 ddr_clk_post);
2515
2516 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2517 DIV_ROUND_UP(ths_prepare, 4) +
2518 DIV_ROUND_UP(ths_zero + 3, 4);
2519
2520 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2521
2522 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2523 FLD_VAL(exit_hs_mode_lat, 15, 0);
2524 dsi_write_reg(DSI_VM_TIMING7, r);
2525
2526 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2527 enter_hs_mode_lat, exit_hs_mode_lat);
2528}
2529
2530
2531#define DSI_DECL_VARS \
2532 int __dsi_cb = 0; u32 __dsi_cv = 0;
2533
2534#define DSI_FLUSH(ch) \
2535 if (__dsi_cb > 0) { \
2536 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2537 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2538 __dsi_cb = __dsi_cv = 0; \
2539 }
2540
2541#define DSI_PUSH(ch, data) \
2542 do { \
2543 __dsi_cv |= (data) << (__dsi_cb * 8); \
2544 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2545 if (++__dsi_cb > 3) \
2546 DSI_FLUSH(ch); \
2547 } while (0)
2548
2549static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2550 int x, int y, int w, int h)
2551{
2552 /* Note: supports only 24bit colors in 32bit container */
2553 int first = 1;
2554 int fifo_stalls = 0;
2555 int max_dsi_packet_size;
2556 int max_data_per_packet;
2557 int max_pixels_per_packet;
2558 int pixels_left;
2559 int bytespp = dssdev->ctrl.pixel_size / 8;
2560 int scr_width;
2561 u32 __iomem *data;
2562 int start_offset;
2563 int horiz_inc;
2564 int current_x;
2565 struct omap_overlay *ovl;
2566
2567 debug_irq = 0;
2568
2569 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2570 x, y, w, h);
2571
2572 ovl = dssdev->manager->overlays[0];
2573
2574 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2575 return -EINVAL;
2576
2577 if (dssdev->ctrl.pixel_size != 24)
2578 return -EINVAL;
2579
2580 scr_width = ovl->info.screen_width;
2581 data = ovl->info.vaddr;
2582
2583 start_offset = scr_width * y + x;
2584 horiz_inc = scr_width - w;
2585 current_x = x;
2586
2587 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2588 * in fifo */
2589
2590 /* When using CPU, max long packet size is TX buffer size */
2591 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2592
2593 /* we seem to get better perf if we divide the tx fifo to half,
2594 and while the other half is being sent, we fill the other half
2595 max_dsi_packet_size /= 2; */
2596
2597 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2598
2599 max_pixels_per_packet = max_data_per_packet / bytespp;
2600
2601 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2602
2603 pixels_left = w * h;
2604
2605 DSSDBG("total pixels %d\n", pixels_left);
2606
2607 data += start_offset;
2608
2609 while (pixels_left > 0) {
2610 /* 0x2c = write_memory_start */
2611 /* 0x3c = write_memory_continue */
2612 u8 dcs_cmd = first ? 0x2c : 0x3c;
2613 int pixels;
2614 DSI_DECL_VARS;
2615 first = 0;
2616
2617#if 1
2618 /* using fifo not empty */
2619 /* TX_FIFO_NOT_EMPTY */
2620 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
3de7a1dc
TV		 2621 fifo_stalls++;
2622 if (fifo_stalls > 0xfffff) {
2623 DSSERR("fifo stalls overflow, pixels left %d\n",
2624 pixels_left);
2625 dsi_if_enable(0);
2626 return -EIO;
2627 }
24be78b3 2628 udelay(1);
3de7a1dc
TV		 2629 }
2630#elif 1
2631 /* using fifo emptiness */
2632 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2633 max_dsi_packet_size) {
2634 fifo_stalls++;
2635 if (fifo_stalls > 0xfffff) {
2636 DSSERR("fifo stalls overflow, pixels left %d\n",
2637 pixels_left);
2638 dsi_if_enable(0);
2639 return -EIO;
2640 }
2641 }
2642#else
2643 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2644 fifo_stalls++;
2645 if (fifo_stalls > 0xfffff) {
2646 DSSERR("fifo stalls overflow, pixels left %d\n",
2647 pixels_left);
2648 dsi_if_enable(0);
2649 return -EIO;
2650 }
2651 }
2652#endif
2653 pixels = min(max_pixels_per_packet, pixels_left);
2654
2655 pixels_left -= pixels;
2656
2657 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2658 1 + pixels * bytespp, 0);
2659
2660 DSI_PUSH(0, dcs_cmd);
2661
2662 while (pixels-- > 0) {
2663 u32 pix = __raw_readl(data++);
2664
2665 DSI_PUSH(0, (pix >> 16) & 0xff);
2666 DSI_PUSH(0, (pix >> 8) & 0xff);
2667 DSI_PUSH(0, (pix >> 0) & 0xff);
2668
2669 current_x++;
2670 if (current_x == x+w) {
2671 current_x = x;
2672 data += horiz_inc;
2673 }
2674 }
2675
2676 DSI_FLUSH(0);
2677 }
2678
2679 return 0;
2680}
2681
2682static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2683 u16 x, u16 y, u16 w, u16 h)
2684{
2685 unsigned bytespp;
2686 unsigned bytespl;
2687 unsigned bytespf;
2688 unsigned total_len;
2689 unsigned packet_payload;
2690 unsigned packet_len;
2691 u32 l;
0f16aa0a 2692 int r;
18946f62 2693 const unsigned channel = dsi.update_channel;
3de7a1dc
TV		 2694 /* line buffer is 1024 x 24bits */
2695 /* XXX: for some reason using full buffer size causes considerable TX
2696 * slowdown with update sizes that fill the whole buffer */
2697 const unsigned line_buf_size = 1023 * 3;
2698
446f7bff
TV		 2699 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2700 x, y, w, h);
3de7a1dc 2701
18946f62
TV		 2702 dsi_vc_config_vp(channel);
2703
3de7a1dc
TV		 2704 bytespp = dssdev->ctrl.pixel_size / 8;
2705 bytespl = w * bytespp;
2706 bytespf = bytespl * h;
2707
2708 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2709 * number of lines in a packet. See errata about VP_CLK_RATIO */
2710
2711 if (bytespf < line_buf_size)
2712 packet_payload = bytespf;
2713 else
2714 packet_payload = (line_buf_size) / bytespl * bytespl;
2715
2716 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2717 total_len = (bytespf / packet_payload) * packet_len;
2718
2719 if (bytespf % packet_payload)
2720 total_len += (bytespf % packet_payload) + 1;
2721
3de7a1dc
TV		 2722 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2723 dsi_write_reg(DSI_VC_TE(channel), l);
2724
2725 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2726
942a91a6 2727 if (dsi.te_enabled)
3de7a1dc
TV		 2728 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2729 else
2730 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2731 dsi_write_reg(DSI_VC_TE(channel), l);
2732
2733 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2734 * because DSS interrupts are not capable of waking up the CPU and the
2735 * framedone interrupt could be delayed for quite a long time. I think
2736 * the same goes for any DSS interrupts, but for some reason I have not
2737 * seen the problem anywhere else than here.
2738 */
2739 dispc_disable_sidle();
2740
18946f62
TV		 2741 dsi_perf_mark_start();
2742
0f16aa0a 2743 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
18946f62 2744 msecs_to_jiffies(250));
0f16aa0a 2745 BUG_ON(r == 0);
18946f62 2746
3de7a1dc
TV		 2747 dss_start_update(dssdev);
2748
942a91a6 2749 if (dsi.te_enabled) {
3de7a1dc
TV		 2750 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2751 * for TE is longer than the timer allows */
2752 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2753
2754 dsi_vc_send_bta(channel);
2755
2756#ifdef DSI_CATCH_MISSING_TE
2757 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2758#endif
2759 }
2760}
2761
2762#ifdef DSI_CATCH_MISSING_TE
2763static void dsi_te_timeout(unsigned long arg)
2764{
2765 DSSERR("TE not received for 250ms!\n");
2766}
2767#endif
2768
ab83b14c 2769static void dsi_handle_framedone(int error)
3de7a1dc 2770{
18946f62 2771 const int channel = dsi.update_channel;
18946f62 2772
ab83b14c 2773 cancel_delayed_work(&dsi.framedone_timeout_work);
3de7a1dc 2774
ab83b14c 2775 dsi_vc_disable_bta_irq(channel);
0f16aa0a 2776
3de7a1dc
TV		 2777 /* SIDLEMODE back to smart-idle */
2778 dispc_enable_sidle();
2779
ab83b14c
TV		 2780 dsi.bta_callback = NULL;
2781
942a91a6 2782 if (dsi.te_enabled) {
18946f62
TV		 2783 /* enable LP_RX_TO again after the TE */
2784 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3de7a1dc
TV		 2785 }
2786
18946f62
TV		 2787 /* RX_FIFO_NOT_EMPTY */
2788 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2789 DSSERR("Received error during frame transfer:\n");
2790 dsi_vc_flush_receive_data(channel);
ab83b14c
TV		 2791 if (!error)
2792 error = -EIO;
18946f62
TV		 2793 }
2794
ab83b14c
TV		 2795 dsi.framedone_callback(error, dsi.framedone_data);
2796
2797 if (!error)
2798 dsi_perf_show("DISPC");
18946f62 2799}
3de7a1dc 2800
ab83b14c 2801static void dsi_framedone_timeout_work_callback(struct work_struct *work)
18946f62 2802{
ab83b14c
TV		 2803 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2804 * 250ms which would conflict with this timeout work. What should be
2805 * done is first cancel the transfer on the HW, and then cancel the
2806 * possibly scheduled framedone work. However, cancelling the transfer
2807 * on the HW is buggy, and would probably require resetting the whole
2808 * DSI */
18946f62 2809
ab83b14c 2810 DSSERR("Framedone not received for 250ms!\n");
3de7a1dc 2811
ab83b14c 2812 dsi_handle_framedone(-ETIMEDOUT);
3de7a1dc
TV		 2813}
2814
ab83b14c
TV		 2815static void dsi_framedone_bta_callback(void)
2816{
2817 dsi_handle_framedone(0);
2818
2819#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2820 dispc_fake_vsync_irq();
2821#endif
2822}
2823
2824static void dsi_framedone_irq_callback(void *data, u32 mask)
3de7a1dc 2825{
18946f62 2826 const int channel = dsi.update_channel;
ab83b14c 2827 int r;
3de7a1dc 2828
ab83b14c
TV		 2829 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2830 * turns itself off. However, DSI still has the pixels in its buffers,
2831 * and is sending the data.
2832 */
3de7a1dc 2833
942a91a6 2834 if (dsi.te_enabled) {
3de7a1dc
TV		 2835 /* enable LP_RX_TO again after the TE */
2836 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2837 }
2838
2839 /* Send BTA after the frame. We need this for the TE to work, as TE
2840 * trigger is only sent for BTAs without preceding packet. Thus we need
2841 * to BTA after the pixel packets so that next BTA will cause TE
2842 * trigger.
2843 *
2844 * This is not needed when TE is not in use, but we do it anyway to
2845 * make sure that the transfer has been completed. It would be more
2846 * optimal, but more complex, to wait only just before starting next
ab83b14c
TV		 2847 * transfer.
2848 *
2849 * Also, as there's no interrupt telling when the transfer has been
2850 * done and the channel could be reconfigured, the only way is to
2851 * busyloop until TE_SIZE is zero. With BTA we can do this
2852 * asynchronously.
2853 * */
3de7a1dc 2854
ab83b14c 2855 dsi.bta_callback = dsi_framedone_bta_callback;
3de7a1dc 2856
ab83b14c 2857 barrier();
3de7a1dc 2858
ab83b14c 2859 dsi_vc_enable_bta_irq(channel);
3de7a1dc 2860
ab83b14c
TV		 2861 r = dsi_vc_send_bta(channel);
2862 if (r) {
2863 DSSERR("BTA after framedone failed\n");
2864 dsi_handle_framedone(-EIO);
2865 }
18946f62 2866}
3de7a1dc 2867
18946f62 2868int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250
TV		 2869 u16 *x, u16 *y, u16 *w, u16 *h,
2870 bool enlarge_update_area)
18946f62
TV		 2871{
2872 u16 dw, dh;
3de7a1dc 2873
18946f62 2874 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3de7a1dc 2875
18946f62
TV		 2876 if (*x > dw || *y > dh)
2877 return -EINVAL;
3de7a1dc 2878
18946f62
TV		 2879 if (*x + *w > dw)
2880 return -EINVAL;
3de7a1dc 2881
18946f62
TV		 2882 if (*y + *h > dh)
2883 return -EINVAL;
3de7a1dc 2884
18946f62
TV		 2885 if (*w == 1)
2886 return -EINVAL;
3de7a1dc 2887
18946f62
TV		 2888 if (*w == 0 || *h == 0)
2889 return -EINVAL;
3de7a1dc 2890
18946f62 2891 dsi_perf_mark_setup();
3de7a1dc 2892
18946f62 2893 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
26a8c250
TV		 2894 dss_setup_partial_planes(dssdev, x, y, w, h,
2895 enlarge_update_area);
64ba4f74 2896 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
18946f62 2897 }
3de7a1dc 2898
18946f62
TV		 2899 return 0;
2900}
2901EXPORT_SYMBOL(omap_dsi_prepare_update);
3de7a1dc 2902
18946f62
TV		 2903int omap_dsi_update(struct omap_dss_device *dssdev,
2904 int channel,
2905 u16 x, u16 y, u16 w, u16 h,
2906 void (*callback)(int, void *), void *data)
2907{
2908 dsi.update_channel = channel;
3de7a1dc 2909
a602771c
TV		 2910 /* OMAP DSS cannot send updates of odd widths.
2911 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2912 * here to make sure we catch erroneous updates. Otherwise we'll only
2913 * see rather obscure HW error happening, as DSS halts. */
2914 BUG_ON(x % 2 == 1);
2915
18946f62
TV		 2916 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2917 dsi.framedone_callback = callback;
2918 dsi.framedone_data = data;
3de7a1dc 2919
18946f62
TV		 2920 dsi.update_region.x = x;
2921 dsi.update_region.y = y;
2922 dsi.update_region.w = w;
2923 dsi.update_region.h = h;
2924 dsi.update_region.device = dssdev;
3de7a1dc 2925
18946f62
TV		 2926 dsi_update_screen_dispc(dssdev, x, y, w, h);
2927 } else {
e9c31afc
AT		 2928 int r;
2929
2930 r = dsi_update_screen_l4(dssdev, x, y, w, h);
2931 if (r)
2932 return r;
2933
18946f62
TV		 2934 dsi_perf_show("L4");
2935 callback(0, data);
3de7a1dc
TV		 2936 }
2937
3de7a1dc
TV		 2938 return 0;
2939}
18946f62 2940EXPORT_SYMBOL(omap_dsi_update);
3de7a1dc
TV		 2941
2942/* Display funcs */
2943
2944static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2945{
2946 int r;
2947
2948 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2949 DISPC_IRQ_FRAMEDONE);
2950 if (r) {
2951 DSSERR("can't get FRAMEDONE irq\n");
2952 return r;
2953 }
2954
64ba4f74
SS		 2955 dispc_set_lcd_display_type(dssdev->manager->id,
2956 OMAP_DSS_LCD_DISPLAY_TFT);
3de7a1dc 2957
64ba4f74
SS		 2958 dispc_set_parallel_interface_mode(dssdev->manager->id,
2959 OMAP_DSS_PARALLELMODE_DSI);
2960 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3de7a1dc 2961
64ba4f74 2962 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3de7a1dc
TV		 2963
2964 {
2965 struct omap_video_timings timings = {
2966 .hsw = 1,
2967 .hfp = 1,
2968 .hbp = 1,
2969 .vsw = 1,
2970 .vfp = 0,
2971 .vbp = 0,
2972 };
2973
64ba4f74 2974 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3de7a1dc
TV		 2975 }
2976
2977 return 0;
2978}
2979
2980static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2981{
2982 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2983 DISPC_IRQ_FRAMEDONE);
2984}
2985
2986static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2987{
2988 struct dsi_clock_info cinfo;
2989 int r;
2990
2991 /* we always use DSS2_FCK as input clock */
2992 cinfo.use_dss2_fck = true;
2993 cinfo.regn = dssdev->phy.dsi.div.regn;
2994 cinfo.regm = dssdev->phy.dsi.div.regm;
2995 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2996 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
ff1b2cde 2997 r = dsi_calc_clock_rates(dssdev, &cinfo);
ebf0a3fe
VS		 2998 if (r) {
2999 DSSERR("Failed to calc dsi clocks\n");
3de7a1dc 3000 return r;
ebf0a3fe 3001 }
3de7a1dc
TV		 3002
3003 r = dsi_pll_set_clock_div(&cinfo);
3004 if (r) {
3005 DSSERR("Failed to set dsi clocks\n");
3006 return r;
3007 }
3008
3009 return 0;
3010}
3011
3012static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3013{
3014 struct dispc_clock_info dispc_cinfo;
3015 int r;
3016 unsigned long long fck;
3017
3018 fck = dsi_get_dsi1_pll_rate();
3019
3020 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3021 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3022
3023 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3024 if (r) {
3025 DSSERR("Failed to calc dispc clocks\n");
3026 return r;
3027 }
3028
ff1b2cde 3029 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3de7a1dc
TV		 3030 if (r) {
3031 DSSERR("Failed to set dispc clocks\n");
3032 return r;
3033 }
3034
3035 return 0;
3036}
3037
3038static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3039{
3040 int r;
3041
3042 _dsi_print_reset_status();
3043
3044 r = dsi_pll_init(dssdev, true, true);
3045 if (r)
3046 goto err0;
3047
3048 r = dsi_configure_dsi_clocks(dssdev);
3049 if (r)
3050 goto err1;
3051
2f18c4d8
TV		 3052 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3053 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3de7a1dc
TV		 3054
3055 DSSDBG("PLL OK\n");
3056
3057 r = dsi_configure_dispc_clocks(dssdev);
3058 if (r)
3059 goto err2;
3060
3061 r = dsi_complexio_init(dssdev);
3062 if (r)
3063 goto err2;
3064
3065 _dsi_print_reset_status();
3066
3067 dsi_proto_timings(dssdev);
3068 dsi_set_lp_clk_divisor(dssdev);
3069
3070 if (1)
3071 _dsi_print_reset_status();
3072
3073 r = dsi_proto_config(dssdev);
3074 if (r)
3075 goto err3;
3076
3077 /* enable interface */
3078 dsi_vc_enable(0, 1);
dd8079d6
TV		 3079 dsi_vc_enable(1, 1);
3080 dsi_vc_enable(2, 1);
3081 dsi_vc_enable(3, 1);
3de7a1dc
TV		 3082 dsi_if_enable(1);
3083 dsi_force_tx_stop_mode_io();
3084
3de7a1dc 3085 return 0;
3de7a1dc
TV		 3086err3:
3087 dsi_complexio_uninit();
3088err2:
2f18c4d8
TV		 3089 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3090 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3de7a1dc
TV		 3091err1:
3092 dsi_pll_uninit();
3093err0:
3094 return r;
3095}
3096
3097static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3098{
d7370104
VS		 3099 /* disable interface */
3100 dsi_if_enable(0);
3101 dsi_vc_enable(0, 0);
3102 dsi_vc_enable(1, 0);
3103 dsi_vc_enable(2, 0);
3104 dsi_vc_enable(3, 0);
3105
2f18c4d8
TV		 3106 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3107 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3de7a1dc
TV		 3108 dsi_complexio_uninit();
3109 dsi_pll_uninit();
3110}
3111
3112static int dsi_core_init(void)
3113{
3114 /* Autoidle */
3115 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3116
3117 /* ENWAKEUP */
3118 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3119
3120 /* SIDLEMODE smart-idle */
3121 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3122
3123 _dsi_initialize_irq();
3124
3125 return 0;
3126}
3127
37ac60e4 3128int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3129{
3130 int r = 0;
3131
3132 DSSDBG("dsi_display_enable\n");
3133
37ac60e4
TV		 3134 WARN_ON(!dsi_bus_is_locked());
3135
3de7a1dc 3136 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3137
3138 r = omap_dss_start_device(dssdev);
3139 if (r) {
3140 DSSERR("failed to start device\n");
3141 goto err0;
3142 }
3143
3de7a1dc
TV		 3144 enable_clocks(1);
3145 dsi_enable_pll_clock(1);
3146
3147 r = _dsi_reset();
3148 if (r)
37ac60e4 3149 goto err1;
3de7a1dc
TV		 3150
3151 dsi_core_init();
3152
3153 r = dsi_display_init_dispc(dssdev);
3154 if (r)
37ac60e4 3155 goto err1;
3de7a1dc
TV		 3156
3157 r = dsi_display_init_dsi(dssdev);
3158 if (r)
37ac60e4 3159 goto err2;
3de7a1dc 3160
3de7a1dc
TV		 3161 mutex_unlock(&dsi.lock);
3162
3163 return 0;
3164
3de7a1dc 3165err2:
37ac60e4
TV		 3166 dsi_display_uninit_dispc(dssdev);
3167err1:
3de7a1dc
TV		 3168 enable_clocks(0);
3169 dsi_enable_pll_clock(0);
3de7a1dc
TV		 3170 omap_dss_stop_device(dssdev);
3171err0:
3de7a1dc
TV		 3172 mutex_unlock(&dsi.lock);
3173 DSSDBG("dsi_display_enable FAILED\n");
3174 return r;
3175}
37ac60e4 3176EXPORT_SYMBOL(omapdss_dsi_display_enable);
3de7a1dc 3177
37ac60e4 3178void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3179{
3180 DSSDBG("dsi_display_disable\n");
3181
37ac60e4 3182 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 3183
3184 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3185
3186 dsi_display_uninit_dispc(dssdev);
3187
3188 dsi_display_uninit_dsi(dssdev);
3189
3190 enable_clocks(0);
3191 dsi_enable_pll_clock(0);
3de7a1dc 3192
37ac60e4 3193 omap_dss_stop_device(dssdev);
3de7a1dc 3194
3de7a1dc 3195 mutex_unlock(&dsi.lock);
3de7a1dc 3196}
37ac60e4 3197EXPORT_SYMBOL(omapdss_dsi_display_disable);
3de7a1dc 3198
225b650d 3199int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3de7a1dc 3200{
3de7a1dc 3201 dsi.te_enabled = enable;
225b650d 3202 return 0;
3de7a1dc 3203}
225b650d 3204EXPORT_SYMBOL(omapdss_dsi_enable_te);
3de7a1dc 3205
3de7a1dc
TV		 3206void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3207 u32 fifo_size, enum omap_burst_size *burst_size,
3208 u32 *fifo_low, u32 *fifo_high)
3209{
3210 unsigned burst_size_bytes;
3211
3212 *burst_size = OMAP_DSS_BURST_16x32;
3213 burst_size_bytes = 16 * 32 / 8;
3214
3215 *fifo_high = fifo_size - burst_size_bytes;
36194b47 3216 *fifo_low = fifo_size - burst_size_bytes * 2;
3de7a1dc
TV		 3217}
3218
3219int dsi_init_display(struct omap_dss_device *dssdev)
3220{
3221 DSSDBG("DSI init\n");
3222
3de7a1dc
TV		 3223 /* XXX these should be figured out dynamically */
3224 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3225 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3226
3227 dsi.vc[0].dssdev = dssdev;
3228 dsi.vc[1].dssdev = dssdev;
3229
5f42f2ce
TV		 3230 if (dsi.vdds_dsi_reg == NULL) {
3231 struct regulator *vdds_dsi;
3232
3233 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3234
3235 if (IS_ERR(vdds_dsi)) {
3236 DSSERR("can't get VDDS_DSI regulator\n");
3237 return PTR_ERR(vdds_dsi);
3238 }
3239
3240 dsi.vdds_dsi_reg = vdds_dsi;
3241 }
3242
3de7a1dc
TV		 3243 return 0;
3244}
3245
e406f907
TV		 3246void dsi_wait_dsi1_pll_active(void)
3247{
3248 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3249 DSSERR("DSI1 PLL clock not active\n");
3250}
3251
3252void dsi_wait_dsi2_pll_active(void)
3253{
3254 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3255 DSSERR("DSI2 PLL clock not active\n");
3256}
3257
c8aac01b 3258static int dsi_init(struct platform_device *pdev)
3de7a1dc
TV		 3259{
3260 u32 rev;
3261 int r;
ea9da36a 3262 struct resource *dsi_mem;
3de7a1dc
TV		 3263
3264 spin_lock_init(&dsi.errors_lock);
3265 dsi.errors = 0;
3266
dfc0fd8d
TV		 3267#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3268 spin_lock_init(&dsi.irq_stats_lock);
3269 dsi.irq_stats.last_reset = jiffies;
3270#endif
3271
3de7a1dc 3272 init_completion(&dsi.bta_completion);
3de7a1dc
TV		 3273
3274 mutex_init(&dsi.lock);
b9eb5d7d 3275 sema_init(&dsi.bus_lock, 1);
3de7a1dc 3276
0f16aa0a
TV		 3277 dsi.workqueue = create_singlethread_workqueue("dsi");
3278 if (dsi.workqueue == NULL)
3279 return -ENOMEM;
3280
18946f62
TV		 3281 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3282 dsi_framedone_timeout_work_callback);
3283
3de7a1dc
TV		 3284#ifdef DSI_CATCH_MISSING_TE
3285 init_timer(&dsi.te_timer);
3286 dsi.te_timer.function = dsi_te_timeout;
3287 dsi.te_timer.data = 0;
3288#endif
ea9da36a
SG		 3289 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3290 if (!dsi_mem) {
3291 DSSERR("can't get IORESOURCE_MEM DSI\n");
3292 r = -EINVAL;
3293 goto err1;
3294 }
3295 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3de7a1dc
TV		 3296 if (!dsi.base) {
3297 DSSERR("can't ioremap DSI\n");
3298 r = -ENOMEM;
3299 goto err1;
3300 }
affe360d 3301 dsi.irq = platform_get_irq(dsi.pdev, 0);
3302 if (dsi.irq < 0) {
3303 DSSERR("platform_get_irq failed\n");
3304 r = -ENODEV;
3305 goto err2;
3306 }
3307
3308 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
3309 "OMAP DSI1", dsi.pdev);
3310 if (r < 0) {
3311 DSSERR("request_irq failed\n");
3312 goto err2;
3313 }
3de7a1dc 3314
3de7a1dc
TV		 3315 enable_clocks(1);
3316
3317 rev = dsi_read_reg(DSI_REVISION);
a06b62f8 3318 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3de7a1dc
TV		 3319 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3320
3321 enable_clocks(0);
3322
3de7a1dc 3323 return 0;
affe360d 3324err2:
3325 iounmap(dsi.base);
3de7a1dc 3326err1:
0f16aa0a 3327 destroy_workqueue(dsi.workqueue);
3de7a1dc
TV		 3328 return r;
3329}
3330
c8aac01b 3331static void dsi_exit(void)
3de7a1dc 3332{
c8aac01b
SG		 3333 if (dsi.vdds_dsi_reg != NULL) {
3334 regulator_put(dsi.vdds_dsi_reg);
3335 dsi.vdds_dsi_reg = NULL;
3336 }
3337
affe360d 3338 free_irq(dsi.irq, dsi.pdev);
3de7a1dc
TV		 3339 iounmap(dsi.base);
3340
0f16aa0a
TV		 3341 destroy_workqueue(dsi.workqueue);
3342
3de7a1dc
TV		 3343 DSSDBG("omap_dsi_exit\n");
3344}
3345
c8aac01b
SG		 3346/* DSI1 HW IP initialisation */
3347static int omap_dsi1hw_probe(struct platform_device *pdev)
3348{
3349 int r;
3350 dsi.pdev = pdev;
3351 r = dsi_init(pdev);
3352 if (r) {
3353 DSSERR("Failed to initialize DSI\n");
3354 goto err_dsi;
3355 }
3356err_dsi:
3357 return r;
3358}
3359
3360static int omap_dsi1hw_remove(struct platform_device *pdev)
3361{
3362 dsi_exit();
3363 return 0;
3364}
3365
3366static struct platform_driver omap_dsi1hw_driver = {
3367 .probe = omap_dsi1hw_probe,
3368 .remove = omap_dsi1hw_remove,
3369 .driver = {
3370 .name = "omapdss_dsi1",
3371 .owner = THIS_MODULE,
3372 },
3373};
3374
3375int dsi_init_platform_driver(void)
3376{
3377 return platform_driver_register(&omap_dsi1hw_driver);
3378}
3379
3380void dsi_uninit_platform_driver(void)
3381{
3382 return platform_driver_unregister(&omap_dsi1hw_driver);
3383}
Linux 6.x block layer and io_uring tree(s)