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3de7a1dc TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dsi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "DSI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
b9eb5d7d | 30 | #include <linux/semaphore.h> |
3de7a1dc TV |
31 | #include <linux/seq_file.h> |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 34 | #include <linux/wait.h> |
18946f62 | 35 | #include <linux/workqueue.h> |
40885ab3 | 36 | #include <linux/sched.h> |
f1da39d9 | 37 | #include <linux/slab.h> |
5a8b572d | 38 | #include <linux/debugfs.h> |
4fbafaf3 | 39 | #include <linux/pm_runtime.h> |
3de7a1dc | 40 | |
a0b38cc4 | 41 | #include <video/omapdss.h> |
7a7c48f9 | 42 | #include <video/mipi_display.h> |
3de7a1dc TV |
43 | #include <plat/clock.h> |
44 | ||
45 | #include "dss.h" | |
819d807c | 46 | #include "dss_features.h" |
3de7a1dc TV |
47 | |
48 | /*#define VERBOSE_IRQ*/ | |
49 | #define DSI_CATCH_MISSING_TE | |
50 | ||
3de7a1dc TV |
51 | struct dsi_reg { u16 idx; }; |
52 | ||
53 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) | |
54 | ||
55 | #define DSI_SZ_REGS SZ_1K | |
56 | /* DSI Protocol Engine */ | |
57 | ||
58 | #define DSI_REVISION DSI_REG(0x0000) | |
59 | #define DSI_SYSCONFIG DSI_REG(0x0010) | |
60 | #define DSI_SYSSTATUS DSI_REG(0x0014) | |
61 | #define DSI_IRQSTATUS DSI_REG(0x0018) | |
62 | #define DSI_IRQENABLE DSI_REG(0x001C) | |
63 | #define DSI_CTRL DSI_REG(0x0040) | |
75d7247c | 64 | #define DSI_GNQ DSI_REG(0x0044) |
3de7a1dc TV |
65 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
66 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) | |
67 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) | |
68 | #define DSI_CLK_CTRL DSI_REG(0x0054) | |
69 | #define DSI_TIMING1 DSI_REG(0x0058) | |
70 | #define DSI_TIMING2 DSI_REG(0x005C) | |
71 | #define DSI_VM_TIMING1 DSI_REG(0x0060) | |
72 | #define DSI_VM_TIMING2 DSI_REG(0x0064) | |
73 | #define DSI_VM_TIMING3 DSI_REG(0x0068) | |
74 | #define DSI_CLK_TIMING DSI_REG(0x006C) | |
75 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) | |
76 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) | |
77 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) | |
78 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) | |
79 | #define DSI_VM_TIMING4 DSI_REG(0x0080) | |
80 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) | |
81 | #define DSI_VM_TIMING5 DSI_REG(0x0088) | |
82 | #define DSI_VM_TIMING6 DSI_REG(0x008C) | |
83 | #define DSI_VM_TIMING7 DSI_REG(0x0090) | |
84 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) | |
85 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) | |
86 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) | |
87 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) | |
88 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) | |
89 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) | |
90 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) | |
91 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) | |
92 | ||
93 | /* DSIPHY_SCP */ | |
94 | ||
95 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) | |
96 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) | |
97 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) | |
98 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) | |
0a0ee46b | 99 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
3de7a1dc TV |
100 | |
101 | /* DSI_PLL_CTRL_SCP */ | |
102 | ||
103 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) | |
104 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) | |
105 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) | |
106 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) | |
107 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) | |
108 | ||
a72b64b9 AT |
109 | #define REG_GET(dsidev, idx, start, end) \ |
110 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | |
3de7a1dc | 111 | |
a72b64b9 AT |
112 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
113 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) | |
3de7a1dc TV |
114 | |
115 | /* Global interrupts */ | |
116 | #define DSI_IRQ_VC0 (1 << 0) | |
117 | #define DSI_IRQ_VC1 (1 << 1) | |
118 | #define DSI_IRQ_VC2 (1 << 2) | |
119 | #define DSI_IRQ_VC3 (1 << 3) | |
120 | #define DSI_IRQ_WAKEUP (1 << 4) | |
121 | #define DSI_IRQ_RESYNC (1 << 5) | |
122 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
123 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
124 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
125 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
126 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
127 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
128 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
129 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
130 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
131 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
132 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
133 | #define DSI_IRQ_ERROR_MASK \ | |
134 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
135 | DSI_IRQ_TA_TIMEOUT) | |
136 | #define DSI_IRQ_CHANNEL_MASK 0xf | |
137 | ||
138 | /* Virtual channel interrupts */ | |
139 | #define DSI_VC_IRQ_CS (1 << 0) | |
140 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
141 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
142 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
143 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
144 | #define DSI_VC_IRQ_BTA (1 << 5) | |
145 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
146 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
147 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
148 | #define DSI_VC_IRQ_ERROR_MASK \ | |
149 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
150 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
151 | DSI_VC_IRQ_FIFO_TX_UDF) | |
152 | ||
153 | /* ComplexIO interrupts */ | |
154 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
155 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
156 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
6705615e TV |
157 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
158 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
3de7a1dc TV |
159 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
160 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
161 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
6705615e TV |
162 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
163 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
3de7a1dc TV |
164 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
165 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
166 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
6705615e TV |
167 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
168 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
3de7a1dc TV |
169 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
170 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
171 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
6705615e TV |
172 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
173 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
3de7a1dc TV |
174 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
175 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
6705615e TV |
180 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
181 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
182 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
183 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
3de7a1dc TV |
184 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
185 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
186 | #define DSI_CIO_IRQ_ERROR_MASK \ |
187 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
6705615e TV |
188 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
189 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
190 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
191 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
192 | DSI_CIO_IRQ_ERRESC5 | \ | |
193 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
194 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
195 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
bbecb50b TV |
196 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
197 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
6705615e TV |
198 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
199 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
200 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
3de7a1dc | 201 | |
4ae2dddd TV |
202 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
203 | ||
204 | #define DSI_MAX_NR_ISRS 2 | |
205 | ||
206 | struct dsi_isr_data { | |
207 | omap_dsi_isr_t isr; | |
208 | void *arg; | |
209 | u32 mask; | |
210 | }; | |
211 | ||
3de7a1dc TV |
212 | enum fifo_size { |
213 | DSI_FIFO_SIZE_0 = 0, | |
214 | DSI_FIFO_SIZE_32 = 1, | |
215 | DSI_FIFO_SIZE_64 = 2, | |
216 | DSI_FIFO_SIZE_96 = 3, | |
217 | DSI_FIFO_SIZE_128 = 4, | |
218 | }; | |
219 | ||
d6049144 AT |
220 | enum dsi_vc_source { |
221 | DSI_VC_SOURCE_L4 = 0, | |
222 | DSI_VC_SOURCE_VP, | |
3de7a1dc TV |
223 | }; |
224 | ||
0a0ee46b TV |
225 | enum dsi_lane { |
226 | DSI_CLK_P = 1 << 0, | |
227 | DSI_CLK_N = 1 << 1, | |
228 | DSI_DATA1_P = 1 << 2, | |
229 | DSI_DATA1_N = 1 << 3, | |
230 | DSI_DATA2_P = 1 << 4, | |
231 | DSI_DATA2_N = 1 << 5, | |
75d7247c AT |
232 | DSI_DATA3_P = 1 << 6, |
233 | DSI_DATA3_N = 1 << 7, | |
234 | DSI_DATA4_P = 1 << 8, | |
235 | DSI_DATA4_N = 1 << 9, | |
0a0ee46b TV |
236 | }; |
237 | ||
3de7a1dc | 238 | struct dsi_update_region { |
3de7a1dc TV |
239 | u16 x, y, w, h; |
240 | struct omap_dss_device *device; | |
241 | }; | |
242 | ||
dfc0fd8d TV |
243 | struct dsi_irq_stats { |
244 | unsigned long last_reset; | |
245 | unsigned irq_count; | |
246 | unsigned dsi_irqs[32]; | |
247 | unsigned vc_irqs[4][32]; | |
248 | unsigned cio_irqs[32]; | |
249 | }; | |
250 | ||
4ae2dddd TV |
251 | struct dsi_isr_tables { |
252 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
253 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
254 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
255 | }; | |
256 | ||
f1da39d9 | 257 | struct dsi_data { |
c8aac01b | 258 | struct platform_device *pdev; |
3de7a1dc | 259 | void __iomem *base; |
4fbafaf3 | 260 | |
affe360d | 261 | int irq; |
3de7a1dc | 262 | |
4fbafaf3 TV |
263 | struct clk *dss_clk; |
264 | struct clk *sys_clk; | |
265 | ||
5bc416cb TV |
266 | int (*enable_pads)(int dsi_id, unsigned lane_mask); |
267 | void (*disable_pads)(int dsi_id, unsigned lane_mask); | |
d1f5857e | 268 | |
3de7a1dc TV |
269 | struct dsi_clock_info current_cinfo; |
270 | ||
2a89dc15 | 271 | bool vdds_dsi_enabled; |
3de7a1dc TV |
272 | struct regulator *vdds_dsi_reg; |
273 | ||
274 | struct { | |
d6049144 | 275 | enum dsi_vc_source source; |
3de7a1dc TV |
276 | struct omap_dss_device *dssdev; |
277 | enum fifo_size fifo_size; | |
5ee3c144 | 278 | int vc_id; |
3de7a1dc TV |
279 | } vc[4]; |
280 | ||
281 | struct mutex lock; | |
b9eb5d7d | 282 | struct semaphore bus_lock; |
3de7a1dc TV |
283 | |
284 | unsigned pll_locked; | |
285 | ||
4ae2dddd TV |
286 | spinlock_t irq_lock; |
287 | struct dsi_isr_tables isr_tables; | |
288 | /* space for a copy used by the interrupt handler */ | |
289 | struct dsi_isr_tables isr_tables_copy; | |
290 | ||
18946f62 | 291 | int update_channel; |
3de7a1dc | 292 | struct dsi_update_region update_region; |
3de7a1dc | 293 | |
3de7a1dc | 294 | bool te_enabled; |
40885ab3 | 295 | bool ulps_enabled; |
3de7a1dc | 296 | |
18946f62 TV |
297 | void (*framedone_callback)(int, void *); |
298 | void *framedone_data; | |
299 | ||
300 | struct delayed_work framedone_timeout_work; | |
301 | ||
3de7a1dc TV |
302 | #ifdef DSI_CATCH_MISSING_TE |
303 | struct timer_list te_timer; | |
304 | #endif | |
305 | ||
306 | unsigned long cache_req_pck; | |
307 | unsigned long cache_clk_freq; | |
308 | struct dsi_clock_info cache_cinfo; | |
309 | ||
310 | u32 errors; | |
311 | spinlock_t errors_lock; | |
312 | #ifdef DEBUG | |
313 | ktime_t perf_setup_time; | |
314 | ktime_t perf_start_time; | |
3de7a1dc TV |
315 | #endif |
316 | int debug_read; | |
317 | int debug_write; | |
dfc0fd8d TV |
318 | |
319 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
320 | spinlock_t irq_stats_lock; | |
321 | struct dsi_irq_stats irq_stats; | |
322 | #endif | |
49641116 TA |
323 | /* DSI PLL Parameter Ranges */ |
324 | unsigned long regm_max, regn_max; | |
325 | unsigned long regm_dispc_max, regm_dsi_max; | |
326 | unsigned long fint_min, fint_max; | |
327 | unsigned long lpdiv_max; | |
24c1ae41 | 328 | |
75d7247c AT |
329 | int num_data_lanes; |
330 | ||
24c1ae41 | 331 | unsigned scp_clk_refcount; |
f1da39d9 | 332 | }; |
3de7a1dc | 333 | |
2e868dbe AT |
334 | struct dsi_packet_sent_handler_data { |
335 | struct platform_device *dsidev; | |
336 | struct completion *completion; | |
337 | }; | |
338 | ||
a72b64b9 AT |
339 | static struct platform_device *dsi_pdev_map[MAX_NUM_DSI]; |
340 | ||
3de7a1dc TV |
341 | #ifdef DEBUG |
342 | static unsigned int dsi_perf; | |
343 | module_param_named(dsi_perf, dsi_perf, bool, 0644); | |
344 | #endif | |
345 | ||
f1da39d9 AT |
346 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
347 | { | |
348 | return dev_get_drvdata(&dsidev->dev); | |
349 | } | |
350 | ||
a72b64b9 AT |
351 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
352 | { | |
353 | return dsi_pdev_map[dssdev->phy.dsi.module]; | |
354 | } | |
355 | ||
356 | struct platform_device *dsi_get_dsidev_from_id(int module) | |
357 | { | |
358 | return dsi_pdev_map[module]; | |
359 | } | |
360 | ||
7c68dd96 | 361 | static inline int dsi_get_dsidev_id(struct platform_device *dsidev) |
f1da39d9 | 362 | { |
7c68dd96 | 363 | return dsidev->id; |
f1da39d9 AT |
364 | } |
365 | ||
a72b64b9 AT |
366 | static inline void dsi_write_reg(struct platform_device *dsidev, |
367 | const struct dsi_reg idx, u32 val) | |
3de7a1dc | 368 | { |
f1da39d9 AT |
369 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
370 | ||
371 | __raw_writel(val, dsi->base + idx.idx); | |
3de7a1dc TV |
372 | } |
373 | ||
a72b64b9 AT |
374 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
375 | const struct dsi_reg idx) | |
3de7a1dc | 376 | { |
f1da39d9 AT |
377 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
378 | ||
379 | return __raw_readl(dsi->base + idx.idx); | |
3de7a1dc TV |
380 | } |
381 | ||
1ffefe75 | 382 | void dsi_bus_lock(struct omap_dss_device *dssdev) |
3de7a1dc | 383 | { |
f1da39d9 AT |
384 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
385 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
386 | ||
387 | down(&dsi->bus_lock); | |
3de7a1dc TV |
388 | } |
389 | EXPORT_SYMBOL(dsi_bus_lock); | |
390 | ||
1ffefe75 | 391 | void dsi_bus_unlock(struct omap_dss_device *dssdev) |
3de7a1dc | 392 | { |
f1da39d9 AT |
393 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
394 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
395 | ||
396 | up(&dsi->bus_lock); | |
3de7a1dc TV |
397 | } |
398 | EXPORT_SYMBOL(dsi_bus_unlock); | |
399 | ||
a72b64b9 | 400 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
4f765023 | 401 | { |
f1da39d9 AT |
402 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
403 | ||
404 | return dsi->bus_lock.count == 0; | |
4f765023 TV |
405 | } |
406 | ||
f36a06e7 TV |
407 | static void dsi_completion_handler(void *data, u32 mask) |
408 | { | |
409 | complete((struct completion *)data); | |
410 | } | |
411 | ||
a72b64b9 AT |
412 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
413 | const struct dsi_reg idx, int bitnum, int value) | |
3de7a1dc TV |
414 | { |
415 | int t = 100000; | |
416 | ||
a72b64b9 | 417 | while (REG_GET(dsidev, idx, bitnum, bitnum) != value) { |
3de7a1dc TV |
418 | if (--t == 0) |
419 | return !value; | |
420 | } | |
421 | ||
422 | return value; | |
423 | } | |
424 | ||
a3b3cc2b AT |
425 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
426 | { | |
427 | switch (fmt) { | |
428 | case OMAP_DSS_DSI_FMT_RGB888: | |
429 | case OMAP_DSS_DSI_FMT_RGB666: | |
430 | return 24; | |
431 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
432 | return 18; | |
433 | case OMAP_DSS_DSI_FMT_RGB565: | |
434 | return 16; | |
435 | default: | |
436 | BUG(); | |
437 | } | |
438 | } | |
439 | ||
3de7a1dc | 440 | #ifdef DEBUG |
a72b64b9 | 441 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
3de7a1dc | 442 | { |
f1da39d9 AT |
443 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
444 | dsi->perf_setup_time = ktime_get(); | |
3de7a1dc TV |
445 | } |
446 | ||
a72b64b9 | 447 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
3de7a1dc | 448 | { |
f1da39d9 AT |
449 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
450 | dsi->perf_start_time = ktime_get(); | |
3de7a1dc TV |
451 | } |
452 | ||
a72b64b9 | 453 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
3de7a1dc | 454 | { |
f1da39d9 | 455 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a3b3cc2b | 456 | struct omap_dss_device *dssdev = dsi->update_region.device; |
3de7a1dc TV |
457 | ktime_t t, setup_time, trans_time; |
458 | u32 total_bytes; | |
459 | u32 setup_us, trans_us, total_us; | |
460 | ||
461 | if (!dsi_perf) | |
462 | return; | |
463 | ||
3de7a1dc TV |
464 | t = ktime_get(); |
465 | ||
f1da39d9 | 466 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
3de7a1dc TV |
467 | setup_us = (u32)ktime_to_us(setup_time); |
468 | if (setup_us == 0) | |
469 | setup_us = 1; | |
470 | ||
f1da39d9 | 471 | trans_time = ktime_sub(t, dsi->perf_start_time); |
3de7a1dc TV |
472 | trans_us = (u32)ktime_to_us(trans_time); |
473 | if (trans_us == 0) | |
474 | trans_us = 1; | |
475 | ||
476 | total_us = setup_us + trans_us; | |
477 | ||
f1da39d9 AT |
478 | total_bytes = dsi->update_region.w * |
479 | dsi->update_region.h * | |
a3b3cc2b | 480 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
3de7a1dc | 481 | |
1bbb275e TV |
482 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
483 | "%u bytes, %u kbytes/sec\n", | |
484 | name, | |
485 | setup_us, | |
486 | trans_us, | |
487 | total_us, | |
488 | 1000*1000 / total_us, | |
489 | total_bytes, | |
490 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
491 | } |
492 | #else | |
4a9a5e39 TV |
493 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
494 | { | |
495 | } | |
496 | ||
497 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) | |
498 | { | |
499 | } | |
500 | ||
501 | static inline void dsi_perf_show(struct platform_device *dsidev, | |
502 | const char *name) | |
503 | { | |
504 | } | |
3de7a1dc TV |
505 | #endif |
506 | ||
507 | static void print_irq_status(u32 status) | |
508 | { | |
d80d499e TV |
509 | if (status == 0) |
510 | return; | |
511 | ||
3de7a1dc TV |
512 | #ifndef VERBOSE_IRQ |
513 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) | |
514 | return; | |
515 | #endif | |
516 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); | |
517 | ||
518 | #define PIS(x) \ | |
519 | if (status & DSI_IRQ_##x) \ | |
520 | printk(#x " "); | |
521 | #ifdef VERBOSE_IRQ | |
522 | PIS(VC0); | |
523 | PIS(VC1); | |
524 | PIS(VC2); | |
525 | PIS(VC3); | |
526 | #endif | |
527 | PIS(WAKEUP); | |
528 | PIS(RESYNC); | |
529 | PIS(PLL_LOCK); | |
530 | PIS(PLL_UNLOCK); | |
531 | PIS(PLL_RECALL); | |
532 | PIS(COMPLEXIO_ERR); | |
533 | PIS(HS_TX_TIMEOUT); | |
534 | PIS(LP_RX_TIMEOUT); | |
535 | PIS(TE_TRIGGER); | |
536 | PIS(ACK_TRIGGER); | |
537 | PIS(SYNC_LOST); | |
538 | PIS(LDO_POWER_GOOD); | |
539 | PIS(TA_TIMEOUT); | |
540 | #undef PIS | |
541 | ||
542 | printk("\n"); | |
543 | } | |
544 | ||
545 | static void print_irq_status_vc(int channel, u32 status) | |
546 | { | |
d80d499e TV |
547 | if (status == 0) |
548 | return; | |
549 | ||
3de7a1dc TV |
550 | #ifndef VERBOSE_IRQ |
551 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) | |
552 | return; | |
553 | #endif | |
554 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); | |
555 | ||
556 | #define PIS(x) \ | |
557 | if (status & DSI_VC_IRQ_##x) \ | |
558 | printk(#x " "); | |
559 | PIS(CS); | |
560 | PIS(ECC_CORR); | |
561 | #ifdef VERBOSE_IRQ | |
562 | PIS(PACKET_SENT); | |
563 | #endif | |
564 | PIS(FIFO_TX_OVF); | |
565 | PIS(FIFO_RX_OVF); | |
566 | PIS(BTA); | |
567 | PIS(ECC_NO_CORR); | |
568 | PIS(FIFO_TX_UDF); | |
569 | PIS(PP_BUSY_CHANGE); | |
570 | #undef PIS | |
571 | printk("\n"); | |
572 | } | |
573 | ||
574 | static void print_irq_status_cio(u32 status) | |
575 | { | |
d80d499e TV |
576 | if (status == 0) |
577 | return; | |
578 | ||
3de7a1dc TV |
579 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
580 | ||
581 | #define PIS(x) \ | |
582 | if (status & DSI_CIO_IRQ_##x) \ | |
583 | printk(#x " "); | |
584 | PIS(ERRSYNCESC1); | |
585 | PIS(ERRSYNCESC2); | |
586 | PIS(ERRSYNCESC3); | |
587 | PIS(ERRESC1); | |
588 | PIS(ERRESC2); | |
589 | PIS(ERRESC3); | |
590 | PIS(ERRCONTROL1); | |
591 | PIS(ERRCONTROL2); | |
592 | PIS(ERRCONTROL3); | |
593 | PIS(STATEULPS1); | |
594 | PIS(STATEULPS2); | |
595 | PIS(STATEULPS3); | |
596 | PIS(ERRCONTENTIONLP0_1); | |
597 | PIS(ERRCONTENTIONLP1_1); | |
598 | PIS(ERRCONTENTIONLP0_2); | |
599 | PIS(ERRCONTENTIONLP1_2); | |
600 | PIS(ERRCONTENTIONLP0_3); | |
601 | PIS(ERRCONTENTIONLP1_3); | |
602 | PIS(ULPSACTIVENOT_ALL0); | |
603 | PIS(ULPSACTIVENOT_ALL1); | |
604 | #undef PIS | |
605 | ||
606 | printk("\n"); | |
607 | } | |
608 | ||
69b281a6 | 609 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
a72b64b9 AT |
610 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
611 | u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 612 | { |
f1da39d9 | 613 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
614 | int i; |
615 | ||
f1da39d9 | 616 | spin_lock(&dsi->irq_stats_lock); |
69b281a6 | 617 | |
f1da39d9 AT |
618 | dsi->irq_stats.irq_count++; |
619 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
69b281a6 TV |
620 | |
621 | for (i = 0; i < 4; ++i) | |
f1da39d9 | 622 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
69b281a6 | 623 | |
f1da39d9 | 624 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
69b281a6 | 625 | |
f1da39d9 | 626 | spin_unlock(&dsi->irq_stats_lock); |
69b281a6 TV |
627 | } |
628 | #else | |
a72b64b9 | 629 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
dfc0fd8d TV |
630 | #endif |
631 | ||
69b281a6 TV |
632 | static int debug_irq; |
633 | ||
a72b64b9 AT |
634 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
635 | u32 *vcstatus, u32 ciostatus) | |
69b281a6 | 636 | { |
f1da39d9 | 637 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
69b281a6 TV |
638 | int i; |
639 | ||
3de7a1dc TV |
640 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
641 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
642 | print_irq_status(irqstatus); | |
f1da39d9 AT |
643 | spin_lock(&dsi->errors_lock); |
644 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
645 | spin_unlock(&dsi->errors_lock); | |
3de7a1dc TV |
646 | } else if (debug_irq) { |
647 | print_irq_status(irqstatus); | |
648 | } | |
649 | ||
3de7a1dc | 650 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
651 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
652 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
653 | i, vcstatus[i]); | |
654 | print_irq_status_vc(i, vcstatus[i]); | |
655 | } else if (debug_irq) { | |
656 | print_irq_status_vc(i, vcstatus[i]); | |
657 | } | |
658 | } | |
3de7a1dc | 659 | |
69b281a6 TV |
660 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
661 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
662 | print_irq_status_cio(ciostatus); | |
663 | } else if (debug_irq) { | |
664 | print_irq_status_cio(ciostatus); | |
665 | } | |
666 | } | |
3de7a1dc | 667 | |
4ae2dddd TV |
668 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
669 | unsigned isr_array_size, u32 irqstatus) | |
670 | { | |
671 | struct dsi_isr_data *isr_data; | |
672 | int i; | |
673 | ||
674 | for (i = 0; i < isr_array_size; i++) { | |
675 | isr_data = &isr_array[i]; | |
676 | if (isr_data->isr && isr_data->mask & irqstatus) | |
677 | isr_data->isr(isr_data->arg, irqstatus); | |
678 | } | |
679 | } | |
680 | ||
681 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
682 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
683 | { | |
684 | int i; | |
685 | ||
686 | dsi_call_isrs(isr_tables->isr_table, | |
687 | ARRAY_SIZE(isr_tables->isr_table), | |
688 | irqstatus); | |
689 | ||
690 | for (i = 0; i < 4; ++i) { | |
691 | if (vcstatus[i] == 0) | |
692 | continue; | |
693 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
694 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
695 | vcstatus[i]); | |
696 | } | |
697 | ||
698 | if (ciostatus != 0) | |
699 | dsi_call_isrs(isr_tables->isr_table_cio, | |
700 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
701 | ciostatus); | |
702 | } | |
703 | ||
69b281a6 TV |
704 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
705 | { | |
a72b64b9 | 706 | struct platform_device *dsidev; |
f1da39d9 | 707 | struct dsi_data *dsi; |
69b281a6 TV |
708 | u32 irqstatus, vcstatus[4], ciostatus; |
709 | int i; | |
dfc0fd8d | 710 | |
a72b64b9 | 711 | dsidev = (struct platform_device *) arg; |
f1da39d9 | 712 | dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 713 | |
f1da39d9 | 714 | spin_lock(&dsi->irq_lock); |
4ae2dddd | 715 | |
a72b64b9 | 716 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
3de7a1dc | 717 | |
69b281a6 | 718 | /* IRQ is not for us */ |
4ae2dddd | 719 | if (!irqstatus) { |
f1da39d9 | 720 | spin_unlock(&dsi->irq_lock); |
69b281a6 | 721 | return IRQ_NONE; |
4ae2dddd | 722 | } |
ab83b14c | 723 | |
a72b64b9 | 724 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
69b281a6 | 725 | /* flush posted write */ |
a72b64b9 | 726 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
69b281a6 TV |
727 | |
728 | for (i = 0; i < 4; ++i) { | |
729 | if ((irqstatus & (1 << i)) == 0) { | |
730 | vcstatus[i] = 0; | |
731 | continue; | |
3de7a1dc TV |
732 | } |
733 | ||
a72b64b9 | 734 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
69b281a6 | 735 | |
a72b64b9 | 736 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
3de7a1dc | 737 | /* flush posted write */ |
a72b64b9 | 738 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
3de7a1dc TV |
739 | } |
740 | ||
741 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
a72b64b9 | 742 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
3de7a1dc | 743 | |
a72b64b9 | 744 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
3de7a1dc | 745 | /* flush posted write */ |
a72b64b9 | 746 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
69b281a6 TV |
747 | } else { |
748 | ciostatus = 0; | |
749 | } | |
3de7a1dc | 750 | |
69b281a6 TV |
751 | #ifdef DSI_CATCH_MISSING_TE |
752 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
f1da39d9 | 753 | del_timer(&dsi->te_timer); |
69b281a6 TV |
754 | #endif |
755 | ||
4ae2dddd TV |
756 | /* make a copy and unlock, so that isrs can unregister |
757 | * themselves */ | |
f1da39d9 AT |
758 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
759 | sizeof(dsi->isr_tables)); | |
4ae2dddd | 760 | |
f1da39d9 | 761 | spin_unlock(&dsi->irq_lock); |
4ae2dddd | 762 | |
f1da39d9 | 763 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
4ae2dddd | 764 | |
a72b64b9 | 765 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
69b281a6 | 766 | |
a72b64b9 | 767 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
dfc0fd8d | 768 | |
affe360d | 769 | return IRQ_HANDLED; |
3de7a1dc TV |
770 | } |
771 | ||
f1da39d9 | 772 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 AT |
773 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
774 | struct dsi_isr_data *isr_array, | |
4ae2dddd TV |
775 | unsigned isr_array_size, u32 default_mask, |
776 | const struct dsi_reg enable_reg, | |
777 | const struct dsi_reg status_reg) | |
3de7a1dc | 778 | { |
4ae2dddd TV |
779 | struct dsi_isr_data *isr_data; |
780 | u32 mask; | |
781 | u32 old_mask; | |
3de7a1dc TV |
782 | int i; |
783 | ||
4ae2dddd | 784 | mask = default_mask; |
3de7a1dc | 785 | |
4ae2dddd TV |
786 | for (i = 0; i < isr_array_size; i++) { |
787 | isr_data = &isr_array[i]; | |
3de7a1dc | 788 | |
4ae2dddd TV |
789 | if (isr_data->isr == NULL) |
790 | continue; | |
791 | ||
792 | mask |= isr_data->mask; | |
3de7a1dc TV |
793 | } |
794 | ||
a72b64b9 | 795 | old_mask = dsi_read_reg(dsidev, enable_reg); |
4ae2dddd | 796 | /* clear the irqstatus for newly enabled irqs */ |
a72b64b9 AT |
797 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
798 | dsi_write_reg(dsidev, enable_reg, mask); | |
4ae2dddd TV |
799 | |
800 | /* flush posted writes */ | |
a72b64b9 AT |
801 | dsi_read_reg(dsidev, enable_reg); |
802 | dsi_read_reg(dsidev, status_reg); | |
4ae2dddd | 803 | } |
3de7a1dc | 804 | |
f1da39d9 | 805 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 806 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
4ae2dddd | 807 | { |
f1da39d9 | 808 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd | 809 | u32 mask = DSI_IRQ_ERROR_MASK; |
3de7a1dc | 810 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 811 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 812 | #endif |
f1da39d9 AT |
813 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
814 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, | |
4ae2dddd TV |
815 | DSI_IRQENABLE, DSI_IRQSTATUS); |
816 | } | |
3de7a1dc | 817 | |
f1da39d9 | 818 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 819 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
4ae2dddd | 820 | { |
f1da39d9 AT |
821 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
822 | ||
823 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], | |
824 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), | |
4ae2dddd TV |
825 | DSI_VC_IRQ_ERROR_MASK, |
826 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
827 | } | |
828 | ||
f1da39d9 | 829 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 830 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
4ae2dddd | 831 | { |
f1da39d9 AT |
832 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
833 | ||
834 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, | |
835 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), | |
4ae2dddd TV |
836 | DSI_CIO_IRQ_ERROR_MASK, |
837 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
838 | } | |
839 | ||
a72b64b9 | 840 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
4ae2dddd | 841 | { |
f1da39d9 | 842 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
843 | unsigned long flags; |
844 | int vc; | |
845 | ||
f1da39d9 | 846 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 847 | |
f1da39d9 | 848 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
4ae2dddd | 849 | |
a72b64b9 | 850 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 851 | for (vc = 0; vc < 4; ++vc) |
a72b64b9 AT |
852 | _omap_dsi_set_irqs_vc(dsidev, vc); |
853 | _omap_dsi_set_irqs_cio(dsidev); | |
4ae2dddd | 854 | |
f1da39d9 | 855 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd | 856 | } |
3de7a1dc | 857 | |
4ae2dddd TV |
858 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
859 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
860 | { | |
861 | struct dsi_isr_data *isr_data; | |
862 | int free_idx; | |
863 | int i; | |
864 | ||
865 | BUG_ON(isr == NULL); | |
866 | ||
867 | /* check for duplicate entry and find a free slot */ | |
868 | free_idx = -1; | |
869 | for (i = 0; i < isr_array_size; i++) { | |
870 | isr_data = &isr_array[i]; | |
871 | ||
872 | if (isr_data->isr == isr && isr_data->arg == arg && | |
873 | isr_data->mask == mask) { | |
874 | return -EINVAL; | |
875 | } | |
876 | ||
877 | if (isr_data->isr == NULL && free_idx == -1) | |
878 | free_idx = i; | |
879 | } | |
880 | ||
881 | if (free_idx == -1) | |
882 | return -EBUSY; | |
883 | ||
884 | isr_data = &isr_array[free_idx]; | |
885 | isr_data->isr = isr; | |
886 | isr_data->arg = arg; | |
887 | isr_data->mask = mask; | |
888 | ||
889 | return 0; | |
890 | } | |
891 | ||
892 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
893 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
894 | { | |
895 | struct dsi_isr_data *isr_data; | |
896 | int i; | |
897 | ||
898 | for (i = 0; i < isr_array_size; i++) { | |
899 | isr_data = &isr_array[i]; | |
900 | if (isr_data->isr != isr || isr_data->arg != arg || | |
901 | isr_data->mask != mask) | |
902 | continue; | |
903 | ||
904 | isr_data->isr = NULL; | |
905 | isr_data->arg = NULL; | |
906 | isr_data->mask = 0; | |
907 | ||
908 | return 0; | |
909 | } | |
910 | ||
911 | return -EINVAL; | |
912 | } | |
913 | ||
a72b64b9 AT |
914 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
915 | void *arg, u32 mask) | |
4ae2dddd | 916 | { |
f1da39d9 | 917 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
918 | unsigned long flags; |
919 | int r; | |
920 | ||
f1da39d9 | 921 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 922 | |
f1da39d9 AT |
923 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
924 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
925 | |
926 | if (r == 0) | |
a72b64b9 | 927 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 928 | |
f1da39d9 | 929 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
930 | |
931 | return r; | |
932 | } | |
933 | ||
a72b64b9 AT |
934 | static int dsi_unregister_isr(struct platform_device *dsidev, |
935 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 936 | { |
f1da39d9 | 937 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
938 | unsigned long flags; |
939 | int r; | |
940 | ||
f1da39d9 | 941 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 942 | |
f1da39d9 AT |
943 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
944 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
945 | |
946 | if (r == 0) | |
a72b64b9 | 947 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 948 | |
f1da39d9 | 949 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
950 | |
951 | return r; | |
952 | } | |
953 | ||
a72b64b9 AT |
954 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
955 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 956 | { |
f1da39d9 | 957 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
958 | unsigned long flags; |
959 | int r; | |
960 | ||
f1da39d9 | 961 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
962 | |
963 | r = _dsi_register_isr(isr, arg, mask, | |
f1da39d9 AT |
964 | dsi->isr_tables.isr_table_vc[channel], |
965 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
966 | |
967 | if (r == 0) | |
a72b64b9 | 968 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 969 | |
f1da39d9 | 970 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
971 | |
972 | return r; | |
973 | } | |
974 | ||
a72b64b9 AT |
975 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
976 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 977 | { |
f1da39d9 | 978 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
979 | unsigned long flags; |
980 | int r; | |
981 | ||
f1da39d9 | 982 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
983 | |
984 | r = _dsi_unregister_isr(isr, arg, mask, | |
f1da39d9 AT |
985 | dsi->isr_tables.isr_table_vc[channel], |
986 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
987 | |
988 | if (r == 0) | |
a72b64b9 | 989 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 990 | |
f1da39d9 | 991 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
992 | |
993 | return r; | |
994 | } | |
995 | ||
a72b64b9 AT |
996 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
997 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 998 | { |
f1da39d9 | 999 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1000 | unsigned long flags; |
1001 | int r; | |
1002 | ||
f1da39d9 | 1003 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1004 | |
f1da39d9 AT |
1005 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1006 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1007 | |
1008 | if (r == 0) | |
a72b64b9 | 1009 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1010 | |
f1da39d9 | 1011 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1012 | |
1013 | return r; | |
1014 | } | |
1015 | ||
a72b64b9 AT |
1016 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
1017 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1018 | { |
f1da39d9 | 1019 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1020 | unsigned long flags; |
1021 | int r; | |
1022 | ||
f1da39d9 | 1023 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1024 | |
f1da39d9 AT |
1025 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1026 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1027 | |
1028 | if (r == 0) | |
a72b64b9 | 1029 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1030 | |
f1da39d9 | 1031 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1032 | |
1033 | return r; | |
3de7a1dc TV |
1034 | } |
1035 | ||
a72b64b9 | 1036 | static u32 dsi_get_errors(struct platform_device *dsidev) |
3de7a1dc | 1037 | { |
f1da39d9 | 1038 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1039 | unsigned long flags; |
1040 | u32 e; | |
f1da39d9 AT |
1041 | spin_lock_irqsave(&dsi->errors_lock, flags); |
1042 | e = dsi->errors; | |
1043 | dsi->errors = 0; | |
1044 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
3de7a1dc TV |
1045 | return e; |
1046 | } | |
1047 | ||
4fbafaf3 | 1048 | int dsi_runtime_get(struct platform_device *dsidev) |
3de7a1dc | 1049 | { |
4fbafaf3 TV |
1050 | int r; |
1051 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1052 | ||
1053 | DSSDBG("dsi_runtime_get\n"); | |
1054 | ||
1055 | r = pm_runtime_get_sync(&dsi->pdev->dev); | |
1056 | WARN_ON(r < 0); | |
1057 | return r < 0 ? r : 0; | |
1058 | } | |
1059 | ||
1060 | void dsi_runtime_put(struct platform_device *dsidev) | |
1061 | { | |
1062 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1063 | int r; | |
1064 | ||
1065 | DSSDBG("dsi_runtime_put\n"); | |
1066 | ||
1067 | r = pm_runtime_put(&dsi->pdev->dev); | |
1068 | WARN_ON(r < 0); | |
3de7a1dc TV |
1069 | } |
1070 | ||
1071 | /* source clock for DSI PLL. this could also be PCLKFREE */ | |
a72b64b9 AT |
1072 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
1073 | bool enable) | |
3de7a1dc | 1074 | { |
f1da39d9 AT |
1075 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1076 | ||
3de7a1dc | 1077 | if (enable) |
4fbafaf3 | 1078 | clk_enable(dsi->sys_clk); |
3de7a1dc | 1079 | else |
4fbafaf3 | 1080 | clk_disable(dsi->sys_clk); |
3de7a1dc | 1081 | |
f1da39d9 | 1082 | if (enable && dsi->pll_locked) { |
a72b64b9 | 1083 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
3de7a1dc TV |
1084 | DSSERR("cannot lock PLL when enabling clocks\n"); |
1085 | } | |
1086 | } | |
1087 | ||
1088 | #ifdef DEBUG | |
a72b64b9 | 1089 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
3de7a1dc TV |
1090 | { |
1091 | u32 l; | |
c335cbf9 | 1092 | int b0, b1, b2; |
3de7a1dc TV |
1093 | |
1094 | if (!dss_debug) | |
1095 | return; | |
1096 | ||
1097 | /* A dummy read using the SCP interface to any DSIPHY register is | |
1098 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1099 | * I/O. */ | |
a72b64b9 | 1100 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc TV |
1101 | |
1102 | printk(KERN_DEBUG "DSI resets: "); | |
1103 | ||
a72b64b9 | 1104 | l = dsi_read_reg(dsidev, DSI_PLL_STATUS); |
3de7a1dc TV |
1105 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
1106 | ||
a72b64b9 | 1107 | l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
3de7a1dc TV |
1108 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
1109 | ||
c335cbf9 TV |
1110 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
1111 | b0 = 28; | |
1112 | b1 = 27; | |
1113 | b2 = 26; | |
1114 | } else { | |
1115 | b0 = 24; | |
1116 | b1 = 25; | |
1117 | b2 = 26; | |
1118 | } | |
1119 | ||
a72b64b9 | 1120 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
c335cbf9 TV |
1121 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
1122 | FLD_GET(l, b0, b0), | |
1123 | FLD_GET(l, b1, b1), | |
1124 | FLD_GET(l, b2, b2), | |
3de7a1dc TV |
1125 | FLD_GET(l, 29, 29), |
1126 | FLD_GET(l, 30, 30), | |
1127 | FLD_GET(l, 31, 31)); | |
1128 | } | |
1129 | #else | |
a72b64b9 | 1130 | #define _dsi_print_reset_status(x) |
3de7a1dc TV |
1131 | #endif |
1132 | ||
a72b64b9 | 1133 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
3de7a1dc TV |
1134 | { |
1135 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1136 | ||
1137 | enable = enable ? 1 : 0; | |
a72b64b9 | 1138 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
3de7a1dc | 1139 | |
a72b64b9 | 1140 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
3de7a1dc TV |
1141 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
1142 | return -EIO; | |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
a72b64b9 | 1148 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
3de7a1dc | 1149 | { |
f1da39d9 AT |
1150 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1151 | ||
1152 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; | |
3de7a1dc TV |
1153 | } |
1154 | ||
a72b64b9 | 1155 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
3de7a1dc | 1156 | { |
f1da39d9 AT |
1157 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1158 | ||
1159 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; | |
3de7a1dc TV |
1160 | } |
1161 | ||
a72b64b9 | 1162 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
3de7a1dc | 1163 | { |
f1da39d9 AT |
1164 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1165 | ||
1166 | return dsi->current_cinfo.clkin4ddr / 16; | |
3de7a1dc TV |
1167 | } |
1168 | ||
a72b64b9 | 1169 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
3de7a1dc TV |
1170 | { |
1171 | unsigned long r; | |
5a8b572d | 1172 | int dsi_module = dsi_get_dsidev_id(dsidev); |
4fbafaf3 | 1173 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc | 1174 | |
5a8b572d | 1175 | if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) { |
1bb47835 | 1176 | /* DSI FCLK source is DSS_CLK_FCK */ |
4fbafaf3 | 1177 | r = clk_get_rate(dsi->dss_clk); |
3de7a1dc | 1178 | } else { |
1bb47835 | 1179 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
a72b64b9 | 1180 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
3de7a1dc TV |
1181 | } |
1182 | ||
1183 | return r; | |
1184 | } | |
1185 | ||
1186 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) | |
1187 | { | |
a72b64b9 | 1188 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 1189 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1190 | unsigned long dsi_fclk; |
1191 | unsigned lp_clk_div; | |
1192 | unsigned long lp_clk; | |
1193 | ||
c6940a3d | 1194 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
3de7a1dc | 1195 | |
f1da39d9 | 1196 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
3de7a1dc TV |
1197 | return -EINVAL; |
1198 | ||
a72b64b9 | 1199 | dsi_fclk = dsi_fclk_rate(dsidev); |
3de7a1dc TV |
1200 | |
1201 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1202 | ||
1203 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
f1da39d9 AT |
1204 | dsi->current_cinfo.lp_clk = lp_clk; |
1205 | dsi->current_cinfo.lp_clk_div = lp_clk_div; | |
3de7a1dc | 1206 | |
a72b64b9 AT |
1207 | /* LP_CLK_DIVISOR */ |
1208 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); | |
3de7a1dc | 1209 | |
a72b64b9 AT |
1210 | /* LP_RX_SYNCHRO_ENABLE */ |
1211 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); | |
3de7a1dc TV |
1212 | |
1213 | return 0; | |
1214 | } | |
1215 | ||
a72b64b9 | 1216 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1217 | { |
f1da39d9 AT |
1218 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1219 | ||
1220 | if (dsi->scp_clk_refcount++ == 0) | |
a72b64b9 | 1221 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 TV |
1222 | } |
1223 | ||
a72b64b9 | 1224 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1225 | { |
f1da39d9 AT |
1226 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1227 | ||
1228 | WARN_ON(dsi->scp_clk_refcount == 0); | |
1229 | if (--dsi->scp_clk_refcount == 0) | |
a72b64b9 | 1230 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 | 1231 | } |
3de7a1dc TV |
1232 | |
1233 | enum dsi_pll_power_state { | |
1234 | DSI_PLL_POWER_OFF = 0x0, | |
1235 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1236 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1237 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1238 | }; | |
1239 | ||
a72b64b9 AT |
1240 | static int dsi_pll_power(struct platform_device *dsidev, |
1241 | enum dsi_pll_power_state state) | |
3de7a1dc TV |
1242 | { |
1243 | int t = 0; | |
1244 | ||
c94dfe05 TV |
1245 | /* DSI-PLL power command 0x3 is not working */ |
1246 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1247 | state == DSI_PLL_POWER_ON_DIV) | |
1248 | state = DSI_PLL_POWER_ON_ALL; | |
1249 | ||
a72b64b9 AT |
1250 | /* PLL_PWR_CMD */ |
1251 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); | |
3de7a1dc TV |
1252 | |
1253 | /* PLL_PWR_STATUS */ | |
a72b64b9 | 1254 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
24be78b3 | 1255 | if (++t > 1000) { |
3de7a1dc TV |
1256 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1257 | state); | |
1258 | return -ENODEV; | |
1259 | } | |
24be78b3 | 1260 | udelay(1); |
3de7a1dc TV |
1261 | } |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
1266 | /* calculate clock rates using dividers in cinfo */ | |
ff1b2cde SS |
1267 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
1268 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1269 | { |
f1da39d9 AT |
1270 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
1271 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1272 | ||
1273 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) | |
3de7a1dc TV |
1274 | return -EINVAL; |
1275 | ||
f1da39d9 | 1276 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
3de7a1dc TV |
1277 | return -EINVAL; |
1278 | ||
f1da39d9 | 1279 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
3de7a1dc TV |
1280 | return -EINVAL; |
1281 | ||
f1da39d9 | 1282 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
3de7a1dc TV |
1283 | return -EINVAL; |
1284 | ||
1bb47835 | 1285 | if (cinfo->use_sys_clk) { |
4fbafaf3 | 1286 | cinfo->clkin = clk_get_rate(dsi->sys_clk); |
3de7a1dc | 1287 | /* XXX it is unclear if highfreq should be used |
1bb47835 | 1288 | * with DSS_SYS_CLK source also */ |
3de7a1dc TV |
1289 | cinfo->highfreq = 0; |
1290 | } else { | |
26d9dd0d | 1291 | cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id); |
3de7a1dc TV |
1292 | |
1293 | if (cinfo->clkin < 32000000) | |
1294 | cinfo->highfreq = 0; | |
1295 | else | |
1296 | cinfo->highfreq = 1; | |
1297 | } | |
1298 | ||
1299 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); | |
1300 | ||
f1da39d9 | 1301 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
3de7a1dc TV |
1302 | return -EINVAL; |
1303 | ||
1304 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; | |
1305 | ||
1306 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) | |
1307 | return -EINVAL; | |
1308 | ||
1bb47835 AT |
1309 | if (cinfo->regm_dispc > 0) |
1310 | cinfo->dsi_pll_hsdiv_dispc_clk = | |
1311 | cinfo->clkin4ddr / cinfo->regm_dispc; | |
3de7a1dc | 1312 | else |
1bb47835 | 1313 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
3de7a1dc | 1314 | |
1bb47835 AT |
1315 | if (cinfo->regm_dsi > 0) |
1316 | cinfo->dsi_pll_hsdiv_dsi_clk = | |
1317 | cinfo->clkin4ddr / cinfo->regm_dsi; | |
3de7a1dc | 1318 | else |
1bb47835 | 1319 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
3de7a1dc TV |
1320 | |
1321 | return 0; | |
1322 | } | |
1323 | ||
a72b64b9 AT |
1324 | int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, |
1325 | unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, | |
3de7a1dc TV |
1326 | struct dispc_clock_info *dispc_cinfo) |
1327 | { | |
f1da39d9 | 1328 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1329 | struct dsi_clock_info cur, best; |
1330 | struct dispc_clock_info best_dispc; | |
1331 | int min_fck_per_pck; | |
1332 | int match = 0; | |
1bb47835 | 1333 | unsigned long dss_sys_clk, max_dss_fck; |
3de7a1dc | 1334 | |
4fbafaf3 | 1335 | dss_sys_clk = clk_get_rate(dsi->sys_clk); |
3de7a1dc | 1336 | |
31ef8237 | 1337 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 1338 | |
f1da39d9 AT |
1339 | if (req_pck == dsi->cache_req_pck && |
1340 | dsi->cache_cinfo.clkin == dss_sys_clk) { | |
3de7a1dc | 1341 | DSSDBG("DSI clock info found from cache\n"); |
f1da39d9 | 1342 | *dsi_cinfo = dsi->cache_cinfo; |
1bb47835 AT |
1343 | dispc_find_clk_divs(is_tft, req_pck, |
1344 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); | |
3de7a1dc TV |
1345 | return 0; |
1346 | } | |
1347 | ||
1348 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
1349 | ||
1350 | if (min_fck_per_pck && | |
819d807c | 1351 | req_pck * min_fck_per_pck > max_dss_fck) { |
3de7a1dc TV |
1352 | DSSERR("Requested pixel clock not possible with the current " |
1353 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
1354 | "the constraint off.\n"); | |
1355 | min_fck_per_pck = 0; | |
1356 | } | |
1357 | ||
1358 | DSSDBG("dsi_pll_calc\n"); | |
1359 | ||
1360 | retry: | |
1361 | memset(&best, 0, sizeof(best)); | |
1362 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
1363 | ||
1364 | memset(&cur, 0, sizeof(cur)); | |
1bb47835 AT |
1365 | cur.clkin = dss_sys_clk; |
1366 | cur.use_sys_clk = 1; | |
3de7a1dc TV |
1367 | cur.highfreq = 0; |
1368 | ||
1369 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ | |
1370 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ | |
1371 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ | |
f1da39d9 | 1372 | for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { |
3de7a1dc TV |
1373 | if (cur.highfreq == 0) |
1374 | cur.fint = cur.clkin / cur.regn; | |
1375 | else | |
1376 | cur.fint = cur.clkin / (2 * cur.regn); | |
1377 | ||
f1da39d9 | 1378 | if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) |
3de7a1dc TV |
1379 | continue; |
1380 | ||
1381 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ | |
f1da39d9 | 1382 | for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { |
3de7a1dc TV |
1383 | unsigned long a, b; |
1384 | ||
1385 | a = 2 * cur.regm * (cur.clkin/1000); | |
1386 | b = cur.regn * (cur.highfreq + 1); | |
1387 | cur.clkin4ddr = a / b * 1000; | |
1388 | ||
1389 | if (cur.clkin4ddr > 1800 * 1000 * 1000) | |
1390 | break; | |
1391 | ||
1bb47835 AT |
1392 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
1393 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ | |
f1da39d9 AT |
1394 | for (cur.regm_dispc = 1; cur.regm_dispc < |
1395 | dsi->regm_dispc_max; ++cur.regm_dispc) { | |
3de7a1dc | 1396 | struct dispc_clock_info cur_dispc; |
1bb47835 AT |
1397 | cur.dsi_pll_hsdiv_dispc_clk = |
1398 | cur.clkin4ddr / cur.regm_dispc; | |
3de7a1dc TV |
1399 | |
1400 | /* this will narrow down the search a bit, | |
1401 | * but still give pixclocks below what was | |
1402 | * requested */ | |
1bb47835 | 1403 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
3de7a1dc TV |
1404 | break; |
1405 | ||
1bb47835 | 1406 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
3de7a1dc TV |
1407 | continue; |
1408 | ||
1409 | if (min_fck_per_pck && | |
1bb47835 | 1410 | cur.dsi_pll_hsdiv_dispc_clk < |
3de7a1dc TV |
1411 | req_pck * min_fck_per_pck) |
1412 | continue; | |
1413 | ||
1414 | match = 1; | |
1415 | ||
1416 | dispc_find_clk_divs(is_tft, req_pck, | |
1bb47835 | 1417 | cur.dsi_pll_hsdiv_dispc_clk, |
3de7a1dc TV |
1418 | &cur_dispc); |
1419 | ||
1420 | if (abs(cur_dispc.pck - req_pck) < | |
1421 | abs(best_dispc.pck - req_pck)) { | |
1422 | best = cur; | |
1423 | best_dispc = cur_dispc; | |
1424 | ||
1425 | if (cur_dispc.pck == req_pck) | |
1426 | goto found; | |
1427 | } | |
1428 | } | |
1429 | } | |
1430 | } | |
1431 | found: | |
1432 | if (!match) { | |
1433 | if (min_fck_per_pck) { | |
1434 | DSSERR("Could not find suitable clock settings.\n" | |
1435 | "Turning FCK/PCK constraint off and" | |
1436 | "trying again.\n"); | |
1437 | min_fck_per_pck = 0; | |
1438 | goto retry; | |
1439 | } | |
1440 | ||
1441 | DSSERR("Could not find suitable clock settings.\n"); | |
1442 | ||
1443 | return -EINVAL; | |
1444 | } | |
1445 | ||
1bb47835 AT |
1446 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
1447 | best.regm_dsi = 0; | |
1448 | best.dsi_pll_hsdiv_dsi_clk = 0; | |
3de7a1dc TV |
1449 | |
1450 | if (dsi_cinfo) | |
1451 | *dsi_cinfo = best; | |
1452 | if (dispc_cinfo) | |
1453 | *dispc_cinfo = best_dispc; | |
1454 | ||
f1da39d9 AT |
1455 | dsi->cache_req_pck = req_pck; |
1456 | dsi->cache_clk_freq = 0; | |
1457 | dsi->cache_cinfo = best; | |
3de7a1dc TV |
1458 | |
1459 | return 0; | |
1460 | } | |
1461 | ||
a72b64b9 AT |
1462 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
1463 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1464 | { |
f1da39d9 | 1465 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1466 | int r = 0; |
1467 | u32 l; | |
9613c02b | 1468 | int f = 0; |
49641116 TA |
1469 | u8 regn_start, regn_end, regm_start, regm_end; |
1470 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; | |
3de7a1dc TV |
1471 | |
1472 | DSSDBGF(); | |
1473 | ||
f1da39d9 AT |
1474 | dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk; |
1475 | dsi->current_cinfo.highfreq = cinfo->highfreq; | |
b2765092 | 1476 | |
f1da39d9 AT |
1477 | dsi->current_cinfo.fint = cinfo->fint; |
1478 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; | |
1479 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = | |
1bb47835 | 1480 | cinfo->dsi_pll_hsdiv_dispc_clk; |
f1da39d9 | 1481 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
1bb47835 | 1482 | cinfo->dsi_pll_hsdiv_dsi_clk; |
3de7a1dc | 1483 | |
f1da39d9 AT |
1484 | dsi->current_cinfo.regn = cinfo->regn; |
1485 | dsi->current_cinfo.regm = cinfo->regm; | |
1486 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; | |
1487 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; | |
3de7a1dc TV |
1488 | |
1489 | DSSDBG("DSI Fint %ld\n", cinfo->fint); | |
1490 | ||
1491 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", | |
1bb47835 | 1492 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
3de7a1dc TV |
1493 | cinfo->clkin, |
1494 | cinfo->highfreq); | |
1495 | ||
1496 | /* DSIPHY == CLKIN4DDR */ | |
1497 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", | |
1498 | cinfo->regm, | |
1499 | cinfo->regn, | |
1500 | cinfo->clkin, | |
1501 | cinfo->highfreq + 1, | |
1502 | cinfo->clkin4ddr); | |
1503 | ||
1504 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", | |
1505 | cinfo->clkin4ddr / 1000 / 1000 / 2); | |
1506 | ||
1507 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | |
1508 | ||
1bb47835 | 1509 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
89a35e51 AT |
1510 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1511 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1512 | cinfo->dsi_pll_hsdiv_dispc_clk); |
1513 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, | |
89a35e51 AT |
1514 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
1515 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | |
1bb47835 | 1516 | cinfo->dsi_pll_hsdiv_dsi_clk); |
3de7a1dc | 1517 | |
49641116 TA |
1518 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
1519 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); | |
1520 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, | |
1521 | ®m_dispc_end); | |
1522 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, | |
1523 | ®m_dsi_end); | |
1524 | ||
a72b64b9 AT |
1525 | /* DSI_PLL_AUTOMODE = manual */ |
1526 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); | |
3de7a1dc | 1527 | |
a72b64b9 | 1528 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
3de7a1dc | 1529 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
49641116 TA |
1530 | /* DSI_PLL_REGN */ |
1531 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); | |
1532 | /* DSI_PLL_REGM */ | |
1533 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); | |
1534 | /* DSI_CLOCK_DIV */ | |
1bb47835 | 1535 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
49641116 TA |
1536 | regm_dispc_start, regm_dispc_end); |
1537 | /* DSIPROTO_CLOCK_DIV */ | |
1bb47835 | 1538 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
49641116 | 1539 | regm_dsi_start, regm_dsi_end); |
a72b64b9 | 1540 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
3de7a1dc | 1541 | |
f1da39d9 | 1542 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
9613c02b AT |
1543 | |
1544 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { | |
1545 | f = cinfo->fint < 1000000 ? 0x3 : | |
1546 | cinfo->fint < 1250000 ? 0x4 : | |
1547 | cinfo->fint < 1500000 ? 0x5 : | |
1548 | cinfo->fint < 1750000 ? 0x6 : | |
1549 | 0x7; | |
1550 | } | |
3de7a1dc | 1551 | |
a72b64b9 | 1552 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
9613c02b AT |
1553 | |
1554 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) | |
1555 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ | |
1bb47835 | 1556 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
3de7a1dc TV |
1557 | 11, 11); /* DSI_PLL_CLKSEL */ |
1558 | l = FLD_MOD(l, cinfo->highfreq, | |
1559 | 12, 12); /* DSI_PLL_HIGHFREQ */ | |
1560 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1561 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ | |
1562 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1563 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc | 1564 | |
a72b64b9 | 1565 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
3de7a1dc | 1566 | |
a72b64b9 | 1567 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
3de7a1dc TV |
1568 | DSSERR("dsi pll go bit not going down.\n"); |
1569 | r = -EIO; | |
1570 | goto err; | |
1571 | } | |
1572 | ||
a72b64b9 | 1573 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
3de7a1dc TV |
1574 | DSSERR("cannot lock PLL\n"); |
1575 | r = -EIO; | |
1576 | goto err; | |
1577 | } | |
1578 | ||
f1da39d9 | 1579 | dsi->pll_locked = 1; |
3de7a1dc | 1580 | |
a72b64b9 | 1581 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
3de7a1dc TV |
1582 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
1583 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ | |
1584 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ | |
1585 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ | |
1586 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ | |
1587 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ | |
1588 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1589 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ | |
1590 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ | |
1591 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ | |
1592 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ | |
1593 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ | |
1594 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ | |
1595 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1596 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc TV |
1597 | |
1598 | DSSDBG("PLL config done\n"); | |
1599 | err: | |
1600 | return r; | |
1601 | } | |
1602 | ||
a72b64b9 AT |
1603 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
1604 | bool enable_hsdiv) | |
3de7a1dc | 1605 | { |
f1da39d9 | 1606 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1607 | int r = 0; |
1608 | enum dsi_pll_power_state pwstate; | |
1609 | ||
1610 | DSSDBG("PLL init\n"); | |
1611 | ||
f1da39d9 | 1612 | if (dsi->vdds_dsi_reg == NULL) { |
f2988ab9 TV |
1613 | struct regulator *vdds_dsi; |
1614 | ||
f1da39d9 | 1615 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
f2988ab9 TV |
1616 | |
1617 | if (IS_ERR(vdds_dsi)) { | |
1618 | DSSERR("can't get VDDS_DSI regulator\n"); | |
1619 | return PTR_ERR(vdds_dsi); | |
1620 | } | |
1621 | ||
f1da39d9 | 1622 | dsi->vdds_dsi_reg = vdds_dsi; |
f2988ab9 | 1623 | } |
f2988ab9 | 1624 | |
a72b64b9 | 1625 | dsi_enable_pll_clock(dsidev, 1); |
24c1ae41 TV |
1626 | /* |
1627 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1628 | */ | |
a72b64b9 | 1629 | dsi_enable_scp_clk(dsidev); |
3de7a1dc | 1630 | |
f1da39d9 AT |
1631 | if (!dsi->vdds_dsi_enabled) { |
1632 | r = regulator_enable(dsi->vdds_dsi_reg); | |
2a89dc15 TV |
1633 | if (r) |
1634 | goto err0; | |
f1da39d9 | 1635 | dsi->vdds_dsi_enabled = true; |
2a89dc15 | 1636 | } |
3de7a1dc TV |
1637 | |
1638 | /* XXX PLL does not come out of reset without this... */ | |
1639 | dispc_pck_free_enable(1); | |
1640 | ||
a72b64b9 | 1641 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
3de7a1dc TV |
1642 | DSSERR("PLL not coming out of reset.\n"); |
1643 | r = -ENODEV; | |
481dfa0e | 1644 | dispc_pck_free_enable(0); |
3de7a1dc TV |
1645 | goto err1; |
1646 | } | |
1647 | ||
1648 | /* XXX ... but if left on, we get problems when planes do not | |
1649 | * fill the whole display. No idea about this */ | |
1650 | dispc_pck_free_enable(0); | |
1651 | ||
1652 | if (enable_hsclk && enable_hsdiv) | |
1653 | pwstate = DSI_PLL_POWER_ON_ALL; | |
1654 | else if (enable_hsclk) | |
1655 | pwstate = DSI_PLL_POWER_ON_HSCLK; | |
1656 | else if (enable_hsdiv) | |
1657 | pwstate = DSI_PLL_POWER_ON_DIV; | |
1658 | else | |
1659 | pwstate = DSI_PLL_POWER_OFF; | |
1660 | ||
a72b64b9 | 1661 | r = dsi_pll_power(dsidev, pwstate); |
3de7a1dc TV |
1662 | |
1663 | if (r) | |
1664 | goto err1; | |
1665 | ||
1666 | DSSDBG("PLL init done\n"); | |
1667 | ||
1668 | return 0; | |
1669 | err1: | |
f1da39d9 AT |
1670 | if (dsi->vdds_dsi_enabled) { |
1671 | regulator_disable(dsi->vdds_dsi_reg); | |
1672 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1673 | } |
3de7a1dc | 1674 | err0: |
a72b64b9 | 1675 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1676 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc TV |
1677 | return r; |
1678 | } | |
1679 | ||
a72b64b9 | 1680 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
3de7a1dc | 1681 | { |
f1da39d9 AT |
1682 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1683 | ||
1684 | dsi->pll_locked = 0; | |
a72b64b9 | 1685 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
2a89dc15 | 1686 | if (disconnect_lanes) { |
f1da39d9 AT |
1687 | WARN_ON(!dsi->vdds_dsi_enabled); |
1688 | regulator_disable(dsi->vdds_dsi_reg); | |
1689 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1690 | } |
24c1ae41 | 1691 | |
a72b64b9 | 1692 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1693 | dsi_enable_pll_clock(dsidev, 0); |
24c1ae41 | 1694 | |
3de7a1dc TV |
1695 | DSSDBG("PLL uninit done\n"); |
1696 | } | |
1697 | ||
5a8b572d AT |
1698 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
1699 | struct seq_file *s) | |
3de7a1dc | 1700 | { |
f1da39d9 AT |
1701 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1702 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; | |
89a35e51 | 1703 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
5a8b572d | 1704 | int dsi_module = dsi_get_dsidev_id(dsidev); |
067a57e4 AT |
1705 | |
1706 | dispc_clk_src = dss_get_dispc_clk_source(); | |
5a8b572d | 1707 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
3de7a1dc | 1708 | |
4fbafaf3 TV |
1709 | if (dsi_runtime_get(dsidev)) |
1710 | return; | |
3de7a1dc | 1711 | |
5a8b572d | 1712 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
3de7a1dc TV |
1713 | |
1714 | seq_printf(s, "dsi pll source = %s\n", | |
a9a6500b | 1715 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); |
3de7a1dc TV |
1716 | |
1717 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); | |
1718 | ||
1719 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | |
1720 | cinfo->clkin4ddr, cinfo->regm); | |
1721 | ||
1bb47835 | 1722 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
067a57e4 AT |
1723 | dss_get_generic_clk_source_name(dispc_clk_src), |
1724 | dss_feat_get_clk_source_name(dispc_clk_src), | |
1bb47835 AT |
1725 | cinfo->dsi_pll_hsdiv_dispc_clk, |
1726 | cinfo->regm_dispc, | |
89a35e51 | 1727 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1728 | "off" : "on"); |
3de7a1dc | 1729 | |
1bb47835 | 1730 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
067a57e4 AT |
1731 | dss_get_generic_clk_source_name(dsi_clk_src), |
1732 | dss_feat_get_clk_source_name(dsi_clk_src), | |
1bb47835 AT |
1733 | cinfo->dsi_pll_hsdiv_dsi_clk, |
1734 | cinfo->regm_dsi, | |
89a35e51 | 1735 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1736 | "off" : "on"); |
3de7a1dc | 1737 | |
5a8b572d | 1738 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
3de7a1dc | 1739 | |
067a57e4 AT |
1740 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1741 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1742 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
3de7a1dc | 1743 | |
a72b64b9 | 1744 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
3de7a1dc TV |
1745 | |
1746 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1747 | cinfo->clkin4ddr / 4); | |
1748 | ||
a72b64b9 | 1749 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
3de7a1dc TV |
1750 | |
1751 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); | |
1752 | ||
4fbafaf3 | 1753 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1754 | } |
1755 | ||
5a8b572d AT |
1756 | void dsi_dump_clocks(struct seq_file *s) |
1757 | { | |
1758 | struct platform_device *dsidev; | |
1759 | int i; | |
1760 | ||
1761 | for (i = 0; i < MAX_NUM_DSI; i++) { | |
1762 | dsidev = dsi_get_dsidev_from_id(i); | |
1763 | if (dsidev) | |
1764 | dsi_dump_dsidev_clocks(dsidev, s); | |
1765 | } | |
1766 | } | |
1767 | ||
dfc0fd8d | 1768 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
5a8b572d AT |
1769 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
1770 | struct seq_file *s) | |
dfc0fd8d | 1771 | { |
f1da39d9 | 1772 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
dfc0fd8d TV |
1773 | unsigned long flags; |
1774 | struct dsi_irq_stats stats; | |
5a8b572d | 1775 | int dsi_module = dsi_get_dsidev_id(dsidev); |
dfc0fd8d | 1776 | |
f1da39d9 | 1777 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
dfc0fd8d | 1778 | |
f1da39d9 AT |
1779 | stats = dsi->irq_stats; |
1780 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); | |
1781 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d | 1782 | |
f1da39d9 | 1783 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
dfc0fd8d TV |
1784 | |
1785 | seq_printf(s, "period %u ms\n", | |
1786 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1787 | ||
1788 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1789 | #define PIS(x) \ | |
1790 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1791 | ||
5a8b572d | 1792 | seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1); |
dfc0fd8d TV |
1793 | PIS(VC0); |
1794 | PIS(VC1); | |
1795 | PIS(VC2); | |
1796 | PIS(VC3); | |
1797 | PIS(WAKEUP); | |
1798 | PIS(RESYNC); | |
1799 | PIS(PLL_LOCK); | |
1800 | PIS(PLL_UNLOCK); | |
1801 | PIS(PLL_RECALL); | |
1802 | PIS(COMPLEXIO_ERR); | |
1803 | PIS(HS_TX_TIMEOUT); | |
1804 | PIS(LP_RX_TIMEOUT); | |
1805 | PIS(TE_TRIGGER); | |
1806 | PIS(ACK_TRIGGER); | |
1807 | PIS(SYNC_LOST); | |
1808 | PIS(LDO_POWER_GOOD); | |
1809 | PIS(TA_TIMEOUT); | |
1810 | #undef PIS | |
1811 | ||
1812 | #define PIS(x) \ | |
1813 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1814 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1815 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1816 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1817 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1818 | ||
1819 | seq_printf(s, "-- VC interrupts --\n"); | |
1820 | PIS(CS); | |
1821 | PIS(ECC_CORR); | |
1822 | PIS(PACKET_SENT); | |
1823 | PIS(FIFO_TX_OVF); | |
1824 | PIS(FIFO_RX_OVF); | |
1825 | PIS(BTA); | |
1826 | PIS(ECC_NO_CORR); | |
1827 | PIS(FIFO_TX_UDF); | |
1828 | PIS(PP_BUSY_CHANGE); | |
1829 | #undef PIS | |
1830 | ||
1831 | #define PIS(x) \ | |
1832 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1833 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1834 | ||
1835 | seq_printf(s, "-- CIO interrupts --\n"); | |
1836 | PIS(ERRSYNCESC1); | |
1837 | PIS(ERRSYNCESC2); | |
1838 | PIS(ERRSYNCESC3); | |
1839 | PIS(ERRESC1); | |
1840 | PIS(ERRESC2); | |
1841 | PIS(ERRESC3); | |
1842 | PIS(ERRCONTROL1); | |
1843 | PIS(ERRCONTROL2); | |
1844 | PIS(ERRCONTROL3); | |
1845 | PIS(STATEULPS1); | |
1846 | PIS(STATEULPS2); | |
1847 | PIS(STATEULPS3); | |
1848 | PIS(ERRCONTENTIONLP0_1); | |
1849 | PIS(ERRCONTENTIONLP1_1); | |
1850 | PIS(ERRCONTENTIONLP0_2); | |
1851 | PIS(ERRCONTENTIONLP1_2); | |
1852 | PIS(ERRCONTENTIONLP0_3); | |
1853 | PIS(ERRCONTENTIONLP1_3); | |
1854 | PIS(ULPSACTIVENOT_ALL0); | |
1855 | PIS(ULPSACTIVENOT_ALL1); | |
1856 | #undef PIS | |
1857 | } | |
dfc0fd8d | 1858 | |
5a8b572d | 1859 | static void dsi1_dump_irqs(struct seq_file *s) |
3de7a1dc | 1860 | { |
a72b64b9 AT |
1861 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
1862 | ||
5a8b572d AT |
1863 | dsi_dump_dsidev_irqs(dsidev, s); |
1864 | } | |
1865 | ||
1866 | static void dsi2_dump_irqs(struct seq_file *s) | |
1867 | { | |
1868 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1869 | ||
1870 | dsi_dump_dsidev_irqs(dsidev, s); | |
1871 | } | |
1872 | ||
1873 | void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir, | |
1874 | const struct file_operations *debug_fops) | |
1875 | { | |
1876 | struct platform_device *dsidev; | |
1877 | ||
1878 | dsidev = dsi_get_dsidev_from_id(0); | |
1879 | if (dsidev) | |
1880 | debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir, | |
1881 | &dsi1_dump_irqs, debug_fops); | |
1882 | ||
1883 | dsidev = dsi_get_dsidev_from_id(1); | |
1884 | if (dsidev) | |
1885 | debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir, | |
1886 | &dsi2_dump_irqs, debug_fops); | |
1887 | } | |
1888 | #endif | |
1889 | ||
1890 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, | |
1891 | struct seq_file *s) | |
1892 | { | |
a72b64b9 | 1893 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
3de7a1dc | 1894 | |
4fbafaf3 TV |
1895 | if (dsi_runtime_get(dsidev)) |
1896 | return; | |
a72b64b9 | 1897 | dsi_enable_scp_clk(dsidev); |
3de7a1dc TV |
1898 | |
1899 | DUMPREG(DSI_REVISION); | |
1900 | DUMPREG(DSI_SYSCONFIG); | |
1901 | DUMPREG(DSI_SYSSTATUS); | |
1902 | DUMPREG(DSI_IRQSTATUS); | |
1903 | DUMPREG(DSI_IRQENABLE); | |
1904 | DUMPREG(DSI_CTRL); | |
1905 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1906 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1907 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1908 | DUMPREG(DSI_CLK_CTRL); | |
1909 | DUMPREG(DSI_TIMING1); | |
1910 | DUMPREG(DSI_TIMING2); | |
1911 | DUMPREG(DSI_VM_TIMING1); | |
1912 | DUMPREG(DSI_VM_TIMING2); | |
1913 | DUMPREG(DSI_VM_TIMING3); | |
1914 | DUMPREG(DSI_CLK_TIMING); | |
1915 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1916 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1917 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1918 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1919 | DUMPREG(DSI_VM_TIMING4); | |
1920 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1921 | DUMPREG(DSI_VM_TIMING5); | |
1922 | DUMPREG(DSI_VM_TIMING6); | |
1923 | DUMPREG(DSI_VM_TIMING7); | |
1924 | DUMPREG(DSI_STOPCLK_TIMING); | |
1925 | ||
1926 | DUMPREG(DSI_VC_CTRL(0)); | |
1927 | DUMPREG(DSI_VC_TE(0)); | |
1928 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1929 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1930 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1931 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1932 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1933 | ||
1934 | DUMPREG(DSI_VC_CTRL(1)); | |
1935 | DUMPREG(DSI_VC_TE(1)); | |
1936 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1937 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1938 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1939 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1940 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1941 | ||
1942 | DUMPREG(DSI_VC_CTRL(2)); | |
1943 | DUMPREG(DSI_VC_TE(2)); | |
1944 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1945 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1946 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1947 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1948 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1949 | ||
1950 | DUMPREG(DSI_VC_CTRL(3)); | |
1951 | DUMPREG(DSI_VC_TE(3)); | |
1952 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1953 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1954 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1955 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1956 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1957 | ||
1958 | DUMPREG(DSI_DSIPHY_CFG0); | |
1959 | DUMPREG(DSI_DSIPHY_CFG1); | |
1960 | DUMPREG(DSI_DSIPHY_CFG2); | |
1961 | DUMPREG(DSI_DSIPHY_CFG5); | |
1962 | ||
1963 | DUMPREG(DSI_PLL_CONTROL); | |
1964 | DUMPREG(DSI_PLL_STATUS); | |
1965 | DUMPREG(DSI_PLL_GO); | |
1966 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1967 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
1968 | ||
a72b64b9 | 1969 | dsi_disable_scp_clk(dsidev); |
4fbafaf3 | 1970 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1971 | #undef DUMPREG |
1972 | } | |
1973 | ||
5a8b572d AT |
1974 | static void dsi1_dump_regs(struct seq_file *s) |
1975 | { | |
1976 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
1977 | ||
1978 | dsi_dump_dsidev_regs(dsidev, s); | |
1979 | } | |
1980 | ||
1981 | static void dsi2_dump_regs(struct seq_file *s) | |
1982 | { | |
1983 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1984 | ||
1985 | dsi_dump_dsidev_regs(dsidev, s); | |
1986 | } | |
1987 | ||
1988 | void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir, | |
1989 | const struct file_operations *debug_fops) | |
1990 | { | |
1991 | struct platform_device *dsidev; | |
1992 | ||
1993 | dsidev = dsi_get_dsidev_from_id(0); | |
1994 | if (dsidev) | |
1995 | debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir, | |
1996 | &dsi1_dump_regs, debug_fops); | |
1997 | ||
1998 | dsidev = dsi_get_dsidev_from_id(1); | |
1999 | if (dsidev) | |
2000 | debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir, | |
2001 | &dsi2_dump_regs, debug_fops); | |
2002 | } | |
cc5c1850 | 2003 | enum dsi_cio_power_state { |
3de7a1dc TV |
2004 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
2005 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
2006 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
2007 | }; | |
2008 | ||
a72b64b9 AT |
2009 | static int dsi_cio_power(struct platform_device *dsidev, |
2010 | enum dsi_cio_power_state state) | |
3de7a1dc TV |
2011 | { |
2012 | int t = 0; | |
2013 | ||
2014 | /* PWR_CMD */ | |
a72b64b9 | 2015 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
3de7a1dc TV |
2016 | |
2017 | /* PWR_STATUS */ | |
a72b64b9 AT |
2018 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
2019 | 26, 25) != state) { | |
24be78b3 | 2020 | if (++t > 1000) { |
3de7a1dc TV |
2021 | DSSERR("failed to set complexio power state to " |
2022 | "%d\n", state); | |
2023 | return -ENODEV; | |
2024 | } | |
24be78b3 | 2025 | udelay(1); |
3de7a1dc TV |
2026 | } |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
75d7247c AT |
2031 | /* Number of data lanes present on DSI interface */ |
2032 | static inline int dsi_get_num_data_lanes(struct platform_device *dsidev) | |
2033 | { | |
2034 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number | |
2035 | * of data lanes as 2 by default */ | |
2036 | if (dss_has_feature(FEAT_DSI_GNQ)) | |
2037 | return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */ | |
2038 | else | |
2039 | return 2; | |
2040 | } | |
2041 | ||
2042 | /* Number of data lanes used by the dss device */ | |
2043 | static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev) | |
2044 | { | |
2045 | int num_data_lanes = 0; | |
2046 | ||
2047 | if (dssdev->phy.dsi.data1_lane != 0) | |
2048 | num_data_lanes++; | |
2049 | if (dssdev->phy.dsi.data2_lane != 0) | |
2050 | num_data_lanes++; | |
2051 | if (dssdev->phy.dsi.data3_lane != 0) | |
2052 | num_data_lanes++; | |
2053 | if (dssdev->phy.dsi.data4_lane != 0) | |
2054 | num_data_lanes++; | |
2055 | ||
2056 | return num_data_lanes; | |
2057 | } | |
2058 | ||
0c65622b AT |
2059 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
2060 | { | |
2061 | int val; | |
2062 | ||
2063 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
2064 | /* XXX: for some reason using full buffer size causes | |
2065 | * considerable TX slowdown with update sizes that fill the | |
2066 | * whole buffer */ | |
2067 | if (!dss_has_feature(FEAT_DSI_GNQ)) | |
2068 | return 1023 * 3; | |
2069 | ||
2070 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ | |
2071 | ||
2072 | switch (val) { | |
2073 | case 1: | |
2074 | return 512 * 3; /* 512x24 bits */ | |
2075 | case 2: | |
2076 | return 682 * 3; /* 682x24 bits */ | |
2077 | case 3: | |
2078 | return 853 * 3; /* 853x24 bits */ | |
2079 | case 4: | |
2080 | return 1024 * 3; /* 1024x24 bits */ | |
2081 | case 5: | |
2082 | return 1194 * 3; /* 1194x24 bits */ | |
2083 | case 6: | |
2084 | return 1365 * 3; /* 1365x24 bits */ | |
2085 | default: | |
2086 | BUG(); | |
2087 | } | |
2088 | } | |
2089 | ||
cc5c1850 | 2090 | static void dsi_set_lane_config(struct omap_dss_device *dssdev) |
3de7a1dc | 2091 | { |
a72b64b9 | 2092 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc | 2093 | u32 r; |
75d7247c | 2094 | int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev); |
3de7a1dc TV |
2095 | |
2096 | int clk_lane = dssdev->phy.dsi.clk_lane; | |
2097 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
2098 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
2099 | int clk_pol = dssdev->phy.dsi.clk_pol; | |
2100 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
2101 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
2102 | ||
a72b64b9 | 2103 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
3de7a1dc TV |
2104 | r = FLD_MOD(r, clk_lane, 2, 0); |
2105 | r = FLD_MOD(r, clk_pol, 3, 3); | |
2106 | r = FLD_MOD(r, data1_lane, 6, 4); | |
2107 | r = FLD_MOD(r, data1_pol, 7, 7); | |
2108 | r = FLD_MOD(r, data2_lane, 10, 8); | |
2109 | r = FLD_MOD(r, data2_pol, 11, 11); | |
75d7247c AT |
2110 | if (num_data_lanes_dssdev > 2) { |
2111 | int data3_lane = dssdev->phy.dsi.data3_lane; | |
2112 | int data3_pol = dssdev->phy.dsi.data3_pol; | |
2113 | ||
2114 | r = FLD_MOD(r, data3_lane, 14, 12); | |
2115 | r = FLD_MOD(r, data3_pol, 15, 15); | |
2116 | } | |
2117 | if (num_data_lanes_dssdev > 3) { | |
2118 | int data4_lane = dssdev->phy.dsi.data4_lane; | |
2119 | int data4_pol = dssdev->phy.dsi.data4_pol; | |
2120 | ||
2121 | r = FLD_MOD(r, data4_lane, 18, 16); | |
2122 | r = FLD_MOD(r, data4_pol, 19, 19); | |
2123 | } | |
a72b64b9 | 2124 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
3de7a1dc TV |
2125 | |
2126 | /* The configuration of the DSI complex I/O (number of data lanes, | |
2127 | position, differential order) should not be changed while | |
2128 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for | |
2129 | the hardware to take into account a new configuration of the complex | |
2130 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to | |
2131 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, | |
2132 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set | |
2133 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the | |
2134 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the | |
2135 | DSI complex I/O configuration is unknown. */ | |
2136 | ||
2137 | /* | |
a72b64b9 AT |
2138 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); |
2139 | REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0); | |
2140 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); | |
2141 | REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0); | |
3de7a1dc TV |
2142 | */ |
2143 | } | |
2144 | ||
a72b64b9 | 2145 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
3de7a1dc | 2146 | { |
f1da39d9 AT |
2147 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2148 | ||
3de7a1dc | 2149 | /* convert time in ns to ddr ticks, rounding up */ |
f1da39d9 | 2150 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
3de7a1dc TV |
2151 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
2152 | } | |
2153 | ||
a72b64b9 | 2154 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
3de7a1dc | 2155 | { |
f1da39d9 AT |
2156 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2157 | ||
2158 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; | |
3de7a1dc TV |
2159 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
2160 | } | |
2161 | ||
a72b64b9 | 2162 | static void dsi_cio_timings(struct platform_device *dsidev) |
3de7a1dc TV |
2163 | { |
2164 | u32 r; | |
2165 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
2166 | u32 tlpx_half, tclk_trail, tclk_zero; | |
2167 | u32 tclk_prepare; | |
2168 | ||
2169 | /* calculate timings */ | |
2170 | ||
2171 | /* 1 * DDR_CLK = 2 * UI */ | |
2172 | ||
2173 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
a72b64b9 | 2174 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
3de7a1dc TV |
2175 | |
2176 | /* min 145ns + 10*UI */ | |
a72b64b9 | 2177 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
3de7a1dc TV |
2178 | |
2179 | /* min max(8*UI, 60ns+4*UI) */ | |
a72b64b9 | 2180 | ths_trail = ns2ddr(dsidev, 60) + 5; |
3de7a1dc TV |
2181 | |
2182 | /* min 100ns */ | |
a72b64b9 | 2183 | ths_exit = ns2ddr(dsidev, 145); |
3de7a1dc TV |
2184 | |
2185 | /* tlpx min 50n */ | |
a72b64b9 | 2186 | tlpx_half = ns2ddr(dsidev, 25); |
3de7a1dc TV |
2187 | |
2188 | /* min 60ns */ | |
a72b64b9 | 2189 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
3de7a1dc TV |
2190 | |
2191 | /* min 38ns, max 95ns */ | |
a72b64b9 | 2192 | tclk_prepare = ns2ddr(dsidev, 65); |
3de7a1dc TV |
2193 | |
2194 | /* min tclk-prepare + tclk-zero = 300ns */ | |
a72b64b9 | 2195 | tclk_zero = ns2ddr(dsidev, 260); |
3de7a1dc TV |
2196 | |
2197 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
a72b64b9 AT |
2198 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
2199 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); | |
3de7a1dc | 2200 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
a72b64b9 AT |
2201 | ths_trail, ddr2ns(dsidev, ths_trail), |
2202 | ths_exit, ddr2ns(dsidev, ths_exit)); | |
3de7a1dc TV |
2203 | |
2204 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
2205 | "tclk_zero %u (%uns)\n", | |
a72b64b9 AT |
2206 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
2207 | tclk_trail, ddr2ns(dsidev, tclk_trail), | |
2208 | tclk_zero, ddr2ns(dsidev, tclk_zero)); | |
3de7a1dc | 2209 | DSSDBG("tclk_prepare %u (%uns)\n", |
a72b64b9 | 2210 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
3de7a1dc TV |
2211 | |
2212 | /* program timings */ | |
2213 | ||
a72b64b9 | 2214 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
2215 | r = FLD_MOD(r, ths_prepare, 31, 24); |
2216 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
2217 | r = FLD_MOD(r, ths_trail, 15, 8); | |
2218 | r = FLD_MOD(r, ths_exit, 7, 0); | |
a72b64b9 | 2219 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
3de7a1dc | 2220 | |
a72b64b9 | 2221 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
2222 | r = FLD_MOD(r, tlpx_half, 22, 16); |
2223 | r = FLD_MOD(r, tclk_trail, 15, 8); | |
2224 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
a72b64b9 | 2225 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
3de7a1dc | 2226 | |
a72b64b9 | 2227 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc | 2228 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
a72b64b9 | 2229 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
3de7a1dc TV |
2230 | } |
2231 | ||
cc5c1850 | 2232 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
0a0ee46b TV |
2233 | enum dsi_lane lanes) |
2234 | { | |
a72b64b9 | 2235 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
75d7247c | 2236 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
0a0ee46b TV |
2237 | int clk_lane = dssdev->phy.dsi.clk_lane; |
2238 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
2239 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
75d7247c AT |
2240 | int data3_lane = dssdev->phy.dsi.data3_lane; |
2241 | int data4_lane = dssdev->phy.dsi.data4_lane; | |
0a0ee46b TV |
2242 | int clk_pol = dssdev->phy.dsi.clk_pol; |
2243 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
2244 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
75d7247c AT |
2245 | int data3_pol = dssdev->phy.dsi.data3_pol; |
2246 | int data4_pol = dssdev->phy.dsi.data4_pol; | |
0a0ee46b TV |
2247 | |
2248 | u32 l = 0; | |
75d7247c | 2249 | u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26; |
0a0ee46b TV |
2250 | |
2251 | if (lanes & DSI_CLK_P) | |
2252 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); | |
2253 | if (lanes & DSI_CLK_N) | |
2254 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); | |
2255 | ||
2256 | if (lanes & DSI_DATA1_P) | |
2257 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); | |
2258 | if (lanes & DSI_DATA1_N) | |
2259 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); | |
2260 | ||
2261 | if (lanes & DSI_DATA2_P) | |
2262 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); | |
2263 | if (lanes & DSI_DATA2_N) | |
2264 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); | |
2265 | ||
75d7247c AT |
2266 | if (lanes & DSI_DATA3_P) |
2267 | l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1)); | |
2268 | if (lanes & DSI_DATA3_N) | |
2269 | l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0)); | |
2270 | ||
2271 | if (lanes & DSI_DATA4_P) | |
2272 | l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1)); | |
2273 | if (lanes & DSI_DATA4_N) | |
2274 | l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0)); | |
0a0ee46b TV |
2275 | /* |
2276 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
2277 | * 17: DY0 18: DX0 | |
2278 | * 19: DY1 20: DX1 | |
2279 | * 21: DY2 22: DX2 | |
75d7247c AT |
2280 | * 23: DY3 24: DX3 |
2281 | * 25: DY4 26: DX4 | |
0a0ee46b TV |
2282 | */ |
2283 | ||
2284 | /* Set the lane override configuration */ | |
a72b64b9 AT |
2285 | |
2286 | /* REGLPTXSCPDAT4TO0DXDY */ | |
75d7247c | 2287 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
0a0ee46b TV |
2288 | |
2289 | /* Enable lane override */ | |
a72b64b9 AT |
2290 | |
2291 | /* ENLPTXSCPDAT */ | |
2292 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); | |
0a0ee46b TV |
2293 | } |
2294 | ||
a72b64b9 | 2295 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
0a0ee46b TV |
2296 | { |
2297 | /* Disable lane override */ | |
a72b64b9 | 2298 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
0a0ee46b | 2299 | /* Reset the lane override configuration */ |
a72b64b9 AT |
2300 | /* REGLPTXSCPDAT4TO0DXDY */ |
2301 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); | |
0a0ee46b | 2302 | } |
3de7a1dc | 2303 | |
03329ace TV |
2304 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
2305 | { | |
a72b64b9 | 2306 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
03329ace TV |
2307 | int t; |
2308 | int bits[3]; | |
2309 | bool in_use[3]; | |
2310 | ||
2311 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { | |
2312 | bits[0] = 28; | |
2313 | bits[1] = 27; | |
2314 | bits[2] = 26; | |
2315 | } else { | |
2316 | bits[0] = 24; | |
2317 | bits[1] = 25; | |
2318 | bits[2] = 26; | |
2319 | } | |
2320 | ||
2321 | in_use[0] = false; | |
2322 | in_use[1] = false; | |
2323 | in_use[2] = false; | |
2324 | ||
2325 | if (dssdev->phy.dsi.clk_lane != 0) | |
2326 | in_use[dssdev->phy.dsi.clk_lane - 1] = true; | |
2327 | if (dssdev->phy.dsi.data1_lane != 0) | |
2328 | in_use[dssdev->phy.dsi.data1_lane - 1] = true; | |
2329 | if (dssdev->phy.dsi.data2_lane != 0) | |
2330 | in_use[dssdev->phy.dsi.data2_lane - 1] = true; | |
2331 | ||
2332 | t = 100000; | |
2333 | while (true) { | |
2334 | u32 l; | |
2335 | int i; | |
2336 | int ok; | |
2337 | ||
a72b64b9 | 2338 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
03329ace TV |
2339 | |
2340 | ok = 0; | |
2341 | for (i = 0; i < 3; ++i) { | |
2342 | if (!in_use[i] || (l & (1 << bits[i]))) | |
2343 | ok++; | |
2344 | } | |
2345 | ||
2346 | if (ok == 3) | |
2347 | break; | |
2348 | ||
2349 | if (--t == 0) { | |
2350 | for (i = 0; i < 3; ++i) { | |
2351 | if (!in_use[i] || (l & (1 << bits[i]))) | |
2352 | continue; | |
2353 | ||
2354 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
2355 | "out of reset\n", i); | |
2356 | } | |
2357 | return -EIO; | |
2358 | } | |
2359 | } | |
2360 | ||
2361 | return 0; | |
2362 | } | |
2363 | ||
5bc416cb TV |
2364 | static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev) |
2365 | { | |
2366 | unsigned lanes = 0; | |
2367 | ||
2368 | if (dssdev->phy.dsi.clk_lane != 0) | |
2369 | lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1); | |
2370 | if (dssdev->phy.dsi.data1_lane != 0) | |
2371 | lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1); | |
2372 | if (dssdev->phy.dsi.data2_lane != 0) | |
2373 | lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1); | |
2374 | if (dssdev->phy.dsi.data3_lane != 0) | |
2375 | lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1); | |
2376 | if (dssdev->phy.dsi.data4_lane != 0) | |
2377 | lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1); | |
2378 | ||
2379 | return lanes; | |
2380 | } | |
2381 | ||
cc5c1850 | 2382 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
3de7a1dc | 2383 | { |
a72b64b9 | 2384 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 2385 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
65c62bb9 | 2386 | int r; |
75d7247c | 2387 | int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev); |
40885ab3 | 2388 | u32 l; |
3de7a1dc | 2389 | |
cc5c1850 | 2390 | DSSDBGF(); |
3de7a1dc | 2391 | |
5bc416cb TV |
2392 | r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
2393 | if (r) | |
2394 | return r; | |
d1f5857e | 2395 | |
a72b64b9 | 2396 | dsi_enable_scp_clk(dsidev); |
40885ab3 | 2397 | |
3de7a1dc TV |
2398 | /* A dummy read using the SCP interface to any DSIPHY register is |
2399 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2400 | * I/O. */ | |
a72b64b9 | 2401 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc | 2402 | |
a72b64b9 | 2403 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
65c62bb9 TV |
2404 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
2405 | r = -EIO; | |
2406 | goto err_scp_clk_dom; | |
3de7a1dc TV |
2407 | } |
2408 | ||
cc5c1850 | 2409 | dsi_set_lane_config(dssdev); |
3de7a1dc | 2410 | |
40885ab3 | 2411 | /* set TX STOP MODE timer to maximum for this operation */ |
a72b64b9 | 2412 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
40885ab3 TV |
2413 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
2414 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2415 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2416 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
a72b64b9 | 2417 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
40885ab3 | 2418 | |
f1da39d9 | 2419 | if (dsi->ulps_enabled) { |
75d7247c AT |
2420 | u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P; |
2421 | ||
65c62bb9 TV |
2422 | DSSDBG("manual ulps exit\n"); |
2423 | ||
40885ab3 TV |
2424 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
2425 | * stop state. DSS HW cannot do this via the normal | |
2426 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2427 | * that we are not in ULPS mode, and refuses to send the | |
2428 | * sequence. So we need to send the ULPS exit sequence | |
2429 | * manually. | |
2430 | */ | |
2431 | ||
75d7247c AT |
2432 | if (num_data_lanes_dssdev > 2) |
2433 | lane_mask |= DSI_DATA3_P; | |
2434 | ||
2435 | if (num_data_lanes_dssdev > 3) | |
2436 | lane_mask |= DSI_DATA4_P; | |
2437 | ||
2438 | dsi_cio_enable_lane_override(dssdev, lane_mask); | |
40885ab3 | 2439 | } |
3de7a1dc | 2440 | |
a72b64b9 | 2441 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
3de7a1dc | 2442 | if (r) |
65c62bb9 TV |
2443 | goto err_cio_pwr; |
2444 | ||
a72b64b9 | 2445 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
65c62bb9 TV |
2446 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
2447 | r = -ENODEV; | |
2448 | goto err_cio_pwr_dom; | |
2449 | } | |
2450 | ||
a72b64b9 AT |
2451 | dsi_if_enable(dsidev, true); |
2452 | dsi_if_enable(dsidev, false); | |
2453 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
3de7a1dc | 2454 | |
03329ace TV |
2455 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
2456 | if (r) | |
2457 | goto err_tx_clk_esc_rst; | |
2458 | ||
f1da39d9 | 2459 | if (dsi->ulps_enabled) { |
40885ab3 TV |
2460 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
2461 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2462 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2463 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2464 | ||
2465 | /* Disable the override. The lanes should be set to Mark-11 | |
2466 | * state by the HW */ | |
a72b64b9 | 2467 | dsi_cio_disable_lane_override(dsidev); |
40885ab3 TV |
2468 | } |
2469 | ||
2470 | /* FORCE_TX_STOP_MODE_IO */ | |
a72b64b9 | 2471 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
40885ab3 | 2472 | |
a72b64b9 | 2473 | dsi_cio_timings(dsidev); |
3de7a1dc | 2474 | |
f1da39d9 | 2475 | dsi->ulps_enabled = false; |
3de7a1dc TV |
2476 | |
2477 | DSSDBG("CIO init done\n"); | |
65c62bb9 TV |
2478 | |
2479 | return 0; | |
2480 | ||
03329ace | 2481 | err_tx_clk_esc_rst: |
a72b64b9 | 2482 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
65c62bb9 | 2483 | err_cio_pwr_dom: |
a72b64b9 | 2484 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
65c62bb9 | 2485 | err_cio_pwr: |
f1da39d9 | 2486 | if (dsi->ulps_enabled) |
a72b64b9 | 2487 | dsi_cio_disable_lane_override(dsidev); |
65c62bb9 | 2488 | err_scp_clk_dom: |
a72b64b9 | 2489 | dsi_disable_scp_clk(dsidev); |
5bc416cb | 2490 | dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2491 | return r; |
2492 | } | |
2493 | ||
5bc416cb | 2494 | static void dsi_cio_uninit(struct omap_dss_device *dssdev) |
3de7a1dc | 2495 | { |
5bc416cb | 2496 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 AT |
2497 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2498 | ||
a72b64b9 AT |
2499 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
2500 | dsi_disable_scp_clk(dsidev); | |
5bc416cb | 2501 | dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2502 | } |
2503 | ||
a72b64b9 AT |
2504 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
2505 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2506 | enum fifo_size size3, enum fifo_size size4) |
2507 | { | |
f1da39d9 | 2508 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2509 | u32 r = 0; |
2510 | int add = 0; | |
2511 | int i; | |
2512 | ||
f1da39d9 AT |
2513 | dsi->vc[0].fifo_size = size1; |
2514 | dsi->vc[1].fifo_size = size2; | |
2515 | dsi->vc[2].fifo_size = size3; | |
2516 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2517 | |
2518 | for (i = 0; i < 4; i++) { | |
2519 | u8 v; | |
f1da39d9 | 2520 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2521 | |
2522 | if (add + size > 4) { | |
2523 | DSSERR("Illegal FIFO configuration\n"); | |
2524 | BUG(); | |
2525 | } | |
2526 | ||
2527 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2528 | r |= v << (8 * i); | |
2529 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2530 | add += size; | |
2531 | } | |
2532 | ||
a72b64b9 | 2533 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2534 | } |
2535 | ||
a72b64b9 AT |
2536 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
2537 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2538 | enum fifo_size size3, enum fifo_size size4) |
2539 | { | |
f1da39d9 | 2540 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2541 | u32 r = 0; |
2542 | int add = 0; | |
2543 | int i; | |
2544 | ||
f1da39d9 AT |
2545 | dsi->vc[0].fifo_size = size1; |
2546 | dsi->vc[1].fifo_size = size2; | |
2547 | dsi->vc[2].fifo_size = size3; | |
2548 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2549 | |
2550 | for (i = 0; i < 4; i++) { | |
2551 | u8 v; | |
f1da39d9 | 2552 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2553 | |
2554 | if (add + size > 4) { | |
2555 | DSSERR("Illegal FIFO configuration\n"); | |
2556 | BUG(); | |
2557 | } | |
2558 | ||
2559 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2560 | r |= v << (8 * i); | |
2561 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2562 | add += size; | |
2563 | } | |
2564 | ||
a72b64b9 | 2565 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2566 | } |
2567 | ||
a72b64b9 | 2568 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
3de7a1dc TV |
2569 | { |
2570 | u32 r; | |
2571 | ||
a72b64b9 | 2572 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 2573 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
a72b64b9 | 2574 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 2575 | |
a72b64b9 | 2576 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
3de7a1dc TV |
2577 | DSSERR("TX_STOP bit not going down\n"); |
2578 | return -EIO; | |
2579 | } | |
2580 | ||
2581 | return 0; | |
2582 | } | |
2583 | ||
a72b64b9 | 2584 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
cf398fb3 | 2585 | { |
a72b64b9 | 2586 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
cf398fb3 AT |
2587 | } |
2588 | ||
2589 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2590 | { | |
2e868dbe AT |
2591 | struct dsi_packet_sent_handler_data *vp_data = |
2592 | (struct dsi_packet_sent_handler_data *) data; | |
2593 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); | |
f1da39d9 AT |
2594 | const int channel = dsi->update_channel; |
2595 | u8 bit = dsi->te_enabled ? 30 : 31; | |
cf398fb3 | 2596 | |
2e868dbe AT |
2597 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
2598 | complete(vp_data->completion); | |
cf398fb3 AT |
2599 | } |
2600 | ||
a72b64b9 | 2601 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
cf398fb3 | 2602 | { |
f1da39d9 | 2603 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2e868dbe AT |
2604 | DECLARE_COMPLETION_ONSTACK(completion); |
2605 | struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion }; | |
cf398fb3 AT |
2606 | int r = 0; |
2607 | u8 bit; | |
2608 | ||
f1da39d9 | 2609 | bit = dsi->te_enabled ? 30 : 31; |
cf398fb3 | 2610 | |
a72b64b9 | 2611 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2612 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2613 | if (r) |
2614 | goto err0; | |
2615 | ||
2616 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
a72b64b9 | 2617 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
cf398fb3 AT |
2618 | if (wait_for_completion_timeout(&completion, |
2619 | msecs_to_jiffies(10)) == 0) { | |
2620 | DSSERR("Failed to complete previous frame transfer\n"); | |
2621 | r = -EIO; | |
2622 | goto err1; | |
2623 | } | |
2624 | } | |
2625 | ||
a72b64b9 | 2626 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2627 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2628 | |
2629 | return 0; | |
2630 | err1: | |
a72b64b9 | 2631 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2632 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2633 | err0: |
2634 | return r; | |
2635 | } | |
2636 | ||
2637 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2638 | { | |
2e868dbe AT |
2639 | struct dsi_packet_sent_handler_data *l4_data = |
2640 | (struct dsi_packet_sent_handler_data *) data; | |
2641 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); | |
f1da39d9 | 2642 | const int channel = dsi->update_channel; |
cf398fb3 | 2643 | |
2e868dbe AT |
2644 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
2645 | complete(l4_data->completion); | |
cf398fb3 AT |
2646 | } |
2647 | ||
a72b64b9 | 2648 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
cf398fb3 | 2649 | { |
cf398fb3 | 2650 | DECLARE_COMPLETION_ONSTACK(completion); |
2e868dbe AT |
2651 | struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion }; |
2652 | int r = 0; | |
cf398fb3 | 2653 | |
a72b64b9 | 2654 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2655 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2656 | if (r) |
2657 | goto err0; | |
2658 | ||
2659 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
a72b64b9 | 2660 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
cf398fb3 AT |
2661 | if (wait_for_completion_timeout(&completion, |
2662 | msecs_to_jiffies(10)) == 0) { | |
2663 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2664 | r = -EIO; | |
2665 | goto err1; | |
2666 | } | |
2667 | } | |
2668 | ||
a72b64b9 | 2669 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2670 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2671 | |
2672 | return 0; | |
2673 | err1: | |
a72b64b9 | 2674 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2675 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2676 | err0: |
2677 | return r; | |
2678 | } | |
2679 | ||
a72b64b9 | 2680 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
cf398fb3 | 2681 | { |
f1da39d9 AT |
2682 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2683 | ||
a72b64b9 | 2684 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
cf398fb3 AT |
2685 | |
2686 | WARN_ON(in_interrupt()); | |
2687 | ||
a72b64b9 | 2688 | if (!dsi_vc_is_enabled(dsidev, channel)) |
cf398fb3 AT |
2689 | return 0; |
2690 | ||
d6049144 AT |
2691 | switch (dsi->vc[channel].source) { |
2692 | case DSI_VC_SOURCE_VP: | |
a72b64b9 | 2693 | return dsi_sync_vc_vp(dsidev, channel); |
d6049144 | 2694 | case DSI_VC_SOURCE_L4: |
a72b64b9 | 2695 | return dsi_sync_vc_l4(dsidev, channel); |
cf398fb3 AT |
2696 | default: |
2697 | BUG(); | |
2698 | } | |
2699 | } | |
2700 | ||
a72b64b9 AT |
2701 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
2702 | bool enable) | |
3de7a1dc | 2703 | { |
446f7bff TV |
2704 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2705 | channel, enable); | |
3de7a1dc TV |
2706 | |
2707 | enable = enable ? 1 : 0; | |
2708 | ||
a72b64b9 | 2709 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
3de7a1dc | 2710 | |
a72b64b9 AT |
2711 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
2712 | 0, enable) != enable) { | |
3de7a1dc TV |
2713 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
2714 | return -EIO; | |
2715 | } | |
2716 | ||
2717 | return 0; | |
2718 | } | |
2719 | ||
a72b64b9 | 2720 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
3de7a1dc TV |
2721 | { |
2722 | u32 r; | |
2723 | ||
2724 | DSSDBGF("%d", channel); | |
2725 | ||
a72b64b9 | 2726 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
3de7a1dc TV |
2727 | |
2728 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2729 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2730 | channel); | |
2731 | ||
2732 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2733 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2734 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2735 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2736 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2737 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2738 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
9613c02b AT |
2739 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
2740 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
3de7a1dc TV |
2741 | |
2742 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2743 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2744 | ||
a72b64b9 | 2745 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
3de7a1dc TV |
2746 | } |
2747 | ||
d6049144 AT |
2748 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
2749 | enum dsi_vc_source source) | |
3de7a1dc | 2750 | { |
f1da39d9 AT |
2751 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2752 | ||
d6049144 | 2753 | if (dsi->vc[channel].source == source) |
9ecd9684 | 2754 | return 0; |
3de7a1dc TV |
2755 | |
2756 | DSSDBGF("%d", channel); | |
2757 | ||
a72b64b9 | 2758 | dsi_sync_vc(dsidev, channel); |
cf398fb3 | 2759 | |
a72b64b9 | 2760 | dsi_vc_enable(dsidev, channel, 0); |
3de7a1dc | 2761 | |
9ecd9684 | 2762 | /* VC_BUSY */ |
a72b64b9 | 2763 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
3de7a1dc | 2764 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2765 | return -EIO; |
2766 | } | |
3de7a1dc | 2767 | |
d6049144 AT |
2768 | /* SOURCE, 0 = L4, 1 = video port */ |
2769 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); | |
3de7a1dc | 2770 | |
9613c02b | 2771 | /* DCS_CMD_ENABLE */ |
d6049144 AT |
2772 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
2773 | bool enable = source == DSI_VC_SOURCE_VP; | |
2774 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); | |
2775 | } | |
9613c02b | 2776 | |
a72b64b9 | 2777 | dsi_vc_enable(dsidev, channel, 1); |
3de7a1dc | 2778 | |
d6049144 | 2779 | dsi->vc[channel].source = source; |
9ecd9684 TV |
2780 | |
2781 | return 0; | |
3de7a1dc TV |
2782 | } |
2783 | ||
1ffefe75 AT |
2784 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
2785 | bool enable) | |
3de7a1dc | 2786 | { |
a72b64b9 AT |
2787 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
2788 | ||
3de7a1dc TV |
2789 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
2790 | ||
a72b64b9 | 2791 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
61140c9a | 2792 | |
a72b64b9 AT |
2793 | dsi_vc_enable(dsidev, channel, 0); |
2794 | dsi_if_enable(dsidev, 0); | |
3de7a1dc | 2795 | |
a72b64b9 | 2796 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
3de7a1dc | 2797 | |
a72b64b9 AT |
2798 | dsi_vc_enable(dsidev, channel, 1); |
2799 | dsi_if_enable(dsidev, 1); | |
3de7a1dc | 2800 | |
a72b64b9 | 2801 | dsi_force_tx_stop_mode_io(dsidev); |
3de7a1dc | 2802 | } |
61140c9a | 2803 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
3de7a1dc | 2804 | |
a72b64b9 | 2805 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
3de7a1dc | 2806 | { |
a72b64b9 | 2807 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2808 | u32 val; |
a72b64b9 | 2809 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
3de7a1dc TV |
2810 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
2811 | (val >> 0) & 0xff, | |
2812 | (val >> 8) & 0xff, | |
2813 | (val >> 16) & 0xff, | |
2814 | (val >> 24) & 0xff); | |
2815 | } | |
2816 | } | |
2817 | ||
2818 | static void dsi_show_rx_ack_with_err(u16 err) | |
2819 | { | |
2820 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2821 | if (err & (1 << 0)) | |
2822 | DSSERR("\t\tSoT Error\n"); | |
2823 | if (err & (1 << 1)) | |
2824 | DSSERR("\t\tSoT Sync Error\n"); | |
2825 | if (err & (1 << 2)) | |
2826 | DSSERR("\t\tEoT Sync Error\n"); | |
2827 | if (err & (1 << 3)) | |
2828 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2829 | if (err & (1 << 4)) | |
2830 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2831 | if (err & (1 << 5)) | |
2832 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2833 | if (err & (1 << 6)) | |
2834 | DSSERR("\t\tFalse Control Error\n"); | |
2835 | if (err & (1 << 7)) | |
2836 | DSSERR("\t\t(reserved7)\n"); | |
2837 | if (err & (1 << 8)) | |
2838 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2839 | if (err & (1 << 9)) | |
2840 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2841 | if (err & (1 << 10)) | |
2842 | DSSERR("\t\tChecksum Error\n"); | |
2843 | if (err & (1 << 11)) | |
2844 | DSSERR("\t\tData type not recognized\n"); | |
2845 | if (err & (1 << 12)) | |
2846 | DSSERR("\t\tInvalid VC ID\n"); | |
2847 | if (err & (1 << 13)) | |
2848 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2849 | if (err & (1 << 14)) | |
2850 | DSSERR("\t\t(reserved14)\n"); | |
2851 | if (err & (1 << 15)) | |
2852 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2853 | } | |
2854 | ||
a72b64b9 AT |
2855 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
2856 | int channel) | |
3de7a1dc TV |
2857 | { |
2858 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 2859 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc TV |
2860 | u32 val; |
2861 | u8 dt; | |
a72b64b9 | 2862 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
86a7867e | 2863 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc | 2864 | dt = FLD_GET(val, 5, 0); |
7a7c48f9 | 2865 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2866 | u16 err = FLD_GET(val, 23, 8); |
2867 | dsi_show_rx_ack_with_err(err); | |
7a7c48f9 | 2868 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
86a7867e | 2869 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc | 2870 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2871 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
86a7867e | 2872 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc | 2873 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2874 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
86a7867e | 2875 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc | 2876 | FLD_GET(val, 23, 8)); |
a72b64b9 | 2877 | dsi_vc_flush_long_data(dsidev, channel); |
3de7a1dc TV |
2878 | } else { |
2879 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2880 | } | |
2881 | } | |
2882 | return 0; | |
2883 | } | |
2884 | ||
a72b64b9 | 2885 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
3de7a1dc | 2886 | { |
f1da39d9 AT |
2887 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2888 | ||
2889 | if (dsi->debug_write || dsi->debug_read) | |
3de7a1dc TV |
2890 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2891 | ||
a72b64b9 | 2892 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2893 | |
a72b64b9 AT |
2894 | /* RX_FIFO_NOT_EMPTY */ |
2895 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
3de7a1dc | 2896 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
a72b64b9 | 2897 | dsi_vc_flush_receive_data(dsidev, channel); |
3de7a1dc TV |
2898 | } |
2899 | ||
a72b64b9 | 2900 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
3de7a1dc TV |
2901 | |
2902 | return 0; | |
2903 | } | |
2904 | ||
1ffefe75 | 2905 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2906 | { |
a72b64b9 | 2907 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f36a06e7 | 2908 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2909 | int r = 0; |
2910 | u32 err; | |
2911 | ||
a72b64b9 | 2912 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2913 | &completion, DSI_VC_IRQ_BTA); |
2914 | if (r) | |
2915 | goto err0; | |
3de7a1dc | 2916 | |
a72b64b9 | 2917 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2918 | DSI_IRQ_ERROR_MASK); |
3de7a1dc | 2919 | if (r) |
f36a06e7 | 2920 | goto err1; |
3de7a1dc | 2921 | |
a72b64b9 | 2922 | r = dsi_vc_send_bta(dsidev, channel); |
773b30b2 TV |
2923 | if (r) |
2924 | goto err2; | |
2925 | ||
f36a06e7 | 2926 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2927 | msecs_to_jiffies(500)) == 0) { |
2928 | DSSERR("Failed to receive BTA\n"); | |
2929 | r = -EIO; | |
773b30b2 | 2930 | goto err2; |
3de7a1dc TV |
2931 | } |
2932 | ||
a72b64b9 | 2933 | err = dsi_get_errors(dsidev); |
3de7a1dc TV |
2934 | if (err) { |
2935 | DSSERR("Error while sending BTA: %x\n", err); | |
2936 | r = -EIO; | |
773b30b2 | 2937 | goto err2; |
3de7a1dc | 2938 | } |
773b30b2 | 2939 | err2: |
a72b64b9 | 2940 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2941 | DSI_IRQ_ERROR_MASK); |
f36a06e7 | 2942 | err1: |
a72b64b9 | 2943 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2944 | &completion, DSI_VC_IRQ_BTA); |
2945 | err0: | |
3de7a1dc TV |
2946 | return r; |
2947 | } | |
2948 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); | |
2949 | ||
a72b64b9 AT |
2950 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
2951 | int channel, u8 data_type, u16 len, u8 ecc) | |
3de7a1dc | 2952 | { |
f1da39d9 | 2953 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2954 | u32 val; |
2955 | u8 data_id; | |
2956 | ||
a72b64b9 | 2957 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2958 | |
f1da39d9 | 2959 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2960 | |
2961 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2962 | FLD_VAL(ecc, 31, 24); | |
2963 | ||
a72b64b9 | 2964 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
3de7a1dc TV |
2965 | } |
2966 | ||
a72b64b9 AT |
2967 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
2968 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) | |
3de7a1dc TV |
2969 | { |
2970 | u32 val; | |
2971 | ||
2972 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2973 | ||
2974 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2975 | b1, b2, b3, b4, val); */ | |
2976 | ||
a72b64b9 | 2977 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
3de7a1dc TV |
2978 | } |
2979 | ||
a72b64b9 AT |
2980 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
2981 | u8 data_type, u8 *data, u16 len, u8 ecc) | |
3de7a1dc TV |
2982 | { |
2983 | /*u32 val; */ | |
f1da39d9 | 2984 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2985 | int i; |
2986 | u8 *p; | |
2987 | int r = 0; | |
2988 | u8 b1, b2, b3, b4; | |
2989 | ||
f1da39d9 | 2990 | if (dsi->debug_write) |
3de7a1dc TV |
2991 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
2992 | ||
2993 | /* len + header */ | |
f1da39d9 | 2994 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { |
3de7a1dc TV |
2995 | DSSERR("unable to send long packet: packet too long.\n"); |
2996 | return -EINVAL; | |
2997 | } | |
2998 | ||
d6049144 | 2999 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3000 | |
a72b64b9 | 3001 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
3de7a1dc | 3002 | |
3de7a1dc TV |
3003 | p = data; |
3004 | for (i = 0; i < len >> 2; i++) { | |
f1da39d9 | 3005 | if (dsi->debug_write) |
3de7a1dc | 3006 | DSSDBG("\tsending full packet %d\n", i); |
3de7a1dc TV |
3007 | |
3008 | b1 = *p++; | |
3009 | b2 = *p++; | |
3010 | b3 = *p++; | |
3011 | b4 = *p++; | |
3012 | ||
a72b64b9 | 3013 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
3de7a1dc TV |
3014 | } |
3015 | ||
3016 | i = len % 4; | |
3017 | if (i) { | |
3018 | b1 = 0; b2 = 0; b3 = 0; | |
3019 | ||
f1da39d9 | 3020 | if (dsi->debug_write) |
3de7a1dc TV |
3021 | DSSDBG("\tsending remainder bytes %d\n", i); |
3022 | ||
3023 | switch (i) { | |
3024 | case 3: | |
3025 | b1 = *p++; | |
3026 | b2 = *p++; | |
3027 | b3 = *p++; | |
3028 | break; | |
3029 | case 2: | |
3030 | b1 = *p++; | |
3031 | b2 = *p++; | |
3032 | break; | |
3033 | case 1: | |
3034 | b1 = *p++; | |
3035 | break; | |
3036 | } | |
3037 | ||
a72b64b9 | 3038 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
3de7a1dc TV |
3039 | } |
3040 | ||
3041 | return r; | |
3042 | } | |
3043 | ||
a72b64b9 AT |
3044 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
3045 | u8 data_type, u16 data, u8 ecc) | |
3de7a1dc | 3046 | { |
f1da39d9 | 3047 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3048 | u32 r; |
3049 | u8 data_id; | |
3050 | ||
a72b64b9 | 3051 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 3052 | |
f1da39d9 | 3053 | if (dsi->debug_write) |
3de7a1dc TV |
3054 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
3055 | channel, | |
3056 | data_type, data & 0xff, (data >> 8) & 0xff); | |
3057 | ||
d6049144 | 3058 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 3059 | |
a72b64b9 | 3060 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
3de7a1dc TV |
3061 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
3062 | return -EINVAL; | |
3063 | } | |
3064 | ||
f1da39d9 | 3065 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
3066 | |
3067 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
3068 | ||
a72b64b9 | 3069 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
3de7a1dc TV |
3070 | |
3071 | return 0; | |
3072 | } | |
3073 | ||
1ffefe75 | 3074 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 3075 | { |
a72b64b9 | 3076 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc | 3077 | u8 nullpkg[] = {0, 0, 0, 0}; |
a72b64b9 | 3078 | |
7a7c48f9 | 3079 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, nullpkg, |
a72b64b9 | 3080 | 4, 0); |
3de7a1dc TV |
3081 | } |
3082 | EXPORT_SYMBOL(dsi_vc_send_null); | |
3083 | ||
6ff8aa31 AT |
3084 | static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev, |
3085 | int channel, u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3086 | { |
a72b64b9 | 3087 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3088 | int r; |
3089 | ||
6ff8aa31 AT |
3090 | if (len == 0) { |
3091 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
7a7c48f9 | 3092 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3093 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
3094 | } else if (len == 1) { | |
3095 | r = dsi_vc_send_short(dsidev, channel, | |
3096 | type == DSS_DSI_CONTENT_GENERIC ? | |
3097 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
7a7c48f9 | 3098 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
3de7a1dc | 3099 | } else if (len == 2) { |
7a7c48f9 | 3100 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3101 | type == DSS_DSI_CONTENT_GENERIC ? |
3102 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
7a7c48f9 | 3103 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
3de7a1dc TV |
3104 | data[0] | (data[1] << 8), 0); |
3105 | } else { | |
6ff8aa31 AT |
3106 | r = dsi_vc_send_long(dsidev, channel, |
3107 | type == DSS_DSI_CONTENT_GENERIC ? | |
3108 | MIPI_DSI_GENERIC_LONG_WRITE : | |
3109 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
3de7a1dc TV |
3110 | } |
3111 | ||
3112 | return r; | |
3113 | } | |
6ff8aa31 AT |
3114 | |
3115 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, | |
3116 | u8 *data, int len) | |
3117 | { | |
3118 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3119 | DSS_DSI_CONTENT_DCS); | |
3120 | } | |
3de7a1dc TV |
3121 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
3122 | ||
6ff8aa31 AT |
3123 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
3124 | u8 *data, int len) | |
3125 | { | |
3126 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3127 | DSS_DSI_CONTENT_GENERIC); | |
3128 | } | |
3129 | EXPORT_SYMBOL(dsi_vc_generic_write_nosync); | |
3130 | ||
3131 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, | |
3132 | u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3133 | { |
a72b64b9 | 3134 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3135 | int r; |
3136 | ||
6ff8aa31 | 3137 | r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type); |
3de7a1dc | 3138 | if (r) |
5d68e032 | 3139 | goto err; |
3de7a1dc | 3140 | |
1ffefe75 | 3141 | r = dsi_vc_send_bta_sync(dssdev, channel); |
5d68e032 TV |
3142 | if (r) |
3143 | goto err; | |
3de7a1dc | 3144 | |
a72b64b9 AT |
3145 | /* RX_FIFO_NOT_EMPTY */ |
3146 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
b63ac1e3 | 3147 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
a72b64b9 | 3148 | dsi_vc_flush_receive_data(dsidev, channel); |
b63ac1e3 TV |
3149 | r = -EIO; |
3150 | goto err; | |
3151 | } | |
3152 | ||
5d68e032 TV |
3153 | return 0; |
3154 | err: | |
6ff8aa31 | 3155 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
5d68e032 | 3156 | channel, data[0], len); |
3de7a1dc TV |
3157 | return r; |
3158 | } | |
6ff8aa31 AT |
3159 | |
3160 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
3161 | int len) | |
3162 | { | |
3163 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3164 | DSS_DSI_CONTENT_DCS); | |
3165 | } | |
3de7a1dc TV |
3166 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
3167 | ||
6ff8aa31 AT |
3168 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
3169 | int len) | |
3170 | { | |
3171 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3172 | DSS_DSI_CONTENT_GENERIC); | |
3173 | } | |
3174 | EXPORT_SYMBOL(dsi_vc_generic_write); | |
3175 | ||
1ffefe75 | 3176 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
828c48f8 | 3177 | { |
1ffefe75 | 3178 | return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1); |
828c48f8 TV |
3179 | } |
3180 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); | |
3181 | ||
6ff8aa31 AT |
3182 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel) |
3183 | { | |
3184 | return dsi_vc_generic_write(dssdev, channel, NULL, 0); | |
3185 | } | |
3186 | EXPORT_SYMBOL(dsi_vc_generic_write_0); | |
3187 | ||
1ffefe75 AT |
3188 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
3189 | u8 param) | |
828c48f8 TV |
3190 | { |
3191 | u8 buf[2]; | |
3192 | buf[0] = dcs_cmd; | |
3193 | buf[1] = param; | |
1ffefe75 | 3194 | return dsi_vc_dcs_write(dssdev, channel, buf, 2); |
828c48f8 TV |
3195 | } |
3196 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); | |
3197 | ||
6ff8aa31 AT |
3198 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
3199 | u8 param) | |
3200 | { | |
3201 | return dsi_vc_generic_write(dssdev, channel, ¶m, 1); | |
3202 | } | |
3203 | EXPORT_SYMBOL(dsi_vc_generic_write_1); | |
3204 | ||
3205 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
3206 | u8 param1, u8 param2) | |
3207 | { | |
3208 | u8 buf[2]; | |
3209 | buf[0] = param1; | |
3210 | buf[1] = param2; | |
3211 | return dsi_vc_generic_write(dssdev, channel, buf, 2); | |
3212 | } | |
3213 | EXPORT_SYMBOL(dsi_vc_generic_write_2); | |
3214 | ||
b850975c AT |
3215 | static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev, |
3216 | int channel, u8 dcs_cmd) | |
3de7a1dc | 3217 | { |
a72b64b9 | 3218 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 3219 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3220 | int r; |
3221 | ||
f1da39d9 | 3222 | if (dsi->debug_read) |
b850975c AT |
3223 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
3224 | channel, dcs_cmd); | |
3de7a1dc | 3225 | |
7a7c48f9 | 3226 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
b850975c AT |
3227 | if (r) { |
3228 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
3229 | " failed\n", channel, dcs_cmd); | |
3230 | return r; | |
3231 | } | |
3de7a1dc | 3232 | |
b850975c AT |
3233 | return 0; |
3234 | } | |
3235 | ||
b3b89c05 AT |
3236 | static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev, |
3237 | int channel, u8 *reqdata, int reqlen) | |
3238 | { | |
3239 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3240 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3241 | u16 data; | |
3242 | u8 data_type; | |
3243 | int r; | |
3244 | ||
3245 | if (dsi->debug_read) | |
3246 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
3247 | channel, reqlen); | |
3248 | ||
3249 | if (reqlen == 0) { | |
3250 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
3251 | data = 0; | |
3252 | } else if (reqlen == 1) { | |
3253 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
3254 | data = reqdata[0]; | |
3255 | } else if (reqlen == 2) { | |
3256 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
3257 | data = reqdata[0] | (reqdata[1] << 8); | |
3258 | } else { | |
3259 | BUG(); | |
3260 | } | |
3261 | ||
3262 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); | |
3263 | if (r) { | |
3264 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
3265 | " failed\n", channel, reqlen); | |
3266 | return r; | |
3267 | } | |
3268 | ||
3269 | return 0; | |
3270 | } | |
3271 | ||
3272 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, | |
3273 | u8 *buf, int buflen, enum dss_dsi_content_type type) | |
b850975c AT |
3274 | { |
3275 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3276 | u32 val; | |
3277 | u8 dt; | |
3278 | int r; | |
3de7a1dc TV |
3279 | |
3280 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 3281 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
3de7a1dc | 3282 | DSSERR("RX fifo empty when trying to read.\n"); |
5d68e032 TV |
3283 | r = -EIO; |
3284 | goto err; | |
3de7a1dc TV |
3285 | } |
3286 | ||
a72b64b9 | 3287 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 3288 | if (dsi->debug_read) |
3de7a1dc TV |
3289 | DSSDBG("\theader: %08x\n", val); |
3290 | dt = FLD_GET(val, 5, 0); | |
7a7c48f9 | 3291 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
3292 | u16 err = FLD_GET(val, 23, 8); |
3293 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
3294 | r = -EIO; |
3295 | goto err; | |
3de7a1dc | 3296 | |
b3b89c05 AT |
3297 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3298 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
3299 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
3de7a1dc | 3300 | u8 data = FLD_GET(val, 15, 8); |
f1da39d9 | 3301 | if (dsi->debug_read) |
b3b89c05 AT |
3302 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
3303 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3304 | "DCS", data); | |
3de7a1dc | 3305 | |
5d68e032 TV |
3306 | if (buflen < 1) { |
3307 | r = -EIO; | |
3308 | goto err; | |
3309 | } | |
3de7a1dc TV |
3310 | |
3311 | buf[0] = data; | |
3312 | ||
3313 | return 1; | |
b3b89c05 AT |
3314 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3315 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
3316 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
3de7a1dc | 3317 | u16 data = FLD_GET(val, 23, 8); |
f1da39d9 | 3318 | if (dsi->debug_read) |
b3b89c05 AT |
3319 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
3320 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3321 | "DCS", data); | |
3de7a1dc | 3322 | |
5d68e032 TV |
3323 | if (buflen < 2) { |
3324 | r = -EIO; | |
3325 | goto err; | |
3326 | } | |
3de7a1dc TV |
3327 | |
3328 | buf[0] = data & 0xff; | |
3329 | buf[1] = (data >> 8) & 0xff; | |
3330 | ||
3331 | return 2; | |
b3b89c05 AT |
3332 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3333 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
3334 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3de7a1dc TV |
3335 | int w; |
3336 | int len = FLD_GET(val, 23, 8); | |
f1da39d9 | 3337 | if (dsi->debug_read) |
b3b89c05 AT |
3338 | DSSDBG("\t%s long response, len %d\n", |
3339 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3340 | "DCS", len); | |
3de7a1dc | 3341 | |
5d68e032 TV |
3342 | if (len > buflen) { |
3343 | r = -EIO; | |
3344 | goto err; | |
3345 | } | |
3de7a1dc TV |
3346 | |
3347 | /* two byte checksum ends the packet, not included in len */ | |
3348 | for (w = 0; w < len + 2;) { | |
3349 | int b; | |
a72b64b9 AT |
3350 | val = dsi_read_reg(dsidev, |
3351 | DSI_VC_SHORT_PACKET_HEADER(channel)); | |
f1da39d9 | 3352 | if (dsi->debug_read) |
3de7a1dc TV |
3353 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
3354 | (val >> 0) & 0xff, | |
3355 | (val >> 8) & 0xff, | |
3356 | (val >> 16) & 0xff, | |
3357 | (val >> 24) & 0xff); | |
3358 | ||
3359 | for (b = 0; b < 4; ++b) { | |
3360 | if (w < len) | |
3361 | buf[w] = (val >> (b * 8)) & 0xff; | |
3362 | /* we discard the 2 byte checksum */ | |
3363 | ++w; | |
3364 | } | |
3365 | } | |
3366 | ||
3367 | return len; | |
3de7a1dc TV |
3368 | } else { |
3369 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
3370 | r = -EIO; |
3371 | goto err; | |
3de7a1dc | 3372 | } |
5d68e032 TV |
3373 | |
3374 | BUG(); | |
3375 | err: | |
b3b89c05 AT |
3376 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
3377 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
b850975c | 3378 | |
5d68e032 | 3379 | return r; |
b850975c AT |
3380 | } |
3381 | ||
3382 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | |
3383 | u8 *buf, int buflen) | |
3384 | { | |
3385 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3386 | int r; | |
3387 | ||
3388 | r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd); | |
3389 | if (r) | |
3390 | goto err; | |
5d68e032 | 3391 | |
b850975c AT |
3392 | r = dsi_vc_send_bta_sync(dssdev, channel); |
3393 | if (r) | |
3394 | goto err; | |
3395 | ||
b3b89c05 AT |
3396 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
3397 | DSS_DSI_CONTENT_DCS); | |
b850975c AT |
3398 | if (r < 0) |
3399 | goto err; | |
3400 | ||
3401 | if (r != buflen) { | |
3402 | r = -EIO; | |
3403 | goto err; | |
3404 | } | |
3405 | ||
3406 | return 0; | |
3407 | err: | |
3408 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3409 | return r; | |
3de7a1dc TV |
3410 | } |
3411 | EXPORT_SYMBOL(dsi_vc_dcs_read); | |
3412 | ||
b3b89c05 AT |
3413 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
3414 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3415 | { | |
3416 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3417 | int r; | |
3418 | ||
3419 | r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen); | |
3420 | if (r) | |
3421 | return r; | |
3422 | ||
3423 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3424 | if (r) | |
3425 | return r; | |
3426 | ||
3427 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3428 | DSS_DSI_CONTENT_GENERIC); | |
3429 | if (r < 0) | |
3430 | return r; | |
3431 | ||
3432 | if (r != buflen) { | |
3433 | r = -EIO; | |
3434 | return r; | |
3435 | } | |
3436 | ||
3437 | return 0; | |
3438 | } | |
3439 | ||
3440 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, | |
3441 | int buflen) | |
3442 | { | |
3443 | int r; | |
3444 | ||
3445 | r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen); | |
3446 | if (r) { | |
3447 | DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel); | |
3448 | return r; | |
3449 | } | |
3450 | ||
3451 | return 0; | |
3452 | } | |
3453 | EXPORT_SYMBOL(dsi_vc_generic_read_0); | |
3454 | ||
3455 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
3456 | u8 *buf, int buflen) | |
3457 | { | |
3458 | int r; | |
3459 | ||
3460 | r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen); | |
3461 | if (r) { | |
3462 | DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel); | |
3463 | return r; | |
3464 | } | |
3465 | ||
3466 | return 0; | |
3467 | } | |
3468 | EXPORT_SYMBOL(dsi_vc_generic_read_1); | |
3469 | ||
3470 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
3471 | u8 param1, u8 param2, u8 *buf, int buflen) | |
3472 | { | |
3473 | int r; | |
3474 | u8 reqdata[2]; | |
3475 | ||
3476 | reqdata[0] = param1; | |
3477 | reqdata[1] = param2; | |
3478 | ||
3479 | r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen); | |
3480 | if (r) { | |
3481 | DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel); | |
3482 | return r; | |
3483 | } | |
3484 | ||
3485 | return 0; | |
3486 | } | |
3487 | EXPORT_SYMBOL(dsi_vc_generic_read_2); | |
3488 | ||
1ffefe75 AT |
3489 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
3490 | u16 len) | |
3de7a1dc | 3491 | { |
a72b64b9 AT |
3492 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3493 | ||
7a7c48f9 AT |
3494 | return dsi_vc_send_short(dsidev, channel, |
3495 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); | |
3de7a1dc TV |
3496 | } |
3497 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); | |
3498 | ||
a72b64b9 | 3499 | static int dsi_enter_ulps(struct platform_device *dsidev) |
40885ab3 | 3500 | { |
f1da39d9 | 3501 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
40885ab3 TV |
3502 | DECLARE_COMPLETION_ONSTACK(completion); |
3503 | int r; | |
3504 | ||
3505 | DSSDBGF(); | |
3506 | ||
a72b64b9 | 3507 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
40885ab3 | 3508 | |
f1da39d9 | 3509 | WARN_ON(dsi->ulps_enabled); |
40885ab3 | 3510 | |
f1da39d9 | 3511 | if (dsi->ulps_enabled) |
40885ab3 TV |
3512 | return 0; |
3513 | ||
a72b64b9 | 3514 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
40885ab3 TV |
3515 | DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n"); |
3516 | return -EIO; | |
3517 | } | |
3518 | ||
a72b64b9 AT |
3519 | dsi_sync_vc(dsidev, 0); |
3520 | dsi_sync_vc(dsidev, 1); | |
3521 | dsi_sync_vc(dsidev, 2); | |
3522 | dsi_sync_vc(dsidev, 3); | |
40885ab3 | 3523 | |
a72b64b9 | 3524 | dsi_force_tx_stop_mode_io(dsidev); |
40885ab3 | 3525 | |
a72b64b9 AT |
3526 | dsi_vc_enable(dsidev, 0, false); |
3527 | dsi_vc_enable(dsidev, 1, false); | |
3528 | dsi_vc_enable(dsidev, 2, false); | |
3529 | dsi_vc_enable(dsidev, 3, false); | |
40885ab3 | 3530 | |
a72b64b9 | 3531 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
40885ab3 TV |
3532 | DSSERR("HS busy when enabling ULPS\n"); |
3533 | return -EIO; | |
3534 | } | |
3535 | ||
a72b64b9 | 3536 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
40885ab3 TV |
3537 | DSSERR("LP busy when enabling ULPS\n"); |
3538 | return -EIO; | |
3539 | } | |
3540 | ||
a72b64b9 | 3541 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3542 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3543 | if (r) | |
3544 | return r; | |
3545 | ||
3546 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ | |
3547 | /* LANEx_ULPS_SIG2 */ | |
a72b64b9 AT |
3548 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2), |
3549 | 7, 5); | |
40885ab3 TV |
3550 | |
3551 | if (wait_for_completion_timeout(&completion, | |
3552 | msecs_to_jiffies(1000)) == 0) { | |
3553 | DSSERR("ULPS enable timeout\n"); | |
3554 | r = -EIO; | |
3555 | goto err; | |
3556 | } | |
3557 | ||
a72b64b9 | 3558 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3559 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3560 | ||
8ef0e614 TV |
3561 | /* Reset LANEx_ULPS_SIG2 */ |
3562 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2), | |
3563 | 7, 5); | |
3564 | ||
a72b64b9 | 3565 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
40885ab3 | 3566 | |
a72b64b9 | 3567 | dsi_if_enable(dsidev, false); |
40885ab3 | 3568 | |
f1da39d9 | 3569 | dsi->ulps_enabled = true; |
40885ab3 TV |
3570 | |
3571 | return 0; | |
3572 | ||
3573 | err: | |
a72b64b9 | 3574 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3575 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3576 | return r; | |
3577 | } | |
3578 | ||
a72b64b9 AT |
3579 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
3580 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3581 | { |
3de7a1dc | 3582 | unsigned long fck; |
4ffa3571 TV |
3583 | unsigned long total_ticks; |
3584 | u32 r; | |
3de7a1dc | 3585 | |
4ffa3571 | 3586 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3587 | |
4ffa3571 | 3588 | /* ticks in DSI_FCK */ |
a72b64b9 | 3589 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3590 | |
a72b64b9 | 3591 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3592 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
4ffa3571 TV |
3593 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
3594 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc | 3595 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
a72b64b9 | 3596 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3597 | |
4ffa3571 TV |
3598 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3599 | ||
3600 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3601 | total_ticks, | |
3602 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3603 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3604 | } |
3605 | ||
a72b64b9 AT |
3606 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
3607 | bool x8, bool x16) | |
3de7a1dc | 3608 | { |
3de7a1dc | 3609 | unsigned long fck; |
4ffa3571 TV |
3610 | unsigned long total_ticks; |
3611 | u32 r; | |
3612 | ||
3613 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
3614 | |
3615 | /* ticks in DSI_FCK */ | |
a72b64b9 | 3616 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3617 | |
a72b64b9 | 3618 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3619 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
4ffa3571 TV |
3620 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
3621 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc | 3622 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
a72b64b9 | 3623 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3624 | |
4ffa3571 TV |
3625 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
3626 | ||
3627 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3628 | total_ticks, | |
3629 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3630 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3631 | } |
3632 | ||
a72b64b9 AT |
3633 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
3634 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3635 | { |
3de7a1dc | 3636 | unsigned long fck; |
4ffa3571 TV |
3637 | unsigned long total_ticks; |
3638 | u32 r; | |
3de7a1dc | 3639 | |
4ffa3571 | 3640 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3641 | |
4ffa3571 | 3642 | /* ticks in DSI_FCK */ |
a72b64b9 | 3643 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3644 | |
a72b64b9 | 3645 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3646 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
4ffa3571 TV |
3647 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
3648 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc | 3649 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
a72b64b9 | 3650 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3651 | |
4ffa3571 TV |
3652 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3653 | ||
3654 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3655 | total_ticks, | |
3656 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3657 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3658 | } |
3659 | ||
a72b64b9 AT |
3660 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
3661 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3662 | { |
3de7a1dc | 3663 | unsigned long fck; |
4ffa3571 TV |
3664 | unsigned long total_ticks; |
3665 | u32 r; | |
3de7a1dc | 3666 | |
4ffa3571 | 3667 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3668 | |
4ffa3571 | 3669 | /* ticks in TxByteClkHS */ |
a72b64b9 | 3670 | fck = dsi_get_txbyteclkhs(dsidev); |
3de7a1dc | 3671 | |
a72b64b9 | 3672 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3673 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
4ffa3571 TV |
3674 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
3675 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc | 3676 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
a72b64b9 | 3677 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3678 | |
4ffa3571 TV |
3679 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3680 | ||
3681 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3682 | total_ticks, | |
3683 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3684 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3685 | } |
3686 | static int dsi_proto_config(struct omap_dss_device *dssdev) | |
3687 | { | |
a72b64b9 | 3688 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3689 | u32 r; |
3690 | int buswidth = 0; | |
3691 | ||
a72b64b9 | 3692 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3693 | DSI_FIFO_SIZE_32, |
3694 | DSI_FIFO_SIZE_32, | |
3695 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 3696 | |
a72b64b9 | 3697 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3698 | DSI_FIFO_SIZE_32, |
3699 | DSI_FIFO_SIZE_32, | |
3700 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
3701 | |
3702 | /* XXX what values for the timeouts? */ | |
a72b64b9 AT |
3703 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
3704 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); | |
3705 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); | |
3706 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); | |
3de7a1dc | 3707 | |
a3b3cc2b | 3708 | switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) { |
3de7a1dc TV |
3709 | case 16: |
3710 | buswidth = 0; | |
3711 | break; | |
3712 | case 18: | |
3713 | buswidth = 1; | |
3714 | break; | |
3715 | case 24: | |
3716 | buswidth = 2; | |
3717 | break; | |
3718 | default: | |
3719 | BUG(); | |
3720 | } | |
3721 | ||
a72b64b9 | 3722 | r = dsi_read_reg(dsidev, DSI_CTRL); |
3de7a1dc TV |
3723 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
3724 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3725 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3726 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3727 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3728 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3729 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ | |
3730 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ | |
3731 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
9613c02b AT |
3732 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
3733 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
3734 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3735 | r = FLD_MOD(r, 0, 25, 25); | |
3736 | } | |
3de7a1dc | 3737 | |
a72b64b9 | 3738 | dsi_write_reg(dsidev, DSI_CTRL, r); |
3de7a1dc | 3739 | |
a72b64b9 AT |
3740 | dsi_vc_initial_config(dsidev, 0); |
3741 | dsi_vc_initial_config(dsidev, 1); | |
3742 | dsi_vc_initial_config(dsidev, 2); | |
3743 | dsi_vc_initial_config(dsidev, 3); | |
3de7a1dc TV |
3744 | |
3745 | return 0; | |
3746 | } | |
3747 | ||
3748 | static void dsi_proto_timings(struct omap_dss_device *dssdev) | |
3749 | { | |
a72b64b9 | 3750 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3751 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
3752 | unsigned tclk_pre, tclk_post; | |
3753 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3754 | unsigned ths_trail, ths_exit; | |
3755 | unsigned ddr_clk_pre, ddr_clk_post; | |
3756 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
3757 | unsigned ths_eot; | |
3758 | u32 r; | |
3759 | ||
a72b64b9 | 3760 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
3761 | ths_prepare = FLD_GET(r, 31, 24); |
3762 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3763 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3764 | ths_trail = FLD_GET(r, 15, 8); | |
3765 | ths_exit = FLD_GET(r, 7, 0); | |
3766 | ||
a72b64b9 | 3767 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
3768 | tlpx = FLD_GET(r, 22, 16) * 2; |
3769 | tclk_trail = FLD_GET(r, 15, 8); | |
3770 | tclk_zero = FLD_GET(r, 7, 0); | |
3771 | ||
a72b64b9 | 3772 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc TV |
3773 | tclk_prepare = FLD_GET(r, 7, 0); |
3774 | ||
3775 | /* min 8*UI */ | |
3776 | tclk_pre = 20; | |
3777 | /* min 60ns + 52*UI */ | |
a72b64b9 | 3778 | tclk_post = ns2ddr(dsidev, 60) + 26; |
3de7a1dc | 3779 | |
75d7247c | 3780 | ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev)); |
3de7a1dc TV |
3781 | |
3782 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3783 | 4); | |
3784 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3785 | ||
3786 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3787 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3788 | ||
a72b64b9 | 3789 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
3de7a1dc TV |
3790 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
3791 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
a72b64b9 | 3792 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
3de7a1dc TV |
3793 | |
3794 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3795 | ddr_clk_pre, | |
3796 | ddr_clk_post); | |
3797 | ||
3798 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3799 | DIV_ROUND_UP(ths_prepare, 4) + | |
3800 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3801 | ||
3802 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3803 | ||
3804 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3805 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
a72b64b9 | 3806 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
3de7a1dc TV |
3807 | |
3808 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3809 | enter_hs_mode_lat, exit_hs_mode_lat); | |
3810 | } | |
3811 | ||
3de7a1dc TV |
3812 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, |
3813 | u16 x, u16 y, u16 w, u16 h) | |
3814 | { | |
a72b64b9 | 3815 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 3816 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3817 | unsigned bytespp; |
3818 | unsigned bytespl; | |
3819 | unsigned bytespf; | |
3820 | unsigned total_len; | |
3821 | unsigned packet_payload; | |
3822 | unsigned packet_len; | |
3823 | u32 l; | |
0f16aa0a | 3824 | int r; |
f1da39d9 | 3825 | const unsigned channel = dsi->update_channel; |
0c65622b | 3826 | const unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
3de7a1dc | 3827 | |
446f7bff TV |
3828 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
3829 | x, y, w, h); | |
3de7a1dc | 3830 | |
d6049144 | 3831 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
18946f62 | 3832 | |
a3b3cc2b | 3833 | bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8; |
3de7a1dc TV |
3834 | bytespl = w * bytespp; |
3835 | bytespf = bytespl * h; | |
3836 | ||
3837 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
3838 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
3839 | ||
3840 | if (bytespf < line_buf_size) | |
3841 | packet_payload = bytespf; | |
3842 | else | |
3843 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
3844 | ||
3845 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
3846 | total_len = (bytespf / packet_payload) * packet_len; | |
3847 | ||
3848 | if (bytespf % packet_payload) | |
3849 | total_len += (bytespf % packet_payload) + 1; | |
3850 | ||
3de7a1dc | 3851 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
a72b64b9 | 3852 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc | 3853 | |
7a7c48f9 | 3854 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
a72b64b9 | 3855 | packet_len, 0); |
3de7a1dc | 3856 | |
f1da39d9 | 3857 | if (dsi->te_enabled) |
3de7a1dc TV |
3858 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
3859 | else | |
3860 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
a72b64b9 | 3861 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc TV |
3862 | |
3863 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
3864 | * because DSS interrupts are not capable of waking up the CPU and the | |
3865 | * framedone interrupt could be delayed for quite a long time. I think | |
3866 | * the same goes for any DSS interrupts, but for some reason I have not | |
3867 | * seen the problem anywhere else than here. | |
3868 | */ | |
3869 | dispc_disable_sidle(); | |
3870 | ||
a72b64b9 | 3871 | dsi_perf_mark_start(dsidev); |
18946f62 | 3872 | |
49dbf589 AT |
3873 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
3874 | msecs_to_jiffies(250)); | |
0f16aa0a | 3875 | BUG_ON(r == 0); |
18946f62 | 3876 | |
3de7a1dc TV |
3877 | dss_start_update(dssdev); |
3878 | ||
f1da39d9 | 3879 | if (dsi->te_enabled) { |
3de7a1dc TV |
3880 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
3881 | * for TE is longer than the timer allows */ | |
a72b64b9 | 3882 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
3de7a1dc | 3883 | |
a72b64b9 | 3884 | dsi_vc_send_bta(dsidev, channel); |
3de7a1dc TV |
3885 | |
3886 | #ifdef DSI_CATCH_MISSING_TE | |
f1da39d9 | 3887 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
3de7a1dc TV |
3888 | #endif |
3889 | } | |
3890 | } | |
3891 | ||
3892 | #ifdef DSI_CATCH_MISSING_TE | |
3893 | static void dsi_te_timeout(unsigned long arg) | |
3894 | { | |
3895 | DSSERR("TE not received for 250ms!\n"); | |
3896 | } | |
3897 | #endif | |
3898 | ||
a72b64b9 | 3899 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
3de7a1dc | 3900 | { |
f1da39d9 AT |
3901 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3902 | ||
3de7a1dc TV |
3903 | /* SIDLEMODE back to smart-idle */ |
3904 | dispc_enable_sidle(); | |
3905 | ||
f1da39d9 | 3906 | if (dsi->te_enabled) { |
18946f62 | 3907 | /* enable LP_RX_TO again after the TE */ |
a72b64b9 | 3908 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
3de7a1dc TV |
3909 | } |
3910 | ||
f1da39d9 | 3911 | dsi->framedone_callback(error, dsi->framedone_data); |
ab83b14c TV |
3912 | |
3913 | if (!error) | |
a72b64b9 | 3914 | dsi_perf_show(dsidev, "DISPC"); |
18946f62 | 3915 | } |
3de7a1dc | 3916 | |
ab83b14c | 3917 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 3918 | { |
f1da39d9 AT |
3919 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
3920 | framedone_timeout_work.work); | |
ab83b14c TV |
3921 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
3922 | * 250ms which would conflict with this timeout work. What should be | |
3923 | * done is first cancel the transfer on the HW, and then cancel the | |
3924 | * possibly scheduled framedone work. However, cancelling the transfer | |
3925 | * on the HW is buggy, and would probably require resetting the whole | |
3926 | * DSI */ | |
18946f62 | 3927 | |
ab83b14c | 3928 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 3929 | |
f1da39d9 | 3930 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
3de7a1dc TV |
3931 | } |
3932 | ||
ab83b14c | 3933 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
3de7a1dc | 3934 | { |
a72b64b9 AT |
3935 | struct omap_dss_device *dssdev = (struct omap_dss_device *) data; |
3936 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
f1da39d9 AT |
3937 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3938 | ||
ab83b14c TV |
3939 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
3940 | * turns itself off. However, DSI still has the pixels in its buffers, | |
3941 | * and is sending the data. | |
3942 | */ | |
3de7a1dc | 3943 | |
f1da39d9 | 3944 | __cancel_delayed_work(&dsi->framedone_timeout_work); |
3de7a1dc | 3945 | |
a72b64b9 | 3946 | dsi_handle_framedone(dsidev, 0); |
3de7a1dc | 3947 | |
cf398fb3 AT |
3948 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
3949 | dispc_fake_vsync_irq(); | |
3950 | #endif | |
18946f62 | 3951 | } |
3de7a1dc | 3952 | |
18946f62 | 3953 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
26a8c250 TV |
3954 | u16 *x, u16 *y, u16 *w, u16 *h, |
3955 | bool enlarge_update_area) | |
18946f62 | 3956 | { |
a72b64b9 | 3957 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
18946f62 | 3958 | u16 dw, dh; |
3de7a1dc | 3959 | |
18946f62 | 3960 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
3de7a1dc | 3961 | |
18946f62 TV |
3962 | if (*x > dw || *y > dh) |
3963 | return -EINVAL; | |
3de7a1dc | 3964 | |
18946f62 TV |
3965 | if (*x + *w > dw) |
3966 | return -EINVAL; | |
3de7a1dc | 3967 | |
18946f62 TV |
3968 | if (*y + *h > dh) |
3969 | return -EINVAL; | |
3de7a1dc | 3970 | |
18946f62 TV |
3971 | if (*w == 1) |
3972 | return -EINVAL; | |
3de7a1dc | 3973 | |
18946f62 TV |
3974 | if (*w == 0 || *h == 0) |
3975 | return -EINVAL; | |
3de7a1dc | 3976 | |
a72b64b9 | 3977 | dsi_perf_mark_setup(dsidev); |
3de7a1dc | 3978 | |
4a9e78ab TV |
3979 | dss_setup_partial_planes(dssdev, x, y, w, h, |
3980 | enlarge_update_area); | |
26d9dd0d | 3981 | dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h); |
3de7a1dc | 3982 | |
18946f62 TV |
3983 | return 0; |
3984 | } | |
3985 | EXPORT_SYMBOL(omap_dsi_prepare_update); | |
3de7a1dc | 3986 | |
18946f62 TV |
3987 | int omap_dsi_update(struct omap_dss_device *dssdev, |
3988 | int channel, | |
3989 | u16 x, u16 y, u16 w, u16 h, | |
3990 | void (*callback)(int, void *), void *data) | |
3991 | { | |
a72b64b9 | 3992 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 3993 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 3994 | |
f1da39d9 | 3995 | dsi->update_channel = channel; |
3de7a1dc | 3996 | |
a602771c TV |
3997 | /* OMAP DSS cannot send updates of odd widths. |
3998 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON | |
3999 | * here to make sure we catch erroneous updates. Otherwise we'll only | |
4000 | * see rather obscure HW error happening, as DSS halts. */ | |
4001 | BUG_ON(x % 2 == 1); | |
4002 | ||
4a9e78ab TV |
4003 | dsi->framedone_callback = callback; |
4004 | dsi->framedone_data = data; | |
e9c31afc | 4005 | |
4a9e78ab TV |
4006 | dsi->update_region.x = x; |
4007 | dsi->update_region.y = y; | |
4008 | dsi->update_region.w = w; | |
4009 | dsi->update_region.h = h; | |
4010 | dsi->update_region.device = dssdev; | |
e9c31afc | 4011 | |
4a9e78ab | 4012 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
3de7a1dc | 4013 | |
3de7a1dc TV |
4014 | return 0; |
4015 | } | |
18946f62 | 4016 | EXPORT_SYMBOL(omap_dsi_update); |
3de7a1dc TV |
4017 | |
4018 | /* Display funcs */ | |
4019 | ||
4020 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) | |
4021 | { | |
4022 | int r; | |
5a8b572d AT |
4023 | u32 irq; |
4024 | ||
4025 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? | |
4026 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; | |
3de7a1dc | 4027 | |
a72b64b9 | 4028 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev, |
5a8b572d | 4029 | irq); |
3de7a1dc TV |
4030 | if (r) { |
4031 | DSSERR("can't get FRAMEDONE irq\n"); | |
4032 | return r; | |
4033 | } | |
4034 | ||
26d9dd0d | 4035 | dispc_mgr_set_lcd_display_type(dssdev->manager->id, |
64ba4f74 | 4036 | OMAP_DSS_LCD_DISPLAY_TFT); |
3de7a1dc | 4037 | |
569969d6 | 4038 | dispc_mgr_enable_stallmode(dssdev->manager->id, true); |
26d9dd0d | 4039 | dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1); |
3de7a1dc | 4040 | |
26d9dd0d | 4041 | dispc_mgr_set_tft_data_lines(dssdev->manager->id, |
a3b3cc2b | 4042 | dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)); |
3de7a1dc TV |
4043 | |
4044 | { | |
4045 | struct omap_video_timings timings = { | |
4046 | .hsw = 1, | |
4047 | .hfp = 1, | |
4048 | .hbp = 1, | |
4049 | .vsw = 1, | |
4050 | .vfp = 0, | |
4051 | .vbp = 0, | |
4052 | }; | |
4053 | ||
26d9dd0d | 4054 | dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings); |
3de7a1dc TV |
4055 | } |
4056 | ||
4057 | return 0; | |
4058 | } | |
4059 | ||
4060 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) | |
4061 | { | |
5a8b572d AT |
4062 | u32 irq; |
4063 | ||
4064 | irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ? | |
4065 | DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2; | |
4066 | ||
a72b64b9 | 4067 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev, |
5a8b572d | 4068 | irq); |
3de7a1dc TV |
4069 | } |
4070 | ||
4071 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) | |
4072 | { | |
a72b64b9 | 4073 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
4074 | struct dsi_clock_info cinfo; |
4075 | int r; | |
4076 | ||
1bb47835 AT |
4077 | /* we always use DSS_CLK_SYSCK as input clock */ |
4078 | cinfo.use_sys_clk = true; | |
c6940a3d TV |
4079 | cinfo.regn = dssdev->clocks.dsi.regn; |
4080 | cinfo.regm = dssdev->clocks.dsi.regm; | |
4081 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; | |
4082 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; | |
ff1b2cde | 4083 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
ebf0a3fe VS |
4084 | if (r) { |
4085 | DSSERR("Failed to calc dsi clocks\n"); | |
3de7a1dc | 4086 | return r; |
ebf0a3fe | 4087 | } |
3de7a1dc | 4088 | |
a72b64b9 | 4089 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
3de7a1dc TV |
4090 | if (r) { |
4091 | DSSERR("Failed to set dsi clocks\n"); | |
4092 | return r; | |
4093 | } | |
4094 | ||
4095 | return 0; | |
4096 | } | |
4097 | ||
4098 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) | |
4099 | { | |
a72b64b9 | 4100 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
4101 | struct dispc_clock_info dispc_cinfo; |
4102 | int r; | |
4103 | unsigned long long fck; | |
4104 | ||
a72b64b9 | 4105 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); |
3de7a1dc | 4106 | |
e8881662 AT |
4107 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
4108 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; | |
3de7a1dc TV |
4109 | |
4110 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
4111 | if (r) { | |
4112 | DSSERR("Failed to calc dispc clocks\n"); | |
4113 | return r; | |
4114 | } | |
4115 | ||
26d9dd0d | 4116 | r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
3de7a1dc TV |
4117 | if (r) { |
4118 | DSSERR("Failed to set dispc clocks\n"); | |
4119 | return r; | |
4120 | } | |
4121 | ||
4122 | return 0; | |
4123 | } | |
4124 | ||
4125 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) | |
4126 | { | |
a72b64b9 | 4127 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5a8b572d | 4128 | int dsi_module = dsi_get_dsidev_id(dsidev); |
3de7a1dc TV |
4129 | int r; |
4130 | ||
a72b64b9 | 4131 | r = dsi_pll_init(dsidev, true, true); |
3de7a1dc TV |
4132 | if (r) |
4133 | goto err0; | |
4134 | ||
4135 | r = dsi_configure_dsi_clocks(dssdev); | |
4136 | if (r) | |
4137 | goto err1; | |
4138 | ||
e8881662 | 4139 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
5a8b572d | 4140 | dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src); |
9613c02b | 4141 | dss_select_lcd_clk_source(dssdev->manager->id, |
e8881662 | 4142 | dssdev->clocks.dispc.channel.lcd_clk_src); |
3de7a1dc TV |
4143 | |
4144 | DSSDBG("PLL OK\n"); | |
4145 | ||
4146 | r = dsi_configure_dispc_clocks(dssdev); | |
4147 | if (r) | |
4148 | goto err2; | |
4149 | ||
cc5c1850 | 4150 | r = dsi_cio_init(dssdev); |
3de7a1dc TV |
4151 | if (r) |
4152 | goto err2; | |
4153 | ||
a72b64b9 | 4154 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4155 | |
4156 | dsi_proto_timings(dssdev); | |
4157 | dsi_set_lp_clk_divisor(dssdev); | |
4158 | ||
4159 | if (1) | |
a72b64b9 | 4160 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4161 | |
4162 | r = dsi_proto_config(dssdev); | |
4163 | if (r) | |
4164 | goto err3; | |
4165 | ||
4166 | /* enable interface */ | |
a72b64b9 AT |
4167 | dsi_vc_enable(dsidev, 0, 1); |
4168 | dsi_vc_enable(dsidev, 1, 1); | |
4169 | dsi_vc_enable(dsidev, 2, 1); | |
4170 | dsi_vc_enable(dsidev, 3, 1); | |
4171 | dsi_if_enable(dsidev, 1); | |
4172 | dsi_force_tx_stop_mode_io(dsidev); | |
3de7a1dc | 4173 | |
3de7a1dc | 4174 | return 0; |
3de7a1dc | 4175 | err3: |
5bc416cb | 4176 | dsi_cio_uninit(dssdev); |
3de7a1dc | 4177 | err2: |
89a35e51 | 4178 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
5a8b572d | 4179 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
5e785091 TV |
4180 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
4181 | ||
3de7a1dc | 4182 | err1: |
a72b64b9 | 4183 | dsi_pll_uninit(dsidev, true); |
3de7a1dc TV |
4184 | err0: |
4185 | return r; | |
4186 | } | |
4187 | ||
2a89dc15 | 4188 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
22d6d676 | 4189 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4190 | { |
a72b64b9 | 4191 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4192 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
5a8b572d | 4193 | int dsi_module = dsi_get_dsidev_id(dsidev); |
a72b64b9 | 4194 | |
f1da39d9 | 4195 | if (enter_ulps && !dsi->ulps_enabled) |
a72b64b9 | 4196 | dsi_enter_ulps(dsidev); |
40885ab3 | 4197 | |
d7370104 | 4198 | /* disable interface */ |
a72b64b9 AT |
4199 | dsi_if_enable(dsidev, 0); |
4200 | dsi_vc_enable(dsidev, 0, 0); | |
4201 | dsi_vc_enable(dsidev, 1, 0); | |
4202 | dsi_vc_enable(dsidev, 2, 0); | |
4203 | dsi_vc_enable(dsidev, 3, 0); | |
d7370104 | 4204 | |
89a35e51 | 4205 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
5a8b572d | 4206 | dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK); |
5e785091 | 4207 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
5bc416cb | 4208 | dsi_cio_uninit(dssdev); |
a72b64b9 | 4209 | dsi_pll_uninit(dsidev, disconnect_lanes); |
3de7a1dc TV |
4210 | } |
4211 | ||
37ac60e4 | 4212 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc | 4213 | { |
a72b64b9 | 4214 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4215 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4216 | int r = 0; |
4217 | ||
4218 | DSSDBG("dsi_display_enable\n"); | |
4219 | ||
a72b64b9 | 4220 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
37ac60e4 | 4221 | |
f1da39d9 | 4222 | mutex_lock(&dsi->lock); |
3de7a1dc | 4223 | |
05e1d606 TV |
4224 | if (dssdev->manager == NULL) { |
4225 | DSSERR("failed to enable display: no manager\n"); | |
4226 | r = -ENODEV; | |
4227 | goto err_start_dev; | |
4228 | } | |
4229 | ||
3de7a1dc TV |
4230 | r = omap_dss_start_device(dssdev); |
4231 | if (r) { | |
4232 | DSSERR("failed to start device\n"); | |
4fbafaf3 | 4233 | goto err_start_dev; |
3de7a1dc TV |
4234 | } |
4235 | ||
4fbafaf3 | 4236 | r = dsi_runtime_get(dsidev); |
3de7a1dc | 4237 | if (r) |
4fbafaf3 TV |
4238 | goto err_get_dsi; |
4239 | ||
4240 | dsi_enable_pll_clock(dsidev, 1); | |
3de7a1dc | 4241 | |
4fbafaf3 | 4242 | _dsi_initialize_irq(dsidev); |
3de7a1dc TV |
4243 | |
4244 | r = dsi_display_init_dispc(dssdev); | |
4245 | if (r) | |
4fbafaf3 | 4246 | goto err_init_dispc; |
3de7a1dc TV |
4247 | |
4248 | r = dsi_display_init_dsi(dssdev); | |
4249 | if (r) | |
4fbafaf3 | 4250 | goto err_init_dsi; |
3de7a1dc | 4251 | |
f1da39d9 | 4252 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4253 | |
4254 | return 0; | |
4255 | ||
4fbafaf3 | 4256 | err_init_dsi: |
37ac60e4 | 4257 | dsi_display_uninit_dispc(dssdev); |
4fbafaf3 | 4258 | err_init_dispc: |
a72b64b9 | 4259 | dsi_enable_pll_clock(dsidev, 0); |
4fbafaf3 TV |
4260 | dsi_runtime_put(dsidev); |
4261 | err_get_dsi: | |
3de7a1dc | 4262 | omap_dss_stop_device(dssdev); |
4fbafaf3 | 4263 | err_start_dev: |
f1da39d9 | 4264 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4265 | DSSDBG("dsi_display_enable FAILED\n"); |
4266 | return r; | |
4267 | } | |
37ac60e4 | 4268 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
3de7a1dc | 4269 | |
2a89dc15 | 4270 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 4271 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4272 | { |
a72b64b9 | 4273 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4274 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4275 | |
3de7a1dc TV |
4276 | DSSDBG("dsi_display_disable\n"); |
4277 | ||
a72b64b9 | 4278 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 4279 | |
f1da39d9 | 4280 | mutex_lock(&dsi->lock); |
3de7a1dc | 4281 | |
15ffa1da TV |
4282 | dsi_sync_vc(dsidev, 0); |
4283 | dsi_sync_vc(dsidev, 1); | |
4284 | dsi_sync_vc(dsidev, 2); | |
4285 | dsi_sync_vc(dsidev, 3); | |
4286 | ||
3de7a1dc TV |
4287 | dsi_display_uninit_dispc(dssdev); |
4288 | ||
22d6d676 | 4289 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
3de7a1dc | 4290 | |
4fbafaf3 | 4291 | dsi_runtime_put(dsidev); |
a72b64b9 | 4292 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc | 4293 | |
37ac60e4 | 4294 | omap_dss_stop_device(dssdev); |
3de7a1dc | 4295 | |
f1da39d9 | 4296 | mutex_unlock(&dsi->lock); |
3de7a1dc | 4297 | } |
37ac60e4 | 4298 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
3de7a1dc | 4299 | |
225b650d | 4300 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 4301 | { |
f1da39d9 AT |
4302 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4303 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4304 | ||
4305 | dsi->te_enabled = enable; | |
225b650d | 4306 | return 0; |
3de7a1dc | 4307 | } |
225b650d | 4308 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
3de7a1dc | 4309 | |
3de7a1dc | 4310 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
5ed8cf5b | 4311 | u32 fifo_size, u32 burst_size, |
3de7a1dc TV |
4312 | u32 *fifo_low, u32 *fifo_high) |
4313 | { | |
5ed8cf5b TV |
4314 | *fifo_high = fifo_size - burst_size; |
4315 | *fifo_low = fifo_size - burst_size * 2; | |
3de7a1dc TV |
4316 | } |
4317 | ||
4318 | int dsi_init_display(struct omap_dss_device *dssdev) | |
4319 | { | |
f1da39d9 AT |
4320 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4321 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
75d7247c | 4322 | int dsi_module = dsi_get_dsidev_id(dsidev); |
f1da39d9 | 4323 | |
3de7a1dc TV |
4324 | DSSDBG("DSI init\n"); |
4325 | ||
7e951ee9 AT |
4326 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4327 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | | |
4328 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; | |
4329 | } | |
3de7a1dc | 4330 | |
f1da39d9 | 4331 | if (dsi->vdds_dsi_reg == NULL) { |
5f42f2ce TV |
4332 | struct regulator *vdds_dsi; |
4333 | ||
f1da39d9 | 4334 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
5f42f2ce TV |
4335 | |
4336 | if (IS_ERR(vdds_dsi)) { | |
4337 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4338 | return PTR_ERR(vdds_dsi); | |
4339 | } | |
4340 | ||
f1da39d9 | 4341 | dsi->vdds_dsi_reg = vdds_dsi; |
5f42f2ce TV |
4342 | } |
4343 | ||
75d7247c AT |
4344 | if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) { |
4345 | DSSERR("DSI%d can't support more than %d data lanes\n", | |
4346 | dsi_module + 1, dsi->num_data_lanes); | |
4347 | return -EINVAL; | |
4348 | } | |
4349 | ||
3de7a1dc TV |
4350 | return 0; |
4351 | } | |
4352 | ||
5ee3c144 AT |
4353 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
4354 | { | |
f1da39d9 AT |
4355 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4356 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5ee3c144 AT |
4357 | int i; |
4358 | ||
f1da39d9 AT |
4359 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
4360 | if (!dsi->vc[i].dssdev) { | |
4361 | dsi->vc[i].dssdev = dssdev; | |
5ee3c144 AT |
4362 | *channel = i; |
4363 | return 0; | |
4364 | } | |
4365 | } | |
4366 | ||
4367 | DSSERR("cannot get VC for display %s", dssdev->name); | |
4368 | return -ENOSPC; | |
4369 | } | |
4370 | EXPORT_SYMBOL(omap_dsi_request_vc); | |
4371 | ||
4372 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) | |
4373 | { | |
f1da39d9 AT |
4374 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4375 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4376 | ||
5ee3c144 AT |
4377 | if (vc_id < 0 || vc_id > 3) { |
4378 | DSSERR("VC ID out of range\n"); | |
4379 | return -EINVAL; | |
4380 | } | |
4381 | ||
4382 | if (channel < 0 || channel > 3) { | |
4383 | DSSERR("Virtual Channel out of range\n"); | |
4384 | return -EINVAL; | |
4385 | } | |
4386 | ||
f1da39d9 | 4387 | if (dsi->vc[channel].dssdev != dssdev) { |
5ee3c144 AT |
4388 | DSSERR("Virtual Channel not allocated to display %s\n", |
4389 | dssdev->name); | |
4390 | return -EINVAL; | |
4391 | } | |
4392 | ||
f1da39d9 | 4393 | dsi->vc[channel].vc_id = vc_id; |
5ee3c144 AT |
4394 | |
4395 | return 0; | |
4396 | } | |
4397 | EXPORT_SYMBOL(omap_dsi_set_vc_id); | |
4398 | ||
4399 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) | |
4400 | { | |
f1da39d9 AT |
4401 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4402 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4403 | ||
5ee3c144 | 4404 | if ((channel >= 0 && channel <= 3) && |
f1da39d9 AT |
4405 | dsi->vc[channel].dssdev == dssdev) { |
4406 | dsi->vc[channel].dssdev = NULL; | |
4407 | dsi->vc[channel].vc_id = 0; | |
5ee3c144 AT |
4408 | } |
4409 | } | |
4410 | EXPORT_SYMBOL(omap_dsi_release_vc); | |
4411 | ||
a72b64b9 | 4412 | void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) |
e406f907 | 4413 | { |
a72b64b9 | 4414 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1) |
067a57e4 | 4415 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4416 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
4417 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | |
e406f907 TV |
4418 | } |
4419 | ||
a72b64b9 | 4420 | void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) |
e406f907 | 4421 | { |
a72b64b9 | 4422 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1) |
067a57e4 | 4423 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4424 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
4425 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | |
e406f907 TV |
4426 | } |
4427 | ||
a72b64b9 | 4428 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
49641116 | 4429 | { |
f1da39d9 AT |
4430 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4431 | ||
4432 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); | |
4433 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); | |
4434 | dsi->regm_dispc_max = | |
4435 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); | |
4436 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); | |
4437 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); | |
4438 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); | |
4439 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
49641116 TA |
4440 | } |
4441 | ||
4fbafaf3 TV |
4442 | static int dsi_get_clocks(struct platform_device *dsidev) |
4443 | { | |
4444 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4445 | struct clk *clk; | |
4446 | ||
4447 | clk = clk_get(&dsidev->dev, "fck"); | |
4448 | if (IS_ERR(clk)) { | |
4449 | DSSERR("can't get fck\n"); | |
4450 | return PTR_ERR(clk); | |
4451 | } | |
4452 | ||
4453 | dsi->dss_clk = clk; | |
4454 | ||
bfe4f8d3 | 4455 | clk = clk_get(&dsidev->dev, "sys_clk"); |
4fbafaf3 TV |
4456 | if (IS_ERR(clk)) { |
4457 | DSSERR("can't get sys_clk\n"); | |
4458 | clk_put(dsi->dss_clk); | |
4459 | dsi->dss_clk = NULL; | |
4460 | return PTR_ERR(clk); | |
4461 | } | |
4462 | ||
4463 | dsi->sys_clk = clk; | |
4464 | ||
4465 | return 0; | |
4466 | } | |
4467 | ||
4468 | static void dsi_put_clocks(struct platform_device *dsidev) | |
4469 | { | |
4470 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4471 | ||
4472 | if (dsi->dss_clk) | |
4473 | clk_put(dsi->dss_clk); | |
4474 | if (dsi->sys_clk) | |
4475 | clk_put(dsi->sys_clk); | |
4476 | } | |
4477 | ||
b98482ed | 4478 | /* DSI1 HW IP initialisation */ |
7c68dd96 | 4479 | static int omap_dsihw_probe(struct platform_device *dsidev) |
3de7a1dc | 4480 | { |
d1f5857e TV |
4481 | struct omap_display_platform_data *dss_plat_data; |
4482 | struct omap_dss_board_info *board_info; | |
3de7a1dc | 4483 | u32 rev; |
f1da39d9 | 4484 | int r, i, dsi_module = dsi_get_dsidev_id(dsidev); |
ea9da36a | 4485 | struct resource *dsi_mem; |
f1da39d9 AT |
4486 | struct dsi_data *dsi; |
4487 | ||
4488 | dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); | |
4489 | if (!dsi) { | |
4490 | r = -ENOMEM; | |
4fbafaf3 | 4491 | goto err_alloc; |
f1da39d9 | 4492 | } |
3de7a1dc | 4493 | |
f1da39d9 AT |
4494 | dsi->pdev = dsidev; |
4495 | dsi_pdev_map[dsi_module] = dsidev; | |
4496 | dev_set_drvdata(&dsidev->dev, dsi); | |
a72b64b9 AT |
4497 | |
4498 | dss_plat_data = dsidev->dev.platform_data; | |
d1f5857e | 4499 | board_info = dss_plat_data->board_data; |
5bc416cb TV |
4500 | dsi->enable_pads = board_info->dsi_enable_pads; |
4501 | dsi->disable_pads = board_info->dsi_disable_pads; | |
d1f5857e | 4502 | |
f1da39d9 AT |
4503 | spin_lock_init(&dsi->irq_lock); |
4504 | spin_lock_init(&dsi->errors_lock); | |
4505 | dsi->errors = 0; | |
3de7a1dc | 4506 | |
dfc0fd8d | 4507 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f1da39d9 AT |
4508 | spin_lock_init(&dsi->irq_stats_lock); |
4509 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d TV |
4510 | #endif |
4511 | ||
f1da39d9 AT |
4512 | mutex_init(&dsi->lock); |
4513 | sema_init(&dsi->bus_lock, 1); | |
3de7a1dc | 4514 | |
4fbafaf3 TV |
4515 | r = dsi_get_clocks(dsidev); |
4516 | if (r) | |
4517 | goto err_get_clk; | |
4518 | ||
4519 | pm_runtime_enable(&dsidev->dev); | |
4520 | ||
f1da39d9 | 4521 | INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work, |
18946f62 TV |
4522 | dsi_framedone_timeout_work_callback); |
4523 | ||
3de7a1dc | 4524 | #ifdef DSI_CATCH_MISSING_TE |
f1da39d9 AT |
4525 | init_timer(&dsi->te_timer); |
4526 | dsi->te_timer.function = dsi_te_timeout; | |
4527 | dsi->te_timer.data = 0; | |
3de7a1dc | 4528 | #endif |
f1da39d9 | 4529 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); |
ea9da36a SG |
4530 | if (!dsi_mem) { |
4531 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
4532 | r = -EINVAL; | |
4fbafaf3 | 4533 | goto err_ioremap; |
ea9da36a | 4534 | } |
f1da39d9 AT |
4535 | dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem)); |
4536 | if (!dsi->base) { | |
3de7a1dc TV |
4537 | DSSERR("can't ioremap DSI\n"); |
4538 | r = -ENOMEM; | |
4fbafaf3 | 4539 | goto err_ioremap; |
3de7a1dc | 4540 | } |
f1da39d9 AT |
4541 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
4542 | if (dsi->irq < 0) { | |
affe360d | 4543 | DSSERR("platform_get_irq failed\n"); |
4544 | r = -ENODEV; | |
4fbafaf3 | 4545 | goto err_get_irq; |
affe360d | 4546 | } |
4547 | ||
f1da39d9 AT |
4548 | r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED, |
4549 | dev_name(&dsidev->dev), dsi->pdev); | |
affe360d | 4550 | if (r < 0) { |
4551 | DSSERR("request_irq failed\n"); | |
4fbafaf3 | 4552 | goto err_get_irq; |
affe360d | 4553 | } |
3de7a1dc | 4554 | |
5ee3c144 | 4555 | /* DSI VCs initialization */ |
f1da39d9 | 4556 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
d6049144 | 4557 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
f1da39d9 AT |
4558 | dsi->vc[i].dssdev = NULL; |
4559 | dsi->vc[i].vc_id = 0; | |
5ee3c144 AT |
4560 | } |
4561 | ||
a72b64b9 | 4562 | dsi_calc_clock_param_ranges(dsidev); |
49641116 | 4563 | |
4fbafaf3 TV |
4564 | r = dsi_runtime_get(dsidev); |
4565 | if (r) | |
4566 | goto err_get_dsi; | |
3de7a1dc | 4567 | |
a72b64b9 AT |
4568 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
4569 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", | |
3de7a1dc TV |
4570 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
4571 | ||
75d7247c AT |
4572 | dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev); |
4573 | ||
4fbafaf3 | 4574 | dsi_runtime_put(dsidev); |
3de7a1dc | 4575 | |
3de7a1dc | 4576 | return 0; |
4fbafaf3 TV |
4577 | |
4578 | err_get_dsi: | |
4579 | free_irq(dsi->irq, dsi->pdev); | |
4580 | err_get_irq: | |
49dbf589 | 4581 | iounmap(dsi->base); |
4fbafaf3 TV |
4582 | err_ioremap: |
4583 | pm_runtime_disable(&dsidev->dev); | |
4584 | err_get_clk: | |
f1da39d9 | 4585 | kfree(dsi); |
4fbafaf3 | 4586 | err_alloc: |
3de7a1dc TV |
4587 | return r; |
4588 | } | |
4589 | ||
7c68dd96 | 4590 | static int omap_dsihw_remove(struct platform_device *dsidev) |
3de7a1dc | 4591 | { |
f1da39d9 AT |
4592 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4593 | ||
b98482ed TV |
4594 | WARN_ON(dsi->scp_clk_refcount > 0); |
4595 | ||
4fbafaf3 TV |
4596 | pm_runtime_disable(&dsidev->dev); |
4597 | ||
4598 | dsi_put_clocks(dsidev); | |
4599 | ||
f1da39d9 AT |
4600 | if (dsi->vdds_dsi_reg != NULL) { |
4601 | if (dsi->vdds_dsi_enabled) { | |
4602 | regulator_disable(dsi->vdds_dsi_reg); | |
4603 | dsi->vdds_dsi_enabled = false; | |
88257b26 TV |
4604 | } |
4605 | ||
f1da39d9 AT |
4606 | regulator_put(dsi->vdds_dsi_reg); |
4607 | dsi->vdds_dsi_reg = NULL; | |
c8aac01b SG |
4608 | } |
4609 | ||
f1da39d9 AT |
4610 | free_irq(dsi->irq, dsi->pdev); |
4611 | iounmap(dsi->base); | |
3de7a1dc | 4612 | |
f1da39d9 | 4613 | kfree(dsi); |
0f16aa0a | 4614 | |
c8aac01b SG |
4615 | return 0; |
4616 | } | |
4617 | ||
4fbafaf3 TV |
4618 | static int dsi_runtime_suspend(struct device *dev) |
4619 | { | |
4fbafaf3 TV |
4620 | dispc_runtime_put(); |
4621 | dss_runtime_put(); | |
4622 | ||
4623 | return 0; | |
4624 | } | |
4625 | ||
4626 | static int dsi_runtime_resume(struct device *dev) | |
4627 | { | |
4fbafaf3 TV |
4628 | int r; |
4629 | ||
4630 | r = dss_runtime_get(); | |
4631 | if (r) | |
4632 | goto err_get_dss; | |
4633 | ||
4634 | r = dispc_runtime_get(); | |
4635 | if (r) | |
4636 | goto err_get_dispc; | |
4637 | ||
4fbafaf3 TV |
4638 | return 0; |
4639 | ||
4640 | err_get_dispc: | |
4641 | dss_runtime_put(); | |
4642 | err_get_dss: | |
4643 | return r; | |
4644 | } | |
4645 | ||
4646 | static const struct dev_pm_ops dsi_pm_ops = { | |
4647 | .runtime_suspend = dsi_runtime_suspend, | |
4648 | .runtime_resume = dsi_runtime_resume, | |
4649 | }; | |
4650 | ||
7c68dd96 TV |
4651 | static struct platform_driver omap_dsihw_driver = { |
4652 | .probe = omap_dsihw_probe, | |
4653 | .remove = omap_dsihw_remove, | |
c8aac01b | 4654 | .driver = { |
7c68dd96 | 4655 | .name = "omapdss_dsi", |
c8aac01b | 4656 | .owner = THIS_MODULE, |
4fbafaf3 | 4657 | .pm = &dsi_pm_ops, |
c8aac01b SG |
4658 | }, |
4659 | }; | |
4660 | ||
4661 | int dsi_init_platform_driver(void) | |
4662 | { | |
7c68dd96 | 4663 | return platform_driver_register(&omap_dsihw_driver); |
c8aac01b SG |
4664 | } |
4665 | ||
4666 | void dsi_uninit_platform_driver(void) | |
4667 | { | |
7c68dd96 | 4668 | return platform_driver_unregister(&omap_dsihw_driver); |
c8aac01b | 4669 | } |