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OMAP2, 3: DSS2: VENC: create platform_driver, move init, exit to driver
[linux-2.6-block.git] / drivers / video / omap2 / dss / dsi.c
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3de7a1dc
TV		 1/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
b9eb5d7d 30#include <linux/semaphore.h>
3de7a1dc
TV		 31#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
3de7a1dc 34#include <linux/wait.h>
18946f62 35#include <linux/workqueue.h>
3de7a1dc
TV		 36
37#include <plat/display.h>
38#include <plat/clock.h>
39
40#include "dss.h"
41
42/*#define VERBOSE_IRQ*/
43#define DSI_CATCH_MISSING_TE
44
45#define DSI_BASE 0x4804FC00
46
47struct dsi_reg { u16 idx; };
48
49#define DSI_REG(idx) ((const struct dsi_reg) { idx })
50
51#define DSI_SZ_REGS SZ_1K
52/* DSI Protocol Engine */
53
54#define DSI_REVISION DSI_REG(0x0000)
55#define DSI_SYSCONFIG DSI_REG(0x0010)
56#define DSI_SYSSTATUS DSI_REG(0x0014)
57#define DSI_IRQSTATUS DSI_REG(0x0018)
58#define DSI_IRQENABLE DSI_REG(0x001C)
59#define DSI_CTRL DSI_REG(0x0040)
60#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
61#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
62#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
63#define DSI_CLK_CTRL DSI_REG(0x0054)
64#define DSI_TIMING1 DSI_REG(0x0058)
65#define DSI_TIMING2 DSI_REG(0x005C)
66#define DSI_VM_TIMING1 DSI_REG(0x0060)
67#define DSI_VM_TIMING2 DSI_REG(0x0064)
68#define DSI_VM_TIMING3 DSI_REG(0x0068)
69#define DSI_CLK_TIMING DSI_REG(0x006C)
70#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
71#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
72#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
73#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
74#define DSI_VM_TIMING4 DSI_REG(0x0080)
75#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
76#define DSI_VM_TIMING5 DSI_REG(0x0088)
77#define DSI_VM_TIMING6 DSI_REG(0x008C)
78#define DSI_VM_TIMING7 DSI_REG(0x0090)
79#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
80#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
81#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
83#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
84#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
85#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
86#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
87
88/* DSIPHY_SCP */
89
90#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
91#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
92#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
93#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
94
95/* DSI_PLL_CTRL_SCP */
96
97#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
98#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
99#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
100#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
101#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
102
103#define REG_GET(idx, start, end) \
104 FLD_GET(dsi_read_reg(idx), start, end)
105
106#define REG_FLD_MOD(idx, val, start, end) \
107 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
108
109/* Global interrupts */
110#define DSI_IRQ_VC0 (1 << 0)
111#define DSI_IRQ_VC1 (1 << 1)
112#define DSI_IRQ_VC2 (1 << 2)
113#define DSI_IRQ_VC3 (1 << 3)
114#define DSI_IRQ_WAKEUP (1 << 4)
115#define DSI_IRQ_RESYNC (1 << 5)
116#define DSI_IRQ_PLL_LOCK (1 << 7)
117#define DSI_IRQ_PLL_UNLOCK (1 << 8)
118#define DSI_IRQ_PLL_RECALL (1 << 9)
119#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
120#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
121#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
122#define DSI_IRQ_TE_TRIGGER (1 << 16)
123#define DSI_IRQ_ACK_TRIGGER (1 << 17)
124#define DSI_IRQ_SYNC_LOST (1 << 18)
125#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
126#define DSI_IRQ_TA_TIMEOUT (1 << 20)
127#define DSI_IRQ_ERROR_MASK \
128 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
129 DSI_IRQ_TA_TIMEOUT)
130#define DSI_IRQ_CHANNEL_MASK 0xf
131
132/* Virtual channel interrupts */
133#define DSI_VC_IRQ_CS (1 << 0)
134#define DSI_VC_IRQ_ECC_CORR (1 << 1)
135#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
136#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
137#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
138#define DSI_VC_IRQ_BTA (1 << 5)
139#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
140#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
141#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
142#define DSI_VC_IRQ_ERROR_MASK \
143 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
144 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
145 DSI_VC_IRQ_FIFO_TX_UDF)
146
147/* ComplexIO interrupts */
148#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
149#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
150#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
151#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
152#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
153#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
154#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
155#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
156#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
157#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
158#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
159#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
164#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
165#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
166#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
167#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
bbecb50b
TV		 168#define DSI_CIO_IRQ_ERROR_MASK \
169 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
170 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
171 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
172 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
174 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
175 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
3de7a1dc
TV		 176
177#define DSI_DT_DCS_SHORT_WRITE_0 0x05
178#define DSI_DT_DCS_SHORT_WRITE_1 0x15
179#define DSI_DT_DCS_READ 0x06
180#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
181#define DSI_DT_NULL_PACKET 0x09
182#define DSI_DT_DCS_LONG_WRITE 0x39
183
184#define DSI_DT_RX_ACK_WITH_ERR 0x02
185#define DSI_DT_RX_DCS_LONG_READ 0x1c
186#define DSI_DT_RX_SHORT_READ_1 0x21
187#define DSI_DT_RX_SHORT_READ_2 0x22
188
189#define FINT_MAX 2100000
190#define FINT_MIN 750000
191#define REGN_MAX (1 << 7)
192#define REGM_MAX ((1 << 11) - 1)
193#define REGM3_MAX (1 << 4)
194#define REGM4_MAX (1 << 4)
195#define LP_DIV_MAX ((1 << 13) - 1)
196
197enum fifo_size {
198 DSI_FIFO_SIZE_0 = 0,
199 DSI_FIFO_SIZE_32 = 1,
200 DSI_FIFO_SIZE_64 = 2,
201 DSI_FIFO_SIZE_96 = 3,
202 DSI_FIFO_SIZE_128 = 4,
203};
204
205enum dsi_vc_mode {
206 DSI_VC_MODE_L4 = 0,
207 DSI_VC_MODE_VP,
208};
209
210struct dsi_update_region {
3de7a1dc
TV		 211 u16 x, y, w, h;
212 struct omap_dss_device *device;
213};
214
dfc0fd8d
TV		 215struct dsi_irq_stats {
216 unsigned long last_reset;
217 unsigned irq_count;
218 unsigned dsi_irqs[32];
219 unsigned vc_irqs[4][32];
220 unsigned cio_irqs[32];
221};
222
3de7a1dc
TV		 223static struct
224{
225 void __iomem *base;
226
227 struct dsi_clock_info current_cinfo;
228
229 struct regulator *vdds_dsi_reg;
230
231 struct {
232 enum dsi_vc_mode mode;
233 struct omap_dss_device *dssdev;
234 enum fifo_size fifo_size;
3de7a1dc
TV		 235 } vc[4];
236
237 struct mutex lock;
b9eb5d7d 238 struct semaphore bus_lock;
3de7a1dc
TV		 239
240 unsigned pll_locked;
241
242 struct completion bta_completion;
ab83b14c 243 void (*bta_callback)(void);
3de7a1dc 244
18946f62 245 int update_channel;
3de7a1dc 246 struct dsi_update_region update_region;
3de7a1dc 247
3de7a1dc 248 bool te_enabled;
3de7a1dc 249
0f16aa0a
TV		 250 struct workqueue_struct *workqueue;
251
18946f62
TV		 252 void (*framedone_callback)(int, void *);
253 void *framedone_data;
254
255 struct delayed_work framedone_timeout_work;
256
3de7a1dc
TV		 257#ifdef DSI_CATCH_MISSING_TE
258 struct timer_list te_timer;
259#endif
260
261 unsigned long cache_req_pck;
262 unsigned long cache_clk_freq;
263 struct dsi_clock_info cache_cinfo;
264
265 u32 errors;
266 spinlock_t errors_lock;
267#ifdef DEBUG
268 ktime_t perf_setup_time;
269 ktime_t perf_start_time;
3de7a1dc
TV		 270#endif
271 int debug_read;
272 int debug_write;
dfc0fd8d
TV		 273
274#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
275 spinlock_t irq_stats_lock;
276 struct dsi_irq_stats irq_stats;
277#endif
3de7a1dc
TV		 278} dsi;
279
280#ifdef DEBUG
281static unsigned int dsi_perf;
282module_param_named(dsi_perf, dsi_perf, bool, 0644);
283#endif
284
285static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
286{
287 __raw_writel(val, dsi.base + idx.idx);
288}
289
290static inline u32 dsi_read_reg(const struct dsi_reg idx)
291{
292 return __raw_readl(dsi.base + idx.idx);
293}
294
295
296void dsi_save_context(void)
297{
298}
299
300void dsi_restore_context(void)
301{
302}
303
304void dsi_bus_lock(void)
305{
b9eb5d7d 306 down(&dsi.bus_lock);
3de7a1dc
TV		 307}
308EXPORT_SYMBOL(dsi_bus_lock);
309
310void dsi_bus_unlock(void)
311{
b9eb5d7d 312 up(&dsi.bus_lock);
3de7a1dc
TV		 313}
314EXPORT_SYMBOL(dsi_bus_unlock);
315
4f765023
TV		 316static bool dsi_bus_is_locked(void)
317{
b9eb5d7d 318 return dsi.bus_lock.count == 0;
4f765023
TV		 319}
320
3de7a1dc
TV		 321static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
322 int value)
323{
324 int t = 100000;
325
326 while (REG_GET(idx, bitnum, bitnum) != value) {
327 if (--t == 0)
328 return !value;
329 }
330
331 return value;
332}
333
334#ifdef DEBUG
335static void dsi_perf_mark_setup(void)
336{
337 dsi.perf_setup_time = ktime_get();
338}
339
340static void dsi_perf_mark_start(void)
341{
342 dsi.perf_start_time = ktime_get();
343}
344
3de7a1dc
TV		 345static void dsi_perf_show(const char *name)
346{
347 ktime_t t, setup_time, trans_time;
348 u32 total_bytes;
349 u32 setup_us, trans_us, total_us;
350
351 if (!dsi_perf)
352 return;
353
3de7a1dc
TV		 354 t = ktime_get();
355
356 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
357 setup_us = (u32)ktime_to_us(setup_time);
358 if (setup_us == 0)
359 setup_us = 1;
360
361 trans_time = ktime_sub(t, dsi.perf_start_time);
362 trans_us = (u32)ktime_to_us(trans_time);
363 if (trans_us == 0)
364 trans_us = 1;
365
366 total_us = setup_us + trans_us;
367
18946f62
TV		 368 total_bytes = dsi.update_region.w *
369 dsi.update_region.h *
370 dsi.update_region.device->ctrl.pixel_size / 8;
3de7a1dc 371
1bbb275e
TV		 372 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
373 "%u bytes, %u kbytes/sec\n",
374 name,
375 setup_us,
376 trans_us,
377 total_us,
378 1000*1000 / total_us,
379 total_bytes,
380 total_bytes * 1000 / total_us);
3de7a1dc
TV		 381}
382#else
383#define dsi_perf_mark_setup()
384#define dsi_perf_mark_start()
3de7a1dc
TV		 385#define dsi_perf_show(x)
386#endif
387
388static void print_irq_status(u32 status)
389{
390#ifndef VERBOSE_IRQ
391 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
392 return;
393#endif
394 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
395
396#define PIS(x) \
397 if (status & DSI_IRQ_##x) \
398 printk(#x " ");
399#ifdef VERBOSE_IRQ
400 PIS(VC0);
401 PIS(VC1);
402 PIS(VC2);
403 PIS(VC3);
404#endif
405 PIS(WAKEUP);
406 PIS(RESYNC);
407 PIS(PLL_LOCK);
408 PIS(PLL_UNLOCK);
409 PIS(PLL_RECALL);
410 PIS(COMPLEXIO_ERR);
411 PIS(HS_TX_TIMEOUT);
412 PIS(LP_RX_TIMEOUT);
413 PIS(TE_TRIGGER);
414 PIS(ACK_TRIGGER);
415 PIS(SYNC_LOST);
416 PIS(LDO_POWER_GOOD);
417 PIS(TA_TIMEOUT);
418#undef PIS
419
420 printk("\n");
421}
422
423static void print_irq_status_vc(int channel, u32 status)
424{
425#ifndef VERBOSE_IRQ
426 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
427 return;
428#endif
429 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
430
431#define PIS(x) \
432 if (status & DSI_VC_IRQ_##x) \
433 printk(#x " ");
434 PIS(CS);
435 PIS(ECC_CORR);
436#ifdef VERBOSE_IRQ
437 PIS(PACKET_SENT);
438#endif
439 PIS(FIFO_TX_OVF);
440 PIS(FIFO_RX_OVF);
441 PIS(BTA);
442 PIS(ECC_NO_CORR);
443 PIS(FIFO_TX_UDF);
444 PIS(PP_BUSY_CHANGE);
445#undef PIS
446 printk("\n");
447}
448
449static void print_irq_status_cio(u32 status)
450{
451 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
452
453#define PIS(x) \
454 if (status & DSI_CIO_IRQ_##x) \
455 printk(#x " ");
456 PIS(ERRSYNCESC1);
457 PIS(ERRSYNCESC2);
458 PIS(ERRSYNCESC3);
459 PIS(ERRESC1);
460 PIS(ERRESC2);
461 PIS(ERRESC3);
462 PIS(ERRCONTROL1);
463 PIS(ERRCONTROL2);
464 PIS(ERRCONTROL3);
465 PIS(STATEULPS1);
466 PIS(STATEULPS2);
467 PIS(STATEULPS3);
468 PIS(ERRCONTENTIONLP0_1);
469 PIS(ERRCONTENTIONLP1_1);
470 PIS(ERRCONTENTIONLP0_2);
471 PIS(ERRCONTENTIONLP1_2);
472 PIS(ERRCONTENTIONLP0_3);
473 PIS(ERRCONTENTIONLP1_3);
474 PIS(ULPSACTIVENOT_ALL0);
475 PIS(ULPSACTIVENOT_ALL1);
476#undef PIS
477
478 printk("\n");
479}
480
481static int debug_irq;
482
483/* called from dss */
484void dsi_irq_handler(void)
485{
486 u32 irqstatus, vcstatus, ciostatus;
487 int i;
488
489 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
490
dfc0fd8d
TV		 491#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
492 spin_lock(&dsi.irq_stats_lock);
493 dsi.irq_stats.irq_count++;
494 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
495#endif
496
3de7a1dc
TV		 497 if (irqstatus & DSI_IRQ_ERROR_MASK) {
498 DSSERR("DSI error, irqstatus %x\n", irqstatus);
499 print_irq_status(irqstatus);
500 spin_lock(&dsi.errors_lock);
501 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
502 spin_unlock(&dsi.errors_lock);
503 } else if (debug_irq) {
504 print_irq_status(irqstatus);
505 }
506
507#ifdef DSI_CATCH_MISSING_TE
508 if (irqstatus & DSI_IRQ_TE_TRIGGER)
509 del_timer(&dsi.te_timer);
510#endif
511
512 for (i = 0; i < 4; ++i) {
513 if ((irqstatus & (1<<i)) == 0)
514 continue;
515
516 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
517
dfc0fd8d
TV		 518#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
519 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
520#endif
521
ab83b14c 522 if (vcstatus & DSI_VC_IRQ_BTA) {
3de7a1dc
TV		 523 complete(&dsi.bta_completion);
524
ab83b14c
TV		 525 if (dsi.bta_callback)
526 dsi.bta_callback();
527 }
528
3de7a1dc
TV		 529 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
530 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
531 i, vcstatus);
532 print_irq_status_vc(i, vcstatus);
533 } else if (debug_irq) {
534 print_irq_status_vc(i, vcstatus);
535 }
536
537 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
538 /* flush posted write */
539 dsi_read_reg(DSI_VC_IRQSTATUS(i));
540 }
541
542 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
543 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
544
dfc0fd8d
TV		 545#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
546 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
547#endif
548
3de7a1dc
TV		 549 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
550 /* flush posted write */
551 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
552
bbecb50b
TV		 553 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
554 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
555 print_irq_status_cio(ciostatus);
556 } else if (debug_irq) {
557 print_irq_status_cio(ciostatus);
558 }
3de7a1dc
TV		 559 }
560
561 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
562 /* flush posted write */
563 dsi_read_reg(DSI_IRQSTATUS);
dfc0fd8d
TV		 564
565#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
566 spin_unlock(&dsi.irq_stats_lock);
567#endif
3de7a1dc
TV		 568}
569
570
571static void _dsi_initialize_irq(void)
572{
573 u32 l;
574 int i;
575
576 /* disable all interrupts */
577 dsi_write_reg(DSI_IRQENABLE, 0);
578 for (i = 0; i < 4; ++i)
579 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
580 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
581
582 /* clear interrupt status */
583 l = dsi_read_reg(DSI_IRQSTATUS);
584 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
585
586 for (i = 0; i < 4; ++i) {
587 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
588 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
589 }
590
591 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
592 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
593
594 /* enable error irqs */
595 l = DSI_IRQ_ERROR_MASK;
596#ifdef DSI_CATCH_MISSING_TE
597 l |= DSI_IRQ_TE_TRIGGER;
598#endif
599 dsi_write_reg(DSI_IRQENABLE, l);
600
601 l = DSI_VC_IRQ_ERROR_MASK;
602 for (i = 0; i < 4; ++i)
603 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
604
bbecb50b
TV		 605 l = DSI_CIO_IRQ_ERROR_MASK;
606 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
3de7a1dc
TV		 607}
608
609static u32 dsi_get_errors(void)
610{
611 unsigned long flags;
612 u32 e;
613 spin_lock_irqsave(&dsi.errors_lock, flags);
614 e = dsi.errors;
615 dsi.errors = 0;
616 spin_unlock_irqrestore(&dsi.errors_lock, flags);
617 return e;
618}
619
620static void dsi_vc_enable_bta_irq(int channel)
621{
622 u32 l;
623
624 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
625
626 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
627 l |= DSI_VC_IRQ_BTA;
628 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
629}
630
631static void dsi_vc_disable_bta_irq(int channel)
632{
633 u32 l;
634
635 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
636 l &= ~DSI_VC_IRQ_BTA;
637 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
638}
639
640/* DSI func clock. this could also be DSI2_PLL_FCLK */
641static inline void enable_clocks(bool enable)
642{
643 if (enable)
644 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
645 else
646 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
647}
648
649/* source clock for DSI PLL. this could also be PCLKFREE */
650static inline void dsi_enable_pll_clock(bool enable)
651{
652 if (enable)
653 dss_clk_enable(DSS_CLK_FCK2);
654 else
655 dss_clk_disable(DSS_CLK_FCK2);
656
657 if (enable && dsi.pll_locked) {
658 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
659 DSSERR("cannot lock PLL when enabling clocks\n");
660 }
661}
662
663#ifdef DEBUG
664static void _dsi_print_reset_status(void)
665{
666 u32 l;
667
668 if (!dss_debug)
669 return;
670
671 /* A dummy read using the SCP interface to any DSIPHY register is
672 * required after DSIPHY reset to complete the reset of the DSI complex
673 * I/O. */
674 l = dsi_read_reg(DSI_DSIPHY_CFG5);
675
676 printk(KERN_DEBUG "DSI resets: ");
677
678 l = dsi_read_reg(DSI_PLL_STATUS);
679 printk("PLL (%d) ", FLD_GET(l, 0, 0));
680
681 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
682 printk("CIO (%d) ", FLD_GET(l, 29, 29));
683
684 l = dsi_read_reg(DSI_DSIPHY_CFG5);
685 printk("PHY (%x, %d, %d, %d)\n",
686 FLD_GET(l, 28, 26),
687 FLD_GET(l, 29, 29),
688 FLD_GET(l, 30, 30),
689 FLD_GET(l, 31, 31));
690}
691#else
692#define _dsi_print_reset_status()
693#endif
694
695static inline int dsi_if_enable(bool enable)
696{
697 DSSDBG("dsi_if_enable(%d)\n", enable);
698
699 enable = enable ? 1 : 0;
700 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
701
702 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
703 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
704 return -EIO;
705 }
706
707 return 0;
708}
709
710unsigned long dsi_get_dsi1_pll_rate(void)
711{
712 return dsi.current_cinfo.dsi1_pll_fclk;
713}
714
715static unsigned long dsi_get_dsi2_pll_rate(void)
716{
717 return dsi.current_cinfo.dsi2_pll_fclk;
718}
719
720static unsigned long dsi_get_txbyteclkhs(void)
721{
722 return dsi.current_cinfo.clkin4ddr / 16;
723}
724
725static unsigned long dsi_fclk_rate(void)
726{
727 unsigned long r;
728
63cf28ac 729 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
3de7a1dc
TV		 730 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
731 r = dss_clk_get_rate(DSS_CLK_FCK1);
732 } else {
733 /* DSI FCLK source is DSI2_PLL_FCLK */
734 r = dsi_get_dsi2_pll_rate();
735 }
736
737 return r;
738}
739
740static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
741{
742 unsigned long dsi_fclk;
743 unsigned lp_clk_div;
744 unsigned long lp_clk;
745
746 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
747
748 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
749 return -EINVAL;
750
751 dsi_fclk = dsi_fclk_rate();
752
753 lp_clk = dsi_fclk / 2 / lp_clk_div;
754
755 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
756 dsi.current_cinfo.lp_clk = lp_clk;
757 dsi.current_cinfo.lp_clk_div = lp_clk_div;
758
759 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
760
761 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
762 21, 21); /* LP_RX_SYNCHRO_ENABLE */
763
764 return 0;
765}
766
767
768enum dsi_pll_power_state {
769 DSI_PLL_POWER_OFF = 0x0,
770 DSI_PLL_POWER_ON_HSCLK = 0x1,
771 DSI_PLL_POWER_ON_ALL = 0x2,
772 DSI_PLL_POWER_ON_DIV = 0x3,
773};
774
775static int dsi_pll_power(enum dsi_pll_power_state state)
776{
777 int t = 0;
778
779 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
780
781 /* PLL_PWR_STATUS */
782 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
24be78b3 783 if (++t > 1000) {
3de7a1dc
TV		 784 DSSERR("Failed to set DSI PLL power mode to %d\n",
785 state);
786 return -ENODEV;
787 }
24be78b3 788 udelay(1);
3de7a1dc
TV		 789 }
790
791 return 0;
792}
793
794/* calculate clock rates using dividers in cinfo */
ff1b2cde
SS		 795static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
796 struct dsi_clock_info *cinfo)
3de7a1dc
TV		 797{
798 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
799 return -EINVAL;
800
801 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
802 return -EINVAL;
803
804 if (cinfo->regm3 > REGM3_MAX)
805 return -EINVAL;
806
807 if (cinfo->regm4 > REGM4_MAX)
808 return -EINVAL;
809
810 if (cinfo->use_dss2_fck) {
811 cinfo->clkin = dss_clk_get_rate(DSS_CLK_FCK2);
812 /* XXX it is unclear if highfreq should be used
813 * with DSS2_FCK source also */
814 cinfo->highfreq = 0;
815 } else {
ff1b2cde 816 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
3de7a1dc
TV		 817
818 if (cinfo->clkin < 32000000)
819 cinfo->highfreq = 0;
820 else
821 cinfo->highfreq = 1;
822 }
823
824 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
825
826 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
827 return -EINVAL;
828
829 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
830
831 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
832 return -EINVAL;
833
834 if (cinfo->regm3 > 0)
835 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
836 else
837 cinfo->dsi1_pll_fclk = 0;
838
839 if (cinfo->regm4 > 0)
840 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
841 else
842 cinfo->dsi2_pll_fclk = 0;
843
844 return 0;
845}
846
847int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
848 struct dsi_clock_info *dsi_cinfo,
849 struct dispc_clock_info *dispc_cinfo)
850{
851 struct dsi_clock_info cur, best;
852 struct dispc_clock_info best_dispc;
853 int min_fck_per_pck;
854 int match = 0;
855 unsigned long dss_clk_fck2;
856
857 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_FCK2);
858
859 if (req_pck == dsi.cache_req_pck &&
860 dsi.cache_cinfo.clkin == dss_clk_fck2) {
861 DSSDBG("DSI clock info found from cache\n");
862 *dsi_cinfo = dsi.cache_cinfo;
863 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
864 dispc_cinfo);
865 return 0;
866 }
867
868 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
869
870 if (min_fck_per_pck &&
871 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
872 DSSERR("Requested pixel clock not possible with the current "
873 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
874 "the constraint off.\n");
875 min_fck_per_pck = 0;
876 }
877
878 DSSDBG("dsi_pll_calc\n");
879
880retry:
881 memset(&best, 0, sizeof(best));
882 memset(&best_dispc, 0, sizeof(best_dispc));
883
884 memset(&cur, 0, sizeof(cur));
885 cur.clkin = dss_clk_fck2;
886 cur.use_dss2_fck = 1;
887 cur.highfreq = 0;
888
889 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
890 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
891 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
892 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
893 if (cur.highfreq == 0)
894 cur.fint = cur.clkin / cur.regn;
895 else
896 cur.fint = cur.clkin / (2 * cur.regn);
897
898 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
899 continue;
900
901 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
902 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
903 unsigned long a, b;
904
905 a = 2 * cur.regm * (cur.clkin/1000);
906 b = cur.regn * (cur.highfreq + 1);
907 cur.clkin4ddr = a / b * 1000;
908
909 if (cur.clkin4ddr > 1800 * 1000 * 1000)
910 break;
911
912 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
913 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
914 ++cur.regm3) {
915 struct dispc_clock_info cur_dispc;
916 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
917
918 /* this will narrow down the search a bit,
919 * but still give pixclocks below what was
920 * requested */
921 if (cur.dsi1_pll_fclk < req_pck)
922 break;
923
924 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
925 continue;
926
927 if (min_fck_per_pck &&
928 cur.dsi1_pll_fclk <
929 req_pck * min_fck_per_pck)
930 continue;
931
932 match = 1;
933
934 dispc_find_clk_divs(is_tft, req_pck,
935 cur.dsi1_pll_fclk,
936 &cur_dispc);
937
938 if (abs(cur_dispc.pck - req_pck) <
939 abs(best_dispc.pck - req_pck)) {
940 best = cur;
941 best_dispc = cur_dispc;
942
943 if (cur_dispc.pck == req_pck)
944 goto found;
945 }
946 }
947 }
948 }
949found:
950 if (!match) {
951 if (min_fck_per_pck) {
952 DSSERR("Could not find suitable clock settings.\n"
953 "Turning FCK/PCK constraint off and"
954 "trying again.\n");
955 min_fck_per_pck = 0;
956 goto retry;
957 }
958
959 DSSERR("Could not find suitable clock settings.\n");
960
961 return -EINVAL;
962 }
963
964 /* DSI2_PLL_FCLK (regm4) is not used */
965 best.regm4 = 0;
966 best.dsi2_pll_fclk = 0;
967
968 if (dsi_cinfo)
969 *dsi_cinfo = best;
970 if (dispc_cinfo)
971 *dispc_cinfo = best_dispc;
972
973 dsi.cache_req_pck = req_pck;
974 dsi.cache_clk_freq = 0;
975 dsi.cache_cinfo = best;
976
977 return 0;
978}
979
980int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
981{
982 int r = 0;
983 u32 l;
984 int f;
985
986 DSSDBGF();
987
988 dsi.current_cinfo.fint = cinfo->fint;
989 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
990 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
991 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
992
993 dsi.current_cinfo.regn = cinfo->regn;
994 dsi.current_cinfo.regm = cinfo->regm;
995 dsi.current_cinfo.regm3 = cinfo->regm3;
996 dsi.current_cinfo.regm4 = cinfo->regm4;
997
998 DSSDBG("DSI Fint %ld\n", cinfo->fint);
999
1000 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1001 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1002 cinfo->clkin,
1003 cinfo->highfreq);
1004
1005 /* DSIPHY == CLKIN4DDR */
1006 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1007 cinfo->regm,
1008 cinfo->regn,
1009 cinfo->clkin,
1010 cinfo->highfreq + 1,
1011 cinfo->clkin4ddr);
1012
1013 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1014 cinfo->clkin4ddr / 1000 / 1000 / 2);
1015
1016 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1017
1018 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1019 cinfo->regm3, cinfo->dsi1_pll_fclk);
1020 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1021 cinfo->regm4, cinfo->dsi2_pll_fclk);
1022
1023 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1024
1025 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1026 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1027 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1028 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1029 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1030 22, 19); /* DSI_CLOCK_DIV */
1031 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1032 26, 23); /* DSIPROTO_CLOCK_DIV */
1033 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1034
1035 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1036 if (cinfo->fint < 1000000)
1037 f = 0x3;
1038 else if (cinfo->fint < 1250000)
1039 f = 0x4;
1040 else if (cinfo->fint < 1500000)
1041 f = 0x5;
1042 else if (cinfo->fint < 1750000)
1043 f = 0x6;
1044 else
1045 f = 0x7;
1046
1047 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1048 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1049 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1050 11, 11); /* DSI_PLL_CLKSEL */
1051 l = FLD_MOD(l, cinfo->highfreq,
1052 12, 12); /* DSI_PLL_HIGHFREQ */
1053 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1054 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1055 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1056 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1057
1058 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1059
1060 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1061 DSSERR("dsi pll go bit not going down.\n");
1062 r = -EIO;
1063 goto err;
1064 }
1065
1066 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1067 DSSERR("cannot lock PLL\n");
1068 r = -EIO;
1069 goto err;
1070 }
1071
1072 dsi.pll_locked = 1;
1073
1074 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1075 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1076 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1077 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1078 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1079 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1080 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1081 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1082 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1083 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1084 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1085 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1086 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1087 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1088 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1089 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1090
1091 DSSDBG("PLL config done\n");
1092err:
1093 return r;
1094}
1095
1096int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1097 bool enable_hsdiv)
1098{
1099 int r = 0;
1100 enum dsi_pll_power_state pwstate;
1101
1102 DSSDBG("PLL init\n");
1103
1104 enable_clocks(1);
1105 dsi_enable_pll_clock(1);
1106
1107 r = regulator_enable(dsi.vdds_dsi_reg);
1108 if (r)
1109 goto err0;
1110
1111 /* XXX PLL does not come out of reset without this... */
1112 dispc_pck_free_enable(1);
1113
1114 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1115 DSSERR("PLL not coming out of reset.\n");
1116 r = -ENODEV;
481dfa0e 1117 dispc_pck_free_enable(0);
3de7a1dc
TV		 1118 goto err1;
1119 }
1120
1121 /* XXX ... but if left on, we get problems when planes do not
1122 * fill the whole display. No idea about this */
1123 dispc_pck_free_enable(0);
1124
1125 if (enable_hsclk && enable_hsdiv)
1126 pwstate = DSI_PLL_POWER_ON_ALL;
1127 else if (enable_hsclk)
1128 pwstate = DSI_PLL_POWER_ON_HSCLK;
1129 else if (enable_hsdiv)
1130 pwstate = DSI_PLL_POWER_ON_DIV;
1131 else
1132 pwstate = DSI_PLL_POWER_OFF;
1133
1134 r = dsi_pll_power(pwstate);
1135
1136 if (r)
1137 goto err1;
1138
1139 DSSDBG("PLL init done\n");
1140
1141 return 0;
1142err1:
1143 regulator_disable(dsi.vdds_dsi_reg);
1144err0:
1145 enable_clocks(0);
1146 dsi_enable_pll_clock(0);
1147 return r;
1148}
1149
1150void dsi_pll_uninit(void)
1151{
1152 enable_clocks(0);
1153 dsi_enable_pll_clock(0);
1154
1155 dsi.pll_locked = 0;
1156 dsi_pll_power(DSI_PLL_POWER_OFF);
1157 regulator_disable(dsi.vdds_dsi_reg);
1158 DSSDBG("PLL uninit done\n");
1159}
1160
1161void dsi_dump_clocks(struct seq_file *s)
1162{
1163 int clksel;
1164 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1165
1166 enable_clocks(1);
1167
1168 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1169
1170 seq_printf(s, "- DSI PLL -\n");
1171
1172 seq_printf(s, "dsi pll source = %s\n",
1173 clksel == 0 ?
1174 "dss2_alwon_fclk" : "pclkfree");
1175
1176 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1177
1178 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1179 cinfo->clkin4ddr, cinfo->regm);
1180
1181 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1182 cinfo->dsi1_pll_fclk,
1183 cinfo->regm3,
63cf28ac
TV		 1184 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1185 "off" : "on");
3de7a1dc
TV		 1186
1187 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1188 cinfo->dsi2_pll_fclk,
1189 cinfo->regm4,
63cf28ac
TV		 1190 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1191 "off" : "on");
3de7a1dc
TV		 1192
1193 seq_printf(s, "- DSI -\n");
1194
1195 seq_printf(s, "dsi fclk source = %s\n",
63cf28ac 1196 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
3de7a1dc
TV		 1197 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1198
1199 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1200
1201 seq_printf(s, "DDR_CLK\t\t%lu\n",
1202 cinfo->clkin4ddr / 4);
1203
1204 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1205
1206 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1207
1208 seq_printf(s, "VP_CLK\t\t%lu\n"
1209 "VP_PCLK\t\t%lu\n",
ff1b2cde
SS		 1210 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1211 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
3de7a1dc
TV		 1212
1213 enable_clocks(0);
1214}
1215
dfc0fd8d
TV		 1216#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1217void dsi_dump_irqs(struct seq_file *s)
1218{
1219 unsigned long flags;
1220 struct dsi_irq_stats stats;
1221
1222 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1223
1224 stats = dsi.irq_stats;
1225 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1226 dsi.irq_stats.last_reset = jiffies;
1227
1228 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1229
1230 seq_printf(s, "period %u ms\n",
1231 jiffies_to_msecs(jiffies - stats.last_reset));
1232
1233 seq_printf(s, "irqs %d\n", stats.irq_count);
1234#define PIS(x) \
1235 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1236
1237 seq_printf(s, "-- DSI interrupts --\n");
1238 PIS(VC0);
1239 PIS(VC1);
1240 PIS(VC2);
1241 PIS(VC3);
1242 PIS(WAKEUP);
1243 PIS(RESYNC);
1244 PIS(PLL_LOCK);
1245 PIS(PLL_UNLOCK);
1246 PIS(PLL_RECALL);
1247 PIS(COMPLEXIO_ERR);
1248 PIS(HS_TX_TIMEOUT);
1249 PIS(LP_RX_TIMEOUT);
1250 PIS(TE_TRIGGER);
1251 PIS(ACK_TRIGGER);
1252 PIS(SYNC_LOST);
1253 PIS(LDO_POWER_GOOD);
1254 PIS(TA_TIMEOUT);
1255#undef PIS
1256
1257#define PIS(x) \
1258 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1259 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1260 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1261 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1262 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1263
1264 seq_printf(s, "-- VC interrupts --\n");
1265 PIS(CS);
1266 PIS(ECC_CORR);
1267 PIS(PACKET_SENT);
1268 PIS(FIFO_TX_OVF);
1269 PIS(FIFO_RX_OVF);
1270 PIS(BTA);
1271 PIS(ECC_NO_CORR);
1272 PIS(FIFO_TX_UDF);
1273 PIS(PP_BUSY_CHANGE);
1274#undef PIS
1275
1276#define PIS(x) \
1277 seq_printf(s, "%-20s %10d\n", #x, \
1278 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1279
1280 seq_printf(s, "-- CIO interrupts --\n");
1281 PIS(ERRSYNCESC1);
1282 PIS(ERRSYNCESC2);
1283 PIS(ERRSYNCESC3);
1284 PIS(ERRESC1);
1285 PIS(ERRESC2);
1286 PIS(ERRESC3);
1287 PIS(ERRCONTROL1);
1288 PIS(ERRCONTROL2);
1289 PIS(ERRCONTROL3);
1290 PIS(STATEULPS1);
1291 PIS(STATEULPS2);
1292 PIS(STATEULPS3);
1293 PIS(ERRCONTENTIONLP0_1);
1294 PIS(ERRCONTENTIONLP1_1);
1295 PIS(ERRCONTENTIONLP0_2);
1296 PIS(ERRCONTENTIONLP1_2);
1297 PIS(ERRCONTENTIONLP0_3);
1298 PIS(ERRCONTENTIONLP1_3);
1299 PIS(ULPSACTIVENOT_ALL0);
1300 PIS(ULPSACTIVENOT_ALL1);
1301#undef PIS
1302}
1303#endif
1304
3de7a1dc
TV		 1305void dsi_dump_regs(struct seq_file *s)
1306{
1307#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1308
1309 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
1310
1311 DUMPREG(DSI_REVISION);
1312 DUMPREG(DSI_SYSCONFIG);
1313 DUMPREG(DSI_SYSSTATUS);
1314 DUMPREG(DSI_IRQSTATUS);
1315 DUMPREG(DSI_IRQENABLE);
1316 DUMPREG(DSI_CTRL);
1317 DUMPREG(DSI_COMPLEXIO_CFG1);
1318 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1319 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1320 DUMPREG(DSI_CLK_CTRL);
1321 DUMPREG(DSI_TIMING1);
1322 DUMPREG(DSI_TIMING2);
1323 DUMPREG(DSI_VM_TIMING1);
1324 DUMPREG(DSI_VM_TIMING2);
1325 DUMPREG(DSI_VM_TIMING3);
1326 DUMPREG(DSI_CLK_TIMING);
1327 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1328 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1329 DUMPREG(DSI_COMPLEXIO_CFG2);
1330 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1331 DUMPREG(DSI_VM_TIMING4);
1332 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1333 DUMPREG(DSI_VM_TIMING5);
1334 DUMPREG(DSI_VM_TIMING6);
1335 DUMPREG(DSI_VM_TIMING7);
1336 DUMPREG(DSI_STOPCLK_TIMING);
1337
1338 DUMPREG(DSI_VC_CTRL(0));
1339 DUMPREG(DSI_VC_TE(0));
1340 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1341 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1342 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1343 DUMPREG(DSI_VC_IRQSTATUS(0));
1344 DUMPREG(DSI_VC_IRQENABLE(0));
1345
1346 DUMPREG(DSI_VC_CTRL(1));
1347 DUMPREG(DSI_VC_TE(1));
1348 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1349 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1350 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1351 DUMPREG(DSI_VC_IRQSTATUS(1));
1352 DUMPREG(DSI_VC_IRQENABLE(1));
1353
1354 DUMPREG(DSI_VC_CTRL(2));
1355 DUMPREG(DSI_VC_TE(2));
1356 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1357 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1358 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1359 DUMPREG(DSI_VC_IRQSTATUS(2));
1360 DUMPREG(DSI_VC_IRQENABLE(2));
1361
1362 DUMPREG(DSI_VC_CTRL(3));
1363 DUMPREG(DSI_VC_TE(3));
1364 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1365 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1366 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1367 DUMPREG(DSI_VC_IRQSTATUS(3));
1368 DUMPREG(DSI_VC_IRQENABLE(3));
1369
1370 DUMPREG(DSI_DSIPHY_CFG0);
1371 DUMPREG(DSI_DSIPHY_CFG1);
1372 DUMPREG(DSI_DSIPHY_CFG2);
1373 DUMPREG(DSI_DSIPHY_CFG5);
1374
1375 DUMPREG(DSI_PLL_CONTROL);
1376 DUMPREG(DSI_PLL_STATUS);
1377 DUMPREG(DSI_PLL_GO);
1378 DUMPREG(DSI_PLL_CONFIGURATION1);
1379 DUMPREG(DSI_PLL_CONFIGURATION2);
1380
1381 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
1382#undef DUMPREG
1383}
1384
1385enum dsi_complexio_power_state {
1386 DSI_COMPLEXIO_POWER_OFF = 0x0,
1387 DSI_COMPLEXIO_POWER_ON = 0x1,
1388 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1389};
1390
1391static int dsi_complexio_power(enum dsi_complexio_power_state state)
1392{
1393 int t = 0;
1394
1395 /* PWR_CMD */
1396 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1397
1398 /* PWR_STATUS */
1399 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
24be78b3 1400 if (++t > 1000) {
3de7a1dc
TV		 1401 DSSERR("failed to set complexio power state to "
1402 "%d\n", state);
1403 return -ENODEV;
1404 }
24be78b3 1405 udelay(1);
3de7a1dc
TV		 1406 }
1407
1408 return 0;
1409}
1410
1411static void dsi_complexio_config(struct omap_dss_device *dssdev)
1412{
1413 u32 r;
1414
1415 int clk_lane = dssdev->phy.dsi.clk_lane;
1416 int data1_lane = dssdev->phy.dsi.data1_lane;
1417 int data2_lane = dssdev->phy.dsi.data2_lane;
1418 int clk_pol = dssdev->phy.dsi.clk_pol;
1419 int data1_pol = dssdev->phy.dsi.data1_pol;
1420 int data2_pol = dssdev->phy.dsi.data2_pol;
1421
1422 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1423 r = FLD_MOD(r, clk_lane, 2, 0);
1424 r = FLD_MOD(r, clk_pol, 3, 3);
1425 r = FLD_MOD(r, data1_lane, 6, 4);
1426 r = FLD_MOD(r, data1_pol, 7, 7);
1427 r = FLD_MOD(r, data2_lane, 10, 8);
1428 r = FLD_MOD(r, data2_pol, 11, 11);
1429 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1430
1431 /* The configuration of the DSI complex I/O (number of data lanes,
1432 position, differential order) should not be changed while
1433 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1434 the hardware to take into account a new configuration of the complex
1435 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1436 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1437 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1438 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1439 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1440 DSI complex I/O configuration is unknown. */
1441
1442 /*
1443 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1444 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1445 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1446 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1447 */
1448}
1449
1450static inline unsigned ns2ddr(unsigned ns)
1451{
1452 /* convert time in ns to ddr ticks, rounding up */
1453 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1454 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1455}
1456
1457static inline unsigned ddr2ns(unsigned ddr)
1458{
1459 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1460 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1461}
1462
1463static void dsi_complexio_timings(void)
1464{
1465 u32 r;
1466 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1467 u32 tlpx_half, tclk_trail, tclk_zero;
1468 u32 tclk_prepare;
1469
1470 /* calculate timings */
1471
1472 /* 1 * DDR_CLK = 2 * UI */
1473
1474 /* min 40ns + 4*UI max 85ns + 6*UI */
1475 ths_prepare = ns2ddr(70) + 2;
1476
1477 /* min 145ns + 10*UI */
1478 ths_prepare_ths_zero = ns2ddr(175) + 2;
1479
1480 /* min max(8*UI, 60ns+4*UI) */
1481 ths_trail = ns2ddr(60) + 5;
1482
1483 /* min 100ns */
1484 ths_exit = ns2ddr(145);
1485
1486 /* tlpx min 50n */
1487 tlpx_half = ns2ddr(25);
1488
1489 /* min 60ns */
1490 tclk_trail = ns2ddr(60) + 2;
1491
1492 /* min 38ns, max 95ns */
1493 tclk_prepare = ns2ddr(65);
1494
1495 /* min tclk-prepare + tclk-zero = 300ns */
1496 tclk_zero = ns2ddr(260);
1497
1498 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1499 ths_prepare, ddr2ns(ths_prepare),
1500 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1501 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1502 ths_trail, ddr2ns(ths_trail),
1503 ths_exit, ddr2ns(ths_exit));
1504
1505 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1506 "tclk_zero %u (%uns)\n",
1507 tlpx_half, ddr2ns(tlpx_half),
1508 tclk_trail, ddr2ns(tclk_trail),
1509 tclk_zero, ddr2ns(tclk_zero));
1510 DSSDBG("tclk_prepare %u (%uns)\n",
1511 tclk_prepare, ddr2ns(tclk_prepare));
1512
1513 /* program timings */
1514
1515 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1516 r = FLD_MOD(r, ths_prepare, 31, 24);
1517 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1518 r = FLD_MOD(r, ths_trail, 15, 8);
1519 r = FLD_MOD(r, ths_exit, 7, 0);
1520 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1521
1522 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1523 r = FLD_MOD(r, tlpx_half, 22, 16);
1524 r = FLD_MOD(r, tclk_trail, 15, 8);
1525 r = FLD_MOD(r, tclk_zero, 7, 0);
1526 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1527
1528 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1529 r = FLD_MOD(r, tclk_prepare, 7, 0);
1530 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1531}
1532
1533
1534static int dsi_complexio_init(struct omap_dss_device *dssdev)
1535{
1536 int r = 0;
1537
1538 DSSDBG("dsi_complexio_init\n");
1539
1540 /* CIO_CLK_ICG, enable L3 clk to CIO */
1541 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1542
1543 /* A dummy read using the SCP interface to any DSIPHY register is
1544 * required after DSIPHY reset to complete the reset of the DSI complex
1545 * I/O. */
1546 dsi_read_reg(DSI_DSIPHY_CFG5);
1547
1548 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1549 DSSERR("ComplexIO PHY not coming out of reset.\n");
1550 r = -ENODEV;
1551 goto err;
1552 }
1553
1554 dsi_complexio_config(dssdev);
1555
1556 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1557
1558 if (r)
1559 goto err;
1560
1561 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1562 DSSERR("ComplexIO not coming out of reset.\n");
1563 r = -ENODEV;
1564 goto err;
1565 }
1566
1567 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1568 DSSERR("ComplexIO LDO power down.\n");
1569 r = -ENODEV;
1570 goto err;
1571 }
1572
1573 dsi_complexio_timings();
1574
1575 /*
1576 The configuration of the DSI complex I/O (number of data lanes,
1577 position, differential order) should not be changed while
1578 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1579 hardware to recognize a new configuration of the complex I/O (done
1580 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1581 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1582 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1583 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1584 bit to 1. If the sequence is not followed, the DSi complex I/O
1585 configuration is undetermined.
1586 */
1587 dsi_if_enable(1);
1588 dsi_if_enable(0);
1589 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1590 dsi_if_enable(1);
1591 dsi_if_enable(0);
1592
1593 DSSDBG("CIO init done\n");
1594err:
1595 return r;
1596}
1597
1598static void dsi_complexio_uninit(void)
1599{
1600 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1601}
1602
1603static int _dsi_wait_reset(void)
1604{
24be78b3 1605 int t = 0;
3de7a1dc
TV		 1606
1607 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
24be78b3 1608 if (++t > 5) {
3de7a1dc
TV		 1609 DSSERR("soft reset failed\n");
1610 return -ENODEV;
1611 }
1612 udelay(1);
1613 }
1614
1615 return 0;
1616}
1617
1618static int _dsi_reset(void)
1619{
1620 /* Soft reset */
1621 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1622 return _dsi_wait_reset();
1623}
1624
1625static void dsi_reset_tx_fifo(int channel)
1626{
1627 u32 mask;
1628 u32 l;
1629
1630 /* set fifosize of the channel to 0, then return the old size */
1631 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1632
1633 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1634 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1635
1636 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1637}
1638
1639static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1640 enum fifo_size size3, enum fifo_size size4)
1641{
1642 u32 r = 0;
1643 int add = 0;
1644 int i;
1645
1646 dsi.vc[0].fifo_size = size1;
1647 dsi.vc[1].fifo_size = size2;
1648 dsi.vc[2].fifo_size = size3;
1649 dsi.vc[3].fifo_size = size4;
1650
1651 for (i = 0; i < 4; i++) {
1652 u8 v;
1653 int size = dsi.vc[i].fifo_size;
1654
1655 if (add + size > 4) {
1656 DSSERR("Illegal FIFO configuration\n");
1657 BUG();
1658 }
1659
1660 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1661 r |= v << (8 * i);
1662 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1663 add += size;
1664 }
1665
1666 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1667}
1668
1669static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1670 enum fifo_size size3, enum fifo_size size4)
1671{
1672 u32 r = 0;
1673 int add = 0;
1674 int i;
1675
1676 dsi.vc[0].fifo_size = size1;
1677 dsi.vc[1].fifo_size = size2;
1678 dsi.vc[2].fifo_size = size3;
1679 dsi.vc[3].fifo_size = size4;
1680
1681 for (i = 0; i < 4; i++) {
1682 u8 v;
1683 int size = dsi.vc[i].fifo_size;
1684
1685 if (add + size > 4) {
1686 DSSERR("Illegal FIFO configuration\n");
1687 BUG();
1688 }
1689
1690 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1691 r |= v << (8 * i);
1692 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1693 add += size;
1694 }
1695
1696 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1697}
1698
1699static int dsi_force_tx_stop_mode_io(void)
1700{
1701 u32 r;
1702
1703 r = dsi_read_reg(DSI_TIMING1);
1704 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1705 dsi_write_reg(DSI_TIMING1, r);
1706
1707 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1708 DSSERR("TX_STOP bit not going down\n");
1709 return -EIO;
1710 }
1711
1712 return 0;
1713}
1714
3de7a1dc
TV		 1715static int dsi_vc_enable(int channel, bool enable)
1716{
446f7bff
TV		 1717 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1718 channel, enable);
3de7a1dc
TV		 1719
1720 enable = enable ? 1 : 0;
1721
1722 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1723
1724 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1725 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1726 return -EIO;
1727 }
1728
1729 return 0;
1730}
1731
1732static void dsi_vc_initial_config(int channel)
1733{
1734 u32 r;
1735
1736 DSSDBGF("%d", channel);
1737
1738 r = dsi_read_reg(DSI_VC_CTRL(channel));
1739
1740 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1741 DSSERR("VC(%d) busy when trying to configure it!\n",
1742 channel);
1743
1744 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1745 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1746 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1747 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1748 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1749 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1750 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1751
1752 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1753 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1754
1755 dsi_write_reg(DSI_VC_CTRL(channel), r);
1756
1757 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1758}
1759
9ecd9684 1760static int dsi_vc_config_l4(int channel)
3de7a1dc
TV		 1761{
1762 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
9ecd9684 1763 return 0;
3de7a1dc
TV		 1764
1765 DSSDBGF("%d", channel);
1766
1767 dsi_vc_enable(channel, 0);
1768
9ecd9684
TV		 1769 /* VC_BUSY */
1770 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1771 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
9ecd9684
TV		 1772 return -EIO;
1773 }
3de7a1dc
TV		 1774
1775 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1776
1777 dsi_vc_enable(channel, 1);
1778
1779 dsi.vc[channel].mode = DSI_VC_MODE_L4;
9ecd9684
TV		 1780
1781 return 0;
3de7a1dc
TV		 1782}
1783
9ecd9684 1784static int dsi_vc_config_vp(int channel)
3de7a1dc
TV		 1785{
1786 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
9ecd9684 1787 return 0;
3de7a1dc
TV		 1788
1789 DSSDBGF("%d", channel);
1790
1791 dsi_vc_enable(channel, 0);
1792
9ecd9684
TV		 1793 /* VC_BUSY */
1794 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1795 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
9ecd9684
TV		 1796 return -EIO;
1797 }
3de7a1dc
TV		 1798
1799 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1800
1801 dsi_vc_enable(channel, 1);
1802
1803 dsi.vc[channel].mode = DSI_VC_MODE_VP;
9ecd9684
TV		 1804
1805 return 0;
3de7a1dc
TV		 1806}
1807
1808
61140c9a 1809void omapdss_dsi_vc_enable_hs(int channel, bool enable)
3de7a1dc
TV		 1810{
1811 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1812
61140c9a
TV		 1813 WARN_ON(!dsi_bus_is_locked());
1814
3de7a1dc
TV		 1815 dsi_vc_enable(channel, 0);
1816 dsi_if_enable(0);
1817
1818 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1819
1820 dsi_vc_enable(channel, 1);
1821 dsi_if_enable(1);
1822
1823 dsi_force_tx_stop_mode_io();
1824}
61140c9a 1825EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
3de7a1dc
TV		 1826
1827static void dsi_vc_flush_long_data(int channel)
1828{
1829 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1830 u32 val;
1831 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1832 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1833 (val >> 0) & 0xff,
1834 (val >> 8) & 0xff,
1835 (val >> 16) & 0xff,
1836 (val >> 24) & 0xff);
1837 }
1838}
1839
1840static void dsi_show_rx_ack_with_err(u16 err)
1841{
1842 DSSERR("\tACK with ERROR (%#x):\n", err);
1843 if (err & (1 << 0))
1844 DSSERR("\t\tSoT Error\n");
1845 if (err & (1 << 1))
1846 DSSERR("\t\tSoT Sync Error\n");
1847 if (err & (1 << 2))
1848 DSSERR("\t\tEoT Sync Error\n");
1849 if (err & (1 << 3))
1850 DSSERR("\t\tEscape Mode Entry Command Error\n");
1851 if (err & (1 << 4))
1852 DSSERR("\t\tLP Transmit Sync Error\n");
1853 if (err & (1 << 5))
1854 DSSERR("\t\tHS Receive Timeout Error\n");
1855 if (err & (1 << 6))
1856 DSSERR("\t\tFalse Control Error\n");
1857 if (err & (1 << 7))
1858 DSSERR("\t\t(reserved7)\n");
1859 if (err & (1 << 8))
1860 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1861 if (err & (1 << 9))
1862 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1863 if (err & (1 << 10))
1864 DSSERR("\t\tChecksum Error\n");
1865 if (err & (1 << 11))
1866 DSSERR("\t\tData type not recognized\n");
1867 if (err & (1 << 12))
1868 DSSERR("\t\tInvalid VC ID\n");
1869 if (err & (1 << 13))
1870 DSSERR("\t\tInvalid Transmission Length\n");
1871 if (err & (1 << 14))
1872 DSSERR("\t\t(reserved14)\n");
1873 if (err & (1 << 15))
1874 DSSERR("\t\tDSI Protocol Violation\n");
1875}
1876
1877static u16 dsi_vc_flush_receive_data(int channel)
1878{
1879 /* RX_FIFO_NOT_EMPTY */
1880 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1881 u32 val;
1882 u8 dt;
1883 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
86a7867e 1884 DSSERR("\trawval %#08x\n", val);
3de7a1dc
TV		 1885 dt = FLD_GET(val, 5, 0);
1886 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1887 u16 err = FLD_GET(val, 23, 8);
1888 dsi_show_rx_ack_with_err(err);
1889 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
86a7867e 1890 DSSERR("\tDCS short response, 1 byte: %#x\n",
3de7a1dc
TV		 1891 FLD_GET(val, 23, 8));
1892 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
86a7867e 1893 DSSERR("\tDCS short response, 2 byte: %#x\n",
3de7a1dc
TV		 1894 FLD_GET(val, 23, 8));
1895 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
86a7867e 1896 DSSERR("\tDCS long response, len %d\n",
3de7a1dc
TV		 1897 FLD_GET(val, 23, 8));
1898 dsi_vc_flush_long_data(channel);
1899 } else {
1900 DSSERR("\tunknown datatype 0x%02x\n", dt);
1901 }
1902 }
1903 return 0;
1904}
1905
1906static int dsi_vc_send_bta(int channel)
1907{
446f7bff 1908 if (dsi.debug_write || dsi.debug_read)
3de7a1dc
TV		 1909 DSSDBG("dsi_vc_send_bta %d\n", channel);
1910
4f765023 1911 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 1912
1913 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1914 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1915 dsi_vc_flush_receive_data(channel);
1916 }
1917
1918 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1919
1920 return 0;
1921}
1922
1923int dsi_vc_send_bta_sync(int channel)
1924{
1925 int r = 0;
1926 u32 err;
1927
1928 INIT_COMPLETION(dsi.bta_completion);
1929
1930 dsi_vc_enable_bta_irq(channel);
1931
1932 r = dsi_vc_send_bta(channel);
1933 if (r)
1934 goto err;
1935
1936 if (wait_for_completion_timeout(&dsi.bta_completion,
1937 msecs_to_jiffies(500)) == 0) {
1938 DSSERR("Failed to receive BTA\n");
1939 r = -EIO;
1940 goto err;
1941 }
1942
1943 err = dsi_get_errors();
1944 if (err) {
1945 DSSERR("Error while sending BTA: %x\n", err);
1946 r = -EIO;
1947 goto err;
1948 }
1949err:
1950 dsi_vc_disable_bta_irq(channel);
1951
1952 return r;
1953}
1954EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1955
1956static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1957 u16 len, u8 ecc)
1958{
1959 u32 val;
1960 u8 data_id;
1961
4f765023 1962 WARN_ON(!dsi_bus_is_locked());
3de7a1dc 1963
dd8079d6 1964 data_id = data_type | channel << 6;
3de7a1dc
TV		 1965
1966 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1967 FLD_VAL(ecc, 31, 24);
1968
1969 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1970}
1971
1972static inline void dsi_vc_write_long_payload(int channel,
1973 u8 b1, u8 b2, u8 b3, u8 b4)
1974{
1975 u32 val;
1976
1977 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1978
1979/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1980 b1, b2, b3, b4, val); */
1981
1982 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1983}
1984
1985static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1986 u8 ecc)
1987{
1988 /*u32 val; */
1989 int i;
1990 u8 *p;
1991 int r = 0;
1992 u8 b1, b2, b3, b4;
1993
1994 if (dsi.debug_write)
1995 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1996
1997 /* len + header */
1998 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1999 DSSERR("unable to send long packet: packet too long.\n");
2000 return -EINVAL;
2001 }
2002
2003 dsi_vc_config_l4(channel);
2004
2005 dsi_vc_write_long_header(channel, data_type, len, ecc);
2006
3de7a1dc
TV		 2007 p = data;
2008 for (i = 0; i < len >> 2; i++) {
2009 if (dsi.debug_write)
2010 DSSDBG("\tsending full packet %d\n", i);
3de7a1dc
TV		 2011
2012 b1 = *p++;
2013 b2 = *p++;
2014 b3 = *p++;
2015 b4 = *p++;
2016
2017 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2018 }
2019
2020 i = len % 4;
2021 if (i) {
2022 b1 = 0; b2 = 0; b3 = 0;
2023
2024 if (dsi.debug_write)
2025 DSSDBG("\tsending remainder bytes %d\n", i);
2026
2027 switch (i) {
2028 case 3:
2029 b1 = *p++;
2030 b2 = *p++;
2031 b3 = *p++;
2032 break;
2033 case 2:
2034 b1 = *p++;
2035 b2 = *p++;
2036 break;
2037 case 1:
2038 b1 = *p++;
2039 break;
2040 }
2041
2042 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2043 }
2044
2045 return r;
2046}
2047
2048static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2049{
2050 u32 r;
2051 u8 data_id;
2052
4f765023 2053 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 2054
2055 if (dsi.debug_write)
2056 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2057 channel,
2058 data_type, data & 0xff, (data >> 8) & 0xff);
2059
2060 dsi_vc_config_l4(channel);
2061
2062 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2063 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2064 return -EINVAL;
2065 }
2066
dd8079d6 2067 data_id = data_type | channel << 6;
3de7a1dc
TV		 2068
2069 r = (data_id << 0) | (data << 8) | (ecc << 24);
2070
2071 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2072
2073 return 0;
2074}
2075
2076int dsi_vc_send_null(int channel)
2077{
2078 u8 nullpkg[] = {0, 0, 0, 0};
397bb3c2 2079 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
3de7a1dc
TV		 2080}
2081EXPORT_SYMBOL(dsi_vc_send_null);
2082
2083int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2084{
2085 int r;
2086
2087 BUG_ON(len == 0);
2088
2089 if (len == 1) {
2090 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2091 data[0], 0);
2092 } else if (len == 2) {
2093 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2094 data[0] | (data[1] << 8), 0);
2095 } else {
2096 /* 0x39 = DCS Long Write */
2097 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2098 data, len, 0);
2099 }
2100
2101 return r;
2102}
2103EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2104
2105int dsi_vc_dcs_write(int channel, u8 *data, int len)
2106{
2107 int r;
2108
2109 r = dsi_vc_dcs_write_nosync(channel, data, len);
2110 if (r)
5d68e032 2111 goto err;
3de7a1dc
TV		 2112
2113 r = dsi_vc_send_bta_sync(channel);
5d68e032
TV		 2114 if (r)
2115 goto err;
3de7a1dc 2116
b63ac1e3
TV		 2117 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2118 DSSERR("rx fifo not empty after write, dumping data:\n");
2119 dsi_vc_flush_receive_data(channel);
2120 r = -EIO;
2121 goto err;
2122 }
2123
5d68e032
TV		 2124 return 0;
2125err:
2126 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2127 channel, data[0], len);
3de7a1dc
TV		 2128 return r;
2129}
2130EXPORT_SYMBOL(dsi_vc_dcs_write);
2131
828c48f8
TV		 2132int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2133{
2134 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2135}
2136EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2137
2138int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2139{
2140 u8 buf[2];
2141 buf[0] = dcs_cmd;
2142 buf[1] = param;
2143 return dsi_vc_dcs_write(channel, buf, 2);
2144}
2145EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2146
3de7a1dc
TV		 2147int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2148{
2149 u32 val;
2150 u8 dt;
2151 int r;
2152
2153 if (dsi.debug_read)
ff90a348 2154 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3de7a1dc
TV		 2155
2156 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2157 if (r)
5d68e032 2158 goto err;
3de7a1dc
TV		 2159
2160 r = dsi_vc_send_bta_sync(channel);
2161 if (r)
5d68e032 2162 goto err;
3de7a1dc
TV		 2163
2164 /* RX_FIFO_NOT_EMPTY */
2165 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2166 DSSERR("RX fifo empty when trying to read.\n");
5d68e032
TV		 2167 r = -EIO;
2168 goto err;
3de7a1dc
TV		 2169 }
2170
2171 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2172 if (dsi.debug_read)
2173 DSSDBG("\theader: %08x\n", val);
2174 dt = FLD_GET(val, 5, 0);
2175 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2176 u16 err = FLD_GET(val, 23, 8);
2177 dsi_show_rx_ack_with_err(err);
5d68e032
TV		 2178 r = -EIO;
2179 goto err;
3de7a1dc
TV		 2180
2181 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2182 u8 data = FLD_GET(val, 15, 8);
2183 if (dsi.debug_read)
2184 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2185
5d68e032
TV		 2186 if (buflen < 1) {
2187 r = -EIO;
2188 goto err;
2189 }
3de7a1dc
TV		 2190
2191 buf[0] = data;
2192
2193 return 1;
2194 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2195 u16 data = FLD_GET(val, 23, 8);
2196 if (dsi.debug_read)
2197 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2198
5d68e032
TV		 2199 if (buflen < 2) {
2200 r = -EIO;
2201 goto err;
2202 }
3de7a1dc
TV		 2203
2204 buf[0] = data & 0xff;
2205 buf[1] = (data >> 8) & 0xff;
2206
2207 return 2;
2208 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2209 int w;
2210 int len = FLD_GET(val, 23, 8);
2211 if (dsi.debug_read)
2212 DSSDBG("\tDCS long response, len %d\n", len);
2213
5d68e032
TV		 2214 if (len > buflen) {
2215 r = -EIO;
2216 goto err;
2217 }
3de7a1dc
TV		 2218
2219 /* two byte checksum ends the packet, not included in len */
2220 for (w = 0; w < len + 2;) {
2221 int b;
2222 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2223 if (dsi.debug_read)
2224 DSSDBG("\t\t%02x %02x %02x %02x\n",
2225 (val >> 0) & 0xff,
2226 (val >> 8) & 0xff,
2227 (val >> 16) & 0xff,
2228 (val >> 24) & 0xff);
2229
2230 for (b = 0; b < 4; ++b) {
2231 if (w < len)
2232 buf[w] = (val >> (b * 8)) & 0xff;
2233 /* we discard the 2 byte checksum */
2234 ++w;
2235 }
2236 }
2237
2238 return len;
3de7a1dc
TV		 2239 } else {
2240 DSSERR("\tunknown datatype 0x%02x\n", dt);
5d68e032
TV		 2241 r = -EIO;
2242 goto err;
3de7a1dc 2243 }
5d68e032
TV		 2244
2245 BUG();
2246err:
2247 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2248 channel, dcs_cmd);
2249 return r;
2250
3de7a1dc
TV		 2251}
2252EXPORT_SYMBOL(dsi_vc_dcs_read);
2253
828c48f8
TV		 2254int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2255{
2256 int r;
2257
2258 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2259
2260 if (r < 0)
2261 return r;
2262
2263 if (r != 1)
2264 return -EIO;
2265
2266 return 0;
2267}
2268EXPORT_SYMBOL(dsi_vc_dcs_read_1);
3de7a1dc 2269
0c244f77 2270int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
53055aae 2271{
0c244f77 2272 u8 buf[2];
53055aae
TV		 2273 int r;
2274
0c244f77 2275 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
53055aae
TV		 2276
2277 if (r < 0)
2278 return r;
2279
2280 if (r != 2)
2281 return -EIO;
2282
0c244f77
TV		 2283 *data1 = buf[0];
2284 *data2 = buf[1];
2285
53055aae
TV		 2286 return 0;
2287}
2288EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2289
3de7a1dc
TV		 2290int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2291{
fa15c79b 2292 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
3de7a1dc 2293 len, 0);
3de7a1dc
TV		 2294}
2295EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2296
4ffa3571 2297static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2298{
3de7a1dc 2299 unsigned long fck;
4ffa3571
TV		 2300 unsigned long total_ticks;
2301 u32 r;
3de7a1dc 2302
4ffa3571 2303 BUG_ON(ticks > 0x1fff);
3de7a1dc 2304
4ffa3571 2305 /* ticks in DSI_FCK */
3de7a1dc 2306 fck = dsi_fclk_rate();
3de7a1dc
TV		 2307
2308 r = dsi_read_reg(DSI_TIMING2);
2309 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
4ffa3571
TV		 2310 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2311 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3de7a1dc
TV		 2312 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2313 dsi_write_reg(DSI_TIMING2, r);
2314
4ffa3571
TV		 2315 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2316
2317 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2318 total_ticks,
2319 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2320 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2321}
2322
4ffa3571 2323static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
3de7a1dc 2324{
3de7a1dc 2325 unsigned long fck;
4ffa3571
TV		 2326 unsigned long total_ticks;
2327 u32 r;
2328
2329 BUG_ON(ticks > 0x1fff);
3de7a1dc
TV		 2330
2331 /* ticks in DSI_FCK */
2332 fck = dsi_fclk_rate();
3de7a1dc
TV		 2333
2334 r = dsi_read_reg(DSI_TIMING1);
2335 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
4ffa3571
TV		 2336 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2337 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3de7a1dc
TV		 2338 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2339 dsi_write_reg(DSI_TIMING1, r);
2340
4ffa3571
TV		 2341 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2342
2343 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2344 total_ticks,
2345 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2346 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2347}
2348
4ffa3571 2349static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
3de7a1dc 2350{
3de7a1dc 2351 unsigned long fck;
4ffa3571
TV		 2352 unsigned long total_ticks;
2353 u32 r;
3de7a1dc 2354
4ffa3571 2355 BUG_ON(ticks > 0x1fff);
3de7a1dc 2356
4ffa3571 2357 /* ticks in DSI_FCK */
3de7a1dc 2358 fck = dsi_fclk_rate();
3de7a1dc
TV		 2359
2360 r = dsi_read_reg(DSI_TIMING1);
2361 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
4ffa3571
TV		 2362 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2363 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3de7a1dc
TV		 2364 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2365 dsi_write_reg(DSI_TIMING1, r);
2366
4ffa3571
TV		 2367 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2368
2369 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2370 total_ticks,
2371 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2372 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2373}
2374
4ffa3571 2375static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2376{
3de7a1dc 2377 unsigned long fck;
4ffa3571
TV		 2378 unsigned long total_ticks;
2379 u32 r;
3de7a1dc 2380
4ffa3571 2381 BUG_ON(ticks > 0x1fff);
3de7a1dc 2382
4ffa3571 2383 /* ticks in TxByteClkHS */
3de7a1dc 2384 fck = dsi_get_txbyteclkhs();
3de7a1dc
TV		 2385
2386 r = dsi_read_reg(DSI_TIMING2);
2387 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
4ffa3571
TV		 2388 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2389 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3de7a1dc
TV		 2390 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2391 dsi_write_reg(DSI_TIMING2, r);
2392
4ffa3571
TV		 2393 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2394
2395 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2396 total_ticks,
2397 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2398 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2399}
2400static int dsi_proto_config(struct omap_dss_device *dssdev)
2401{
2402 u32 r;
2403 int buswidth = 0;
2404
dd8079d6
TV		 2405 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2406 DSI_FIFO_SIZE_32,
2407 DSI_FIFO_SIZE_32,
2408 DSI_FIFO_SIZE_32);
3de7a1dc 2409
dd8079d6
TV		 2410 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2411 DSI_FIFO_SIZE_32,
2412 DSI_FIFO_SIZE_32,
2413 DSI_FIFO_SIZE_32);
3de7a1dc
TV		 2414
2415 /* XXX what values for the timeouts? */
4ffa3571
TV		 2416 dsi_set_stop_state_counter(0x1000, false, false);
2417 dsi_set_ta_timeout(0x1fff, true, true);
2418 dsi_set_lp_rx_timeout(0x1fff, true, true);
2419 dsi_set_hs_tx_timeout(0x1fff, true, true);
3de7a1dc
TV		 2420
2421 switch (dssdev->ctrl.pixel_size) {
2422 case 16:
2423 buswidth = 0;
2424 break;
2425 case 18:
2426 buswidth = 1;
2427 break;
2428 case 24:
2429 buswidth = 2;
2430 break;
2431 default:
2432 BUG();
2433 }
2434
2435 r = dsi_read_reg(DSI_CTRL);
2436 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2437 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2438 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2439 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2440 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2441 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2442 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2443 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2444 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2445 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2446 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2447
2448 dsi_write_reg(DSI_CTRL, r);
2449
2450 dsi_vc_initial_config(0);
dd8079d6
TV		 2451 dsi_vc_initial_config(1);
2452 dsi_vc_initial_config(2);
2453 dsi_vc_initial_config(3);
3de7a1dc
TV		 2454
2455 return 0;
2456}
2457
2458static void dsi_proto_timings(struct omap_dss_device *dssdev)
2459{
2460 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2461 unsigned tclk_pre, tclk_post;
2462 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2463 unsigned ths_trail, ths_exit;
2464 unsigned ddr_clk_pre, ddr_clk_post;
2465 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2466 unsigned ths_eot;
2467 u32 r;
2468
2469 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2470 ths_prepare = FLD_GET(r, 31, 24);
2471 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2472 ths_zero = ths_prepare_ths_zero - ths_prepare;
2473 ths_trail = FLD_GET(r, 15, 8);
2474 ths_exit = FLD_GET(r, 7, 0);
2475
2476 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2477 tlpx = FLD_GET(r, 22, 16) * 2;
2478 tclk_trail = FLD_GET(r, 15, 8);
2479 tclk_zero = FLD_GET(r, 7, 0);
2480
2481 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2482 tclk_prepare = FLD_GET(r, 7, 0);
2483
2484 /* min 8*UI */
2485 tclk_pre = 20;
2486 /* min 60ns + 52*UI */
2487 tclk_post = ns2ddr(60) + 26;
2488
2489 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2490 if (dssdev->phy.dsi.data1_lane != 0 &&
2491 dssdev->phy.dsi.data2_lane != 0)
2492 ths_eot = 2;
2493 else
2494 ths_eot = 4;
2495
2496 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2497 4);
2498 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2499
2500 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2501 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2502
2503 r = dsi_read_reg(DSI_CLK_TIMING);
2504 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2505 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2506 dsi_write_reg(DSI_CLK_TIMING, r);
2507
2508 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2509 ddr_clk_pre,
2510 ddr_clk_post);
2511
2512 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2513 DIV_ROUND_UP(ths_prepare, 4) +
2514 DIV_ROUND_UP(ths_zero + 3, 4);
2515
2516 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2517
2518 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2519 FLD_VAL(exit_hs_mode_lat, 15, 0);
2520 dsi_write_reg(DSI_VM_TIMING7, r);
2521
2522 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2523 enter_hs_mode_lat, exit_hs_mode_lat);
2524}
2525
2526
2527#define DSI_DECL_VARS \
2528 int __dsi_cb = 0; u32 __dsi_cv = 0;
2529
2530#define DSI_FLUSH(ch) \
2531 if (__dsi_cb > 0) { \
2532 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2533 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2534 __dsi_cb = __dsi_cv = 0; \
2535 }
2536
2537#define DSI_PUSH(ch, data) \
2538 do { \
2539 __dsi_cv |= (data) << (__dsi_cb * 8); \
2540 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2541 if (++__dsi_cb > 3) \
2542 DSI_FLUSH(ch); \
2543 } while (0)
2544
2545static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2546 int x, int y, int w, int h)
2547{
2548 /* Note: supports only 24bit colors in 32bit container */
2549 int first = 1;
2550 int fifo_stalls = 0;
2551 int max_dsi_packet_size;
2552 int max_data_per_packet;
2553 int max_pixels_per_packet;
2554 int pixels_left;
2555 int bytespp = dssdev->ctrl.pixel_size / 8;
2556 int scr_width;
2557 u32 __iomem *data;
2558 int start_offset;
2559 int horiz_inc;
2560 int current_x;
2561 struct omap_overlay *ovl;
2562
2563 debug_irq = 0;
2564
2565 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2566 x, y, w, h);
2567
2568 ovl = dssdev->manager->overlays[0];
2569
2570 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2571 return -EINVAL;
2572
2573 if (dssdev->ctrl.pixel_size != 24)
2574 return -EINVAL;
2575
2576 scr_width = ovl->info.screen_width;
2577 data = ovl->info.vaddr;
2578
2579 start_offset = scr_width * y + x;
2580 horiz_inc = scr_width - w;
2581 current_x = x;
2582
2583 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2584 * in fifo */
2585
2586 /* When using CPU, max long packet size is TX buffer size */
2587 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2588
2589 /* we seem to get better perf if we divide the tx fifo to half,
2590 and while the other half is being sent, we fill the other half
2591 max_dsi_packet_size /= 2; */
2592
2593 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2594
2595 max_pixels_per_packet = max_data_per_packet / bytespp;
2596
2597 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2598
2599 pixels_left = w * h;
2600
2601 DSSDBG("total pixels %d\n", pixels_left);
2602
2603 data += start_offset;
2604
2605 while (pixels_left > 0) {
2606 /* 0x2c = write_memory_start */
2607 /* 0x3c = write_memory_continue */
2608 u8 dcs_cmd = first ? 0x2c : 0x3c;
2609 int pixels;
2610 DSI_DECL_VARS;
2611 first = 0;
2612
2613#if 1
2614 /* using fifo not empty */
2615 /* TX_FIFO_NOT_EMPTY */
2616 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
3de7a1dc
TV		 2617 fifo_stalls++;
2618 if (fifo_stalls > 0xfffff) {
2619 DSSERR("fifo stalls overflow, pixels left %d\n",
2620 pixels_left);
2621 dsi_if_enable(0);
2622 return -EIO;
2623 }
24be78b3 2624 udelay(1);
3de7a1dc
TV		 2625 }
2626#elif 1
2627 /* using fifo emptiness */
2628 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2629 max_dsi_packet_size) {
2630 fifo_stalls++;
2631 if (fifo_stalls > 0xfffff) {
2632 DSSERR("fifo stalls overflow, pixels left %d\n",
2633 pixels_left);
2634 dsi_if_enable(0);
2635 return -EIO;
2636 }
2637 }
2638#else
2639 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2640 fifo_stalls++;
2641 if (fifo_stalls > 0xfffff) {
2642 DSSERR("fifo stalls overflow, pixels left %d\n",
2643 pixels_left);
2644 dsi_if_enable(0);
2645 return -EIO;
2646 }
2647 }
2648#endif
2649 pixels = min(max_pixels_per_packet, pixels_left);
2650
2651 pixels_left -= pixels;
2652
2653 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2654 1 + pixels * bytespp, 0);
2655
2656 DSI_PUSH(0, dcs_cmd);
2657
2658 while (pixels-- > 0) {
2659 u32 pix = __raw_readl(data++);
2660
2661 DSI_PUSH(0, (pix >> 16) & 0xff);
2662 DSI_PUSH(0, (pix >> 8) & 0xff);
2663 DSI_PUSH(0, (pix >> 0) & 0xff);
2664
2665 current_x++;
2666 if (current_x == x+w) {
2667 current_x = x;
2668 data += horiz_inc;
2669 }
2670 }
2671
2672 DSI_FLUSH(0);
2673 }
2674
2675 return 0;
2676}
2677
2678static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2679 u16 x, u16 y, u16 w, u16 h)
2680{
2681 unsigned bytespp;
2682 unsigned bytespl;
2683 unsigned bytespf;
2684 unsigned total_len;
2685 unsigned packet_payload;
2686 unsigned packet_len;
2687 u32 l;
0f16aa0a 2688 int r;
18946f62 2689 const unsigned channel = dsi.update_channel;
3de7a1dc
TV		 2690 /* line buffer is 1024 x 24bits */
2691 /* XXX: for some reason using full buffer size causes considerable TX
2692 * slowdown with update sizes that fill the whole buffer */
2693 const unsigned line_buf_size = 1023 * 3;
2694
446f7bff
TV		 2695 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2696 x, y, w, h);
3de7a1dc 2697
18946f62
TV		 2698 dsi_vc_config_vp(channel);
2699
3de7a1dc
TV		 2700 bytespp = dssdev->ctrl.pixel_size / 8;
2701 bytespl = w * bytespp;
2702 bytespf = bytespl * h;
2703
2704 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2705 * number of lines in a packet. See errata about VP_CLK_RATIO */
2706
2707 if (bytespf < line_buf_size)
2708 packet_payload = bytespf;
2709 else
2710 packet_payload = (line_buf_size) / bytespl * bytespl;
2711
2712 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2713 total_len = (bytespf / packet_payload) * packet_len;
2714
2715 if (bytespf % packet_payload)
2716 total_len += (bytespf % packet_payload) + 1;
2717
3de7a1dc
TV		 2718 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2719 dsi_write_reg(DSI_VC_TE(channel), l);
2720
2721 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2722
942a91a6 2723 if (dsi.te_enabled)
3de7a1dc
TV		 2724 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2725 else
2726 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2727 dsi_write_reg(DSI_VC_TE(channel), l);
2728
2729 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2730 * because DSS interrupts are not capable of waking up the CPU and the
2731 * framedone interrupt could be delayed for quite a long time. I think
2732 * the same goes for any DSS interrupts, but for some reason I have not
2733 * seen the problem anywhere else than here.
2734 */
2735 dispc_disable_sidle();
2736
18946f62
TV		 2737 dsi_perf_mark_start();
2738
0f16aa0a 2739 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
18946f62 2740 msecs_to_jiffies(250));
0f16aa0a 2741 BUG_ON(r == 0);
18946f62 2742
3de7a1dc
TV		 2743 dss_start_update(dssdev);
2744
942a91a6 2745 if (dsi.te_enabled) {
3de7a1dc
TV		 2746 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2747 * for TE is longer than the timer allows */
2748 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2749
2750 dsi_vc_send_bta(channel);
2751
2752#ifdef DSI_CATCH_MISSING_TE
2753 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2754#endif
2755 }
2756}
2757
2758#ifdef DSI_CATCH_MISSING_TE
2759static void dsi_te_timeout(unsigned long arg)
2760{
2761 DSSERR("TE not received for 250ms!\n");
2762}
2763#endif
2764
ab83b14c 2765static void dsi_handle_framedone(int error)
3de7a1dc 2766{
18946f62 2767 const int channel = dsi.update_channel;
18946f62 2768
ab83b14c 2769 cancel_delayed_work(&dsi.framedone_timeout_work);
3de7a1dc 2770
ab83b14c 2771 dsi_vc_disable_bta_irq(channel);
0f16aa0a 2772
3de7a1dc
TV		 2773 /* SIDLEMODE back to smart-idle */
2774 dispc_enable_sidle();
2775
ab83b14c
TV		 2776 dsi.bta_callback = NULL;
2777
942a91a6 2778 if (dsi.te_enabled) {
18946f62
TV		 2779 /* enable LP_RX_TO again after the TE */
2780 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3de7a1dc
TV		 2781 }
2782
18946f62
TV		 2783 /* RX_FIFO_NOT_EMPTY */
2784 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2785 DSSERR("Received error during frame transfer:\n");
2786 dsi_vc_flush_receive_data(channel);
ab83b14c
TV		 2787 if (!error)
2788 error = -EIO;
18946f62
TV		 2789 }
2790
ab83b14c
TV		 2791 dsi.framedone_callback(error, dsi.framedone_data);
2792
2793 if (!error)
2794 dsi_perf_show("DISPC");
18946f62 2795}
3de7a1dc 2796
ab83b14c 2797static void dsi_framedone_timeout_work_callback(struct work_struct *work)
18946f62 2798{
ab83b14c
TV		 2799 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2800 * 250ms which would conflict with this timeout work. What should be
2801 * done is first cancel the transfer on the HW, and then cancel the
2802 * possibly scheduled framedone work. However, cancelling the transfer
2803 * on the HW is buggy, and would probably require resetting the whole
2804 * DSI */
18946f62 2805
ab83b14c 2806 DSSERR("Framedone not received for 250ms!\n");
3de7a1dc 2807
ab83b14c 2808 dsi_handle_framedone(-ETIMEDOUT);
3de7a1dc
TV		 2809}
2810
ab83b14c
TV		 2811static void dsi_framedone_bta_callback(void)
2812{
2813 dsi_handle_framedone(0);
2814
2815#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2816 dispc_fake_vsync_irq();
2817#endif
2818}
2819
2820static void dsi_framedone_irq_callback(void *data, u32 mask)
3de7a1dc 2821{
18946f62 2822 const int channel = dsi.update_channel;
ab83b14c 2823 int r;
3de7a1dc 2824
ab83b14c
TV		 2825 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2826 * turns itself off. However, DSI still has the pixels in its buffers,
2827 * and is sending the data.
2828 */
3de7a1dc 2829
942a91a6 2830 if (dsi.te_enabled) {
3de7a1dc
TV		 2831 /* enable LP_RX_TO again after the TE */
2832 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2833 }
2834
2835 /* Send BTA after the frame. We need this for the TE to work, as TE
2836 * trigger is only sent for BTAs without preceding packet. Thus we need
2837 * to BTA after the pixel packets so that next BTA will cause TE
2838 * trigger.
2839 *
2840 * This is not needed when TE is not in use, but we do it anyway to
2841 * make sure that the transfer has been completed. It would be more
2842 * optimal, but more complex, to wait only just before starting next
ab83b14c
TV		 2843 * transfer.
2844 *
2845 * Also, as there's no interrupt telling when the transfer has been
2846 * done and the channel could be reconfigured, the only way is to
2847 * busyloop until TE_SIZE is zero. With BTA we can do this
2848 * asynchronously.
2849 * */
3de7a1dc 2850
ab83b14c 2851 dsi.bta_callback = dsi_framedone_bta_callback;
3de7a1dc 2852
ab83b14c 2853 barrier();
3de7a1dc 2854
ab83b14c 2855 dsi_vc_enable_bta_irq(channel);
3de7a1dc 2856
ab83b14c
TV		 2857 r = dsi_vc_send_bta(channel);
2858 if (r) {
2859 DSSERR("BTA after framedone failed\n");
2860 dsi_handle_framedone(-EIO);
2861 }
18946f62 2862}
3de7a1dc 2863
18946f62 2864int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250
TV		 2865 u16 *x, u16 *y, u16 *w, u16 *h,
2866 bool enlarge_update_area)
18946f62
TV		 2867{
2868 u16 dw, dh;
3de7a1dc 2869
18946f62 2870 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3de7a1dc 2871
18946f62
TV		 2872 if (*x > dw || *y > dh)
2873 return -EINVAL;
3de7a1dc 2874
18946f62
TV		 2875 if (*x + *w > dw)
2876 return -EINVAL;
3de7a1dc 2877
18946f62
TV		 2878 if (*y + *h > dh)
2879 return -EINVAL;
3de7a1dc 2880
18946f62
TV		 2881 if (*w == 1)
2882 return -EINVAL;
3de7a1dc 2883
18946f62
TV		 2884 if (*w == 0 || *h == 0)
2885 return -EINVAL;
3de7a1dc 2886
18946f62 2887 dsi_perf_mark_setup();
3de7a1dc 2888
18946f62 2889 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
26a8c250
TV		 2890 dss_setup_partial_planes(dssdev, x, y, w, h,
2891 enlarge_update_area);
64ba4f74 2892 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
18946f62 2893 }
3de7a1dc 2894
18946f62
TV		 2895 return 0;
2896}
2897EXPORT_SYMBOL(omap_dsi_prepare_update);
3de7a1dc 2898
18946f62
TV		 2899int omap_dsi_update(struct omap_dss_device *dssdev,
2900 int channel,
2901 u16 x, u16 y, u16 w, u16 h,
2902 void (*callback)(int, void *), void *data)
2903{
2904 dsi.update_channel = channel;
3de7a1dc 2905
a602771c
TV		 2906 /* OMAP DSS cannot send updates of odd widths.
2907 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2908 * here to make sure we catch erroneous updates. Otherwise we'll only
2909 * see rather obscure HW error happening, as DSS halts. */
2910 BUG_ON(x % 2 == 1);
2911
18946f62
TV		 2912 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2913 dsi.framedone_callback = callback;
2914 dsi.framedone_data = data;
3de7a1dc 2915
18946f62
TV		 2916 dsi.update_region.x = x;
2917 dsi.update_region.y = y;
2918 dsi.update_region.w = w;
2919 dsi.update_region.h = h;
2920 dsi.update_region.device = dssdev;
3de7a1dc 2921
18946f62
TV		 2922 dsi_update_screen_dispc(dssdev, x, y, w, h);
2923 } else {
e9c31afc
AT		 2924 int r;
2925
2926 r = dsi_update_screen_l4(dssdev, x, y, w, h);
2927 if (r)
2928 return r;
2929
18946f62
TV		 2930 dsi_perf_show("L4");
2931 callback(0, data);
3de7a1dc
TV		 2932 }
2933
3de7a1dc
TV		 2934 return 0;
2935}
18946f62 2936EXPORT_SYMBOL(omap_dsi_update);
3de7a1dc
TV		 2937
2938/* Display funcs */
2939
2940static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2941{
2942 int r;
2943
2944 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2945 DISPC_IRQ_FRAMEDONE);
2946 if (r) {
2947 DSSERR("can't get FRAMEDONE irq\n");
2948 return r;
2949 }
2950
64ba4f74
SS		 2951 dispc_set_lcd_display_type(dssdev->manager->id,
2952 OMAP_DSS_LCD_DISPLAY_TFT);
3de7a1dc 2953
64ba4f74
SS		 2954 dispc_set_parallel_interface_mode(dssdev->manager->id,
2955 OMAP_DSS_PARALLELMODE_DSI);
2956 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3de7a1dc 2957
64ba4f74 2958 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3de7a1dc
TV		 2959
2960 {
2961 struct omap_video_timings timings = {
2962 .hsw = 1,
2963 .hfp = 1,
2964 .hbp = 1,
2965 .vsw = 1,
2966 .vfp = 0,
2967 .vbp = 0,
2968 };
2969
64ba4f74 2970 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3de7a1dc
TV		 2971 }
2972
2973 return 0;
2974}
2975
2976static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2977{
2978 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2979 DISPC_IRQ_FRAMEDONE);
2980}
2981
2982static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2983{
2984 struct dsi_clock_info cinfo;
2985 int r;
2986
2987 /* we always use DSS2_FCK as input clock */
2988 cinfo.use_dss2_fck = true;
2989 cinfo.regn = dssdev->phy.dsi.div.regn;
2990 cinfo.regm = dssdev->phy.dsi.div.regm;
2991 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2992 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
ff1b2cde 2993 r = dsi_calc_clock_rates(dssdev, &cinfo);
ebf0a3fe
VS		 2994 if (r) {
2995 DSSERR("Failed to calc dsi clocks\n");
3de7a1dc 2996 return r;
ebf0a3fe 2997 }
3de7a1dc
TV		 2998
2999 r = dsi_pll_set_clock_div(&cinfo);
3000 if (r) {
3001 DSSERR("Failed to set dsi clocks\n");
3002 return r;
3003 }
3004
3005 return 0;
3006}
3007
3008static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3009{
3010 struct dispc_clock_info dispc_cinfo;
3011 int r;
3012 unsigned long long fck;
3013
3014 fck = dsi_get_dsi1_pll_rate();
3015
3016 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3017 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3018
3019 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3020 if (r) {
3021 DSSERR("Failed to calc dispc clocks\n");
3022 return r;
3023 }
3024
ff1b2cde 3025 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3de7a1dc
TV		 3026 if (r) {
3027 DSSERR("Failed to set dispc clocks\n");
3028 return r;
3029 }
3030
3031 return 0;
3032}
3033
3034static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3035{
3036 int r;
3037
3038 _dsi_print_reset_status();
3039
3040 r = dsi_pll_init(dssdev, true, true);
3041 if (r)
3042 goto err0;
3043
3044 r = dsi_configure_dsi_clocks(dssdev);
3045 if (r)
3046 goto err1;
3047
2f18c4d8
TV		 3048 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3049 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3de7a1dc
TV		 3050
3051 DSSDBG("PLL OK\n");
3052
3053 r = dsi_configure_dispc_clocks(dssdev);
3054 if (r)
3055 goto err2;
3056
3057 r = dsi_complexio_init(dssdev);
3058 if (r)
3059 goto err2;
3060
3061 _dsi_print_reset_status();
3062
3063 dsi_proto_timings(dssdev);
3064 dsi_set_lp_clk_divisor(dssdev);
3065
3066 if (1)
3067 _dsi_print_reset_status();
3068
3069 r = dsi_proto_config(dssdev);
3070 if (r)
3071 goto err3;
3072
3073 /* enable interface */
3074 dsi_vc_enable(0, 1);
dd8079d6
TV		 3075 dsi_vc_enable(1, 1);
3076 dsi_vc_enable(2, 1);
3077 dsi_vc_enable(3, 1);
3de7a1dc
TV		 3078 dsi_if_enable(1);
3079 dsi_force_tx_stop_mode_io();
3080
3de7a1dc 3081 return 0;
3de7a1dc
TV		 3082err3:
3083 dsi_complexio_uninit();
3084err2:
2f18c4d8
TV		 3085 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3086 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3de7a1dc
TV		 3087err1:
3088 dsi_pll_uninit();
3089err0:
3090 return r;
3091}
3092
3093static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3094{
d7370104
VS		 3095 /* disable interface */
3096 dsi_if_enable(0);
3097 dsi_vc_enable(0, 0);
3098 dsi_vc_enable(1, 0);
3099 dsi_vc_enable(2, 0);
3100 dsi_vc_enable(3, 0);
3101
2f18c4d8
TV		 3102 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3103 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3de7a1dc
TV		 3104 dsi_complexio_uninit();
3105 dsi_pll_uninit();
3106}
3107
3108static int dsi_core_init(void)
3109{
3110 /* Autoidle */
3111 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3112
3113 /* ENWAKEUP */
3114 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3115
3116 /* SIDLEMODE smart-idle */
3117 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3118
3119 _dsi_initialize_irq();
3120
3121 return 0;
3122}
3123
37ac60e4 3124int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3125{
3126 int r = 0;
3127
3128 DSSDBG("dsi_display_enable\n");
3129
37ac60e4
TV		 3130 WARN_ON(!dsi_bus_is_locked());
3131
3de7a1dc 3132 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3133
3134 r = omap_dss_start_device(dssdev);
3135 if (r) {
3136 DSSERR("failed to start device\n");
3137 goto err0;
3138 }
3139
3de7a1dc
TV		 3140 enable_clocks(1);
3141 dsi_enable_pll_clock(1);
3142
3143 r = _dsi_reset();
3144 if (r)
37ac60e4 3145 goto err1;
3de7a1dc
TV		 3146
3147 dsi_core_init();
3148
3149 r = dsi_display_init_dispc(dssdev);
3150 if (r)
37ac60e4 3151 goto err1;
3de7a1dc
TV		 3152
3153 r = dsi_display_init_dsi(dssdev);
3154 if (r)
37ac60e4 3155 goto err2;
3de7a1dc 3156
3de7a1dc
TV		 3157 mutex_unlock(&dsi.lock);
3158
3159 return 0;
3160
3de7a1dc 3161err2:
37ac60e4
TV		 3162 dsi_display_uninit_dispc(dssdev);
3163err1:
3de7a1dc
TV		 3164 enable_clocks(0);
3165 dsi_enable_pll_clock(0);
3de7a1dc
TV		 3166 omap_dss_stop_device(dssdev);
3167err0:
3de7a1dc
TV		 3168 mutex_unlock(&dsi.lock);
3169 DSSDBG("dsi_display_enable FAILED\n");
3170 return r;
3171}
37ac60e4 3172EXPORT_SYMBOL(omapdss_dsi_display_enable);
3de7a1dc 3173
37ac60e4 3174void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3175{
3176 DSSDBG("dsi_display_disable\n");
3177
37ac60e4 3178 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 3179
3180 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3181
3182 dsi_display_uninit_dispc(dssdev);
3183
3184 dsi_display_uninit_dsi(dssdev);
3185
3186 enable_clocks(0);
3187 dsi_enable_pll_clock(0);
3de7a1dc 3188
37ac60e4 3189 omap_dss_stop_device(dssdev);
3de7a1dc 3190
3de7a1dc 3191 mutex_unlock(&dsi.lock);
3de7a1dc 3192}
37ac60e4 3193EXPORT_SYMBOL(omapdss_dsi_display_disable);
3de7a1dc 3194
225b650d 3195int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3de7a1dc 3196{
3de7a1dc 3197 dsi.te_enabled = enable;
225b650d 3198 return 0;
3de7a1dc 3199}
225b650d 3200EXPORT_SYMBOL(omapdss_dsi_enable_te);
3de7a1dc 3201
3de7a1dc
TV		 3202void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3203 u32 fifo_size, enum omap_burst_size *burst_size,
3204 u32 *fifo_low, u32 *fifo_high)
3205{
3206 unsigned burst_size_bytes;
3207
3208 *burst_size = OMAP_DSS_BURST_16x32;
3209 burst_size_bytes = 16 * 32 / 8;
3210
3211 *fifo_high = fifo_size - burst_size_bytes;
36194b47 3212 *fifo_low = fifo_size - burst_size_bytes * 2;
3de7a1dc
TV		 3213}
3214
3215int dsi_init_display(struct omap_dss_device *dssdev)
3216{
3217 DSSDBG("DSI init\n");
3218
3de7a1dc
TV		 3219 /* XXX these should be figured out dynamically */
3220 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3221 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3222
3223 dsi.vc[0].dssdev = dssdev;
3224 dsi.vc[1].dssdev = dssdev;
3225
3226 return 0;
3227}
3228
e406f907
TV		 3229void dsi_wait_dsi1_pll_active(void)
3230{
3231 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3232 DSSERR("DSI1 PLL clock not active\n");
3233}
3234
3235void dsi_wait_dsi2_pll_active(void)
3236{
3237 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3238 DSSERR("DSI2 PLL clock not active\n");
3239}
3240
3de7a1dc
TV		 3241int dsi_init(struct platform_device *pdev)
3242{
3243 u32 rev;
3244 int r;
3de7a1dc
TV		 3245
3246 spin_lock_init(&dsi.errors_lock);
3247 dsi.errors = 0;
3248
dfc0fd8d
TV		 3249#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3250 spin_lock_init(&dsi.irq_stats_lock);
3251 dsi.irq_stats.last_reset = jiffies;
3252#endif
3253
3de7a1dc 3254 init_completion(&dsi.bta_completion);
3de7a1dc
TV		 3255
3256 mutex_init(&dsi.lock);
b9eb5d7d 3257 sema_init(&dsi.bus_lock, 1);
3de7a1dc 3258
0f16aa0a
TV		 3259 dsi.workqueue = create_singlethread_workqueue("dsi");
3260 if (dsi.workqueue == NULL)
3261 return -ENOMEM;
3262
18946f62
TV		 3263 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3264 dsi_framedone_timeout_work_callback);
3265
3de7a1dc
TV		 3266#ifdef DSI_CATCH_MISSING_TE
3267 init_timer(&dsi.te_timer);
3268 dsi.te_timer.function = dsi_te_timeout;
3269 dsi.te_timer.data = 0;
3270#endif
3de7a1dc
TV		 3271 dsi.base = ioremap(DSI_BASE, DSI_SZ_REGS);
3272 if (!dsi.base) {
3273 DSSERR("can't ioremap DSI\n");
3274 r = -ENOMEM;
3275 goto err1;
3276 }
3277
8a2cfea8 3278 dsi.vdds_dsi_reg = dss_get_vdds_dsi();
3de7a1dc 3279 if (IS_ERR(dsi.vdds_dsi_reg)) {
3de7a1dc
TV		 3280 DSSERR("can't get VDDS_DSI regulator\n");
3281 r = PTR_ERR(dsi.vdds_dsi_reg);
3282 goto err2;
3283 }
3284
3285 enable_clocks(1);
3286
3287 rev = dsi_read_reg(DSI_REVISION);
3288 printk(KERN_INFO "OMAP DSI rev %d.%d\n",
3289 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3290
3291 enable_clocks(0);
3292
3de7a1dc
TV		 3293 return 0;
3294err2:
3295 iounmap(dsi.base);
3296err1:
0f16aa0a 3297 destroy_workqueue(dsi.workqueue);
3de7a1dc
TV		 3298 return r;
3299}
3300
3301void dsi_exit(void)
3302{
3de7a1dc
TV		 3303 iounmap(dsi.base);
3304
0f16aa0a
TV		 3305 destroy_workqueue(dsi.workqueue);
3306
3de7a1dc
TV		 3307 DSSDBG("omap_dsi_exit\n");
3308}
3309
Linux 6.x block layer and io_uring tree(s)