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OMAPDSS: DISPC: use get_framedone_irq in disable_digit_out
[linux-2.6-block.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
33366d0e 39#include <linux/sizes.h>
80c39712 40
a0b38cc4 41#include <video/omapdss.h>
80c39712
TV		 42
43#include "dss.h"
a0acb557 44#include "dss_features.h"
9b372c2d 45#include "dispc.h"
80c39712
TV		 46
47/* DISPC */
8613b000 48#define DISPC_SZ_REGS SZ_4K
80c39712 49
80c39712
TV		 50#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57#define DISPC_MAX_NR_ISRS 8
58
59struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63};
64
5ed8cf5b
TV		 65enum omap_burst_size {
66 BURST_SIZE_X2 = 0,
67 BURST_SIZE_X4 = 1,
68 BURST_SIZE_X8 = 2,
69};
70
80c39712
TV		 71#define REG_GET(idx, start, end) \
72 FLD_GET(dispc_read_reg(idx), start, end)
73
74#define REG_FLD_MOD(idx, val, start, end) \
75 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
dfc0fd8d
TV		 77struct dispc_irq_stats {
78 unsigned long last_reset;
79 unsigned irq_count;
80 unsigned irqs[32];
81};
82
dcbe765b
CM		 83struct dispc_features {
84 u8 sw_start;
85 u8 fp_start;
86 u8 bp_start;
87 u16 sw_max;
88 u16 vp_max;
89 u16 hp_max;
33b89928
AT		 90 u8 mgr_width_start;
91 u8 mgr_height_start;
92 u16 mgr_width_max;
93 u16 mgr_height_max;
3e8a6ff2 94 int (*calc_scaling) (enum omap_plane plane,
dcbe765b
CM		 95 const struct omap_video_timings *mgr_timings,
96 u16 width, u16 height, u16 out_width, u16 out_height,
97 enum omap_color_mode color_mode, bool *five_taps,
98 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 99 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
3e8a6ff2 100 unsigned long (*calc_core_clk) (enum omap_plane plane,
8ba85306
AT		 101 u16 width, u16 height, u16 out_width, u16 out_height,
102 bool mem_to_mem);
42a6961c 103 u8 num_fifos;
66a0f9e4
TV		 104
105 /* swap GFX & WB fifos */
106 bool gfx_fifo_workaround:1;
cffa947d
TV		 107
108 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
109 bool no_framedone_tv:1;
dcbe765b
CM		 110};
111
42a6961c
TV		 112#define DISPC_MAX_NR_FIFOS 5
113
80c39712 114static struct {
060b6d9c 115 struct platform_device *pdev;
80c39712 116 void __iomem *base;
4fbafaf3
TV		 117
118 int ctx_loss_cnt;
119
affe360d 120 int irq;
4fbafaf3 121 struct clk *dss_clk;
80c39712 122
42a6961c
TV		 123 u32 fifo_size[DISPC_MAX_NR_FIFOS];
124 /* maps which plane is using a fifo. fifo-id -> plane-id */
125 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 126
127 spinlock_t irq_lock;
128 u32 irq_error_mask;
129 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
130 u32 error_irqs;
131 struct work_struct error_work;
132
49ea86f3 133 bool ctx_valid;
80c39712 134 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 135
dcbe765b
CM		 136 const struct dispc_features *feat;
137
dfc0fd8d
TV		 138#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
139 spinlock_t irq_stats_lock;
140 struct dispc_irq_stats irq_stats;
141#endif
80c39712
TV		 142} dispc;
143
0d66cbb5
AJ		 144enum omap_color_component {
145 /* used for all color formats for OMAP3 and earlier
146 * and for RGB and Y color component on OMAP4
147 */
148 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
149 /* used for UV component for
150 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
151 * color formats on OMAP4
152 */
153 DISPC_COLOR_COMPONENT_UV = 1 << 1,
154};
155
efa70b3b
CM		 156enum mgr_reg_fields {
157 DISPC_MGR_FLD_ENABLE,
158 DISPC_MGR_FLD_STNTFT,
159 DISPC_MGR_FLD_GO,
160 DISPC_MGR_FLD_TFTDATALINES,
161 DISPC_MGR_FLD_STALLMODE,
162 DISPC_MGR_FLD_TCKENABLE,
163 DISPC_MGR_FLD_TCKSELECTION,
164 DISPC_MGR_FLD_CPR,
165 DISPC_MGR_FLD_FIFOHANDCHECK,
166 /* used to maintain a count of the above fields */
167 DISPC_MGR_FLD_NUM,
168};
169
170static const struct {
171 const char *name;
172 u32 vsync_irq;
173 u32 framedone_irq;
174 u32 sync_lost_irq;
175 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
176} mgr_desc[] = {
177 [OMAP_DSS_CHANNEL_LCD] = {
178 .name = "LCD",
179 .vsync_irq = DISPC_IRQ_VSYNC,
180 .framedone_irq = DISPC_IRQ_FRAMEDONE,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
184 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
187 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
190 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_DIGIT] = {
195 .name = "DIGIT",
196 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 197 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
201 [DISPC_MGR_FLD_STNTFT] = { },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { },
204 [DISPC_MGR_FLD_STALLMODE] = { },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
207 [DISPC_MGR_FLD_CPR] = { },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
209 },
210 },
211 [OMAP_DSS_CHANNEL_LCD2] = {
212 .name = "LCD2",
213 .vsync_irq = DISPC_IRQ_VSYNC2,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
226 },
227 },
e86d456a
CM		 228 [OMAP_DSS_CHANNEL_LCD3] = {
229 .name = "LCD3",
230 .vsync_irq = DISPC_IRQ_VSYNC3,
231 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
232 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
233 .reg_desc = {
234 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
235 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
236 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
237 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
238 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
239 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
240 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
241 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
242 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
243 },
244 },
efa70b3b
CM		 245};
246
6e5264b0
AT		 247struct color_conv_coef {
248 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
249 int full_range;
250};
251
80c39712 252static void _omap_dispc_set_irqs(void);
3e8a6ff2
AT		 253static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
254static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 255
55978cc2 256static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 257{
55978cc2 258 __raw_writel(val, dispc.base + idx);
80c39712
TV		 259}
260
55978cc2 261static inline u32 dispc_read_reg(const u16 idx)
80c39712 262{
55978cc2 263 return __raw_readl(dispc.base + idx);
80c39712
TV		 264}
265
efa70b3b
CM		 266static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
267{
268 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
269 return REG_GET(rfld.reg, rfld.high, rfld.low);
270}
271
272static void mgr_fld_write(enum omap_channel channel,
273 enum mgr_reg_fields regfld, int val) {
274 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
275 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
276}
277
80c39712 278#define SR(reg) \
55978cc2 279 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 280#define RR(reg) \
55978cc2 281 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 282
4fbafaf3 283static void dispc_save_context(void)
80c39712 284{
c6104b8e 285 int i, j;
80c39712 286
4fbafaf3
TV		 287 DSSDBG("dispc_save_context\n");
288
80c39712
TV		 289 SR(IRQENABLE);
290 SR(CONTROL);
291 SR(CONFIG);
80c39712 292 SR(LINE_NUMBER);
11354dd5
AT		 293 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
294 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 295 SR(GLOBAL_ALPHA);
2a205f34
SS		 296 if (dss_has_feature(FEAT_MGR_LCD2)) {
297 SR(CONTROL2);
2a205f34
SS		 298 SR(CONFIG2);
299 }
e86d456a
CM		 300 if (dss_has_feature(FEAT_MGR_LCD3)) {
301 SR(CONTROL3);
302 SR(CONFIG3);
303 }
80c39712 304
c6104b8e
AT		 305 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
306 SR(DEFAULT_COLOR(i));
307 SR(TRANS_COLOR(i));
308 SR(SIZE_MGR(i));
309 if (i == OMAP_DSS_CHANNEL_DIGIT)
310 continue;
311 SR(TIMING_H(i));
312 SR(TIMING_V(i));
313 SR(POL_FREQ(i));
314 SR(DIVISORo(i));
315
316 SR(DATA_CYCLE1(i));
317 SR(DATA_CYCLE2(i));
318 SR(DATA_CYCLE3(i));
319
332e9d70 320 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 321 SR(CPR_COEF_R(i));
322 SR(CPR_COEF_G(i));
323 SR(CPR_COEF_B(i));
332e9d70 324 }
2a205f34 325 }
80c39712 326
c6104b8e
AT		 327 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
328 SR(OVL_BA0(i));
329 SR(OVL_BA1(i));
330 SR(OVL_POSITION(i));
331 SR(OVL_SIZE(i));
332 SR(OVL_ATTRIBUTES(i));
333 SR(OVL_FIFO_THRESHOLD(i));
334 SR(OVL_ROW_INC(i));
335 SR(OVL_PIXEL_INC(i));
336 if (dss_has_feature(FEAT_PRELOAD))
337 SR(OVL_PRELOAD(i));
338 if (i == OMAP_DSS_GFX) {
339 SR(OVL_WINDOW_SKIP(i));
340 SR(OVL_TABLE_BA(i));
341 continue;
342 }
343 SR(OVL_FIR(i));
344 SR(OVL_PICTURE_SIZE(i));
345 SR(OVL_ACCU0(i));
346 SR(OVL_ACCU1(i));
9b372c2d 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 5; j++)
355 SR(OVL_CONV_COEF(i, j));
ab5ca071 356
c6104b8e
AT		 357 if (dss_has_feature(FEAT_FIR_COEF_V)) {
358 for (j = 0; j < 8; j++)
359 SR(OVL_FIR_COEF_V(i, j));
360 }
9b372c2d 361
c6104b8e
AT		 362 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
363 SR(OVL_BA0_UV(i));
364 SR(OVL_BA1_UV(i));
365 SR(OVL_FIR2(i));
366 SR(OVL_ACCU2_0(i));
367 SR(OVL_ACCU2_1(i));
ab5ca071 368
c6104b8e
AT		 369 for (j = 0; j < 8; j++)
370 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 371
c6104b8e
AT		 372 for (j = 0; j < 8; j++)
373 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 374
c6104b8e
AT		 375 for (j = 0; j < 8; j++)
376 SR(OVL_FIR_COEF_V2(i, j));
377 }
378 if (dss_has_feature(FEAT_ATTR2))
379 SR(OVL_ATTRIBUTES2(i));
ab5ca071 380 }
0cf35df3
MR		 381
382 if (dss_has_feature(FEAT_CORE_CLK_DIV))
383 SR(DIVISOR);
49ea86f3 384
00928eaf 385 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 386 dispc.ctx_valid = true;
387
388 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 389}
390
4fbafaf3 391static void dispc_restore_context(void)
80c39712 392{
c6104b8e 393 int i, j, ctx;
4fbafaf3
TV		 394
395 DSSDBG("dispc_restore_context\n");
396
49ea86f3
TV		 397 if (!dispc.ctx_valid)
398 return;
399
00928eaf 400 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 401
402 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
403 return;
404
405 DSSDBG("ctx_loss_count: saved %d, current %d\n",
406 dispc.ctx_loss_cnt, ctx);
407
75c7d59d 408 /*RR(IRQENABLE);*/
80c39712
TV		 409 /*RR(CONTROL);*/
410 RR(CONFIG);
80c39712 411 RR(LINE_NUMBER);
11354dd5
AT		 412 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
413 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 414 RR(GLOBAL_ALPHA);
c6104b8e 415 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 416 RR(CONFIG2);
e86d456a
CM		 417 if (dss_has_feature(FEAT_MGR_LCD3))
418 RR(CONFIG3);
80c39712 419
c6104b8e
AT		 420 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
421 RR(DEFAULT_COLOR(i));
422 RR(TRANS_COLOR(i));
423 RR(SIZE_MGR(i));
424 if (i == OMAP_DSS_CHANNEL_DIGIT)
425 continue;
426 RR(TIMING_H(i));
427 RR(TIMING_V(i));
428 RR(POL_FREQ(i));
429 RR(DIVISORo(i));
430
431 RR(DATA_CYCLE1(i));
432 RR(DATA_CYCLE2(i));
433 RR(DATA_CYCLE3(i));
2a205f34 434
332e9d70 435 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 436 RR(CPR_COEF_R(i));
437 RR(CPR_COEF_G(i));
438 RR(CPR_COEF_B(i));
332e9d70 439 }
2a205f34 440 }
80c39712 441
c6104b8e
AT		 442 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
443 RR(OVL_BA0(i));
444 RR(OVL_BA1(i));
445 RR(OVL_POSITION(i));
446 RR(OVL_SIZE(i));
447 RR(OVL_ATTRIBUTES(i));
448 RR(OVL_FIFO_THRESHOLD(i));
449 RR(OVL_ROW_INC(i));
450 RR(OVL_PIXEL_INC(i));
451 if (dss_has_feature(FEAT_PRELOAD))
452 RR(OVL_PRELOAD(i));
453 if (i == OMAP_DSS_GFX) {
454 RR(OVL_WINDOW_SKIP(i));
455 RR(OVL_TABLE_BA(i));
456 continue;
457 }
458 RR(OVL_FIR(i));
459 RR(OVL_PICTURE_SIZE(i));
460 RR(OVL_ACCU0(i));
461 RR(OVL_ACCU1(i));
9b372c2d 462
c6104b8e
AT		 463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 465
c6104b8e
AT		 466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 468
c6104b8e
AT		 469 for (j = 0; j < 5; j++)
470 RR(OVL_CONV_COEF(i, j));
ab5ca071 471
c6104b8e
AT		 472 if (dss_has_feature(FEAT_FIR_COEF_V)) {
473 for (j = 0; j < 8; j++)
474 RR(OVL_FIR_COEF_V(i, j));
475 }
9b372c2d 476
c6104b8e
AT		 477 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
478 RR(OVL_BA0_UV(i));
479 RR(OVL_BA1_UV(i));
480 RR(OVL_FIR2(i));
481 RR(OVL_ACCU2_0(i));
482 RR(OVL_ACCU2_1(i));
ab5ca071 483
c6104b8e
AT		 484 for (j = 0; j < 8; j++)
485 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 486
c6104b8e
AT		 487 for (j = 0; j < 8; j++)
488 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 489
c6104b8e
AT		 490 for (j = 0; j < 8; j++)
491 RR(OVL_FIR_COEF_V2(i, j));
492 }
493 if (dss_has_feature(FEAT_ATTR2))
494 RR(OVL_ATTRIBUTES2(i));
ab5ca071 495 }
80c39712 496
0cf35df3
MR		 497 if (dss_has_feature(FEAT_CORE_CLK_DIV))
498 RR(DIVISOR);
499
80c39712
TV		 500 /* enable last, because LCD & DIGIT enable are here */
501 RR(CONTROL);
2a205f34
SS		 502 if (dss_has_feature(FEAT_MGR_LCD2))
503 RR(CONTROL2);
e86d456a
CM		 504 if (dss_has_feature(FEAT_MGR_LCD3))
505 RR(CONTROL3);
75c7d59d 506 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 507 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 508
509 /*
510 * enable last so IRQs won't trigger before
511 * the context is fully restored
512 */
513 RR(IRQENABLE);
49ea86f3
TV		 514
515 DSSDBG("context restored\n");
80c39712
TV		 516}
517
518#undef SR
519#undef RR
520
4fbafaf3
TV		 521int dispc_runtime_get(void)
522{
523 int r;
524
525 DSSDBG("dispc_runtime_get\n");
526
527 r = pm_runtime_get_sync(&dispc.pdev->dev);
528 WARN_ON(r < 0);
529 return r < 0 ? r : 0;
530}
531
532void dispc_runtime_put(void)
533{
534 int r;
535
536 DSSDBG("dispc_runtime_put\n");
537
0eaf9f52 538 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 539 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 540}
541
3dcec4d6
TV		 542u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
543{
efa70b3b 544 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 545}
546
7d1365c9
TV		 547u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
548{
cffa947d
TV		 549 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
550 return 0;
551
efa70b3b 552 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 553}
554
cb699200
TV		 555u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556{
557 return mgr_desc[channel].sync_lost_irq;
558}
559
0b23e5b8
AT		 560u32 dispc_wb_get_framedone_irq(void)
561{
562 return DISPC_IRQ_FRAMEDONEWB;
563}
564
26d9dd0d 565bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 566{
efa70b3b 567 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 568}
569
26d9dd0d 570void dispc_mgr_go(enum omap_channel channel)
80c39712 571{
2a205f34 572 bool enable_bit, go_bit;
80c39712 573
80c39712 574 /* if the channel is not enabled, we don't need GO */
efa70b3b 575 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 576
577 if (!enable_bit)
e6d80f95 578 return;
80c39712 579
efa70b3b 580 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 581
582 if (go_bit) {
80c39712 583 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 584 return;
80c39712
TV		 585 }
586
efa70b3b 587 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 588
efa70b3b 589 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 590}
591
0b23e5b8
AT		 592bool dispc_wb_go_busy(void)
593{
594 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
595}
596
597void dispc_wb_go(void)
598{
599 enum omap_plane plane = OMAP_DSS_WB;
600 bool enable, go;
601
602 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
603
604 if (!enable)
605 return;
606
607 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
608 if (go) {
609 DSSERR("GO bit not down for WB\n");
610 return;
611 }
612
613 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
614}
615
f0e5caab 616static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 617{
9b372c2d 618 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 619}
620
f0e5caab 621static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 622{
9b372c2d 623 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 624}
625
f0e5caab 626static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 627{
9b372c2d 628 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 629}
630
f0e5caab 631static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 632{
633 BUG_ON(plane == OMAP_DSS_GFX);
634
635 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
636}
637
f0e5caab
TV		 638static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
639 u32 value)
ab5ca071
AJ		 640{
641 BUG_ON(plane == OMAP_DSS_GFX);
642
643 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
644}
645
f0e5caab 646static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 647{
648 BUG_ON(plane == OMAP_DSS_GFX);
649
650 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
651}
652
debd9074
CM		 653static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
654 int fir_vinc, int five_taps,
655 enum omap_color_component color_comp)
80c39712 656{
debd9074 657 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 658 int i;
659
debd9074
CM		 660 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
661 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 662
663 for (i = 0; i < 8; i++) {
664 u32 h, hv;
665
debd9074
CM		 666 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
667 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
668 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
669 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
670 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
671 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
672 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
673 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 674
0d66cbb5 675 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 676 dispc_ovl_write_firh_reg(plane, i, h);
677 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 678 } else {
f0e5caab
TV		 679 dispc_ovl_write_firh2_reg(plane, i, h);
680 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 681 }
682
80c39712
TV		 683 }
684
66be8f6c
GI		 685 if (five_taps) {
686 for (i = 0; i < 8; i++) {
687 u32 v;
debd9074
CM		 688 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
689 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 690 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 691 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 692 else
f0e5caab 693 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 694 }
80c39712
TV		 695 }
696}
697
80c39712 698
6e5264b0
AT		 699static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
700 const struct color_conv_coef *ct)
701{
80c39712
TV		 702#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
703
6e5264b0
AT		 704 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
705 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
706 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
707 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
708 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 709
6e5264b0 710 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 711
712#undef CVAL
80c39712
TV		 713}
714
6e5264b0
AT		 715static void dispc_setup_color_conv_coef(void)
716{
717 int i;
718 int num_ovl = dss_feat_get_num_ovls();
719 int num_wb = dss_feat_get_num_wbs();
720 const struct color_conv_coef ctbl_bt601_5_ovl = {
721 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
722 };
723 const struct color_conv_coef ctbl_bt601_5_wb = {
724 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
725 };
726
727 for (i = 1; i < num_ovl; i++)
728 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
729
730 for (; i < num_wb; i++)
731 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
732}
80c39712 733
f0e5caab 734static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 735{
9b372c2d 736 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 737}
738
f0e5caab 739static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 740{
9b372c2d 741 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 742}
743
f0e5caab 744static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 745{
746 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
747}
748
f0e5caab 749static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 750{
751 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
752}
753
d79db853
AT		 754static void dispc_ovl_set_pos(enum omap_plane plane,
755 enum omap_overlay_caps caps, int x, int y)
80c39712 756{
d79db853
AT		 757 u32 val;
758
759 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
760 return;
761
762 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 763
764 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 765}
766
78b687fc
AT		 767static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
768 int height)
80c39712 769{
80c39712 770 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 771
36d87d95 772 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 773 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
774 else
775 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 776}
777
78b687fc
AT		 778static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
779 int height)
80c39712
TV		 780{
781 u32 val;
80c39712
TV		 782
783 BUG_ON(plane == OMAP_DSS_GFX);
784
785 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 786
36d87d95
AT		 787 if (plane == OMAP_DSS_WB)
788 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
789 else
790 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 791}
792
5b54ed3e
AT		 793static void dispc_ovl_set_zorder(enum omap_plane plane,
794 enum omap_overlay_caps caps, u8 zorder)
54128701 795{
5b54ed3e 796 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 797 return;
798
799 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
800}
801
802static void dispc_ovl_enable_zorder_planes(void)
803{
804 int i;
805
806 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
807 return;
808
809 for (i = 0; i < dss_feat_get_num_ovls(); i++)
810 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
811}
812
5b54ed3e
AT		 813static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
814 enum omap_overlay_caps caps, bool enable)
fd28a390 815{
5b54ed3e 816 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 817 return;
818
9b372c2d 819 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 820}
821
5b54ed3e
AT		 822static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
823 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 824{
b8c095b4 825 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 826 int shift;
827
5b54ed3e 828 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 829 return;
a0acb557 830
fe3cc9d6
TV		 831 shift = shifts[plane];
832 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 833}
834
f0e5caab 835static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 836{
9b372c2d 837 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 838}
839
f0e5caab 840static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 841{
9b372c2d 842 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 843}
844
f0e5caab 845static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 846 enum omap_color_mode color_mode)
847{
848 u32 m = 0;
f20e4220
AJ		 849 if (plane != OMAP_DSS_GFX) {
850 switch (color_mode) {
851 case OMAP_DSS_COLOR_NV12:
852 m = 0x0; break;
08f3267e 853 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 854 m = 0x1; break;
855 case OMAP_DSS_COLOR_RGBA16:
856 m = 0x2; break;
08f3267e 857 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 858 m = 0x4; break;
859 case OMAP_DSS_COLOR_ARGB16:
860 m = 0x5; break;
861 case OMAP_DSS_COLOR_RGB16:
862 m = 0x6; break;
863 case OMAP_DSS_COLOR_ARGB16_1555:
864 m = 0x7; break;
865 case OMAP_DSS_COLOR_RGB24U:
866 m = 0x8; break;
867 case OMAP_DSS_COLOR_RGB24P:
868 m = 0x9; break;
869 case OMAP_DSS_COLOR_YUV2:
870 m = 0xa; break;
871 case OMAP_DSS_COLOR_UYVY:
872 m = 0xb; break;
873 case OMAP_DSS_COLOR_ARGB32:
874 m = 0xc; break;
875 case OMAP_DSS_COLOR_RGBA32:
876 m = 0xd; break;
877 case OMAP_DSS_COLOR_RGBX32:
878 m = 0xe; break;
879 case OMAP_DSS_COLOR_XRGB16_1555:
880 m = 0xf; break;
881 default:
c6eee968 882 BUG(); return;
f20e4220
AJ		 883 }
884 } else {
885 switch (color_mode) {
886 case OMAP_DSS_COLOR_CLUT1:
887 m = 0x0; break;
888 case OMAP_DSS_COLOR_CLUT2:
889 m = 0x1; break;
890 case OMAP_DSS_COLOR_CLUT4:
891 m = 0x2; break;
892 case OMAP_DSS_COLOR_CLUT8:
893 m = 0x3; break;
894 case OMAP_DSS_COLOR_RGB12U:
895 m = 0x4; break;
896 case OMAP_DSS_COLOR_ARGB16:
897 m = 0x5; break;
898 case OMAP_DSS_COLOR_RGB16:
899 m = 0x6; break;
900 case OMAP_DSS_COLOR_ARGB16_1555:
901 m = 0x7; break;
902 case OMAP_DSS_COLOR_RGB24U:
903 m = 0x8; break;
904 case OMAP_DSS_COLOR_RGB24P:
905 m = 0x9; break;
08f3267e 906 case OMAP_DSS_COLOR_RGBX16:
f20e4220 907 m = 0xa; break;
08f3267e 908 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 909 m = 0xb; break;
910 case OMAP_DSS_COLOR_ARGB32:
911 m = 0xc; break;
912 case OMAP_DSS_COLOR_RGBA32:
913 m = 0xd; break;
914 case OMAP_DSS_COLOR_RGBX32:
915 m = 0xe; break;
916 case OMAP_DSS_COLOR_XRGB16_1555:
917 m = 0xf; break;
918 default:
c6eee968 919 BUG(); return;
f20e4220 920 }
80c39712
TV		 921 }
922
9b372c2d 923 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 924}
925
65e006ff
CM		 926static void dispc_ovl_configure_burst_type(enum omap_plane plane,
927 enum omap_dss_rotation_type rotation_type)
928{
929 if (dss_has_feature(FEAT_BURST_2D) == 0)
930 return;
931
932 if (rotation_type == OMAP_DSS_ROT_TILER)
933 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
934 else
935 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
936}
937
f427984e 938void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 939{
940 int shift;
941 u32 val;
2a205f34 942 int chan = 0, chan2 = 0;
80c39712
TV		 943
944 switch (plane) {
945 case OMAP_DSS_GFX:
946 shift = 8;
947 break;
948 case OMAP_DSS_VIDEO1:
949 case OMAP_DSS_VIDEO2:
b8c095b4 950 case OMAP_DSS_VIDEO3:
80c39712
TV		 951 shift = 16;
952 break;
953 default:
954 BUG();
955 return;
956 }
957
9b372c2d 958 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 959 if (dss_has_feature(FEAT_MGR_LCD2)) {
960 switch (channel) {
961 case OMAP_DSS_CHANNEL_LCD:
962 chan = 0;
963 chan2 = 0;
964 break;
965 case OMAP_DSS_CHANNEL_DIGIT:
966 chan = 1;
967 chan2 = 0;
968 break;
969 case OMAP_DSS_CHANNEL_LCD2:
970 chan = 0;
971 chan2 = 1;
972 break;
e86d456a
CM		 973 case OMAP_DSS_CHANNEL_LCD3:
974 if (dss_has_feature(FEAT_MGR_LCD3)) {
975 chan = 0;
976 chan2 = 2;
977 } else {
978 BUG();
979 return;
980 }
981 break;
2a205f34
SS		 982 default:
983 BUG();
c6eee968 984 return;
2a205f34
SS		 985 }
986
987 val = FLD_MOD(val, chan, shift, shift);
988 val = FLD_MOD(val, chan2, 31, 30);
989 } else {
990 val = FLD_MOD(val, channel, shift, shift);
991 }
9b372c2d 992 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 993}
994
2cc5d1af
TV		 995static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
996{
997 int shift;
998 u32 val;
999 enum omap_channel channel;
1000
1001 switch (plane) {
1002 case OMAP_DSS_GFX:
1003 shift = 8;
1004 break;
1005 case OMAP_DSS_VIDEO1:
1006 case OMAP_DSS_VIDEO2:
1007 case OMAP_DSS_VIDEO3:
1008 shift = 16;
1009 break;
1010 default:
1011 BUG();
c6eee968 1012 return 0;
2cc5d1af
TV		 1013 }
1014
1015 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1016
e86d456a
CM		 1017 if (dss_has_feature(FEAT_MGR_LCD3)) {
1018 if (FLD_GET(val, 31, 30) == 0)
1019 channel = FLD_GET(val, shift, shift);
1020 else if (FLD_GET(val, 31, 30) == 1)
1021 channel = OMAP_DSS_CHANNEL_LCD2;
1022 else
1023 channel = OMAP_DSS_CHANNEL_LCD3;
1024 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1025 if (FLD_GET(val, 31, 30) == 0)
1026 channel = FLD_GET(val, shift, shift);
1027 else
1028 channel = OMAP_DSS_CHANNEL_LCD2;
1029 } else {
1030 channel = FLD_GET(val, shift, shift);
1031 }
1032
1033 return channel;
1034}
1035
d9ac773c
AT		 1036void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1037{
1038 enum omap_plane plane = OMAP_DSS_WB;
1039
1040 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1041}
1042
f0e5caab 1043static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1044 enum omap_burst_size burst_size)
1045{
8bbe09ee 1046 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1047 int shift;
80c39712 1048
fe3cc9d6 1049 shift = shifts[plane];
5ed8cf5b 1050 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1051}
1052
5ed8cf5b
TV		 1053static void dispc_configure_burst_sizes(void)
1054{
1055 int i;
1056 const int burst_size = BURST_SIZE_X8;
1057
1058 /* Configure burst size always to maximum size */
392faa0e 1059 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1060 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1061}
1062
83fa2f2e 1063static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1064{
1065 unsigned unit = dss_feat_get_burst_size_unit();
1066 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1067 return unit * 8;
1068}
1069
d3862610
M		 1070void dispc_enable_gamma_table(bool enable)
1071{
1072 /*
1073 * This is partially implemented to support only disabling of
1074 * the gamma table.
1075 */
1076 if (enable) {
1077 DSSWARN("Gamma table enabling for TV not yet supported");
1078 return;
1079 }
1080
1081 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1082}
1083
c64dca40 1084static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1085{
efa70b3b 1086 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1087 return;
1088
efa70b3b 1089 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1090}
1091
c64dca40 1092static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1093 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1094{
1095 u32 coef_r, coef_g, coef_b;
1096
dd88b7a6 1097 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1098 return;
1099
1100 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1101 FLD_VAL(coefs->rb, 9, 0);
1102 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1103 FLD_VAL(coefs->gb, 9, 0);
1104 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1105 FLD_VAL(coefs->bb, 9, 0);
1106
1107 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1108 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1109 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1110}
1111
f0e5caab 1112static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1113{
1114 u32 val;
1115
1116 BUG_ON(plane == OMAP_DSS_GFX);
1117
9b372c2d 1118 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1119 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1120 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1121}
1122
d79db853
AT		 1123static void dispc_ovl_enable_replication(enum omap_plane plane,
1124 enum omap_overlay_caps caps, bool enable)
80c39712 1125{
b8c095b4 1126 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1127 int shift;
80c39712 1128
d79db853
AT		 1129 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1130 return;
1131
fe3cc9d6
TV		 1132 shift = shifts[plane];
1133 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1134}
1135
8f366162 1136static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1137 u16 height)
80c39712
TV		 1138{
1139 u32 val;
80c39712 1140
33b89928
AT		 1141 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1142 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1143
8f366162 1144 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1145}
1146
42a6961c 1147static void dispc_init_fifos(void)
80c39712 1148{
80c39712 1149 u32 size;
42a6961c 1150 int fifo;
a0acb557 1151 u8 start, end;
5ed8cf5b
TV		 1152 u32 unit;
1153
1154 unit = dss_feat_get_buffer_size_unit();
80c39712 1155
a0acb557 1156 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1157
42a6961c
TV		 1158 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1159 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1160 size *= unit;
42a6961c
TV		 1161 dispc.fifo_size[fifo] = size;
1162
1163 /*
1164 * By default fifos are mapped directly to overlays, fifo 0 to
1165 * ovl 0, fifo 1 to ovl 1, etc.
1166 */
1167 dispc.fifo_assignment[fifo] = fifo;
80c39712 1168 }
66a0f9e4
TV		 1169
1170 /*
1171 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1172 * causes problems with certain use cases, like using the tiler in 2D
1173 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1174 * giving GFX plane a larger fifo. WB but should work fine with a
1175 * smaller fifo.
1176 */
1177 if (dispc.feat->gfx_fifo_workaround) {
1178 u32 v;
1179
1180 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1181
1182 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1183 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1184 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1185 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1186
1187 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1188
1189 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1190 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1191 }
80c39712
TV		 1192}
1193
83fa2f2e 1194static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1195{
42a6961c
TV		 1196 int fifo;
1197 u32 size = 0;
1198
1199 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1200 if (dispc.fifo_assignment[fifo] == plane)
1201 size += dispc.fifo_size[fifo];
1202 }
1203
1204 return size;
80c39712
TV		 1205}
1206
6f04e1bf 1207void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1208{
a0acb557 1209 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1210 u32 unit;
1211
1212 unit = dss_feat_get_buffer_size_unit();
1213
1214 WARN_ON(low % unit != 0);
1215 WARN_ON(high % unit != 0);
1216
1217 low /= unit;
1218 high /= unit;
a0acb557 1219
9b372c2d
AT		 1220 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1221 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1222
3cb5d966 1223 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1224 plane,
9b372c2d 1225 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1226 lo_start, lo_end) * unit,
9b372c2d 1227 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1228 hi_start, hi_end) * unit,
1229 low * unit, high * unit);
80c39712 1230
9b372c2d 1231 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1232 FLD_VAL(high, hi_start, hi_end) |
1233 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1234}
1235
1236void dispc_enable_fifomerge(bool enable)
1237{
e6b0f884
TV		 1238 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1239 WARN_ON(enable);
1240 return;
1241 }
1242
80c39712
TV		 1243 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1244 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1245}
1246
83fa2f2e 1247void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1248 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1249 bool manual_update)
83fa2f2e
TV		 1250{
1251 /*
1252 * All sizes are in bytes. Both the buffer and burst are made of
1253 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1254 */
1255
1256 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1257 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1258 int i;
83fa2f2e
TV		 1259
1260 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1261 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1262
e0e405b9
TV		 1263 if (use_fifomerge) {
1264 total_fifo_size = 0;
392faa0e 1265 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1266 total_fifo_size += dispc_ovl_get_fifo_size(i);
1267 } else {
1268 total_fifo_size = ovl_fifo_size;
1269 }
1270
1271 /*
1272 * We use the same low threshold for both fifomerge and non-fifomerge
1273 * cases, but for fifomerge we calculate the high threshold using the
1274 * combined fifo size
1275 */
1276
3568f2a4 1277 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1278 *fifo_low = ovl_fifo_size - burst_size * 2;
1279 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1280 } else if (plane == OMAP_DSS_WB) {
1281 /*
1282 * Most optimal configuration for writeback is to push out data
1283 * to the interconnect the moment writeback pushes enough pixels
1284 * in the FIFO to form a burst
1285 */
1286 *fifo_low = 0;
1287 *fifo_high = burst_size;
e0e405b9
TV		 1288 } else {
1289 *fifo_low = ovl_fifo_size - burst_size;
1290 *fifo_high = total_fifo_size - buf_unit;
1291 }
83fa2f2e
TV		 1292}
1293
f0e5caab 1294static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1295 int hinc, int vinc,
1296 enum omap_color_component color_comp)
80c39712
TV		 1297{
1298 u32 val;
80c39712 1299
0d66cbb5
AJ		 1300 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1301 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1302
0d66cbb5
AJ		 1303 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1304 &hinc_start, &hinc_end);
1305 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1306 &vinc_start, &vinc_end);
1307 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1308 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1309
0d66cbb5
AJ		 1310 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1311 } else {
1312 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1313 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1314 }
80c39712
TV		 1315}
1316
f0e5caab 1317static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1318{
1319 u32 val;
87a7484b 1320 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1321
87a7484b
AT		 1322 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1323 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1324
1325 val = FLD_VAL(vaccu, vert_start, vert_end) |
1326 FLD_VAL(haccu, hor_start, hor_end);
1327
9b372c2d 1328 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1329}
1330
f0e5caab 1331static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1332{
1333 u32 val;
87a7484b 1334 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1335
87a7484b
AT		 1336 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1337 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1338
1339 val = FLD_VAL(vaccu, vert_start, vert_end) |
1340 FLD_VAL(haccu, hor_start, hor_end);
1341
9b372c2d 1342 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1343}
1344
f0e5caab
TV		 1345static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1346 int vaccu)
ab5ca071
AJ		 1347{
1348 u32 val;
1349
1350 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1351 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1352}
1353
f0e5caab
TV		 1354static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1355 int vaccu)
ab5ca071
AJ		 1356{
1357 u32 val;
1358
1359 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1360 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1361}
80c39712 1362
f0e5caab 1363static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1364 u16 orig_width, u16 orig_height,
1365 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1366 bool five_taps, u8 rotation,
1367 enum omap_color_component color_comp)
80c39712 1368{
0d66cbb5 1369 int fir_hinc, fir_vinc;
80c39712 1370
ed14a3ce
AJ		 1371 fir_hinc = 1024 * orig_width / out_width;
1372 fir_vinc = 1024 * orig_height / out_height;
80c39712 1373
debd9074
CM		 1374 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1375 color_comp);
f0e5caab 1376 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1377}
1378
05dd0f53
CM		 1379static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1380 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1381 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1382{
1383 int h_accu2_0, h_accu2_1;
1384 int v_accu2_0, v_accu2_1;
1385 int chroma_hinc, chroma_vinc;
1386 int idx;
1387
1388 struct accu {
1389 s8 h0_m, h0_n;
1390 s8 h1_m, h1_n;
1391 s8 v0_m, v0_n;
1392 s8 v1_m, v1_n;
1393 };
1394
1395 const struct accu *accu_table;
1396 const struct accu *accu_val;
1397
1398 static const struct accu accu_nv12[4] = {
1399 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1400 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1401 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1402 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1403 };
1404
1405 static const struct accu accu_nv12_ilace[4] = {
1406 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1407 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1408 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1409 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1410 };
1411
1412 static const struct accu accu_yuv[4] = {
1413 { 0, 1, 0, 1, 0, 1, 0, 1 },
1414 { 0, 1, 0, 1, 0, 1, 0, 1 },
1415 { -1, 1, 0, 1, 0, 1, 0, 1 },
1416 { 0, 1, 0, 1, -1, 1, 0, 1 },
1417 };
1418
1419 switch (rotation) {
1420 case OMAP_DSS_ROT_0:
1421 idx = 0;
1422 break;
1423 case OMAP_DSS_ROT_90:
1424 idx = 1;
1425 break;
1426 case OMAP_DSS_ROT_180:
1427 idx = 2;
1428 break;
1429 case OMAP_DSS_ROT_270:
1430 idx = 3;
1431 break;
1432 default:
1433 BUG();
c6eee968 1434 return;
05dd0f53
CM		 1435 }
1436
1437 switch (color_mode) {
1438 case OMAP_DSS_COLOR_NV12:
1439 if (ilace)
1440 accu_table = accu_nv12_ilace;
1441 else
1442 accu_table = accu_nv12;
1443 break;
1444 case OMAP_DSS_COLOR_YUV2:
1445 case OMAP_DSS_COLOR_UYVY:
1446 accu_table = accu_yuv;
1447 break;
1448 default:
1449 BUG();
c6eee968 1450 return;
05dd0f53
CM		 1451 }
1452
1453 accu_val = &accu_table[idx];
1454
1455 chroma_hinc = 1024 * orig_width / out_width;
1456 chroma_vinc = 1024 * orig_height / out_height;
1457
1458 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1459 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1460 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1461 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1462
1463 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1464 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1465}
1466
f0e5caab 1467static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1468 u16 orig_width, u16 orig_height,
1469 u16 out_width, u16 out_height,
1470 bool ilace, bool five_taps,
1471 bool fieldmode, enum omap_color_mode color_mode,
1472 u8 rotation)
1473{
1474 int accu0 = 0;
1475 int accu1 = 0;
1476 u32 l;
80c39712 1477
f0e5caab 1478 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1479 out_width, out_height, five_taps,
1480 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1481 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1482
87a7484b
AT		 1483 /* RESIZEENABLE and VERTICALTAPS */
1484 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1485 l |= (orig_width != out_width) ? (1 << 5) : 0;
1486 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1487 l |= five_taps ? (1 << 21) : 0;
80c39712 1488
87a7484b
AT		 1489 /* VRESIZECONF and HRESIZECONF */
1490 if (dss_has_feature(FEAT_RESIZECONF)) {
1491 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1492 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1493 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1494 }
80c39712 1495
87a7484b
AT		 1496 /* LINEBUFFERSPLIT */
1497 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1498 l &= ~(0x1 << 22);
1499 l |= five_taps ? (1 << 22) : 0;
1500 }
80c39712 1501
9b372c2d 1502 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1503
1504 /*
1505 * field 0 = even field = bottom field
1506 * field 1 = odd field = top field
1507 */
1508 if (ilace && !fieldmode) {
1509 accu1 = 0;
0d66cbb5 1510 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1511 if (accu0 >= 1024/2) {
1512 accu1 = 1024/2;
1513 accu0 -= accu1;
1514 }
1515 }
1516
f0e5caab
TV		 1517 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1518 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1519}
1520
f0e5caab 1521static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1522 u16 orig_width, u16 orig_height,
1523 u16 out_width, u16 out_height,
1524 bool ilace, bool five_taps,
1525 bool fieldmode, enum omap_color_mode color_mode,
1526 u8 rotation)
1527{
1528 int scale_x = out_width != orig_width;
1529 int scale_y = out_height != orig_height;
f92afae2 1530 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1531
1532 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1533 return;
1534 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1535 color_mode != OMAP_DSS_COLOR_UYVY &&
1536 color_mode != OMAP_DSS_COLOR_NV12)) {
1537 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1538 if (plane != OMAP_DSS_WB)
1539 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1540 return;
1541 }
36377357
TV		 1542
1543 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1544 out_height, ilace, color_mode, rotation);
1545
0d66cbb5
AJ		 1546 switch (color_mode) {
1547 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1548 if (chroma_upscale) {
1549 /* UV is subsampled by 2 horizontally and vertically */
1550 orig_height >>= 1;
1551 orig_width >>= 1;
1552 } else {
1553 /* UV is downsampled by 2 horizontally and vertically */
1554 orig_height <<= 1;
1555 orig_width <<= 1;
1556 }
1557
0d66cbb5
AJ		 1558 break;
1559 case OMAP_DSS_COLOR_YUV2:
1560 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1561 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1562 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1563 rotation == OMAP_DSS_ROT_180) {
1564 if (chroma_upscale)
1565 /* UV is subsampled by 2 horizontally */
1566 orig_width >>= 1;
1567 else
1568 /* UV is downsampled by 2 horizontally */
1569 orig_width <<= 1;
1570 }
1571
0d66cbb5
AJ		 1572 /* must use FIR for YUV422 if rotated */
1573 if (rotation != OMAP_DSS_ROT_0)
1574 scale_x = scale_y = true;
20fbb50b 1575
0d66cbb5
AJ		 1576 break;
1577 default:
1578 BUG();
c6eee968 1579 return;
0d66cbb5
AJ		 1580 }
1581
1582 if (out_width != orig_width)
1583 scale_x = true;
1584 if (out_height != orig_height)
1585 scale_y = true;
1586
f0e5caab 1587 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1588 out_width, out_height, five_taps,
1589 rotation, DISPC_COLOR_COMPONENT_UV);
1590
2a5561b1
AT		 1591 if (plane != OMAP_DSS_WB)
1592 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1593 (scale_x || scale_y) ? 1 : 0, 8, 8);
1594
0d66cbb5
AJ		 1595 /* set H scaling */
1596 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1597 /* set V scaling */
1598 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1599}
1600
f0e5caab 1601static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1602 u16 orig_width, u16 orig_height,
1603 u16 out_width, u16 out_height,
1604 bool ilace, bool five_taps,
1605 bool fieldmode, enum omap_color_mode color_mode,
1606 u8 rotation)
1607{
1608 BUG_ON(plane == OMAP_DSS_GFX);
1609
f0e5caab 1610 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1611 orig_width, orig_height,
1612 out_width, out_height,
1613 ilace, five_taps,
1614 fieldmode, color_mode,
1615 rotation);
1616
f0e5caab 1617 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1618 orig_width, orig_height,
1619 out_width, out_height,
1620 ilace, five_taps,
1621 fieldmode, color_mode,
1622 rotation);
1623}
1624
f0e5caab 1625static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1626 bool mirroring, enum omap_color_mode color_mode)
1627{
87a7484b
AT		 1628 bool row_repeat = false;
1629 int vidrot = 0;
1630
80c39712
TV		 1631 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1632 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1633
1634 if (mirroring) {
1635 switch (rotation) {
1636 case OMAP_DSS_ROT_0:
1637 vidrot = 2;
1638 break;
1639 case OMAP_DSS_ROT_90:
1640 vidrot = 1;
1641 break;
1642 case OMAP_DSS_ROT_180:
1643 vidrot = 0;
1644 break;
1645 case OMAP_DSS_ROT_270:
1646 vidrot = 3;
1647 break;
1648 }
1649 } else {
1650 switch (rotation) {
1651 case OMAP_DSS_ROT_0:
1652 vidrot = 0;
1653 break;
1654 case OMAP_DSS_ROT_90:
1655 vidrot = 1;
1656 break;
1657 case OMAP_DSS_ROT_180:
1658 vidrot = 2;
1659 break;
1660 case OMAP_DSS_ROT_270:
1661 vidrot = 3;
1662 break;
1663 }
1664 }
1665
80c39712 1666 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1667 row_repeat = true;
80c39712 1668 else
87a7484b 1669 row_repeat = false;
80c39712 1670 }
87a7484b 1671
9b372c2d 1672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1673 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1674 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1675 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1676}
1677
1678static int color_mode_to_bpp(enum omap_color_mode color_mode)
1679{
1680 switch (color_mode) {
1681 case OMAP_DSS_COLOR_CLUT1:
1682 return 1;
1683 case OMAP_DSS_COLOR_CLUT2:
1684 return 2;
1685 case OMAP_DSS_COLOR_CLUT4:
1686 return 4;
1687 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1688 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1689 return 8;
1690 case OMAP_DSS_COLOR_RGB12U:
1691 case OMAP_DSS_COLOR_RGB16:
1692 case OMAP_DSS_COLOR_ARGB16:
1693 case OMAP_DSS_COLOR_YUV2:
1694 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1695 case OMAP_DSS_COLOR_RGBA16:
1696 case OMAP_DSS_COLOR_RGBX16:
1697 case OMAP_DSS_COLOR_ARGB16_1555:
1698 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1699 return 16;
1700 case OMAP_DSS_COLOR_RGB24P:
1701 return 24;
1702 case OMAP_DSS_COLOR_RGB24U:
1703 case OMAP_DSS_COLOR_ARGB32:
1704 case OMAP_DSS_COLOR_RGBA32:
1705 case OMAP_DSS_COLOR_RGBX32:
1706 return 32;
1707 default:
1708 BUG();
c6eee968 1709 return 0;
80c39712
TV		 1710 }
1711}
1712
1713static s32 pixinc(int pixels, u8 ps)
1714{
1715 if (pixels == 1)
1716 return 1;
1717 else if (pixels > 1)
1718 return 1 + (pixels - 1) * ps;
1719 else if (pixels < 0)
1720 return 1 - (-pixels + 1) * ps;
1721 else
1722 BUG();
c6eee968 1723 return 0;
80c39712
TV		 1724}
1725
1726static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1727 u16 screen_width,
1728 u16 width, u16 height,
1729 enum omap_color_mode color_mode, bool fieldmode,
1730 unsigned int field_offset,
1731 unsigned *offset0, unsigned *offset1,
aed74b55 1732 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1733{
1734 u8 ps;
1735
1736 /* FIXME CLUT formats */
1737 switch (color_mode) {
1738 case OMAP_DSS_COLOR_CLUT1:
1739 case OMAP_DSS_COLOR_CLUT2:
1740 case OMAP_DSS_COLOR_CLUT4:
1741 case OMAP_DSS_COLOR_CLUT8:
1742 BUG();
1743 return;
1744 case OMAP_DSS_COLOR_YUV2:
1745 case OMAP_DSS_COLOR_UYVY:
1746 ps = 4;
1747 break;
1748 default:
1749 ps = color_mode_to_bpp(color_mode) / 8;
1750 break;
1751 }
1752
1753 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1754 width, height);
1755
1756 /*
1757 * field 0 = even field = bottom field
1758 * field 1 = odd field = top field
1759 */
1760 switch (rotation + mirror * 4) {
1761 case OMAP_DSS_ROT_0:
1762 case OMAP_DSS_ROT_180:
1763 /*
1764 * If the pixel format is YUV or UYVY divide the width
1765 * of the image by 2 for 0 and 180 degree rotation.
1766 */
1767 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1768 color_mode == OMAP_DSS_COLOR_UYVY)
1769 width = width >> 1;
1770 case OMAP_DSS_ROT_90:
1771 case OMAP_DSS_ROT_270:
1772 *offset1 = 0;
1773 if (field_offset)
1774 *offset0 = field_offset * screen_width * ps;
1775 else
1776 *offset0 = 0;
1777
aed74b55
CM		 1778 *row_inc = pixinc(1 +
1779 (y_predecim * screen_width - x_predecim * width) +
1780 (fieldmode ? screen_width : 0), ps);
1781 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1782 break;
1783
1784 case OMAP_DSS_ROT_0 + 4:
1785 case OMAP_DSS_ROT_180 + 4:
1786 /* If the pixel format is YUV or UYVY divide the width
1787 * of the image by 2 for 0 degree and 180 degree
1788 */
1789 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1790 color_mode == OMAP_DSS_COLOR_UYVY)
1791 width = width >> 1;
1792 case OMAP_DSS_ROT_90 + 4:
1793 case OMAP_DSS_ROT_270 + 4:
1794 *offset1 = 0;
1795 if (field_offset)
1796 *offset0 = field_offset * screen_width * ps;
1797 else
1798 *offset0 = 0;
aed74b55
CM		 1799 *row_inc = pixinc(1 -
1800 (y_predecim * screen_width + x_predecim * width) -
1801 (fieldmode ? screen_width : 0), ps);
1802 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1803 break;
1804
1805 default:
1806 BUG();
c6eee968 1807 return;
80c39712
TV		 1808 }
1809}
1810
1811static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1812 u16 screen_width,
1813 u16 width, u16 height,
1814 enum omap_color_mode color_mode, bool fieldmode,
1815 unsigned int field_offset,
1816 unsigned *offset0, unsigned *offset1,
aed74b55 1817 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1818{
1819 u8 ps;
1820 u16 fbw, fbh;
1821
1822 /* FIXME CLUT formats */
1823 switch (color_mode) {
1824 case OMAP_DSS_COLOR_CLUT1:
1825 case OMAP_DSS_COLOR_CLUT2:
1826 case OMAP_DSS_COLOR_CLUT4:
1827 case OMAP_DSS_COLOR_CLUT8:
1828 BUG();
1829 return;
1830 default:
1831 ps = color_mode_to_bpp(color_mode) / 8;
1832 break;
1833 }
1834
1835 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1836 width, height);
1837
1838 /* width & height are overlay sizes, convert to fb sizes */
1839
1840 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1841 fbw = width;
1842 fbh = height;
1843 } else {
1844 fbw = height;
1845 fbh = width;
1846 }
1847
1848 /*
1849 * field 0 = even field = bottom field
1850 * field 1 = odd field = top field
1851 */
1852 switch (rotation + mirror * 4) {
1853 case OMAP_DSS_ROT_0:
1854 *offset1 = 0;
1855 if (field_offset)
1856 *offset0 = *offset1 + field_offset * screen_width * ps;
1857 else
1858 *offset0 = *offset1;
aed74b55
CM		 1859 *row_inc = pixinc(1 +
1860 (y_predecim * screen_width - fbw * x_predecim) +
1861 (fieldmode ? screen_width : 0), ps);
1862 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1863 color_mode == OMAP_DSS_COLOR_UYVY)
1864 *pix_inc = pixinc(x_predecim, 2 * ps);
1865 else
1866 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1867 break;
1868 case OMAP_DSS_ROT_90:
1869 *offset1 = screen_width * (fbh - 1) * ps;
1870 if (field_offset)
1871 *offset0 = *offset1 + field_offset * ps;
1872 else
1873 *offset0 = *offset1;
aed74b55
CM		 1874 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1875 y_predecim + (fieldmode ? 1 : 0), ps);
1876 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1877 break;
1878 case OMAP_DSS_ROT_180:
1879 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1880 if (field_offset)
1881 *offset0 = *offset1 - field_offset * screen_width * ps;
1882 else
1883 *offset0 = *offset1;
1884 *row_inc = pixinc(-1 -
aed74b55
CM		 1885 (y_predecim * screen_width - fbw * x_predecim) -
1886 (fieldmode ? screen_width : 0), ps);
1887 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1888 color_mode == OMAP_DSS_COLOR_UYVY)
1889 *pix_inc = pixinc(-x_predecim, 2 * ps);
1890 else
1891 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1892 break;
1893 case OMAP_DSS_ROT_270:
1894 *offset1 = (fbw - 1) * ps;
1895 if (field_offset)
1896 *offset0 = *offset1 - field_offset * ps;
1897 else
1898 *offset0 = *offset1;
aed74b55
CM		 1899 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1900 y_predecim - (fieldmode ? 1 : 0), ps);
1901 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1902 break;
1903
1904 /* mirroring */
1905 case OMAP_DSS_ROT_0 + 4:
1906 *offset1 = (fbw - 1) * ps;
1907 if (field_offset)
1908 *offset0 = *offset1 + field_offset * screen_width * ps;
1909 else
1910 *offset0 = *offset1;
aed74b55 1911 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1912 (fieldmode ? screen_width : 0),
1913 ps);
aed74b55
CM		 1914 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1915 color_mode == OMAP_DSS_COLOR_UYVY)
1916 *pix_inc = pixinc(-x_predecim, 2 * ps);
1917 else
1918 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1919 break;
1920
1921 case OMAP_DSS_ROT_90 + 4:
1922 *offset1 = 0;
1923 if (field_offset)
1924 *offset0 = *offset1 + field_offset * ps;
1925 else
1926 *offset0 = *offset1;
aed74b55
CM		 1927 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1928 y_predecim + (fieldmode ? 1 : 0),
80c39712 1929 ps);
aed74b55 1930 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1931 break;
1932
1933 case OMAP_DSS_ROT_180 + 4:
1934 *offset1 = screen_width * (fbh - 1) * ps;
1935 if (field_offset)
1936 *offset0 = *offset1 - field_offset * screen_width * ps;
1937 else
1938 *offset0 = *offset1;
aed74b55 1939 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1940 (fieldmode ? screen_width : 0),
1941 ps);
aed74b55
CM		 1942 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1943 color_mode == OMAP_DSS_COLOR_UYVY)
1944 *pix_inc = pixinc(x_predecim, 2 * ps);
1945 else
1946 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1947 break;
1948
1949 case OMAP_DSS_ROT_270 + 4:
1950 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1951 if (field_offset)
1952 *offset0 = *offset1 - field_offset * ps;
1953 else
1954 *offset0 = *offset1;
aed74b55
CM		 1955 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1956 y_predecim - (fieldmode ? 1 : 0),
80c39712 1957 ps);
aed74b55 1958 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1959 break;
1960
1961 default:
1962 BUG();
c6eee968 1963 return;
80c39712
TV		 1964 }
1965}
1966
65e006ff
CM		 1967static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1968 enum omap_color_mode color_mode, bool fieldmode,
1969 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1970 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1971{
1972 u8 ps;
1973
1974 switch (color_mode) {
1975 case OMAP_DSS_COLOR_CLUT1:
1976 case OMAP_DSS_COLOR_CLUT2:
1977 case OMAP_DSS_COLOR_CLUT4:
1978 case OMAP_DSS_COLOR_CLUT8:
1979 BUG();
1980 return;
1981 default:
1982 ps = color_mode_to_bpp(color_mode) / 8;
1983 break;
1984 }
1985
1986 DSSDBG("scrw %d, width %d\n", screen_width, width);
1987
1988 /*
1989 * field 0 = even field = bottom field
1990 * field 1 = odd field = top field
1991 */
1992 *offset1 = 0;
1993 if (field_offset)
1994 *offset0 = *offset1 + field_offset * screen_width * ps;
1995 else
1996 *offset0 = *offset1;
1997 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1998 (fieldmode ? screen_width : 0), ps);
1999 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2000 color_mode == OMAP_DSS_COLOR_UYVY)
2001 *pix_inc = pixinc(x_predecim, 2 * ps);
2002 else
2003 *pix_inc = pixinc(x_predecim, ps);
2004}
2005
7faa9233
CM		 2006/*
2007 * This function is used to avoid synclosts in OMAP3, because of some
2008 * undocumented horizontal position and timing related limitations.
2009 */
3e8a6ff2 2010static int check_horiz_timing_omap3(enum omap_plane plane,
81ab95b7 2011 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 2012 u16 width, u16 height, u16 out_width, u16 out_height)
2013{
230edc03 2014 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2015 unsigned long nonactive;
7faa9233
CM		 2016 static const u8 limits[3] = { 8, 10, 20 };
2017 u64 val, blank;
3e8a6ff2
AT		 2018 unsigned long pclk = dispc_plane_pclk_rate(plane);
2019 unsigned long lclk = dispc_plane_lclk_rate(plane);
7faa9233
CM		 2020 int i;
2021
81ab95b7 2022 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2023
2024 i = 0;
2025 if (out_height < height)
2026 i++;
2027 if (out_width < width)
2028 i++;
81ab95b7 2029 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2030 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2031 if (blank <= limits[i])
2032 return -EINVAL;
2033
2034 /*
2035 * Pixel data should be prepared before visible display point starts.
2036 * So, atleast DS-2 lines must have already been fetched by DISPC
2037 * during nonactive - pos_x period.
2038 */
2039 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2040 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2041 val, max(0, ds - 2) * width);
2042 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2043 return -EINVAL;
2044
2045 /*
2046 * All lines need to be refilled during the nonactive period of which
2047 * only one line can be loaded during the active period. So, atleast
2048 * DS - 1 lines should be loaded during nonactive period.
2049 */
2050 val = div_u64((u64)nonactive * lclk, pclk);
2051 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2052 val, max(0, ds - 1) * width);
2053 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2054 return -EINVAL;
2055
2056 return 0;
2057}
2058
3e8a6ff2 2059static unsigned long calc_core_clk_five_taps(enum omap_plane plane,
81ab95b7
AT		 2060 const struct omap_video_timings *mgr_timings, u16 width,
2061 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2062 enum omap_color_mode color_mode)
80c39712 2063{
8b53d991 2064 u32 core_clk = 0;
3e8a6ff2
AT		 2065 u64 tmp;
2066 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712 2067
7282f1b7
CM		 2068 if (height <= out_height && width <= out_width)
2069 return (unsigned long) pclk;
2070
80c39712 2071 if (height > out_height) {
81ab95b7 2072 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2073
2074 tmp = pclk * height * out_width;
2075 do_div(tmp, 2 * out_height * ppl);
8b53d991 2076 core_clk = tmp;
80c39712 2077
2d9c5597
VS		 2078 if (height > 2 * out_height) {
2079 if (ppl == out_width)
2080 return 0;
2081
80c39712
TV		 2082 tmp = pclk * (height - 2 * out_height) * out_width;
2083 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2084 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2085 }
2086 }
2087
2088 if (width > out_width) {
2089 tmp = pclk * width;
2090 do_div(tmp, out_width);
8b53d991 2091 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2092
2093 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2094 core_clk <<= 1;
80c39712
TV		 2095 }
2096
8b53d991 2097 return core_clk;
80c39712
TV		 2098}
2099
3e8a6ff2 2100static unsigned long calc_core_clk_24xx(enum omap_plane plane, u16 width,
8ba85306 2101 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2102{
3e8a6ff2 2103 unsigned long pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2104
2105 if (height > out_height && width > out_width)
2106 return pclk * 4;
2107 else
2108 return pclk * 2;
2109}
2110
3e8a6ff2 2111static unsigned long calc_core_clk_34xx(enum omap_plane plane, u16 width,
8ba85306 2112 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2113{
2114 unsigned int hf, vf;
3e8a6ff2 2115 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712
TV		 2116
2117 /*
2118 * FIXME how to determine the 'A' factor
2119 * for the no downscaling case ?
2120 */
2121
2122 if (width > 3 * out_width)
2123 hf = 4;
2124 else if (width > 2 * out_width)
2125 hf = 3;
2126 else if (width > out_width)
2127 hf = 2;
2128 else
2129 hf = 1;
80c39712
TV		 2130 if (height > out_height)
2131 vf = 2;
2132 else
2133 vf = 1;
2134
dcbe765b
CM		 2135 return pclk * vf * hf;
2136}
2137
3e8a6ff2 2138static unsigned long calc_core_clk_44xx(enum omap_plane plane, u16 width,
8ba85306 2139 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2140{
8ba85306
AT		 2141 unsigned long pclk;
2142
2143 /*
2144 * If the overlay/writeback is in mem to mem mode, there are no
2145 * downscaling limitations with respect to pixel clock, return 1 as
2146 * required core clock to represent that we have sufficient enough
2147 * core clock to do maximum downscaling
2148 */
2149 if (mem_to_mem)
2150 return 1;
2151
2152 pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2153
2154 if (width > out_width)
2155 return DIV_ROUND_UP(pclk, out_width) * width;
2156 else
2157 return pclk;
2158}
2159
3e8a6ff2 2160static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
dcbe765b
CM		 2161 const struct omap_video_timings *mgr_timings,
2162 u16 width, u16 height, u16 out_width, u16 out_height,
2163 enum omap_color_mode color_mode, bool *five_taps,
2164 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2165 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2166{
2167 int error;
2168 u16 in_width, in_height;
2169 int min_factor = min(*decim_x, *decim_y);
2170 const int maxsinglelinewidth =
2171 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2172
dcbe765b
CM		 2173 *five_taps = false;
2174
2175 do {
2176 in_height = DIV_ROUND_UP(height, *decim_y);
2177 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2178 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306 2179 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2180 error = (in_width > maxsinglelinewidth || !*core_clk ||
2181 *core_clk > dispc_core_clk_rate());
2182 if (error) {
2183 if (*decim_x == *decim_y) {
2184 *decim_x = min_factor;
2185 ++*decim_y;
2186 } else {
2187 swap(*decim_x, *decim_y);
2188 if (*decim_x < *decim_y)
2189 ++*decim_x;
2190 }
2191 }
2192 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2193
2194 if (in_width > maxsinglelinewidth) {
2195 DSSERR("Cannot scale max input width exceeded");
2196 return -EINVAL;
2197 }
2198 return 0;
2199}
2200
3e8a6ff2 2201static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
dcbe765b
CM		 2202 const struct omap_video_timings *mgr_timings,
2203 u16 width, u16 height, u16 out_width, u16 out_height,
2204 enum omap_color_mode color_mode, bool *five_taps,
2205 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2206 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2207{
2208 int error;
2209 u16 in_width, in_height;
2210 int min_factor = min(*decim_x, *decim_y);
2211 const int maxsinglelinewidth =
2212 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2213
2214 do {
2215 in_height = DIV_ROUND_UP(height, *decim_y);
2216 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2217 *core_clk = calc_core_clk_five_taps(plane, mgr_timings,
dcbe765b
CM		 2218 in_width, in_height, out_width, out_height, color_mode);
2219
3e8a6ff2
AT		 2220 error = check_horiz_timing_omap3(plane, mgr_timings,
2221 pos_x, in_width, in_height, out_width,
2222 out_height);
dcbe765b
CM		 2223
2224 if (in_width > maxsinglelinewidth)
2225 if (in_height > out_height &&
2226 in_height < out_height * 2)
2227 *five_taps = false;
2228 if (!*five_taps)
3e8a6ff2 2229 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306
AT		 2230 in_height, out_width, out_height,
2231 mem_to_mem);
dcbe765b
CM		 2232
2233 error = (error || in_width > maxsinglelinewidth * 2 ||
2234 (in_width > maxsinglelinewidth && *five_taps) ||
2235 !*core_clk || *core_clk > dispc_core_clk_rate());
2236 if (error) {
2237 if (*decim_x == *decim_y) {
2238 *decim_x = min_factor;
2239 ++*decim_y;
2240 } else {
2241 swap(*decim_x, *decim_y);
2242 if (*decim_x < *decim_y)
2243 ++*decim_x;
2244 }
2245 }
2246 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2247
3e8a6ff2 2248 if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
dcbe765b
CM		 2249 out_width, out_height)){
2250 DSSERR("horizontal timing too tight\n");
2251 return -EINVAL;
7282f1b7 2252 }
dcbe765b
CM		 2253
2254 if (in_width > (maxsinglelinewidth * 2)) {
2255 DSSERR("Cannot setup scaling");
2256 DSSERR("width exceeds maximum width possible");
2257 return -EINVAL;
2258 }
2259
2260 if (in_width > maxsinglelinewidth && *five_taps) {
2261 DSSERR("cannot setup scaling with five taps");
2262 return -EINVAL;
2263 }
2264 return 0;
2265}
2266
3e8a6ff2 2267static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
dcbe765b
CM		 2268 const struct omap_video_timings *mgr_timings,
2269 u16 width, u16 height, u16 out_width, u16 out_height,
2270 enum omap_color_mode color_mode, bool *five_taps,
2271 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2272 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2273{
2274 u16 in_width, in_width_max;
2275 int decim_x_min = *decim_x;
2276 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2277 const int maxsinglelinewidth =
2278 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2279 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2280
5d501085
AT		 2281 if (mem_to_mem) {
2282 in_width_max = out_width * maxdownscale;
2283 } else {
2284 unsigned long pclk = dispc_plane_pclk_rate(plane);
2285
8ba85306
AT		 2286 in_width_max = dispc_core_clk_rate() /
2287 DIV_ROUND_UP(pclk, out_width);
5d501085 2288 }
dcbe765b 2289
dcbe765b
CM		 2290 *decim_x = DIV_ROUND_UP(width, in_width_max);
2291
2292 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2293 if (*decim_x > *x_predecim)
2294 return -EINVAL;
2295
2296 do {
2297 in_width = DIV_ROUND_UP(width, *decim_x);
2298 } while (*decim_x <= *x_predecim &&
2299 in_width > maxsinglelinewidth && ++*decim_x);
2300
2301 if (in_width > maxsinglelinewidth) {
2302 DSSERR("Cannot scale width exceeds max line width");
2303 return -EINVAL;
2304 }
2305
3e8a6ff2 2306 *core_clk = dispc.feat->calc_core_clk(plane, in_width, in_height,
8ba85306 2307 out_width, out_height, mem_to_mem);
dcbe765b 2308 return 0;
80c39712
TV		 2309}
2310
79ad75f2 2311static int dispc_ovl_calc_scaling(enum omap_plane plane,
3e8a6ff2 2312 enum omap_overlay_caps caps,
81ab95b7
AT		 2313 const struct omap_video_timings *mgr_timings,
2314 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2315 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2316 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2317 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2318{
0373cac6 2319 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2320 const int max_decim_limit = 16;
8b53d991 2321 unsigned long core_clk = 0;
dcbe765b 2322 int decim_x, decim_y, ret;
79ad75f2 2323
f95cb5eb
TV		 2324 if (width == out_width && height == out_height)
2325 return 0;
2326
5b54ed3e 2327 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2328 return -EINVAL;
79ad75f2 2329
1c031441
AT		 2330 if (plane == OMAP_DSS_WB) {
2331 *x_predecim = *y_predecim = 1;
2332 } else {
2333 *x_predecim = max_decim_limit;
2334 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2335 dss_has_feature(FEAT_BURST_2D)) ?
2336 2 : max_decim_limit;
2337 }
aed74b55
CM		 2338
2339 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2340 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2341 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2342 color_mode == OMAP_DSS_COLOR_CLUT8) {
2343 *x_predecim = 1;
2344 *y_predecim = 1;
2345 *five_taps = false;
2346 return 0;
2347 }
2348
2349 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2350 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2351
aed74b55 2352 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2353 return -EINVAL;
2354
aed74b55 2355 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2356 return -EINVAL;
2357
3e8a6ff2
AT		 2358 ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2359 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2360 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2361 mem_to_mem);
dcbe765b
CM		 2362 if (ret)
2363 return ret;
79ad75f2 2364
8b53d991
CM		 2365 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2366 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2367
8b53d991 2368 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2369 DSSERR("failed to set up scaling, "
8b53d991
CM		 2370 "required core clk rate = %lu Hz, "
2371 "current core clk rate = %lu Hz\n",
2372 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2373 return -EINVAL;
2374 }
2375
aed74b55
CM		 2376 *x_predecim = decim_x;
2377 *y_predecim = decim_y;
79ad75f2
AT		 2378 return 0;
2379}
2380
84a880fd 2381static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2382 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2383 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2384 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2385 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2386 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2387 bool replication, const struct omap_video_timings *mgr_timings,
2388 bool mem_to_mem)
80c39712 2389{
7282f1b7 2390 bool five_taps = true;
80c39712 2391 bool fieldmode = 0;
79ad75f2 2392 int r, cconv = 0;
80c39712
TV		 2393 unsigned offset0, offset1;
2394 s32 row_inc;
2395 s32 pix_inc;
6be0d73e 2396 u16 frame_width, frame_height;
80c39712 2397 unsigned int field_offset = 0;
84a880fd
AT		 2398 u16 in_height = height;
2399 u16 in_width = width;
aed74b55 2400 int x_predecim = 1, y_predecim = 1;
8050cbe4 2401 bool ilace = mgr_timings->interlace;
e6d80f95 2402
84a880fd 2403 if (paddr == 0)
80c39712
TV		 2404 return -EINVAL;
2405
84a880fd
AT		 2406 out_width = out_width == 0 ? width : out_width;
2407 out_height = out_height == 0 ? height : out_height;
cf073668 2408
84a880fd 2409 if (ilace && height == out_height)
80c39712
TV		 2410 fieldmode = 1;
2411
2412 if (ilace) {
2413 if (fieldmode)
aed74b55 2414 in_height /= 2;
8eeb7019 2415 pos_y /= 2;
aed74b55 2416 out_height /= 2;
80c39712
TV		 2417
2418 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2419 "out_height %d\n", in_height, pos_y,
2420 out_height);
80c39712
TV		 2421 }
2422
84a880fd 2423 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2424 return -EINVAL;
2425
3e8a6ff2 2426 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
84a880fd
AT		 2427 in_height, out_width, out_height, color_mode,
2428 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2429 rotation_type, mem_to_mem);
79ad75f2
AT		 2430 if (r)
2431 return r;
80c39712 2432
aed74b55
CM		 2433 in_width = DIV_ROUND_UP(in_width, x_predecim);
2434 in_height = DIV_ROUND_UP(in_height, y_predecim);
2435
84a880fd
AT		 2436 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2437 color_mode == OMAP_DSS_COLOR_UYVY ||
2438 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2439 cconv = 1;
80c39712
TV		 2440
2441 if (ilace && !fieldmode) {
2442 /*
2443 * when downscaling the bottom field may have to start several
2444 * source lines below the top field. Unfortunately ACCUI
2445 * registers will only hold the fractional part of the offset
2446 * so the integer part must be added to the base address of the
2447 * bottom field.
2448 */
aed74b55 2449 if (!in_height || in_height == out_height)
80c39712
TV		 2450 field_offset = 0;
2451 else
aed74b55 2452 field_offset = in_height / out_height / 2;
80c39712
TV		 2453 }
2454
2455 /* Fields are independent but interleaved in memory. */
2456 if (fieldmode)
2457 field_offset = 1;
2458
c6eee968
TV		 2459 offset0 = 0;
2460 offset1 = 0;
2461 row_inc = 0;
2462 pix_inc = 0;
2463
6be0d73e
AT		 2464 if (plane == OMAP_DSS_WB) {
2465 frame_width = out_width;
2466 frame_height = out_height;
2467 } else {
2468 frame_width = in_width;
2469 frame_height = height;
2470 }
2471
84a880fd 2472 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2473 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2474 color_mode, fieldmode, field_offset,
65e006ff
CM		 2475 &offset0, &offset1, &row_inc, &pix_inc,
2476 x_predecim, y_predecim);
84a880fd 2477 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2478 calc_dma_rotation_offset(rotation, mirror, screen_width,
2479 frame_width, frame_height,
84a880fd 2480 color_mode, fieldmode, field_offset,
aed74b55
CM		 2481 &offset0, &offset1, &row_inc, &pix_inc,
2482 x_predecim, y_predecim);
80c39712 2483 else
84a880fd 2484 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2485 screen_width, frame_width, frame_height,
84a880fd 2486 color_mode, fieldmode, field_offset,
aed74b55
CM		 2487 &offset0, &offset1, &row_inc, &pix_inc,
2488 x_predecim, y_predecim);
80c39712
TV		 2489
2490 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2491 offset0, offset1, row_inc, pix_inc);
2492
84a880fd 2493 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2494
84a880fd 2495 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2496
84a880fd
AT		 2497 dispc_ovl_set_ba0(plane, paddr + offset0);
2498 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2499
84a880fd
AT		 2500 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2501 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2502 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2503 }
2504
f0e5caab
TV		 2505 dispc_ovl_set_row_inc(plane, row_inc);
2506 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2507
84a880fd 2508 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2509 in_height, out_width, out_height);
80c39712 2510
84a880fd 2511 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2512
78b687fc 2513 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2514
5b54ed3e 2515 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2516 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2517 out_height, ilace, five_taps, fieldmode,
84a880fd 2518 color_mode, rotation);
78b687fc 2519 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2520 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2521 }
2522
84a880fd 2523 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
80c39712 2524
84a880fd
AT		 2525 dispc_ovl_set_zorder(plane, caps, zorder);
2526 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2527 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2528
d79db853 2529 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2530
80c39712
TV		 2531 return 0;
2532}
2533
84a880fd 2534int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2535 bool replication, const struct omap_video_timings *mgr_timings,
2536 bool mem_to_mem)
84a880fd
AT		 2537{
2538 int r;
16bf20c7 2539 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2540 enum omap_channel channel;
2541
2542 channel = dispc_ovl_get_channel_out(plane);
2543
2544 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2545 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2546 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2547 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2548 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2549
16bf20c7 2550 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2551 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2552 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2553 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2554 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2555
2556 return r;
2557}
2558
749feffa 2559int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2560 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2561{
2562 int r;
9e4a0fc7 2563 u32 l;
749feffa
AT		 2564 enum omap_plane plane = OMAP_DSS_WB;
2565 const int pos_x = 0, pos_y = 0;
2566 const u8 zorder = 0, global_alpha = 0;
2567 const bool replication = false;
9e4a0fc7 2568 bool truncation;
749feffa
AT		 2569 int in_width = mgr_timings->x_res;
2570 int in_height = mgr_timings->y_res;
2571 enum omap_overlay_caps caps =
2572 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2573
2574 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2575 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2576 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2577 wi->mirror);
2578
2579 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2580 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2581 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2582 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2583 replication, mgr_timings, mem_to_mem);
2584
2585 switch (wi->color_mode) {
2586 case OMAP_DSS_COLOR_RGB16:
2587 case OMAP_DSS_COLOR_RGB24P:
2588 case OMAP_DSS_COLOR_ARGB16:
2589 case OMAP_DSS_COLOR_RGBA16:
2590 case OMAP_DSS_COLOR_RGB12U:
2591 case OMAP_DSS_COLOR_ARGB16_1555:
2592 case OMAP_DSS_COLOR_XRGB16_1555:
2593 case OMAP_DSS_COLOR_RGBX16:
2594 truncation = true;
2595 break;
2596 default:
2597 truncation = false;
2598 break;
2599 }
2600
2601 /* setup extra DISPC_WB_ATTRIBUTES */
2602 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2603 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2604 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2605 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2606
2607 return r;
2608}
2609
f0e5caab 2610int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2611{
e6d80f95
TV		 2612 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2613
9b372c2d 2614 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2615
2616 return 0;
80c39712
TV		 2617}
2618
04bd8ac1
TV		 2619bool dispc_ovl_enabled(enum omap_plane plane)
2620{
2621 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2622}
2623
b1112249 2624static void dispc_mgr_disable_isr(void *data, u32 mask)
80c39712
TV		 2625{
2626 struct completion *compl = data;
2627 complete(compl);
2628}
2629
f1a813d3 2630void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2631{
efa70b3b
CM		 2632 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2633 /* flush posted write */
2634 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2635}
2636
65398511
TV		 2637bool dispc_mgr_is_enabled(enum omap_channel channel)
2638{
2639 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2640}
2641
b1112249 2642static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
80c39712 2643{
f1a813d3 2644 dispc_mgr_enable(channel, true);
b1112249
TV		 2645}
2646
2647static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
2648{
2649 DECLARE_COMPLETION_ONSTACK(framedone_compl);
80c39712 2650 int r;
2a205f34 2651 u32 irq;
80c39712 2652
b1112249
TV		 2653 if (dispc_mgr_is_enabled(channel) == false)
2654 return;
2a205f34 2655
b1112249
TV		 2656 /*
2657 * When we disable LCD output, we need to wait for FRAMEDONE to know
2658 * that DISPC has finished with the LCD output.
2659 */
80c39712 2660
b1112249 2661 irq = dispc_mgr_get_framedone_irq(channel);
80c39712 2662
b1112249
TV		 2663 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
2664 irq);
2665 if (r)
2666 DSSERR("failed to register FRAMEDONE isr\n");
80c39712 2667
f1a813d3 2668 dispc_mgr_enable(channel, false);
b1112249
TV		 2669
2670 /* if we couldn't register for framedone, just sleep and exit */
2671 if (r) {
2672 msleep(100);
2673 return;
80c39712
TV		 2674 }
2675
b1112249
TV		 2676 if (!wait_for_completion_timeout(&framedone_compl,
2677 msecs_to_jiffies(100)))
2678 DSSERR("timeout waiting for FRAME DONE\n");
80c39712 2679
b1112249
TV		 2680 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
2681 irq);
2682 if (r)
2683 DSSERR("failed to unregister FRAMEDONE isr\n");
2684}
80c39712 2685
b1112249
TV		 2686static void dispc_digit_out_enable_isr(void *data, u32 mask)
2687{
2688 struct completion *compl = data;
80c39712 2689
b1112249
TV		 2690 /* ignore any sync lost interrupts */
2691 if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
2692 complete(compl);
2693}
2694
2695static void dispc_mgr_enable_digit_out(void)
2696{
2697 DECLARE_COMPLETION_ONSTACK(vsync_compl);
2698 int r;
2699 u32 irq_mask;
2700
2701 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
2702 return;
2703
2704 /*
2705 * Digit output produces some sync lost interrupts during the first
2706 * frame when enabling. Those need to be ignored, so we register for the
2707 * sync lost irq to prevent the error handler from triggering.
2708 */
2709
2710 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
2711 dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
2712
2713 r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
2714 irq_mask);
2715 if (r) {
2716 DSSERR("failed to register %x isr\n", irq_mask);
2717 return;
80c39712 2718 }
b1112249 2719
f1a813d3 2720 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, true);
b1112249
TV		 2721
2722 /* wait for the first evsync */
2723 if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
2724 DSSERR("timeout waiting for digit out to start\n");
2725
2726 r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
2727 irq_mask);
2728 if (r)
2729 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2730}
2731
b1112249 2732static void dispc_mgr_disable_digit_out(void)
80c39712 2733{
b1112249 2734 DECLARE_COMPLETION_ONSTACK(framedone_compl);
e82b090b
TV		 2735 int r, i;
2736 u32 irq_mask;
2737 int num_irqs;
80c39712 2738
b1112249 2739 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
80c39712 2740 return;
80c39712 2741
b1112249
TV		 2742 /*
2743 * When we disable the digit output, we need to wait for FRAMEDONE to
15f5e732 2744 * know that DISPC has finished with the output.
b1112249 2745 */
80c39712 2746
15f5e732
TV		 2747 irq_mask = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_DIGIT);
2748 num_irqs = 1;
2749
2750 if (!irq_mask) {
2751 /*
2752 * omap 2/3 don't have framedone irq for TV, so we need to use
2753 * vsyncs for this.
2754 */
2755
b1112249
TV		 2756 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
2757 /*
2758 * We need to wait for both even and odd vsyncs. Note that this
2759 * is not totally reliable, as we could get a vsync interrupt
2760 * before we disable the output, which leads to timeout in the
2761 * wait_for_completion.
2762 */
e82b090b
TV		 2763 num_irqs = 2;
2764 }
2765
b1112249 2766 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2767 irq_mask);
80c39712 2768 if (r)
e82b090b 2769 DSSERR("failed to register %x isr\n", irq_mask);
80c39712 2770
f1a813d3 2771 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, false);
b1112249
TV		 2772
2773 /* if we couldn't register the irq, just sleep and exit */
2774 if (r) {
2775 msleep(100);
2776 return;
2777 }
80c39712 2778
e82b090b 2779 for (i = 0; i < num_irqs; ++i) {
b1112249 2780 if (!wait_for_completion_timeout(&framedone_compl,
e82b090b 2781 msecs_to_jiffies(100)))
b1112249 2782 DSSERR("timeout waiting for digit out to stop\n");
e82b090b 2783 }
80c39712 2784
b1112249 2785 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2786 irq_mask);
80c39712 2787 if (r)
e82b090b 2788 DSSERR("failed to unregister %x isr\n", irq_mask);
b1112249 2789}
80c39712 2790
3a979f8a 2791void dispc_mgr_enable_sync(enum omap_channel channel)
b1112249
TV		 2792{
2793 if (dss_mgr_is_lcd(channel))
2794 dispc_mgr_enable_lcd_out(channel);
2795 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2796 dispc_mgr_enable_digit_out();
2797 else
2798 WARN_ON(1);
80c39712
TV		 2799}
2800
3a979f8a 2801void dispc_mgr_disable_sync(enum omap_channel channel)
a2faee84 2802{
dd88b7a6 2803 if (dss_mgr_is_lcd(channel))
b1112249 2804 dispc_mgr_disable_lcd_out(channel);
a2faee84 2805 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
b1112249 2806 dispc_mgr_disable_digit_out();
a2faee84 2807 else
b1112249 2808 WARN_ON(1);
a2faee84
TV		 2809}
2810
0b23e5b8
AT		 2811void dispc_wb_enable(bool enable)
2812{
2813 enum omap_plane plane = OMAP_DSS_WB;
2814 struct completion frame_done_completion;
2815 bool is_on;
2816 int r;
2817 u32 irq;
2818
2819 is_on = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2820 irq = DISPC_IRQ_FRAMEDONEWB;
2821
2822 if (!enable && is_on) {
2823 init_completion(&frame_done_completion);
2824
b1112249 2825 r = omap_dispc_register_isr(dispc_mgr_disable_isr,
0b23e5b8
AT		 2826 &frame_done_completion, irq);
2827 if (r)
2828 DSSERR("failed to register FRAMEDONEWB isr\n");
2829 }
2830
2831 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2832
2833 if (!enable && is_on) {
2834 if (!wait_for_completion_timeout(&frame_done_completion,
2835 msecs_to_jiffies(100)))
2836 DSSERR("timeout waiting for FRAMEDONEWB\n");
2837
b1112249 2838 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr,
0b23e5b8
AT		 2839 &frame_done_completion, irq);
2840 if (r)
2841 DSSERR("failed to unregister FRAMEDONEWB isr\n");
2842 }
2843}
2844
2845bool dispc_wb_is_enabled(void)
2846{
2847 enum omap_plane plane = OMAP_DSS_WB;
2848
2849 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2850}
2851
fb2cec1f 2852static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2853{
6ced40bf
AT		 2854 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2855 return;
2856
80c39712 2857 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2858}
2859
2860void dispc_lcd_enable_signal(bool enable)
2861{
6ced40bf
AT		 2862 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2863 return;
2864
80c39712 2865 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2866}
2867
2868void dispc_pck_free_enable(bool enable)
2869{
6ced40bf
AT		 2870 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2871 return;
2872
80c39712 2873 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2874}
2875
fb2cec1f 2876static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2877{
efa70b3b 2878 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2879}
2880
2881
fb2cec1f 2882static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2883{
d21f43bc 2884 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2885}
2886
2887void dispc_set_loadmode(enum omap_dss_load_mode mode)
2888{
80c39712 2889 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2890}
2891
2892
c64dca40 2893static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2894{
8613b000 2895 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2896}
2897
c64dca40 2898static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2899 enum omap_dss_trans_key_type type,
2900 u32 trans_key)
2901{
efa70b3b 2902 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2903
8613b000 2904 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2905}
2906
c64dca40 2907static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2908{
efa70b3b 2909 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2910}
11354dd5 2911
c64dca40
TV		 2912static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2913 bool enable)
80c39712 2914{
11354dd5 2915 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2916 return;
2917
80c39712
TV		 2918 if (ch == OMAP_DSS_CHANNEL_LCD)
2919 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2920 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2921 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2922}
11354dd5 2923
c64dca40 2924void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2925 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2926{
2927 dispc_mgr_set_default_color(channel, info->default_color);
2928 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2929 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2930 dispc_mgr_enable_alpha_fixed_zorder(channel,
2931 info->partial_alpha_enabled);
2932 if (dss_has_feature(FEAT_CPR)) {
2933 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2934 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2935 }
2936}
80c39712 2937
fb2cec1f 2938static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2939{
2940 int code;
2941
2942 switch (data_lines) {
2943 case 12:
2944 code = 0;
2945 break;
2946 case 16:
2947 code = 1;
2948 break;
2949 case 18:
2950 code = 2;
2951 break;
2952 case 24:
2953 code = 3;
2954 break;
2955 default:
2956 BUG();
2957 return;
2958 }
2959
efa70b3b 2960 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2961}
2962
fb2cec1f 2963static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2964{
2965 u32 l;
569969d6 2966 int gpout0, gpout1;
80c39712
TV		 2967
2968 switch (mode) {
569969d6
AT		 2969 case DSS_IO_PAD_MODE_RESET:
2970 gpout0 = 0;
2971 gpout1 = 0;
80c39712 2972 break;
569969d6
AT		 2973 case DSS_IO_PAD_MODE_RFBI:
2974 gpout0 = 1;
80c39712
TV		 2975 gpout1 = 0;
2976 break;
569969d6
AT		 2977 case DSS_IO_PAD_MODE_BYPASS:
2978 gpout0 = 1;
80c39712
TV		 2979 gpout1 = 1;
2980 break;
80c39712
TV		 2981 default:
2982 BUG();
2983 return;
2984 }
2985
569969d6
AT		 2986 l = dispc_read_reg(DISPC_CONTROL);
2987 l = FLD_MOD(l, gpout0, 15, 15);
2988 l = FLD_MOD(l, gpout1, 16, 16);
2989 dispc_write_reg(DISPC_CONTROL, l);
2990}
2991
fb2cec1f 2992static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2993{
efa70b3b 2994 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2995}
2996
fb2cec1f
TV		 2997void dispc_mgr_set_lcd_config(enum omap_channel channel,
2998 const struct dss_lcd_mgr_config *config)
2999{
3000 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
3001
3002 dispc_mgr_enable_stallmode(channel, config->stallmode);
3003 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
3004
3005 dispc_mgr_set_clock_div(channel, &config->clock_info);
3006
3007 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
3008
3009 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
3010
3011 dispc_mgr_set_lcd_type_tft(channel);
3012}
3013
8f366162
AT		 3014static bool _dispc_mgr_size_ok(u16 width, u16 height)
3015{
33b89928
AT		 3016 return width <= dispc.feat->mgr_width_max &&
3017 height <= dispc.feat->mgr_height_max;
8f366162
AT		 3018}
3019
80c39712
TV		 3020static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
3021 int vsw, int vfp, int vbp)
3022{
dcbe765b
CM		 3023 if (hsw < 1 || hsw > dispc.feat->sw_max ||
3024 hfp < 1 || hfp > dispc.feat->hp_max ||
3025 hbp < 1 || hbp > dispc.feat->hp_max ||
3026 vsw < 1 || vsw > dispc.feat->sw_max ||
3027 vfp < 0 || vfp > dispc.feat->vp_max ||
3028 vbp < 0 || vbp > dispc.feat->vp_max)
3029 return false;
80c39712
TV		 3030 return true;
3031}
3032
8f366162 3033bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3034 const struct omap_video_timings *timings)
80c39712 3035{
8f366162
AT		 3036 bool timings_ok;
3037
3038 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
3039
dd88b7a6 3040 if (dss_mgr_is_lcd(channel))
8f366162
AT		 3041 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
3042 timings->hfp, timings->hbp,
3043 timings->vsw, timings->vfp,
3044 timings->vbp);
3045
3046 return timings_ok;
80c39712
TV		 3047}
3048
26d9dd0d 3049static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3050 int hfp, int hbp, int vsw, int vfp, int vbp,
3051 enum omap_dss_signal_level vsync_level,
3052 enum omap_dss_signal_level hsync_level,
3053 enum omap_dss_signal_edge data_pclk_edge,
3054 enum omap_dss_signal_level de_level,
3055 enum omap_dss_signal_edge sync_pclk_edge)
3056
80c39712 3057{
655e2941
AT		 3058 u32 timing_h, timing_v, l;
3059 bool onoff, rf, ipc;
80c39712 3060
dcbe765b
CM		 3061 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3062 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3063 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3064 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3065 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3066 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3067
64ba4f74
SS		 3068 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3069 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 3070
3071 switch (data_pclk_edge) {
3072 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3073 ipc = false;
3074 break;
3075 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3076 ipc = true;
3077 break;
3078 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3079 default:
3080 BUG();
3081 }
3082
3083 switch (sync_pclk_edge) {
3084 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3085 onoff = false;
3086 rf = false;
3087 break;
3088 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3089 onoff = true;
3090 rf = false;
3091 break;
3092 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3093 onoff = true;
3094 rf = true;
3095 break;
3096 default:
3097 BUG();
3098 };
3099
3100 l = dispc_read_reg(DISPC_POL_FREQ(channel));
3101 l |= FLD_VAL(onoff, 17, 17);
3102 l |= FLD_VAL(rf, 16, 16);
3103 l |= FLD_VAL(de_level, 15, 15);
3104 l |= FLD_VAL(ipc, 14, 14);
3105 l |= FLD_VAL(hsync_level, 13, 13);
3106 l |= FLD_VAL(vsync_level, 12, 12);
3107 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3108}
3109
3110/* change name to mode? */
c51d921a 3111void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3112 const struct omap_video_timings *timings)
80c39712
TV		 3113{
3114 unsigned xtot, ytot;
3115 unsigned long ht, vt;
2aefad49 3116 struct omap_video_timings t = *timings;
80c39712 3117
2aefad49 3118 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3119
2aefad49 3120 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3121 BUG();
c6eee968
TV		 3122 return;
3123 }
80c39712 3124
dd88b7a6 3125 if (dss_mgr_is_lcd(channel)) {
2aefad49 3126 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3127 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3128 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3129
2aefad49
AT		 3130 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3131 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3132
c51d921a
AT		 3133 ht = (timings->pixel_clock * 1000) / xtot;
3134 vt = (timings->pixel_clock * 1000) / xtot / ytot;
3135
3136 DSSDBG("pck %u\n", timings->pixel_clock);
3137 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3138 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3139 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3140 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3141 t.de_level, t.sync_pclk_edge);
80c39712 3142
c51d921a 3143 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3144 } else {
23c8f88e 3145 if (t.interlace == true)
2aefad49 3146 t.y_res /= 2;
c51d921a 3147 }
8f366162 3148
2aefad49 3149 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 3150}
3151
26d9dd0d 3152static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3153 u16 pck_div)
80c39712
TV		 3154{
3155 BUG_ON(lck_div < 1);
9eaaf207 3156 BUG_ON(pck_div < 1);
80c39712 3157
ce7fa5eb 3158 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3159 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 3160}
3161
26d9dd0d 3162static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3163 int *pck_div)
80c39712
TV		 3164{
3165 u32 l;
ce7fa5eb 3166 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3167 *lck_div = FLD_GET(l, 23, 16);
3168 *pck_div = FLD_GET(l, 7, 0);
3169}
3170
3171unsigned long dispc_fclk_rate(void)
3172{
a72b64b9 3173 struct platform_device *dsidev;
80c39712
TV		 3174 unsigned long r = 0;
3175
66534e8e 3176 switch (dss_get_dispc_clk_source()) {
89a35e51 3177 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3178 r = clk_get_rate(dispc.dss_clk);
66534e8e 3179 break;
89a35e51 3180 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3181 dsidev = dsi_get_dsidev_from_id(0);
3182 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3183 break;
5a8b572d
AT		 3184 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3185 dsidev = dsi_get_dsidev_from_id(1);
3186 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3187 break;
66534e8e
TA		 3188 default:
3189 BUG();
c6eee968 3190 return 0;
66534e8e
TA		 3191 }
3192
80c39712
TV		 3193 return r;
3194}
3195
26d9dd0d 3196unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3197{
a72b64b9 3198 struct platform_device *dsidev;
80c39712
TV		 3199 int lcd;
3200 unsigned long r;
3201 u32 l;
3202
c31cba8a
TV		 3203 if (dss_mgr_is_lcd(channel)) {
3204 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3205
c31cba8a 3206 lcd = FLD_GET(l, 23, 16);
80c39712 3207
c31cba8a
TV		 3208 switch (dss_get_lcd_clk_source(channel)) {
3209 case OMAP_DSS_CLK_SRC_FCK:
3210 r = clk_get_rate(dispc.dss_clk);
3211 break;
3212 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3213 dsidev = dsi_get_dsidev_from_id(0);
3214 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3215 break;
3216 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3217 dsidev = dsi_get_dsidev_from_id(1);
3218 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3219 break;
3220 default:
3221 BUG();
3222 return 0;
3223 }
80c39712 3224
c31cba8a
TV		 3225 return r / lcd;
3226 } else {
3227 return dispc_fclk_rate();
3228 }
80c39712
TV		 3229}
3230
26d9dd0d 3231unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3232{
80c39712 3233 unsigned long r;
80c39712 3234
dd88b7a6 3235 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3236 int pcd;
3237 u32 l;
80c39712 3238
c3dc6a7a 3239 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3240
c3dc6a7a 3241 pcd = FLD_GET(l, 7, 0);
80c39712 3242
c3dc6a7a
AT		 3243 r = dispc_mgr_lclk_rate(channel);
3244
3245 return r / pcd;
3246 } else {
3fa03ba8 3247 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 3248
3fa03ba8
AT		 3249 source = dss_get_hdmi_venc_clk_source();
3250
3251 switch (source) {
3252 case DSS_VENC_TV_CLK:
c3dc6a7a 3253 return venc_get_pixel_clock();
3fa03ba8 3254 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 3255 return hdmi_get_pixel_clock();
3256 default:
3257 BUG();
c6eee968 3258 return 0;
c3dc6a7a
AT		 3259 }
3260 }
80c39712
TV		 3261}
3262
8b53d991
CM		 3263unsigned long dispc_core_clk_rate(void)
3264{
3265 int lcd;
3266 unsigned long fclk = dispc_fclk_rate();
3267
3268 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3269 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3270 else
3271 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3272
3273 return fclk / lcd;
3274}
3275
3e8a6ff2
AT		 3276static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3277{
3278 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3279
3280 return dispc_mgr_pclk_rate(channel);
3281}
3282
3283static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3284{
3285 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3286
c31cba8a 3287 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3288}
c31cba8a 3289
6f1891fc 3290static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3291{
3292 int lcd, pcd;
6f1891fc
CM		 3293 enum omap_dss_clk_source lcd_clk_src;
3294
3295 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3296
3297 lcd_clk_src = dss_get_lcd_clk_source(channel);
3298
3299 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3300 dss_get_generic_clk_source_name(lcd_clk_src),
3301 dss_feat_get_clk_source_name(lcd_clk_src));
3302
3303 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3304
3305 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3306 dispc_mgr_lclk_rate(channel), lcd);
3307 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3308 dispc_mgr_pclk_rate(channel), pcd);
3309}
3310
3311void dispc_dump_clocks(struct seq_file *s)
3312{
3313 int lcd;
0cf35df3 3314 u32 l;
89a35e51 3315 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3316
4fbafaf3
TV		 3317 if (dispc_runtime_get())
3318 return;
80c39712 3319
80c39712
TV		 3320 seq_printf(s, "- DISPC -\n");
3321
067a57e4
AT		 3322 seq_printf(s, "dispc fclk source = %s (%s)\n",
3323 dss_get_generic_clk_source_name(dispc_clk_src),
3324 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3325
3326 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3327
0cf35df3
MR		 3328 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3329 seq_printf(s, "- DISPC-CORE-CLK -\n");
3330 l = dispc_read_reg(DISPC_DIVISOR);
3331 lcd = FLD_GET(l, 23, 16);
3332
3333 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3334 (dispc_fclk_rate()/lcd), lcd);
3335 }
2a205f34 3336
6f1891fc 3337 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3338
6f1891fc
CM		 3339 if (dss_has_feature(FEAT_MGR_LCD2))
3340 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3341 if (dss_has_feature(FEAT_MGR_LCD3))
3342 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3343
3344 dispc_runtime_put();
80c39712
TV		 3345}
3346
dfc0fd8d 3347#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5b30b7fb 3348static void dispc_dump_irqs(struct seq_file *s)
dfc0fd8d
TV		 3349{
3350 unsigned long flags;
3351 struct dispc_irq_stats stats;
3352
3353 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3354
3355 stats = dispc.irq_stats;
3356 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3357 dispc.irq_stats.last_reset = jiffies;
3358
3359 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3360
3361 seq_printf(s, "period %u ms\n",
3362 jiffies_to_msecs(jiffies - stats.last_reset));
3363
3364 seq_printf(s, "irqs %d\n", stats.irq_count);
3365#define PIS(x) \
3366 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3367
3368 PIS(FRAMEDONE);
3369 PIS(VSYNC);
3370 PIS(EVSYNC_EVEN);
3371 PIS(EVSYNC_ODD);
3372 PIS(ACBIAS_COUNT_STAT);
3373 PIS(PROG_LINE_NUM);
3374 PIS(GFX_FIFO_UNDERFLOW);
3375 PIS(GFX_END_WIN);
3376 PIS(PAL_GAMMA_MASK);
3377 PIS(OCP_ERR);
3378 PIS(VID1_FIFO_UNDERFLOW);
3379 PIS(VID1_END_WIN);
3380 PIS(VID2_FIFO_UNDERFLOW);
3381 PIS(VID2_END_WIN);
b8c095b4
AT		 3382 if (dss_feat_get_num_ovls() > 3) {
3383 PIS(VID3_FIFO_UNDERFLOW);
3384 PIS(VID3_END_WIN);
3385 }
dfc0fd8d
TV		 3386 PIS(SYNC_LOST);
3387 PIS(SYNC_LOST_DIGIT);
3388 PIS(WAKEUP);
2a205f34
SS		 3389 if (dss_has_feature(FEAT_MGR_LCD2)) {
3390 PIS(FRAMEDONE2);
3391 PIS(VSYNC2);
3392 PIS(ACBIAS_COUNT_STAT2);
3393 PIS(SYNC_LOST2);
3394 }
6f1891fc
CM		 3395 if (dss_has_feature(FEAT_MGR_LCD3)) {
3396 PIS(FRAMEDONE3);
3397 PIS(VSYNC3);
3398 PIS(ACBIAS_COUNT_STAT3);
3399 PIS(SYNC_LOST3);
3400 }
dfc0fd8d
TV		 3401#undef PIS
3402}
dfc0fd8d
TV		 3403#endif
3404
e40402cf 3405static void dispc_dump_regs(struct seq_file *s)
80c39712 3406{
4dd2da15
AT		 3407 int i, j;
3408 const char *mgr_names[] = {
3409 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3410 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3411 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3412 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3413 };
3414 const char *ovl_names[] = {
3415 [OMAP_DSS_GFX] = "GFX",
3416 [OMAP_DSS_VIDEO1] = "VID1",
3417 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3418 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3419 };
3420 const char **p_names;
3421
9b372c2d 3422#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3423
4fbafaf3
TV		 3424 if (dispc_runtime_get())
3425 return;
80c39712 3426
5010be80 3427 /* DISPC common registers */
80c39712
TV		 3428 DUMPREG(DISPC_REVISION);
3429 DUMPREG(DISPC_SYSCONFIG);
3430 DUMPREG(DISPC_SYSSTATUS);
3431 DUMPREG(DISPC_IRQSTATUS);
3432 DUMPREG(DISPC_IRQENABLE);
3433 DUMPREG(DISPC_CONTROL);
3434 DUMPREG(DISPC_CONFIG);
3435 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3436 DUMPREG(DISPC_LINE_STATUS);
3437 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3438 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3439 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3440 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3441 if (dss_has_feature(FEAT_MGR_LCD2)) {
3442 DUMPREG(DISPC_CONTROL2);
3443 DUMPREG(DISPC_CONFIG2);
5010be80 3444 }
6f1891fc
CM		 3445 if (dss_has_feature(FEAT_MGR_LCD3)) {
3446 DUMPREG(DISPC_CONTROL3);
3447 DUMPREG(DISPC_CONFIG3);
3448 }
5010be80
AT		 3449
3450#undef DUMPREG
3451
3452#define DISPC_REG(i, name) name(i)
4dd2da15 3453#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3454 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3455 dispc_read_reg(DISPC_REG(i, r)))
3456
4dd2da15 3457 p_names = mgr_names;
5010be80 3458
4dd2da15
AT		 3459 /* DISPC channel specific registers */
3460 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3461 DUMPREG(i, DISPC_DEFAULT_COLOR);
3462 DUMPREG(i, DISPC_TRANS_COLOR);
3463 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3464
4dd2da15
AT		 3465 if (i == OMAP_DSS_CHANNEL_DIGIT)
3466 continue;
5010be80 3467
4dd2da15
AT		 3468 DUMPREG(i, DISPC_DEFAULT_COLOR);
3469 DUMPREG(i, DISPC_TRANS_COLOR);
3470 DUMPREG(i, DISPC_TIMING_H);
3471 DUMPREG(i, DISPC_TIMING_V);
3472 DUMPREG(i, DISPC_POL_FREQ);
3473 DUMPREG(i, DISPC_DIVISORo);
3474 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3475
4dd2da15
AT		 3476 DUMPREG(i, DISPC_DATA_CYCLE1);
3477 DUMPREG(i, DISPC_DATA_CYCLE2);
3478 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3479
332e9d70 3480 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3481 DUMPREG(i, DISPC_CPR_COEF_R);
3482 DUMPREG(i, DISPC_CPR_COEF_G);
3483 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3484 }
2a205f34 3485 }
80c39712 3486
4dd2da15
AT		 3487 p_names = ovl_names;
3488
3489 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3490 DUMPREG(i, DISPC_OVL_BA0);
3491 DUMPREG(i, DISPC_OVL_BA1);
3492 DUMPREG(i, DISPC_OVL_POSITION);
3493 DUMPREG(i, DISPC_OVL_SIZE);
3494 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3495 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3496 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3497 DUMPREG(i, DISPC_OVL_ROW_INC);
3498 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3499 if (dss_has_feature(FEAT_PRELOAD))
3500 DUMPREG(i, DISPC_OVL_PRELOAD);
3501
3502 if (i == OMAP_DSS_GFX) {
3503 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3504 DUMPREG(i, DISPC_OVL_TABLE_BA);
3505 continue;
3506 }
3507
3508 DUMPREG(i, DISPC_OVL_FIR);
3509 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3510 DUMPREG(i, DISPC_OVL_ACCU0);
3511 DUMPREG(i, DISPC_OVL_ACCU1);
3512 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3513 DUMPREG(i, DISPC_OVL_BA0_UV);
3514 DUMPREG(i, DISPC_OVL_BA1_UV);
3515 DUMPREG(i, DISPC_OVL_FIR2);
3516 DUMPREG(i, DISPC_OVL_ACCU2_0);
3517 DUMPREG(i, DISPC_OVL_ACCU2_1);
3518 }
3519 if (dss_has_feature(FEAT_ATTR2))
3520 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3521 if (dss_has_feature(FEAT_PRELOAD))
3522 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3523 }
5010be80
AT		 3524
3525#undef DISPC_REG
3526#undef DUMPREG
3527
3528#define DISPC_REG(plane, name, i) name(plane, i)
3529#define DUMPREG(plane, name, i) \
4dd2da15 3530 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3531 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3532 dispc_read_reg(DISPC_REG(plane, name, i)))
3533
4dd2da15 3534 /* Video pipeline coefficient registers */
332e9d70 3535
4dd2da15
AT		 3536 /* start from OMAP_DSS_VIDEO1 */
3537 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3538 for (j = 0; j < 8; j++)
3539 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3540
4dd2da15
AT		 3541 for (j = 0; j < 8; j++)
3542 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3543
4dd2da15
AT		 3544 for (j = 0; j < 5; j++)
3545 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3546
4dd2da15
AT		 3547 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3548 for (j = 0; j < 8; j++)
3549 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3550 }
3551
3552 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3553 for (j = 0; j < 8; j++)
3554 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3555
3556 for (j = 0; j < 8; j++)
3557 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3558
3559 for (j = 0; j < 8; j++)
3560 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3561 }
332e9d70 3562 }
80c39712 3563
4fbafaf3 3564 dispc_runtime_put();
5010be80
AT		 3565
3566#undef DISPC_REG
80c39712
TV		 3567#undef DUMPREG
3568}
3569
80c39712 3570/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3571void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3572 struct dispc_clock_info *cinfo)
3573{
9eaaf207 3574 u16 pcd_min, pcd_max;
80c39712
TV		 3575 unsigned long best_pck;
3576 u16 best_ld, cur_ld;
3577 u16 best_pd, cur_pd;
3578
9eaaf207
TV		 3579 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3580 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3581
80c39712
TV		 3582 best_pck = 0;
3583 best_ld = 0;
3584 best_pd = 0;
3585
3586 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3587 unsigned long lck = fck / cur_ld;
3588
9eaaf207 3589 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3590 unsigned long pck = lck / cur_pd;
3591 long old_delta = abs(best_pck - req_pck);
3592 long new_delta = abs(pck - req_pck);
3593
3594 if (best_pck == 0 || new_delta < old_delta) {
3595 best_pck = pck;
3596 best_ld = cur_ld;
3597 best_pd = cur_pd;
3598
3599 if (pck == req_pck)
3600 goto found;
3601 }
3602
3603 if (pck < req_pck)
3604 break;
3605 }
3606
3607 if (lck / pcd_min < req_pck)
3608 break;
3609 }
3610
3611found:
3612 cinfo->lck_div = best_ld;
3613 cinfo->pck_div = best_pd;
3614 cinfo->lck = fck / cinfo->lck_div;
3615 cinfo->pck = cinfo->lck / cinfo->pck_div;
3616}
3617
3618/* calculate clock rates using dividers in cinfo */
3619int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3620 struct dispc_clock_info *cinfo)
3621{
3622 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3623 return -EINVAL;
9eaaf207 3624 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3625 return -EINVAL;
3626
3627 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3628 cinfo->pck = cinfo->lck / cinfo->pck_div;
3629
3630 return 0;
3631}
3632
f0d08f89 3633void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3634 const struct dispc_clock_info *cinfo)
80c39712
TV		 3635{
3636 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3637 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3638
26d9dd0d 3639 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3640}
3641
26d9dd0d 3642int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3643 struct dispc_clock_info *cinfo)
80c39712
TV		 3644{
3645 unsigned long fck;
3646
3647 fck = dispc_fclk_rate();
3648
ce7fa5eb
MR		 3649 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3650 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3651
3652 cinfo->lck = fck / cinfo->lck_div;
3653 cinfo->pck = cinfo->lck / cinfo->pck_div;
3654
3655 return 0;
3656}
3657
4e0397cf
TV		 3658u32 dispc_read_irqstatus(void)
3659{
3660 return dispc_read_reg(DISPC_IRQSTATUS);
3661}
3662
3663void dispc_clear_irqstatus(u32 mask)
3664{
3665 dispc_write_reg(DISPC_IRQSTATUS, mask);
3666}
3667
3668u32 dispc_read_irqenable(void)
3669{
3670 return dispc_read_reg(DISPC_IRQENABLE);
3671}
3672
3673void dispc_write_irqenable(u32 mask)
3674{
3675 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3676
3677 /* clear the irqstatus for newly enabled irqs */
3678 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3679
3680 dispc_write_reg(DISPC_IRQENABLE, mask);
3681}
3682
80c39712
TV		 3683/* dispc.irq_lock has to be locked by the caller */
3684static void _omap_dispc_set_irqs(void)
3685{
3686 u32 mask;
80c39712
TV		 3687 int i;
3688 struct omap_dispc_isr_data *isr_data;
3689
3690 mask = dispc.irq_error_mask;
3691
3692 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3693 isr_data = &dispc.registered_isr[i];
3694
3695 if (isr_data->isr == NULL)
3696 continue;
3697
3698 mask |= isr_data->mask;
3699 }
3700
4e0397cf 3701 dispc_write_irqenable(mask);
80c39712
TV		 3702}
3703
3704int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3705{
3706 int i;
3707 int ret;
3708 unsigned long flags;
3709 struct omap_dispc_isr_data *isr_data;
3710
3711 if (isr == NULL)
3712 return -EINVAL;
3713
3714 spin_lock_irqsave(&dispc.irq_lock, flags);
3715
3716 /* check for duplicate entry */
3717 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3718 isr_data = &dispc.registered_isr[i];
3719 if (isr_data->isr == isr && isr_data->arg == arg &&
3720 isr_data->mask == mask) {
3721 ret = -EINVAL;
3722 goto err;
3723 }
3724 }
3725
3726 isr_data = NULL;
3727 ret = -EBUSY;
3728
3729 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3730 isr_data = &dispc.registered_isr[i];
3731
3732 if (isr_data->isr != NULL)
3733 continue;
3734
3735 isr_data->isr = isr;
3736 isr_data->arg = arg;
3737 isr_data->mask = mask;
3738 ret = 0;
3739
3740 break;
3741 }
3742
b9cb0984
TV		 3743 if (ret)
3744 goto err;
3745
80c39712
TV		 3746 _omap_dispc_set_irqs();
3747
3748 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3749
3750 return 0;
3751err:
3752 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3753
3754 return ret;
3755}
3756EXPORT_SYMBOL(omap_dispc_register_isr);
3757
3758int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3759{
3760 int i;
3761 unsigned long flags;
3762 int ret = -EINVAL;
3763 struct omap_dispc_isr_data *isr_data;
3764
3765 spin_lock_irqsave(&dispc.irq_lock, flags);
3766
3767 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3768 isr_data = &dispc.registered_isr[i];
3769 if (isr_data->isr != isr || isr_data->arg != arg ||
3770 isr_data->mask != mask)
3771 continue;
3772
3773 /* found the correct isr */
3774
3775 isr_data->isr = NULL;
3776 isr_data->arg = NULL;
3777 isr_data->mask = 0;
3778
3779 ret = 0;
3780 break;
3781 }
3782
3783 if (ret == 0)
3784 _omap_dispc_set_irqs();
3785
3786 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3787
3788 return ret;
3789}
3790EXPORT_SYMBOL(omap_dispc_unregister_isr);
3791
80c39712
TV		 3792static void print_irq_status(u32 status)
3793{
3794 if ((status & dispc.irq_error_mask) == 0)
3795 return;
3796
f30be7d3
CM		 3797#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
3798
3799 pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
3800 status,
3801 PIS(OCP_ERR),
3802 PIS(GFX_FIFO_UNDERFLOW),
3803 PIS(VID1_FIFO_UNDERFLOW),
3804 PIS(VID2_FIFO_UNDERFLOW),
3805 dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
3806 PIS(SYNC_LOST),
3807 PIS(SYNC_LOST_DIGIT),
3808 dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
3809 dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
80c39712 3810#undef PIS
80c39712 3811}
80c39712
TV		 3812
3813/* Called from dss.c. Note that we don't touch clocks here,
3814 * but we presume they are on because we got an IRQ. However,
3815 * an irq handler may turn the clocks off, so we may not have
3816 * clock later in the function. */
affe360d 3817static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3818{
3819 int i;
affe360d 3820 u32 irqstatus, irqenable;
80c39712
TV		 3821 u32 handledirqs = 0;
3822 u32 unhandled_errors;
3823 struct omap_dispc_isr_data *isr_data;
3824 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3825
3826 spin_lock(&dispc.irq_lock);
3827
4e0397cf
TV		 3828 irqstatus = dispc_read_irqstatus();
3829 irqenable = dispc_read_irqenable();
affe360d 3830
3831 /* IRQ is not for us */
3832 if (!(irqstatus & irqenable)) {
3833 spin_unlock(&dispc.irq_lock);
3834 return IRQ_NONE;
3835 }
80c39712 3836
dfc0fd8d
TV		 3837#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3838 spin_lock(&dispc.irq_stats_lock);
3839 dispc.irq_stats.irq_count++;
3840 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3841 spin_unlock(&dispc.irq_stats_lock);
3842#endif
3843
28bcd199
CM		 3844 print_irq_status(irqstatus);
3845
80c39712
TV		 3846 /* Ack the interrupt. Do it here before clocks are possibly turned
3847 * off */
4e0397cf 3848 dispc_clear_irqstatus(irqstatus);
80c39712 3849 /* flush posted write */
4e0397cf 3850 dispc_read_irqstatus();
80c39712
TV		 3851
3852 /* make a copy and unlock, so that isrs can unregister
3853 * themselves */
3854 memcpy(registered_isr, dispc.registered_isr,
3855 sizeof(registered_isr));
3856
3857 spin_unlock(&dispc.irq_lock);
3858
3859 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3860 isr_data = &registered_isr[i];
3861
3862 if (!isr_data->isr)
3863 continue;
3864
3865 if (isr_data->mask & irqstatus) {
3866 isr_data->isr(isr_data->arg, irqstatus);
3867 handledirqs |= isr_data->mask;
3868 }
3869 }
3870
3871 spin_lock(&dispc.irq_lock);
3872
3873 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3874
3875 if (unhandled_errors) {
3876 dispc.error_irqs |= unhandled_errors;
3877
3878 dispc.irq_error_mask &= ~unhandled_errors;
3879 _omap_dispc_set_irqs();
3880
3881 schedule_work(&dispc.error_work);
3882 }
3883
3884 spin_unlock(&dispc.irq_lock);
affe360d 3885
3886 return IRQ_HANDLED;
80c39712
TV		 3887}
3888
3889static void dispc_error_worker(struct work_struct *work)
3890{
3891 int i;
3892 u32 errors;
3893 unsigned long flags;
fe3cc9d6
TV		 3894 static const unsigned fifo_underflow_bits[] = {
3895 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3896 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3897 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3898 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3899 };
3900
80c39712
TV		 3901 spin_lock_irqsave(&dispc.irq_lock, flags);
3902 errors = dispc.error_irqs;
3903 dispc.error_irqs = 0;
3904 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3905
13eae1f9
DZ		 3906 dispc_runtime_get();
3907
fe3cc9d6
TV		 3908 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3909 struct omap_overlay *ovl;
3910 unsigned bit;
80c39712 3911
fe3cc9d6
TV		 3912 ovl = omap_dss_get_overlay(i);
3913 bit = fifo_underflow_bits[i];
80c39712 3914
fe3cc9d6
TV		 3915 if (bit & errors) {
3916 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3917 ovl->name);
f0e5caab 3918 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3919 dispc_mgr_go(ovl->manager->id);
d7ad718d 3920 msleep(50);
80c39712
TV		 3921 }
3922 }
3923
fe3cc9d6
TV		 3924 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3925 struct omap_overlay_manager *mgr;
3926 unsigned bit;
80c39712 3927
fe3cc9d6 3928 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3929 bit = mgr_desc[i].sync_lost_irq;
80c39712 3930
fe3cc9d6 3931 if (bit & errors) {
4c6c65b0 3932 int j;
80c39712 3933
fe3cc9d6
TV		 3934 DSSERR("SYNC_LOST on channel %s, restarting the output "
3935 "with video overlays disabled\n",
3936 mgr->name);
2a205f34 3937
b276dd09 3938 dss_mgr_disable(mgr);
2a205f34 3939
4c6c65b0 3940 for (j = 0; j < omap_dss_get_num_overlays(); ++j) {
2a205f34 3941 struct omap_overlay *ovl;
4c6c65b0 3942 ovl = omap_dss_get_overlay(j);
2a205f34 3943
fe3cc9d6
TV		 3944 if (ovl->id != OMAP_DSS_GFX &&
3945 ovl->manager == mgr)
b276dd09 3946 ovl->disable(ovl);
2a205f34
SS		 3947 }
3948
b276dd09 3949 dss_mgr_enable(mgr);
2a205f34
SS		 3950 }
3951 }
3952
80c39712
TV		 3953 if (errors & DISPC_IRQ_OCP_ERR) {
3954 DSSERR("OCP_ERR\n");
3955 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3956 struct omap_overlay_manager *mgr;
794bc4ee 3957
80c39712 3958 mgr = omap_dss_get_overlay_manager(i);
b276dd09 3959 dss_mgr_disable(mgr);
80c39712
TV		 3960 }
3961 }
3962
3963 spin_lock_irqsave(&dispc.irq_lock, flags);
3964 dispc.irq_error_mask |= errors;
3965 _omap_dispc_set_irqs();
3966 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3967
3968 dispc_runtime_put();
80c39712
TV		 3969}
3970
3971int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3972{
3973 void dispc_irq_wait_handler(void *data, u32 mask)
3974 {
3975 complete((struct completion *)data);
3976 }
3977
3978 int r;
3979 DECLARE_COMPLETION_ONSTACK(completion);
3980
3981 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3982 irqmask);
3983
3984 if (r)
3985 return r;
3986
3987 timeout = wait_for_completion_timeout(&completion, timeout);
3988
3989 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3990
3991 if (timeout == 0)
3992 return -ETIMEDOUT;
3993
80c39712
TV		 3994 return 0;
3995}
3996
3997int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3998 unsigned long timeout)
3999{
4000 void dispc_irq_wait_handler(void *data, u32 mask)
4001 {
4002 complete((struct completion *)data);
4003 }
4004
4005 int r;
4006 DECLARE_COMPLETION_ONSTACK(completion);
4007
4008 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
4009 irqmask);
4010
4011 if (r)
4012 return r;
4013
4014 timeout = wait_for_completion_interruptible_timeout(&completion,
4015 timeout);
4016
4017 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
4018
4019 if (timeout == 0)
4020 return -ETIMEDOUT;
4021
4022 if (timeout == -ERESTARTSYS)
4023 return -ERESTARTSYS;
4024
4025 return 0;
4026}
4027
80c39712
TV		 4028static void _omap_dispc_initialize_irq(void)
4029{
4030 unsigned long flags;
4031
4032 spin_lock_irqsave(&dispc.irq_lock, flags);
4033
4034 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
4035
4036 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 4037 if (dss_has_feature(FEAT_MGR_LCD2))
4038 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 4039 if (dss_has_feature(FEAT_MGR_LCD3))
4040 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 4041 if (dss_feat_get_num_ovls() > 3)
4042 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 4043
4044 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
4045 * so clear it */
4e0397cf 4046 dispc_clear_irqstatus(dispc_read_irqstatus());
80c39712
TV		 4047
4048 _omap_dispc_set_irqs();
4049
4050 spin_unlock_irqrestore(&dispc.irq_lock, flags);
4051}
4052
4053void dispc_enable_sidle(void)
4054{
4055 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
4056}
4057
4058void dispc_disable_sidle(void)
4059{
4060 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
4061}
4062
4063static void _omap_dispc_initial_config(void)
4064{
4065 u32 l;
4066
0cf35df3
MR		 4067 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4068 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
4069 l = dispc_read_reg(DISPC_DIVISOR);
4070 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
4071 l = FLD_MOD(l, 1, 0, 0);
4072 l = FLD_MOD(l, 1, 23, 16);
4073 dispc_write_reg(DISPC_DIVISOR, l);
4074 }
4075
80c39712 4076 /* FUNCGATED */
6ced40bf
AT		 4077 if (dss_has_feature(FEAT_FUNCGATED))
4078 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 4079
6e5264b0 4080 dispc_setup_color_conv_coef();
80c39712
TV		 4081
4082 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
4083
42a6961c 4084 dispc_init_fifos();
5ed8cf5b
TV		 4085
4086 dispc_configure_burst_sizes();
54128701
AT		 4087
4088 dispc_ovl_enable_zorder_planes();
80c39712
TV		 4089}
4090
dcbe765b
CM		 4091static const struct dispc_features omap24xx_dispc_feats __initconst = {
4092 .sw_start = 5,
4093 .fp_start = 15,
4094 .bp_start = 27,
4095 .sw_max = 64,
4096 .vp_max = 255,
4097 .hp_max = 256,
33b89928
AT		 4098 .mgr_width_start = 10,
4099 .mgr_height_start = 26,
4100 .mgr_width_max = 2048,
4101 .mgr_height_max = 2048,
dcbe765b
CM		 4102 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4103 .calc_core_clk = calc_core_clk_24xx,
42a6961c 4104 .num_fifos = 3,
cffa947d 4105 .no_framedone_tv = true,
dcbe765b
CM		 4106};
4107
4108static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
4109 .sw_start = 5,
4110 .fp_start = 15,
4111 .bp_start = 27,
4112 .sw_max = 64,
4113 .vp_max = 255,
4114 .hp_max = 256,
33b89928
AT		 4115 .mgr_width_start = 10,
4116 .mgr_height_start = 26,
4117 .mgr_width_max = 2048,
4118 .mgr_height_max = 2048,
dcbe765b
CM		 4119 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4120 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4121 .num_fifos = 3,
cffa947d 4122 .no_framedone_tv = true,
dcbe765b
CM		 4123};
4124
4125static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
4126 .sw_start = 7,
4127 .fp_start = 19,
4128 .bp_start = 31,
4129 .sw_max = 256,
4130 .vp_max = 4095,
4131 .hp_max = 4096,
33b89928
AT		 4132 .mgr_width_start = 10,
4133 .mgr_height_start = 26,
4134 .mgr_width_max = 2048,
4135 .mgr_height_max = 2048,
dcbe765b
CM		 4136 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4137 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4138 .num_fifos = 3,
cffa947d 4139 .no_framedone_tv = true,
dcbe765b
CM		 4140};
4141
4142static const struct dispc_features omap44xx_dispc_feats __initconst = {
4143 .sw_start = 7,
4144 .fp_start = 19,
4145 .bp_start = 31,
4146 .sw_max = 256,
4147 .vp_max = 4095,
4148 .hp_max = 4096,
33b89928
AT		 4149 .mgr_width_start = 10,
4150 .mgr_height_start = 26,
4151 .mgr_width_max = 2048,
4152 .mgr_height_max = 2048,
dcbe765b
CM		 4153 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4154 .calc_core_clk = calc_core_clk_44xx,
42a6961c 4155 .num_fifos = 5,
66a0f9e4 4156 .gfx_fifo_workaround = true,
dcbe765b
CM		 4157};
4158
264236f8
AT		 4159static const struct dispc_features omap54xx_dispc_feats __initconst = {
4160 .sw_start = 7,
4161 .fp_start = 19,
4162 .bp_start = 31,
4163 .sw_max = 256,
4164 .vp_max = 4095,
4165 .hp_max = 4096,
4166 .mgr_width_start = 11,
4167 .mgr_height_start = 27,
4168 .mgr_width_max = 4096,
4169 .mgr_height_max = 4096,
4170 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4171 .calc_core_clk = calc_core_clk_44xx,
4172 .num_fifos = 5,
4173 .gfx_fifo_workaround = true,
4174};
4175
84b47623 4176static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 4177{
4178 const struct dispc_features *src;
4179 struct dispc_features *dst;
4180
84b47623 4181 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 4182 if (!dst) {
84b47623 4183 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 4184 return -ENOMEM;
4185 }
4186
b2c7d54f 4187 switch (omapdss_get_version()) {
84b47623 4188 case OMAPDSS_VER_OMAP24xx:
dcbe765b 4189 src = &omap24xx_dispc_feats;
84b47623
TV		 4190 break;
4191
4192 case OMAPDSS_VER_OMAP34xx_ES1:
4193 src = &omap34xx_rev1_0_dispc_feats;
4194 break;
4195
4196 case OMAPDSS_VER_OMAP34xx_ES3:
4197 case OMAPDSS_VER_OMAP3630:
4198 case OMAPDSS_VER_AM35xx:
4199 src = &omap34xx_rev3_0_dispc_feats;
4200 break;
4201
4202 case OMAPDSS_VER_OMAP4430_ES1:
4203 case OMAPDSS_VER_OMAP4430_ES2:
4204 case OMAPDSS_VER_OMAP4:
dcbe765b 4205 src = &omap44xx_dispc_feats;
84b47623
TV		 4206 break;
4207
4208 case OMAPDSS_VER_OMAP5:
264236f8 4209 src = &omap54xx_dispc_feats;
84b47623
TV		 4210 break;
4211
4212 default:
dcbe765b
CM		 4213 return -ENODEV;
4214 }
4215
4216 memcpy(dst, src, sizeof(*dst));
4217 dispc.feat = dst;
4218
4219 return 0;
4220}
4221
060b6d9c 4222/* DISPC HW IP initialisation */
6e7e8f06 4223static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 4224{
4225 u32 rev;
affe360d 4226 int r = 0;
ea9da36a 4227 struct resource *dispc_mem;
4fbafaf3 4228 struct clk *clk;
ea9da36a 4229
060b6d9c
SG		 4230 dispc.pdev = pdev;
4231
84b47623 4232 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4233 if (r)
4234 return r;
4235
060b6d9c
SG		 4236 spin_lock_init(&dispc.irq_lock);
4237
4238#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4239 spin_lock_init(&dispc.irq_stats_lock);
4240 dispc.irq_stats.last_reset = jiffies;
4241#endif
4242
4243 INIT_WORK(&dispc.error_work, dispc_error_worker);
4244
ea9da36a
SG		 4245 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4246 if (!dispc_mem) {
4247 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4248 return -EINVAL;
ea9da36a 4249 }
cd3b3449 4250
6e2a14d2
JL		 4251 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4252 resource_size(dispc_mem));
060b6d9c
SG		 4253 if (!dispc.base) {
4254 DSSERR("can't ioremap DISPC\n");
cd3b3449 4255 return -ENOMEM;
affe360d 4256 }
cd3b3449 4257
affe360d 4258 dispc.irq = platform_get_irq(dispc.pdev, 0);
4259 if (dispc.irq < 0) {
4260 DSSERR("platform_get_irq failed\n");
cd3b3449 4261 return -ENODEV;
affe360d 4262 }
4263
6e2a14d2
JL		 4264 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4265 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 4266 if (r < 0) {
4267 DSSERR("request_irq failed\n");
cd3b3449
TV		 4268 return r;
4269 }
4270
4271 clk = clk_get(&pdev->dev, "fck");
4272 if (IS_ERR(clk)) {
4273 DSSERR("can't get fck\n");
4274 r = PTR_ERR(clk);
4275 return r;
060b6d9c
SG		 4276 }
4277
cd3b3449
TV		 4278 dispc.dss_clk = clk;
4279
4fbafaf3
TV		 4280 pm_runtime_enable(&pdev->dev);
4281
4282 r = dispc_runtime_get();
4283 if (r)
4284 goto err_runtime_get;
060b6d9c
SG		 4285
4286 _omap_dispc_initial_config();
4287
4288 _omap_dispc_initialize_irq();
4289
060b6d9c 4290 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4291 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4292 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4293
4fbafaf3 4294 dispc_runtime_put();
060b6d9c 4295
e40402cf
TV		 4296 dss_debugfs_create_file("dispc", dispc_dump_regs);
4297
4298#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4299 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4300#endif
060b6d9c 4301 return 0;
4fbafaf3
TV		 4302
4303err_runtime_get:
4304 pm_runtime_disable(&pdev->dev);
4fbafaf3 4305 clk_put(dispc.dss_clk);
affe360d 4306 return r;
060b6d9c
SG		 4307}
4308
6e7e8f06 4309static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4310{
4fbafaf3
TV		 4311 pm_runtime_disable(&pdev->dev);
4312
4313 clk_put(dispc.dss_clk);
4314
060b6d9c
SG		 4315 return 0;
4316}
4317
4fbafaf3
TV		 4318static int dispc_runtime_suspend(struct device *dev)
4319{
4320 dispc_save_context();
4fbafaf3
TV		 4321
4322 return 0;
4323}
4324
4325static int dispc_runtime_resume(struct device *dev)
4326{
49ea86f3 4327 dispc_restore_context();
4fbafaf3
TV		 4328
4329 return 0;
4330}
4331
4332static const struct dev_pm_ops dispc_pm_ops = {
4333 .runtime_suspend = dispc_runtime_suspend,
4334 .runtime_resume = dispc_runtime_resume,
4335};
4336
060b6d9c 4337static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4338 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4339 .driver = {
4340 .name = "omapdss_dispc",
4341 .owner = THIS_MODULE,
4fbafaf3 4342 .pm = &dispc_pm_ops,
060b6d9c
SG		 4343 },
4344};
4345
6e7e8f06 4346int __init dispc_init_platform_driver(void)
060b6d9c 4347{
11436e1d 4348 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4349}
4350
6e7e8f06 4351void __exit dispc_uninit_platform_driver(void)
060b6d9c 4352{
04c742c3 4353 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4354}
Linux 6.x block layer and io_uring tree(s)