projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| fc4effc7 DV |
1 | /* |
| 2 | * Geode GX video device | |
| 3 | * | |
| 4 | * Copyright (C) 2006 Arcom Control Systems Ltd. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License as published by | |
| 8 | * the Free Software Foundation; either version 2 of the License, or | |
| 9 | * (at your option) any later version. | |
| 10 | */ | |
| 11 | #ifndef __VIDEO_GX_H__ | |
| 12 | #define __VIDEO_GX_H__ | |
| 13 | ||
| 14 | extern struct geode_vid_ops gx_vid_ops; | |
| 15 | ||
| ab1db0cf | 16 | /* GX Flatpanel control MSR */ |
| 53d53bd4 | 17 | #define GX_VP_MSR_PAD_SELECT 0xC0002011 |
| ab1db0cf JC |
18 | #define GX_VP_PAD_SELECT_MASK 0x3FFFFFFF |
| 19 | #define GX_VP_PAD_SELECT_TFT 0x1FFFFFFF | |
| 20 | ||
| fc4effc7 DV |
21 | /* Geode GX video processor registers */ |
| 22 | ||
| 23 | #define GX_DCFG 0x0008 | |
| 24 | # define GX_DCFG_CRT_EN 0x00000001 | |
| 25 | # define GX_DCFG_HSYNC_EN 0x00000002 | |
| 26 | # define GX_DCFG_VSYNC_EN 0x00000004 | |
| 27 | # define GX_DCFG_DAC_BL_EN 0x00000008 | |
| 58219896 JC |
28 | # define GX_DCFG_FP_PWR_EN 0x00000040 |
| 29 | # define GX_DCFG_FP_DATA_EN 0x00000080 | |
| fc4effc7 DV |
30 | # define GX_DCFG_CRT_HSYNC_POL 0x00000100 |
| 31 | # define GX_DCFG_CRT_VSYNC_POL 0x00000200 | |
| 32 | # define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 | |
| 33 | # define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000 | |
| 34 | # define GX_DCFG_VG_CK 0x00100000 | |
| 35 | # define GX_DCFG_GV_GAM 0x00200000 | |
| 36 | # define GX_DCFG_DAC_VREF 0x04000000 | |
| 37 | ||
| f378819a JC |
38 | /* Geode GX MISC video configuration */ |
| 39 | ||
| 40 | #define GX_MISC 0x50 | |
| 41 | #define GX_MISC_GAM_EN 0x00000001 | |
| 42 | #define GX_MISC_DAC_PWRDN 0x00000400 | |
| 43 | #define GX_MISC_A_PWRDN 0x00000800 | |
| 44 | ||
| fc4effc7 | 45 | /* Geode GX flat panel display control registers */ |
| ab1db0cf JC |
46 | |
| 47 | #define GX_FP_PT1 0x0400 | |
| 48 | #define GX_FP_PT1_VSIZE_MASK 0x7FF0000 | |
| 49 | #define GX_FP_PT1_VSIZE_SHIFT 16 | |
| 50 | ||
| 51 | #define GX_FP_PT2 0x408 | |
| 52 | #define GX_FP_PT2_VSP (1 << 23) | |
| 53 | #define GX_FP_PT2_HSP (1 << 22) | |
| 54 | ||
| fc4effc7 DV |
55 | #define GX_FP_PM 0x410 |
| 56 | # define GX_FP_PM_P 0x01000000 | |
| 57 | ||
| ab1db0cf JC |
58 | #define GX_FP_DFC 0x418 |
| 59 | ||
| fc4effc7 DV |
60 | /* Geode GX clock control MSRs */ |
| 61 | ||
| 62 | #define MSR_GLCP_SYS_RSTPLL 0x4c000014 | |
| 63 | # define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull) | |
| 64 | # define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull) | |
| 65 | # define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull) | |
| 66 | ||
| 67 | #define MSR_GLCP_DOTPLL 0x4c000015 | |
| 68 | # define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull) | |
| 69 | # define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull) | |
| 70 | # define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull) | |
| 71 | ||
| 72 | #endif /* !__VIDEO_GX_H__ */ |