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drivers/video: fsl-diu-fb: only DIU modes 0 and 1 are supported
[linux-block.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
b715f9f0 33#include <linux/spinlock.h>
9b53a9e2 34
9b53a9e2 35#include <sysdev/fsl_soc.h>
0814a979 36#include <linux/fsl-diu-fb.h>
8b856f04 37#include "edid.h"
9b53a9e2 38
b715f9f0
TT		 39#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
40 /* 1 for plane 0, 2 for plane 1&2 each */
41
42/* HW cursor parameters */
43#define MAX_CURS 32
44
45/* INT_STATUS/INT_MASK field descriptions */
46#define INT_VSYNC 0x01 /* Vsync interrupt */
47#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
48#define INT_UNDRUN 0x04 /* Under run exception interrupt */
49#define INT_PARERR 0x08 /* Display parameters error interrupt */
50#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
51
b715f9f0
TT		 52struct diu_hw {
53 struct diu __iomem *diu_reg;
54 spinlock_t reg_lock;
b715f9f0
TT		 55};
56
57struct diu_addr {
58 void *vaddr; /* Virtual address */
59 dma_addr_t paddr; /* Physical address */
60 __u32 offset;
61};
62
63struct diu_pool {
64 struct diu_addr ad;
65 struct diu_addr gamma;
66 struct diu_addr pallete;
67 struct diu_addr cursor;
68};
69
9b53a9e2 70/*
63cf8df4
TT		 71 * List of supported video modes
72 *
760af8f8
TT		 73 * The first entry is the default video mode. The remain entries are in
74 * order if increasing resolution and frequency. The 320x240-60 mode is
75 * the initial AOI for the second and third planes.
9b53a9e2 76 */
9b53a9e2
YS		 77static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
78 {
9b53a9e2
YS		 79 .refresh = 60,
80 .xres = 1024,
81 .yres = 768,
82 .pixclock = 15385,
83 .left_margin = 160,
84 .right_margin = 24,
85 .upper_margin = 29,
86 .lower_margin = 3,
87 .hsync_len = 136,
88 .vsync_len = 6,
89 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
90 .vmode = FB_VMODE_NONINTERLACED
91 },
92 {
760af8f8
TT		 93 .refresh = 60,
94 .xres = 320,
95 .yres = 240,
96 .pixclock = 79440,
97 .left_margin = 16,
98 .right_margin = 16,
99 .upper_margin = 16,
100 .lower_margin = 5,
101 .hsync_len = 48,
102 .vsync_len = 1,
103 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
104 .vmode = FB_VMODE_NONINTERLACED
105 },
106 {
107 .refresh = 60,
108 .xres = 640,
109 .yres = 480,
110 .pixclock = 39722,
111 .left_margin = 48,
112 .right_margin = 16,
113 .upper_margin = 33,
114 .lower_margin = 10,
115 .hsync_len = 96,
116 .vsync_len = 2,
117 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 .vmode = FB_VMODE_NONINTERLACED
119 },
120 {
121 .refresh = 72,
122 .xres = 640,
123 .yres = 480,
124 .pixclock = 32052,
125 .left_margin = 128,
126 .right_margin = 24,
127 .upper_margin = 28,
128 .lower_margin = 9,
129 .hsync_len = 40,
130 .vsync_len = 3,
131 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
132 .vmode = FB_VMODE_NONINTERLACED
133 },
134 {
135 .refresh = 75,
136 .xres = 640,
137 .yres = 480,
138 .pixclock = 31747,
139 .left_margin = 120,
140 .right_margin = 16,
141 .upper_margin = 16,
142 .lower_margin = 1,
143 .hsync_len = 64,
144 .vsync_len = 3,
145 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
146 .vmode = FB_VMODE_NONINTERLACED
147 },
148 {
149 .refresh = 90,
150 .xres = 640,
151 .yres = 480,
152 .pixclock = 25057,
153 .left_margin = 120,
154 .right_margin = 32,
155 .upper_margin = 14,
156 .lower_margin = 25,
157 .hsync_len = 40,
158 .vsync_len = 14,
159 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
160 .vmode = FB_VMODE_NONINTERLACED
161 },
162 {
163 .refresh = 100,
164 .xres = 640,
165 .yres = 480,
166 .pixclock = 22272,
167 .left_margin = 48,
168 .right_margin = 32,
169 .upper_margin = 17,
170 .lower_margin = 22,
171 .hsync_len = 128,
172 .vsync_len = 12,
173 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
174 .vmode = FB_VMODE_NONINTERLACED
175 },
176 {
177 .refresh = 60,
178 .xres = 800,
179 .yres = 480,
180 .pixclock = 33805,
181 .left_margin = 96,
182 .right_margin = 24,
183 .upper_margin = 10,
184 .lower_margin = 3,
185 .hsync_len = 72,
186 .vsync_len = 7,
187 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
188 .vmode = FB_VMODE_NONINTERLACED
189 },
190 {
191 .refresh = 60,
192 .xres = 800,
193 .yres = 600,
194 .pixclock = 25000,
195 .left_margin = 88,
196 .right_margin = 40,
197 .upper_margin = 23,
198 .lower_margin = 1,
199 .hsync_len = 128,
200 .vsync_len = 4,
201 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
202 .vmode = FB_VMODE_NONINTERLACED
203 },
204 {
205 .refresh = 60,
206 .xres = 854,
207 .yres = 480,
208 .pixclock = 31518,
209 .left_margin = 104,
210 .right_margin = 16,
211 .upper_margin = 13,
212 .lower_margin = 1,
213 .hsync_len = 88,
214 .vsync_len = 3,
215 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
216 .vmode = FB_VMODE_NONINTERLACED
217 },
218 {
9b53a9e2
YS		 219 .refresh = 70,
220 .xres = 1024,
221 .yres = 768,
222 .pixclock = 16886,
223 .left_margin = 3,
224 .right_margin = 3,
225 .upper_margin = 2,
226 .lower_margin = 2,
227 .hsync_len = 40,
228 .vsync_len = 18,
229 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
230 .vmode = FB_VMODE_NONINTERLACED
231 },
232 {
9b53a9e2
YS		 233 .refresh = 75,
234 .xres = 1024,
235 .yres = 768,
236 .pixclock = 15009,
237 .left_margin = 3,
238 .right_margin = 3,
239 .upper_margin = 2,
240 .lower_margin = 2,
241 .hsync_len = 80,
242 .vsync_len = 32,
243 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
244 .vmode = FB_VMODE_NONINTERLACED
245 },
246 {
760af8f8
TT		 247 .refresh = 60,
248 .xres = 1280,
249 .yres = 480,
250 .pixclock = 18939,
251 .left_margin = 353,
252 .right_margin = 47,
253 .upper_margin = 39,
254 .lower_margin = 4,
255 .hsync_len = 8,
256 .vsync_len = 2,
257 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
258 .vmode = FB_VMODE_NONINTERLACED
259 },
260 {
261 .refresh = 60,
262 .xres = 1280,
263 .yres = 720,
264 .pixclock = 13426,
265 .left_margin = 192,
266 .right_margin = 64,
267 .upper_margin = 22,
268 .lower_margin = 1,
269 .hsync_len = 136,
270 .vsync_len = 3,
271 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
272 .vmode = FB_VMODE_NONINTERLACED
273 },
274 {
9b53a9e2
YS		 275 .refresh = 60,
276 .xres = 1280,
277 .yres = 1024,
278 .pixclock = 9375,
279 .left_margin = 38,
280 .right_margin = 128,
281 .upper_margin = 2,
282 .lower_margin = 7,
283 .hsync_len = 216,
284 .vsync_len = 37,
285 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
286 .vmode = FB_VMODE_NONINTERLACED
287 },
288 {
9b53a9e2
YS		 289 .refresh = 70,
290 .xres = 1280,
291 .yres = 1024,
292 .pixclock = 9380,
293 .left_margin = 6,
294 .right_margin = 6,
295 .upper_margin = 4,
296 .lower_margin = 4,
297 .hsync_len = 60,
298 .vsync_len = 94,
299 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
300 .vmode = FB_VMODE_NONINTERLACED
301 },
302 {
9b53a9e2
YS		 303 .refresh = 75,
304 .xres = 1280,
305 .yres = 1024,
306 .pixclock = 9380,
307 .left_margin = 6,
308 .right_margin = 6,
309 .upper_margin = 4,
310 .lower_margin = 4,
311 .hsync_len = 60,
312 .vsync_len = 15,
313 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
314 .vmode = FB_VMODE_NONINTERLACED
315 },
316 {
9b53a9e2 317 .refresh = 60,
760af8f8
TT		 318 .xres = 1920,
319 .yres = 1080,
320 .pixclock = 5787,
321 .left_margin = 328,
322 .right_margin = 120,
323 .upper_margin = 34,
324 .lower_margin = 1,
325 .hsync_len = 208,
326 .vsync_len = 3,
9b53a9e2
YS		 327 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
328 .vmode = FB_VMODE_NONINTERLACED
329 },
330};
331
760af8f8 332static char *fb_mode;
9b53a9e2 333static unsigned long default_bpp = 32;
7653aaab
TT		 334static enum fsl_diu_monitor_port monitor_port;
335static char *monitor_string;
9b53a9e2
YS		 336
337#if defined(CONFIG_NOT_COHERENT_CACHE)
338static u8 *coherence_data;
339static size_t coherence_data_size;
340static unsigned int d_cache_line_size;
341#endif
342
343static DEFINE_SPINLOCK(diu_lock);
344
345struct fsl_diu_data {
346 struct fb_info *fsl_diu_info[FSL_AOI_NUM - 1];
347 /*FSL_AOI_NUM has one dummy AOI */
348 struct device_attribute dev_attr;
349 struct diu_ad *dummy_ad;
350 void *dummy_aoi_virt;
351 unsigned int irq;
352 int fb_enabled;
7653aaab 353 enum fsl_diu_monitor_port monitor_port;
9b53a9e2
YS		 354};
355
2572df91
TT		 356enum mfb_index {
357 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
358 PLANE1_AOI0, /* Plane 1, first AOI */
359 PLANE1_AOI1, /* Plane 1, second AOI */
360 PLANE2_AOI0, /* Plane 2, first AOI */
361 PLANE2_AOI1, /* Plane 2, second AOI */
362};
363
9b53a9e2 364struct mfb_info {
2572df91 365 enum mfb_index index;
9b53a9e2
YS		 366 char *id;
367 int registered;
9b53a9e2
YS		 368 unsigned long pseudo_palette[16];
369 struct diu_ad *ad;
370 int cursor_reset;
371 unsigned char g_alpha;
372 unsigned int count;
373 int x_aoi_d; /* aoi display x offset to physical screen */
374 int y_aoi_d; /* aoi display y offset to physical screen */
375 struct fsl_diu_data *parent;
8b856f04 376 u8 *edid_data;
9b53a9e2
YS		 377};
378
379
380static struct mfb_info mfb_template[] = {
2572df91
TT		 381 {
382 .index = PLANE0,
4a85dc8b
TT		 383 .id = "Panel0",
384 .registered = 0,
385 .count = 0,
386 .x_aoi_d = 0,
387 .y_aoi_d = 0,
9b53a9e2 388 },
2572df91
TT		 389 {
390 .index = PLANE1_AOI0,
4a85dc8b
TT		 391 .id = "Panel1 AOI0",
392 .registered = 0,
393 .g_alpha = 0xff,
394 .count = 0,
395 .x_aoi_d = 0,
396 .y_aoi_d = 0,
9b53a9e2 397 },
2572df91
TT		 398 {
399 .index = PLANE1_AOI1,
4a85dc8b
TT		 400 .id = "Panel1 AOI1",
401 .registered = 0,
402 .g_alpha = 0xff,
403 .count = 0,
404 .x_aoi_d = 0,
405 .y_aoi_d = 480,
9b53a9e2 406 },
2572df91
TT		 407 {
408 .index = PLANE2_AOI0,
4a85dc8b
TT		 409 .id = "Panel2 AOI0",
410 .registered = 0,
411 .g_alpha = 0xff,
412 .count = 0,
413 .x_aoi_d = 640,
414 .y_aoi_d = 0,
9b53a9e2 415 },
2572df91
TT		 416 {
417 .index = PLANE2_AOI1,
4a85dc8b
TT		 418 .id = "Panel2 AOI1",
419 .registered = 0,
420 .g_alpha = 0xff,
421 .count = 0,
422 .x_aoi_d = 640,
423 .y_aoi_d = 480,
9b53a9e2
YS		 424 },
425};
426
427static struct diu_hw dr = {
9b53a9e2
YS		 428 .reg_lock = __SPIN_LOCK_UNLOCKED(diu_hw.reg_lock),
429};
430
431static struct diu_pool pool;
432
7653aaab
TT		 433/**
434 * fsl_diu_name_to_port - convert a port name to a monitor port enum
435 *
436 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
437 * the enum fsl_diu_monitor_port that corresponds to that string.
438 *
439 * For compatibility with older versions, a number ("0", "1", or "2") is also
440 * supported.
441 *
442 * If the string is unknown, DVI is assumed.
443 *
444 * If the particular port is not supported by the platform, another port
445 * (platform-specific) is chosen instead.
446 */
447static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
448{
449 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
450 unsigned long val;
451
452 if (s) {
453 if (!strict_strtoul(s, 10, &val) && (val <= 2))
454 port = (enum fsl_diu_monitor_port) val;
455 else if (strncmp(s, "lvds", 4) == 0)
456 port = FSL_DIU_PORT_LVDS;
457 else if (strncmp(s, "dlvds", 5) == 0)
458 port = FSL_DIU_PORT_DLVDS;
459 }
460
461 return diu_ops.valid_monitor_port(port);
462}
463
6b51d51a
TT		 464/**
465 * fsl_diu_alloc - allocate memory for the DIU
466 * @size: number of bytes to allocate
467 * @param: returned physical address of memory
468 *
469 * This function allocates a physically-contiguous block of memory.
9b53a9e2 470 */
6b51d51a 471static void *fsl_diu_alloc(size_t size, phys_addr_t *phys)
9b53a9e2
YS		 472{
473 void *virt;
474
6b51d51a 475 virt = alloc_pages_exact(size, GFP_DMA | __GFP_ZERO);
154152ae 476 if (virt)
9b53a9e2 477 *phys = virt_to_phys(virt);
9b53a9e2 478
9b53a9e2
YS		 479 return virt;
480}
481
6b51d51a
TT		 482/**
483 * fsl_diu_free - release DIU memory
484 * @virt: pointer returned by fsl_diu_alloc()
485 * @size: number of bytes allocated by fsl_diu_alloc()
486 *
487 * This function releases memory allocated by fsl_diu_alloc().
488 */
489static void fsl_diu_free(void *virt, size_t size)
9b53a9e2 490{
6b51d51a
TT		 491 if (virt && size)
492 free_pages_exact(virt, size);
9b53a9e2
YS		 493}
494
0d9dab39
AG		 495/*
496 * Workaround for failed writing desc register of planes.
497 * Needed with MPC5121 DIU rev 2.0 silicon.
498 */
499void wr_reg_wa(u32 *reg, u32 val)
500{
501 do {
502 out_be32(reg, val);
503 } while (in_be32(reg) != val);
504}
505
7e47c211 506static void fsl_diu_enable_panel(struct fb_info *info)
9b53a9e2
YS		 507{
508 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
509 struct diu *hw = dr.diu_reg;
510 struct diu_ad *ad = mfbi->ad;
511 struct fsl_diu_data *machine_data = mfbi->parent;
9b53a9e2 512
7e47c211
TT		 513 switch (mfbi->index) {
514 case PLANE0:
515 if (hw->desc[0] != ad->paddr)
516 wr_reg_wa(&hw->desc[0], ad->paddr);
517 break;
518 case PLANE1_AOI0:
519 cmfbi = machine_data->fsl_diu_info[2]->par;
520 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
521 if (cmfbi->count > 0) /* AOI1 open */
522 ad->next_ad =
523 cpu_to_le32(cmfbi->ad->paddr);
524 else
525 ad->next_ad = 0;
526 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2 527 }
7e47c211
TT		 528 break;
529 case PLANE2_AOI0:
530 cmfbi = machine_data->fsl_diu_info[4]->par;
531 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
532 if (cmfbi->count > 0) /* AOI1 open */
533 ad->next_ad =
534 cpu_to_le32(cmfbi->ad->paddr);
535 else
536 ad->next_ad = 0;
537 wr_reg_wa(&hw->desc[2], ad->paddr);
538 }
539 break;
540 case PLANE1_AOI1:
541 pmfbi = machine_data->fsl_diu_info[1]->par;
542 ad->next_ad = 0;
543 if (hw->desc[1] == machine_data->dummy_ad->paddr)
544 wr_reg_wa(&hw->desc[1], ad->paddr);
545 else /* AOI0 open */
546 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
547 break;
548 case PLANE2_AOI1:
549 pmfbi = machine_data->fsl_diu_info[3]->par;
550 ad->next_ad = 0;
551 if (hw->desc[2] == machine_data->dummy_ad->paddr)
552 wr_reg_wa(&hw->desc[2], ad->paddr);
553 else /* AOI0 was open */
554 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
555 break;
556 }
9b53a9e2
YS		 557}
558
2572df91 559static void fsl_diu_disable_panel(struct fb_info *info)
9b53a9e2
YS		 560{
561 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
562 struct diu *hw = dr.diu_reg;
563 struct diu_ad *ad = mfbi->ad;
564 struct fsl_diu_data *machine_data = mfbi->parent;
9b53a9e2
YS		 565
566 switch (mfbi->index) {
2572df91 567 case PLANE0:
9b53a9e2 568 if (hw->desc[0] != machine_data->dummy_ad->paddr)
0d9dab39 569 wr_reg_wa(&hw->desc[0], machine_data->dummy_ad->paddr);
9b53a9e2 570 break;
2572df91 571 case PLANE1_AOI0:
9b53a9e2
YS		 572 cmfbi = machine_data->fsl_diu_info[2]->par;
573 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 574 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 575 /* move AOI1 to the first */
576 else /* AOI1 was closed */
0d9dab39 577 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 578 /* close AOI 0 */
579 break;
2572df91 580 case PLANE2_AOI0:
9b53a9e2
YS		 581 cmfbi = machine_data->fsl_diu_info[4]->par;
582 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 583 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 584 /* move AOI1 to the first */
585 else /* AOI1 was closed */
0d9dab39 586 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 587 /* close AOI 0 */
588 break;
2572df91 589 case PLANE1_AOI1:
9b53a9e2
YS		 590 pmfbi = machine_data->fsl_diu_info[1]->par;
591 if (hw->desc[1] != ad->paddr) {
592 /* AOI1 is not the first in the chain */
593 if (pmfbi->count > 0)
594 /* AOI0 is open, must be the first */
595 pmfbi->ad->next_ad = 0;
596 } else /* AOI1 is the first in the chain */
0d9dab39 597 wr_reg_wa(&hw->desc[1], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 598 /* close AOI 1 */
599 break;
2572df91 600 case PLANE2_AOI1:
9b53a9e2
YS		 601 pmfbi = machine_data->fsl_diu_info[3]->par;
602 if (hw->desc[2] != ad->paddr) {
603 /* AOI1 is not the first in the chain */
604 if (pmfbi->count > 0)
605 /* AOI0 is open, must be the first */
606 pmfbi->ad->next_ad = 0;
607 } else /* AOI1 is the first in the chain */
0d9dab39 608 wr_reg_wa(&hw->desc[2], machine_data->dummy_ad->paddr);
9b53a9e2
YS		 609 /* close AOI 1 */
610 break;
9b53a9e2 611 }
9b53a9e2
YS		 612}
613
614static void enable_lcdc(struct fb_info *info)
615{
616 struct diu *hw = dr.diu_reg;
617 struct mfb_info *mfbi = info->par;
618 struct fsl_diu_data *machine_data = mfbi->parent;
619
620 if (!machine_data->fb_enabled) {
c4e5a023 621 out_be32(&hw->diu_mode, MFB_MODE1);
9b53a9e2
YS		 622 machine_data->fb_enabled++;
623 }
624}
625
626static void disable_lcdc(struct fb_info *info)
627{
628 struct diu *hw = dr.diu_reg;
629 struct mfb_info *mfbi = info->par;
630 struct fsl_diu_data *machine_data = mfbi->parent;
631
632 if (machine_data->fb_enabled) {
633 out_be32(&hw->diu_mode, 0);
634 machine_data->fb_enabled = 0;
635 }
636}
637
638static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
639 struct fb_info *info)
640{
641 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
642 struct fsl_diu_data *machine_data = mfbi->parent;
2572df91
TT		 643 int available_height, upper_aoi_bottom;
644 enum mfb_index index = mfbi->index;
9b53a9e2
YS		 645 int lower_aoi_is_open, upper_aoi_is_open;
646 __u32 base_plane_width, base_plane_height, upper_aoi_height;
647
648 base_plane_width = machine_data->fsl_diu_info[0]->var.xres;
649 base_plane_height = machine_data->fsl_diu_info[0]->var.yres;
650
fdfaa483
YS		 651 if (mfbi->x_aoi_d < 0)
652 mfbi->x_aoi_d = 0;
653 if (mfbi->y_aoi_d < 0)
654 mfbi->y_aoi_d = 0;
9b53a9e2 655 switch (index) {
2572df91 656 case PLANE0:
9b53a9e2
YS		 657 if (mfbi->x_aoi_d != 0)
658 mfbi->x_aoi_d = 0;
659 if (mfbi->y_aoi_d != 0)
660 mfbi->y_aoi_d = 0;
661 break;
2572df91
TT		 662 case PLANE1_AOI0:
663 case PLANE2_AOI0:
9b53a9e2
YS		 664 lower_aoi_mfbi = machine_data->fsl_diu_info[index+1]->par;
665 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
666 if (var->xres > base_plane_width)
667 var->xres = base_plane_width;
668 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
669 mfbi->x_aoi_d = base_plane_width - var->xres;
670
671 if (lower_aoi_is_open)
672 available_height = lower_aoi_mfbi->y_aoi_d;
673 else
674 available_height = base_plane_height;
675 if (var->yres > available_height)
676 var->yres = available_height;
677 if ((mfbi->y_aoi_d + var->yres) > available_height)
678 mfbi->y_aoi_d = available_height - var->yres;
679 break;
2572df91
TT		 680 case PLANE1_AOI1:
681 case PLANE2_AOI1:
9b53a9e2
YS		 682 upper_aoi_mfbi = machine_data->fsl_diu_info[index-1]->par;
683 upper_aoi_height =
684 machine_data->fsl_diu_info[index-1]->var.yres;
685 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
686 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
687 if (var->xres > base_plane_width)
688 var->xres = base_plane_width;
689 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
690 mfbi->x_aoi_d = base_plane_width - var->xres;
691 if (mfbi->y_aoi_d < 0)
692 mfbi->y_aoi_d = 0;
693 if (upper_aoi_is_open) {
694 if (mfbi->y_aoi_d < upper_aoi_bottom)
695 mfbi->y_aoi_d = upper_aoi_bottom;
696 available_height = base_plane_height
697 - upper_aoi_bottom;
698 } else
699 available_height = base_plane_height;
700 if (var->yres > available_height)
701 var->yres = available_height;
702 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
703 mfbi->y_aoi_d = base_plane_height - var->yres;
704 break;
705 }
706}
707/*
708 * Checks to see if the hardware supports the state requested by var passed
709 * in. This function does not alter the hardware state! If the var passed in
710 * is slightly off by what the hardware can support then we alter the var
711 * PASSED in to what we can do. If the hardware doesn't support mode change
712 * a -EINVAL will be returned by the upper layers.
713 */
714static int fsl_diu_check_var(struct fb_var_screeninfo *var,
715 struct fb_info *info)
716{
9b53a9e2
YS		 717 if (var->xres_virtual < var->xres)
718 var->xres_virtual = var->xres;
719 if (var->yres_virtual < var->yres)
720 var->yres_virtual = var->yres;
721
722 if (var->xoffset < 0)
723 var->xoffset = 0;
724
725 if (var->yoffset < 0)
726 var->yoffset = 0;
727
728 if (var->xoffset + info->var.xres > info->var.xres_virtual)
729 var->xoffset = info->var.xres_virtual - info->var.xres;
730
731 if (var->yoffset + info->var.yres > info->var.yres_virtual)
732 var->yoffset = info->var.yres_virtual - info->var.yres;
733
734 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
735 (var->bits_per_pixel != 16))
736 var->bits_per_pixel = default_bpp;
737
738 switch (var->bits_per_pixel) {
739 case 16:
740 var->red.length = 5;
741 var->red.offset = 11;
742 var->red.msb_right = 0;
743
744 var->green.length = 6;
745 var->green.offset = 5;
746 var->green.msb_right = 0;
747
748 var->blue.length = 5;
749 var->blue.offset = 0;
750 var->blue.msb_right = 0;
751
752 var->transp.length = 0;
753 var->transp.offset = 0;
754 var->transp.msb_right = 0;
755 break;
756 case 24:
757 var->red.length = 8;
758 var->red.offset = 0;
759 var->red.msb_right = 0;
760
761 var->green.length = 8;
762 var->green.offset = 8;
763 var->green.msb_right = 0;
764
765 var->blue.length = 8;
766 var->blue.offset = 16;
767 var->blue.msb_right = 0;
768
769 var->transp.length = 0;
770 var->transp.offset = 0;
771 var->transp.msb_right = 0;
772 break;
773 case 32:
774 var->red.length = 8;
775 var->red.offset = 16;
776 var->red.msb_right = 0;
777
778 var->green.length = 8;
779 var->green.offset = 8;
780 var->green.msb_right = 0;
781
782 var->blue.length = 8;
783 var->blue.offset = 0;
784 var->blue.msb_right = 0;
785
786 var->transp.length = 8;
787 var->transp.offset = 24;
788 var->transp.msb_right = 0;
789
790 break;
791 }
9b53a9e2
YS		 792
793 var->height = -1;
794 var->width = -1;
795 var->grayscale = 0;
796
797 /* Copy nonstd field to/from sync for fbset usage */
798 var->sync |= var->nonstd;
799 var->nonstd |= var->sync;
800
801 adjust_aoi_size_position(var, info);
802 return 0;
803}
804
805static void set_fix(struct fb_info *info)
806{
807 struct fb_fix_screeninfo *fix = &info->fix;
808 struct fb_var_screeninfo *var = &info->var;
809 struct mfb_info *mfbi = info->par;
810
ec02dd23 811 strncpy(fix->id, mfbi->id, sizeof(fix->id));
9b53a9e2
YS		 812 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
813 fix->type = FB_TYPE_PACKED_PIXELS;
814 fix->accel = FB_ACCEL_NONE;
815 fix->visual = FB_VISUAL_TRUECOLOR;
816 fix->xpanstep = 1;
817 fix->ypanstep = 1;
818}
819
820static void update_lcdc(struct fb_info *info)
821{
822 struct fb_var_screeninfo *var = &info->var;
823 struct mfb_info *mfbi = info->par;
824 struct fsl_diu_data *machine_data = mfbi->parent;
825 struct diu *hw;
826 int i, j;
827 char __iomem *cursor_base, *gamma_table_base;
828
829 u32 temp;
830
831 hw = dr.diu_reg;
832
9b53a9e2
YS		 833 diu_ops.set_monitor_port(machine_data->monitor_port);
834 gamma_table_base = pool.gamma.vaddr;
835 cursor_base = pool.cursor.vaddr;
836 /* Prep for DIU init - gamma table, cursor table */
837
838 for (i = 0; i <= 2; i++)
4a85dc8b
TT		 839 for (j = 0; j <= 255; j++)
840 *gamma_table_base++ = j;
9b53a9e2
YS		 841
842 diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
843
9b53a9e2
YS		 844 disable_lcdc(info);
845
846 /* Program DIU registers */
847
848 out_be32(&hw->gamma, pool.gamma.paddr);
849 out_be32(&hw->cursor, pool.cursor.paddr);
850
851 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
852 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
853 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
854 /* DISP SIZE */
9b53a9e2
YS		 855 out_be32(&hw->wb_size, 0); /* WB SIZE */
856 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
857
858 /* Horizontal and vertical configuration register */
859 temp = var->left_margin << 22 | /* BP_H */
860 var->hsync_len << 11 | /* PW_H */
861 var->right_margin; /* FP_H */
862
863 out_be32(&hw->hsyn_para, temp);
864
865 temp = var->upper_margin << 22 | /* BP_V */
866 var->vsync_len << 11 | /* PW_V */
867 var->lower_margin; /* FP_V */
868
869 out_be32(&hw->vsyn_para, temp);
870
9b53a9e2
YS		 871 diu_ops.set_pixel_clock(var->pixclock);
872
873 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
874 out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
875 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
876 out_be32(&hw->plut, 0x01F5F666);
877
878 /* Enable the DIU */
879 enable_lcdc(info);
880}
881
882static int map_video_memory(struct fb_info *info)
883{
884 phys_addr_t phys;
537a1bf0 885 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
9b53a9e2 886
537a1bf0 887 info->screen_base = fsl_diu_alloc(smem_len, &phys);
05946bce 888 if (info->screen_base == NULL) {
154152ae 889 dev_err(info->dev, "unable to allocate fb memory\n");
9b53a9e2
YS		 890 return -ENOMEM;
891 }
537a1bf0 892 mutex_lock(&info->mm_lock);
9b53a9e2 893 info->fix.smem_start = (unsigned long) phys;
537a1bf0
KH		 894 info->fix.smem_len = smem_len;
895 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 896 info->screen_size = info->fix.smem_len;
897
9b53a9e2
YS		 898 return 0;
899}
900
901static void unmap_video_memory(struct fb_info *info)
902{
903 fsl_diu_free(info->screen_base, info->fix.smem_len);
537a1bf0 904 mutex_lock(&info->mm_lock);
05946bce 905 info->screen_base = NULL;
9b53a9e2
YS		 906 info->fix.smem_start = 0;
907 info->fix.smem_len = 0;
537a1bf0 908 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 909}
910
ae5591e3
YS		 911/*
912 * Using the fb_var_screeninfo in fb_info we set the aoi of this
913 * particular framebuffer. It is a light version of fsl_diu_set_par.
914 */
915static int fsl_diu_set_aoi(struct fb_info *info)
916{
917 struct fb_var_screeninfo *var = &info->var;
918 struct mfb_info *mfbi = info->par;
919 struct diu_ad *ad = mfbi->ad;
920
921 /* AOI should not be greater than display size */
922 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
923 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
924 return 0;
925}
926
9b53a9e2
YS		 927/*
928 * Using the fb_var_screeninfo in fb_info we set the resolution of this
929 * particular framebuffer. This function alters the fb_fix_screeninfo stored
930 * in fb_info. It does not alter var in fb_info since we are using that
931 * data. This means we depend on the data in var inside fb_info to be
932 * supported by the hardware. fsl_diu_check_var is always called before
933 * fsl_diu_set_par to ensure this.
934 */
935static int fsl_diu_set_par(struct fb_info *info)
936{
937 unsigned long len;
938 struct fb_var_screeninfo *var = &info->var;
939 struct mfb_info *mfbi = info->par;
940 struct fsl_diu_data *machine_data = mfbi->parent;
941 struct diu_ad *ad = mfbi->ad;
942 struct diu *hw;
943
944 hw = dr.diu_reg;
945
946 set_fix(info);
947 mfbi->cursor_reset = 1;
948
949 len = info->var.yres_virtual * info->fix.line_length;
950 /* Alloc & dealloc each time resolution/bpp change */
951 if (len != info->fix.smem_len) {
952 if (info->fix.smem_start)
953 unmap_video_memory(info);
9b53a9e2
YS		 954
955 /* Memory allocation for framebuffer */
956 if (map_video_memory(info)) {
154152ae 957 dev_err(info->dev, "unable to allocate fb memory 1\n");
9b53a9e2
YS		 958 return -ENOMEM;
959 }
960 }
961
7653aaab
TT		 962 ad->pix_fmt = diu_ops.get_pixel_format(machine_data->monitor_port,
963 var->bits_per_pixel);
9b53a9e2 964 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 965 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
966 var->xres_virtual) | mfbi->g_alpha;
967 /* AOI should not be greater than display size */
9b53a9e2 968 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 969 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 970 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
971
972 /* Disable chroma keying function */
973 ad->ckmax_r = 0;
974 ad->ckmax_g = 0;
975 ad->ckmax_b = 0;
976
977 ad->ckmin_r = 255;
978 ad->ckmin_g = 255;
979 ad->ckmin_b = 255;
980
2572df91 981 if (mfbi->index == PLANE0)
9b53a9e2
YS		 982 update_lcdc(info);
983 return 0;
984}
985
986static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
987{
4a85dc8b 988 return ((val << width) + 0x7FFF - val) >> 16;
9b53a9e2
YS		 989}
990
991/*
992 * Set a single color register. The values supplied have a 16 bit magnitude
993 * which needs to be scaled in this function for the hardware. Things to take
994 * into consideration are how many color registers, if any, are supported with
995 * the current color visual. With truecolor mode no color palettes are
25985edc 996 * supported. Here a pseudo palette is created which we store the value in
9b53a9e2
YS		 997 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
998 * color palette.
999 */
4a85dc8b
TT		 1000static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
1001 unsigned int green, unsigned int blue,
1002 unsigned int transp, struct fb_info *info)
9b53a9e2
YS		 1003{
1004 int ret = 1;
1005
1006 /*
1007 * If greyscale is true, then we convert the RGB value
1008 * to greyscale no matter what visual we are using.
1009 */
1010 if (info->var.grayscale)
1011 red = green = blue = (19595 * red + 38470 * green +
1012 7471 * blue) >> 16;
1013 switch (info->fix.visual) {
1014 case FB_VISUAL_TRUECOLOR:
1015 /*
1016 * 16-bit True Colour. We encode the RGB value
1017 * according to the RGB bitfield information.
1018 */
1019 if (regno < 16) {
1020 u32 *pal = info->pseudo_palette;
1021 u32 v;
1022
1023 red = CNVT_TOHW(red, info->var.red.length);
1024 green = CNVT_TOHW(green, info->var.green.length);
1025 blue = CNVT_TOHW(blue, info->var.blue.length);
1026 transp = CNVT_TOHW(transp, info->var.transp.length);
1027
1028 v = (red << info->var.red.offset) |
1029 (green << info->var.green.offset) |
1030 (blue << info->var.blue.offset) |
1031 (transp << info->var.transp.offset);
1032
1033 pal[regno] = v;
1034 ret = 0;
1035 }
1036 break;
9b53a9e2
YS		 1037 }
1038
1039 return ret;
1040}
1041
1042/*
1043 * Pan (or wrap, depending on the `vmode' field) the display using the
1044 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
1045 * don't fit, return -EINVAL.
1046 */
1047static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
1048 struct fb_info *info)
1049{
1050 if ((info->var.xoffset == var->xoffset) &&
1051 (info->var.yoffset == var->yoffset))
1052 return 0; /* No change, do nothing */
1053
1054 if (var->xoffset < 0 || var->yoffset < 0
1055 || var->xoffset + info->var.xres > info->var.xres_virtual
1056 || var->yoffset + info->var.yres > info->var.yres_virtual)
1057 return -EINVAL;
1058
1059 info->var.xoffset = var->xoffset;
1060 info->var.yoffset = var->yoffset;
1061
1062 if (var->vmode & FB_VMODE_YWRAP)
1063 info->var.vmode |= FB_VMODE_YWRAP;
1064 else
1065 info->var.vmode &= ~FB_VMODE_YWRAP;
1066
ae5591e3
YS		 1067 fsl_diu_set_aoi(info);
1068
9b53a9e2
YS		 1069 return 0;
1070}
1071
9b53a9e2
YS		 1072static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1073 unsigned long arg)
1074{
1075 struct mfb_info *mfbi = info->par;
1076 struct diu_ad *ad = mfbi->ad;
1077 struct mfb_chroma_key ck;
1078 unsigned char global_alpha;
1079 struct aoi_display_offset aoi_d;
1080 __u32 pix_fmt;
1081 void __user *buf = (void __user *)arg;
1082
1083 if (!arg)
1084 return -EINVAL;
1085 switch (cmd) {
36b0b1d4
TT		 1086 case MFB_SET_PIXFMT_OLD:
1087 dev_warn(info->dev,
1088 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
1089 MFB_SET_PIXFMT_OLD);
9b53a9e2
YS		 1090 case MFB_SET_PIXFMT:
1091 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1092 return -EFAULT;
1093 ad->pix_fmt = pix_fmt;
9b53a9e2 1094 break;
36b0b1d4
TT		 1095 case MFB_GET_PIXFMT_OLD:
1096 dev_warn(info->dev,
1097 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
1098 MFB_GET_PIXFMT_OLD);
9b53a9e2
YS		 1099 case MFB_GET_PIXFMT:
1100 pix_fmt = ad->pix_fmt;
1101 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1102 return -EFAULT;
9b53a9e2
YS		 1103 break;
1104 case MFB_SET_AOID:
1105 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1106 return -EFAULT;
1107 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1108 mfbi->y_aoi_d = aoi_d.y_aoi_d;
9b53a9e2 1109 fsl_diu_check_var(&info->var, info);
ae5591e3 1110 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1111 break;
1112 case MFB_GET_AOID:
1113 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1114 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1115 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1116 return -EFAULT;
9b53a9e2
YS		 1117 break;
1118 case MFB_GET_ALPHA:
1119 global_alpha = mfbi->g_alpha;
1120 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1121 return -EFAULT;
9b53a9e2
YS		 1122 break;
1123 case MFB_SET_ALPHA:
1124 /* set panel information */
1125 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1126 return -EFAULT;
1127 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1128 (global_alpha & 0xff);
1129 mfbi->g_alpha = global_alpha;
9b53a9e2
YS		 1130 break;
1131 case MFB_SET_CHROMA_KEY:
1132 /* set panel winformation */
1133 if (copy_from_user(&ck, buf, sizeof(ck)))
1134 return -EFAULT;
1135
1136 if (ck.enable &&
1137 (ck.red_max < ck.red_min ||
1138 ck.green_max < ck.green_min ||
1139 ck.blue_max < ck.blue_min))
1140 return -EINVAL;
1141
1142 if (!ck.enable) {
1143 ad->ckmax_r = 0;
1144 ad->ckmax_g = 0;
1145 ad->ckmax_b = 0;
1146 ad->ckmin_r = 255;
1147 ad->ckmin_g = 255;
1148 ad->ckmin_b = 255;
1149 } else {
1150 ad->ckmax_r = ck.red_max;
1151 ad->ckmax_g = ck.green_max;
1152 ad->ckmax_b = ck.blue_max;
1153 ad->ckmin_r = ck.red_min;
1154 ad->ckmin_g = ck.green_min;
1155 ad->ckmin_b = ck.blue_min;
1156 }
9b53a9e2 1157 break;
9b53a9e2 1158 default:
154152ae 1159 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
9b53a9e2
YS		 1160 return -ENOIOCTLCMD;
1161 }
1162
1163 return 0;
1164}
1165
1166/* turn on fb if count == 1
1167 */
1168static int fsl_diu_open(struct fb_info *info, int user)
1169{
1170 struct mfb_info *mfbi = info->par;
1171 int res = 0;
1172
4b5006ec 1173 /* free boot splash memory on first /dev/fb0 open */
2572df91 1174 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
4b5006ec
AG		 1175 diu_ops.release_bootmem();
1176
9b53a9e2
YS		 1177 spin_lock(&diu_lock);
1178 mfbi->count++;
1179 if (mfbi->count == 1) {
9b53a9e2
YS		 1180 fsl_diu_check_var(&info->var, info);
1181 res = fsl_diu_set_par(info);
1182 if (res < 0)
1183 mfbi->count--;
7e47c211
TT		 1184 else
1185 fsl_diu_enable_panel(info);
9b53a9e2
YS		 1186 }
1187
1188 spin_unlock(&diu_lock);
1189 return res;
1190}
1191
1192/* turn off fb if count == 0
1193 */
1194static int fsl_diu_release(struct fb_info *info, int user)
1195{
1196 struct mfb_info *mfbi = info->par;
1197 int res = 0;
1198
1199 spin_lock(&diu_lock);
1200 mfbi->count--;
2572df91
TT		 1201 if (mfbi->count == 0)
1202 fsl_diu_disable_panel(info);
1203
9b53a9e2
YS		 1204 spin_unlock(&diu_lock);
1205 return res;
1206}
1207
1208static struct fb_ops fsl_diu_ops = {
1209 .owner = THIS_MODULE,
1210 .fb_check_var = fsl_diu_check_var,
1211 .fb_set_par = fsl_diu_set_par,
1212 .fb_setcolreg = fsl_diu_setcolreg,
9b53a9e2
YS		 1213 .fb_pan_display = fsl_diu_pan_display,
1214 .fb_fillrect = cfb_fillrect,
1215 .fb_copyarea = cfb_copyarea,
1216 .fb_imageblit = cfb_imageblit,
1217 .fb_ioctl = fsl_diu_ioctl,
1218 .fb_open = fsl_diu_open,
1219 .fb_release = fsl_diu_release,
1220};
1221
1222static int init_fbinfo(struct fb_info *info)
1223{
1224 struct mfb_info *mfbi = info->par;
1225
1226 info->device = NULL;
1227 info->var.activate = FB_ACTIVATE_NOW;
1228 info->fbops = &fsl_diu_ops;
1229 info->flags = FBINFO_FLAG_DEFAULT;
1230 info->pseudo_palette = &mfbi->pseudo_palette;
1231
1232 /* Allocate colormap */
1233 fb_alloc_cmap(&info->cmap, 16, 0);
1234 return 0;
1235}
1236
05946bce 1237static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1238{
1239 int rc;
1240 struct mfb_info *mfbi = info->par;
1241 const char *aoi_mode, *init_aoi_mode = "320x240";
8b856f04
AG		 1242 struct fb_videomode *db = fsl_diu_mode_db;
1243 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1244 int has_default_mode = 1;
9b53a9e2
YS		 1245
1246 if (init_fbinfo(info))
1247 return -EINVAL;
1248
2572df91 1249 if (mfbi->index == PLANE0) {
8b856f04
AG		 1250 if (mfbi->edid_data) {
1251 /* Now build modedb from EDID */
1252 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1253 fb_videomode_to_modelist(info->monspecs.modedb,
1254 info->monspecs.modedb_len,
1255 &info->modelist);
1256 db = info->monspecs.modedb;
1257 dbsize = info->monspecs.modedb_len;
1258 }
9b53a9e2 1259 aoi_mode = fb_mode;
8b856f04 1260 } else {
9b53a9e2 1261 aoi_mode = init_aoi_mode;
8b856f04 1262 }
63cf8df4
TT		 1263 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
1264 default_bpp);
154152ae 1265 if (!rc) {
8b856f04
AG		 1266 /*
1267 * For plane 0 we continue and look into
1268 * driver's internal modedb.
1269 */
2572df91 1270 if ((mfbi->index == PLANE0) && mfbi->edid_data)
8b856f04
AG		 1271 has_default_mode = 0;
1272 else
1273 return -EINVAL;
9b53a9e2
YS		 1274 }
1275
8b856f04
AG		 1276 if (!has_default_mode) {
1277 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
63cf8df4
TT		 1278 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
1279 if (rc)
8b856f04
AG		 1280 has_default_mode = 1;
1281 }
1282
1283 /* Still not found, use preferred mode from database if any */
1284 if (!has_default_mode && info->monspecs.modedb) {
1285 struct fb_monspecs *specs = &info->monspecs;
1286 struct fb_videomode *modedb = &specs->modedb[0];
1287
1288 /*
1289 * Get preferred timing. If not found,
1290 * first mode in database will be used.
1291 */
1292 if (specs->misc & FB_MISC_1ST_DETAIL) {
1293 int i;
1294
1295 for (i = 0; i < specs->modedb_len; i++) {
1296 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1297 modedb = &specs->modedb[i];
1298 break;
1299 }
1300 }
1301 }
1302
1303 info->var.bits_per_pixel = default_bpp;
1304 fb_videomode_to_var(&info->var, modedb);
1305 }
1306
9b53a9e2 1307 if (fsl_diu_check_var(&info->var, info)) {
154152ae 1308 dev_err(info->dev, "fsl_diu_check_var failed\n");
589c7971 1309 unmap_video_memory(info);
9b53a9e2
YS		 1310 fb_dealloc_cmap(&info->cmap);
1311 return -EINVAL;
1312 }
1313
9b53a9e2 1314 if (register_framebuffer(info) < 0) {
154152ae 1315 dev_err(info->dev, "register_framebuffer failed\n");
9b53a9e2
YS		 1316 unmap_video_memory(info);
1317 fb_dealloc_cmap(&info->cmap);
1318 return -EINVAL;
1319 }
1320
1321 mfbi->registered = 1;
154152ae 1322 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
9b53a9e2
YS		 1323
1324 return 0;
1325}
1326
05946bce 1327static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1328{
1329 struct mfb_info *mfbi = info->par;
1330
1331 if (!mfbi->registered)
1332 return;
1333
2572df91 1334 if (mfbi->index == PLANE0)
8b856f04
AG		 1335 kfree(mfbi->edid_data);
1336
9b53a9e2
YS		 1337 unregister_framebuffer(info);
1338 unmap_video_memory(info);
1339 if (&info->cmap)
1340 fb_dealloc_cmap(&info->cmap);
1341
1342 mfbi->registered = 0;
1343}
1344
1345static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1346{
1347 struct diu *hw = dr.diu_reg;
1348 unsigned int status = in_be32(&hw->int_status);
1349
1350 if (status) {
1351 /* This is the workaround for underrun */
1352 if (status & INT_UNDRUN) {
1353 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 1354 udelay(1);
1355 out_be32(&hw->diu_mode, 1);
1356 }
1357#if defined(CONFIG_NOT_COHERENT_CACHE)
1358 else if (status & INT_VSYNC) {
1359 unsigned int i;
4a85dc8b 1360
9b53a9e2
YS		 1361 for (i = 0; i < coherence_data_size;
1362 i += d_cache_line_size)
1363 __asm__ __volatile__ (
1364 "dcbz 0, %[input]"
1365 ::[input]"r"(&coherence_data[i]));
1366 }
1367#endif
1368 return IRQ_HANDLED;
1369 }
1370 return IRQ_NONE;
1371}
1372
1373static int request_irq_local(int irq)
1374{
bada04fc 1375 u32 ints;
9b53a9e2
YS		 1376 struct diu *hw;
1377 int ret;
1378
1379 hw = dr.diu_reg;
1380
1381 /* Read to clear the status */
bada04fc 1382 in_be32(&hw->int_status);
9b53a9e2 1383
f8c6bf6a 1384 ret = request_irq(irq, fsl_diu_isr, 0, "fsl-diu-fb", NULL);
154152ae 1385 if (!ret) {
9b53a9e2
YS		 1386 ints = INT_PARERR | INT_LS_BF_VS;
1387#if !defined(CONFIG_NOT_COHERENT_CACHE)
1388 ints |= INT_VSYNC;
1389#endif
4a85dc8b 1390
9b53a9e2 1391 /* Read to clear the status */
bada04fc 1392 in_be32(&hw->int_status);
9b53a9e2
YS		 1393 out_be32(&hw->int_mask, ints);
1394 }
4a85dc8b 1395
9b53a9e2
YS		 1396 return ret;
1397}
1398
1399static void free_irq_local(int irq)
1400{
1401 struct diu *hw = dr.diu_reg;
1402
1403 /* Disable all LCDC interrupt */
1404 out_be32(&hw->int_mask, 0x1f);
1405
05946bce 1406 free_irq(irq, NULL);
9b53a9e2
YS		 1407}
1408
1409#ifdef CONFIG_PM
1410/*
1411 * Power management hooks. Note that we won't be called from IRQ context,
1412 * unlike the blank functions above, so we may sleep.
1413 */
2dc11581 1414static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
9b53a9e2
YS		 1415{
1416 struct fsl_diu_data *machine_data;
1417
48948a3e 1418 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1419 disable_lcdc(machine_data->fsl_diu_info[0]);
1420
1421 return 0;
1422}
1423
2dc11581 1424static int fsl_diu_resume(struct platform_device *ofdev)
9b53a9e2
YS		 1425{
1426 struct fsl_diu_data *machine_data;
1427
48948a3e 1428 machine_data = dev_get_drvdata(&ofdev->dev);
9b53a9e2
YS		 1429 enable_lcdc(machine_data->fsl_diu_info[0]);
1430
1431 return 0;
1432}
1433
1434#else
1435#define fsl_diu_suspend NULL
1436#define fsl_diu_resume NULL
1437#endif /* CONFIG_PM */
1438
1439/* Align to 64-bit(8-byte), 32-byte, etc. */
f3791889
AV		 1440static int allocate_buf(struct device *dev, struct diu_addr *buf, u32 size,
1441 u32 bytes_align)
9b53a9e2 1442{
bada04fc
TT		 1443 u32 offset;
1444 dma_addr_t mask;
9b53a9e2 1445
bada04fc
TT		 1446 buf->vaddr =
1447 dma_alloc_coherent(dev, size + bytes_align, &buf->paddr,
1448 GFP_DMA | __GFP_ZERO);
9b53a9e2
YS		 1449 if (!buf->vaddr)
1450 return -ENOMEM;
1451
9b53a9e2 1452 mask = bytes_align - 1;
bada04fc 1453 offset = buf->paddr & mask;
9b53a9e2
YS		 1454 if (offset) {
1455 buf->offset = bytes_align - offset;
bada04fc 1456 buf->paddr = buf->paddr + offset;
9b53a9e2
YS		 1457 } else
1458 buf->offset = 0;
4a85dc8b 1459
9b53a9e2
YS		 1460 return 0;
1461}
1462
f3791889
AV		 1463static void free_buf(struct device *dev, struct diu_addr *buf, u32 size,
1464 u32 bytes_align)
9b53a9e2 1465{
4a85dc8b
TT		 1466 dma_free_coherent(dev, size + bytes_align, buf->vaddr,
1467 buf->paddr - buf->offset);
9b53a9e2
YS		 1468}
1469
1470static ssize_t store_monitor(struct device *device,
1471 struct device_attribute *attr, const char *buf, size_t count)
1472{
7653aaab 1473 enum fsl_diu_monitor_port old_monitor_port;
9b53a9e2
YS		 1474 struct fsl_diu_data *machine_data =
1475 container_of(attr, struct fsl_diu_data, dev_attr);
1476
9b53a9e2 1477 old_monitor_port = machine_data->monitor_port;
7653aaab 1478 machine_data->monitor_port = fsl_diu_name_to_port(buf);
9b53a9e2
YS		 1479
1480 if (old_monitor_port != machine_data->monitor_port) {
1481 /* All AOIs need adjust pixel format
1482 * fsl_diu_set_par only change the pixsel format here
1483 * unlikely to fail. */
1484 fsl_diu_set_par(machine_data->fsl_diu_info[0]);
1485 fsl_diu_set_par(machine_data->fsl_diu_info[1]);
1486 fsl_diu_set_par(machine_data->fsl_diu_info[2]);
1487 fsl_diu_set_par(machine_data->fsl_diu_info[3]);
1488 fsl_diu_set_par(machine_data->fsl_diu_info[4]);
1489 }
1490 return count;
1491}
1492
1493static ssize_t show_monitor(struct device *device,
1494 struct device_attribute *attr, char *buf)
1495{
1496 struct fsl_diu_data *machine_data =
1497 container_of(attr, struct fsl_diu_data, dev_attr);
7653aaab
TT		 1498
1499 switch (machine_data->monitor_port) {
1500 case FSL_DIU_PORT_DVI:
1501 return sprintf(buf, "DVI\n");
1502 case FSL_DIU_PORT_LVDS:
1503 return sprintf(buf, "Single-link LVDS\n");
1504 case FSL_DIU_PORT_DLVDS:
1505 return sprintf(buf, "Dual-link LVDS\n");
1506 }
1507
1508 return 0;
9b53a9e2
YS		 1509}
1510
9e52ba61 1511static int __devinit fsl_diu_probe(struct platform_device *pdev)
9b53a9e2 1512{
9e52ba61 1513 struct device_node *np = pdev->dev.of_node;
9b53a9e2 1514 struct mfb_info *mfbi;
89f08e3e 1515 phys_addr_t dummy_ad_addr = 0;
9b53a9e2 1516 int ret, i, error = 0;
9b53a9e2 1517 struct fsl_diu_data *machine_data;
4b5006ec 1518 int diu_mode;
9b53a9e2
YS		 1519
1520 machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
1521 if (!machine_data)
1522 return -ENOMEM;
1523
1524 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1525 machine_data->fsl_diu_info[i] =
9e52ba61 1526 framebuffer_alloc(sizeof(struct mfb_info), &pdev->dev);
9b53a9e2 1527 if (!machine_data->fsl_diu_info[i]) {
9e52ba61 1528 dev_err(&pdev->dev, "cannot allocate memory\n");
9b53a9e2
YS		 1529 ret = -ENOMEM;
1530 goto error2;
1531 }
1532 mfbi = machine_data->fsl_diu_info[i]->par;
1533 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
1534 mfbi->parent = machine_data;
8b856f04 1535
2572df91 1536 if (mfbi->index == PLANE0) {
8b856f04
AG		 1537 const u8 *prop;
1538 int len;
1539
1540 /* Get EDID */
1541 prop = of_get_property(np, "edid", &len);
1542 if (prop && len == EDID_LENGTH)
1543 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1544 GFP_KERNEL);
1545 }
9b53a9e2
YS		 1546 }
1547
9e52ba61 1548 dr.diu_reg = of_iomap(np, 0);
9b53a9e2 1549 if (!dr.diu_reg) {
9e52ba61 1550 dev_err(&pdev->dev, "cannot map DIU registers\n");
9b53a9e2
YS		 1551 ret = -EFAULT;
1552 goto error2;
1553 }
1554
4b5006ec 1555 diu_mode = in_be32(&dr.diu_reg->diu_mode);
c4e5a023 1556 if (diu_mode == MFB_MODE0)
4b5006ec 1557 out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1558
1559 /* Get the IRQ of the DIU */
1560 machine_data->irq = irq_of_parse_and_map(np, 0);
1561
1562 if (!machine_data->irq) {
9e52ba61 1563 dev_err(&pdev->dev, "could not get DIU IRQ\n");
9b53a9e2
YS		 1564 ret = -EINVAL;
1565 goto error;
1566 }
1567 machine_data->monitor_port = monitor_port;
1568
1569 /* Area descriptor memory pool aligns to 64-bit boundary */
9e52ba61 1570 if (allocate_buf(&pdev->dev, &pool.ad,
f3791889 1571 sizeof(struct diu_ad) * FSL_AOI_NUM, 8))
9b53a9e2
YS		 1572 return -ENOMEM;
1573
1574 /* Get memory for Gamma Table - 32-byte aligned memory */
9e52ba61 1575 if (allocate_buf(&pdev->dev, &pool.gamma, 768, 32)) {
9b53a9e2
YS		 1576 ret = -ENOMEM;
1577 goto error;
1578 }
1579
1580 /* For performance, cursor bitmap buffer aligns to 32-byte boundary */
9e52ba61 1581 if (allocate_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1582 32)) {
9b53a9e2
YS		 1583 ret = -ENOMEM;
1584 goto error;
1585 }
1586
1587 i = ARRAY_SIZE(machine_data->fsl_diu_info);
1588 machine_data->dummy_ad = (struct diu_ad *)
1589 ((u32)pool.ad.vaddr + pool.ad.offset) + i;
1590 machine_data->dummy_ad->paddr = pool.ad.paddr +
1591 i * sizeof(struct diu_ad);
1592 machine_data->dummy_aoi_virt = fsl_diu_alloc(64, &dummy_ad_addr);
1593 if (!machine_data->dummy_aoi_virt) {
1594 ret = -ENOMEM;
1595 goto error;
1596 }
1597 machine_data->dummy_ad->addr = cpu_to_le32(dummy_ad_addr);
1598 machine_data->dummy_ad->pix_fmt = 0x88882317;
1599 machine_data->dummy_ad->src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1600 machine_data->dummy_ad->aoi_size = cpu_to_le32((4 << 16) | 2);
1601 machine_data->dummy_ad->offset_xyi = 0;
1602 machine_data->dummy_ad->offset_xyd = 0;
1603 machine_data->dummy_ad->next_ad = 0;
1604
4b5006ec
AG		 1605 /*
1606 * Let DIU display splash screen if it was pre-initialized
1607 * by the bootloader, set dummy area descriptor otherwise.
1608 */
c4e5a023 1609 if (diu_mode == MFB_MODE0)
4b5006ec
AG		 1610 out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
1611
9b53a9e2
YS		 1612 out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
1613 out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
1614
1615 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
1616 machine_data->fsl_diu_info[i]->fix.smem_start = 0;
1617 mfbi = machine_data->fsl_diu_info[i]->par;
1618 mfbi->ad = (struct diu_ad *)((u32)pool.ad.vaddr
1619 + pool.ad.offset) + i;
1620 mfbi->ad->paddr = pool.ad.paddr + i * sizeof(struct diu_ad);
1621 ret = install_fb(machine_data->fsl_diu_info[i]);
1622 if (ret) {
9e52ba61 1623 dev_err(&pdev->dev, "could not register fb %d\n", i);
9b53a9e2
YS		 1624 goto error;
1625 }
1626 }
1627
1628 if (request_irq_local(machine_data->irq)) {
9e52ba61 1629 dev_err(&pdev->dev, "could not claim irq\n");
9b53a9e2
YS		 1630 goto error;
1631 }
1632
12765517 1633 sysfs_attr_init(&machine_data->dev_attr.attr);
9b53a9e2
YS		 1634 machine_data->dev_attr.attr.name = "monitor";
1635 machine_data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1636 machine_data->dev_attr.show = show_monitor;
1637 machine_data->dev_attr.store = store_monitor;
1638 error = device_create_file(machine_data->fsl_diu_info[0]->dev,
1639 &machine_data->dev_attr);
1640 if (error) {
9e52ba61 1641 dev_err(&pdev->dev, "could not create sysfs file %s\n",
9b53a9e2
YS		 1642 machine_data->dev_attr.attr.name);
1643 }
1644
9e52ba61 1645 dev_set_drvdata(&pdev->dev, machine_data);
9b53a9e2
YS		 1646 return 0;
1647
1648error:
3f78bbd1
TT		 1649 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1650 uninstall_fb(machine_data->fsl_diu_info[i]);
1651
9b53a9e2 1652 if (pool.ad.vaddr)
9e52ba61 1653 free_buf(&pdev->dev, &pool.ad,
f3791889 1654 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1655 if (pool.gamma.vaddr)
9e52ba61 1656 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1657 if (pool.cursor.vaddr)
9e52ba61 1658 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2,
f3791889 1659 32);
9b53a9e2
YS		 1660 if (machine_data->dummy_aoi_virt)
1661 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1662 iounmap(dr.diu_reg);
1663
1664error2:
1665 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1666 if (machine_data->fsl_diu_info[i])
1667 framebuffer_release(machine_data->fsl_diu_info[i]);
1668 kfree(machine_data);
1669
1670 return ret;
1671}
1672
9e52ba61 1673static int fsl_diu_remove(struct platform_device *pdev)
9b53a9e2
YS		 1674{
1675 struct fsl_diu_data *machine_data;
1676 int i;
1677
9e52ba61 1678 machine_data = dev_get_drvdata(&pdev->dev);
9b53a9e2
YS		 1679 disable_lcdc(machine_data->fsl_diu_info[0]);
1680 free_irq_local(machine_data->irq);
3f78bbd1
TT		 1681 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1682 uninstall_fb(machine_data->fsl_diu_info[i]);
9b53a9e2 1683 if (pool.ad.vaddr)
9e52ba61 1684 free_buf(&pdev->dev, &pool.ad,
f3791889 1685 sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
9b53a9e2 1686 if (pool.gamma.vaddr)
9e52ba61 1687 free_buf(&pdev->dev, &pool.gamma, 768, 32);
9b53a9e2 1688 if (pool.cursor.vaddr)
9e52ba61 1689 free_buf(&pdev->dev, &pool.cursor, MAX_CURS * MAX_CURS * 2, 32);
9b53a9e2
YS		 1690 if (machine_data->dummy_aoi_virt)
1691 fsl_diu_free(machine_data->dummy_aoi_virt, 64);
1692 iounmap(dr.diu_reg);
1693 for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
1694 if (machine_data->fsl_diu_info[i])
1695 framebuffer_release(machine_data->fsl_diu_info[i]);
1696 kfree(machine_data);
1697
1698 return 0;
1699}
1700
1701#ifndef MODULE
1702static int __init fsl_diu_setup(char *options)
1703{
1704 char *opt;
1705 unsigned long val;
1706
1707 if (!options || !*options)
1708 return 0;
1709
1710 while ((opt = strsep(&options, ",")) != NULL) {
1711 if (!*opt)
1712 continue;
1713 if (!strncmp(opt, "monitor=", 8)) {
7653aaab 1714 monitor_port = fsl_diu_name_to_port(opt + 8);
9b53a9e2
YS		 1715 } else if (!strncmp(opt, "bpp=", 4)) {
1716 if (!strict_strtoul(opt + 4, 10, &val))
1717 default_bpp = val;
1718 } else
1719 fb_mode = opt;
1720 }
1721
1722 return 0;
1723}
1724#endif
1725
1726static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1727#ifdef CONFIG_PPC_MPC512x
1728 {
1729 .compatible = "fsl,mpc5121-diu",
1730 },
1731#endif
9b53a9e2
YS		 1732 {
1733 .compatible = "fsl,diu",
1734 },
1735 {}
1736};
1737MODULE_DEVICE_TABLE(of, fsl_diu_match);
1738
28541d0f 1739static struct platform_driver fsl_diu_driver = {
4018294b 1740 .driver = {
f8c6bf6a 1741 .name = "fsl-diu-fb",
4018294b
GL		 1742 .owner = THIS_MODULE,
1743 .of_match_table = fsl_diu_match,
1744 },
9b53a9e2
YS		 1745 .probe = fsl_diu_probe,
1746 .remove = fsl_diu_remove,
1747 .suspend = fsl_diu_suspend,
1748 .resume = fsl_diu_resume,
1749};
1750
1751static int __init fsl_diu_init(void)
1752{
1753#ifdef CONFIG_NOT_COHERENT_CACHE
1754 struct device_node *np;
1755 const u32 *prop;
1756#endif
1757 int ret;
1758#ifndef MODULE
1759 char *option;
1760
1761 /*
1762 * For kernel boot options (in 'video=xxxfb:<options>' format)
1763 */
1764 if (fb_get_options("fslfb", &option))
1765 return -ENODEV;
1766 fsl_diu_setup(option);
7653aaab
TT		 1767#else
1768 monitor_port = fsl_diu_name_to_port(monitor_string);
9b53a9e2 1769#endif
154152ae 1770 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
9b53a9e2
YS		 1771
1772#ifdef CONFIG_NOT_COHERENT_CACHE
1773 np = of_find_node_by_type(NULL, "cpu");
1774 if (!np) {
154152ae 1775 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
9b53a9e2
YS		 1776 return -ENODEV;
1777 }
1778
1779 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f 1780 if (prop == NULL) {
154152ae
TT		 1781 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1782 "in 'cpu' node\n");
5394ba0f 1783 of_node_put(np);
9b53a9e2 1784 return -ENODEV;
5394ba0f 1785 }
9b53a9e2 1786
4a85dc8b
TT		 1787 /*
1788 * Freescale PLRU requires 13/8 times the cache size to do a proper
1789 * displacement flush
9b53a9e2 1790 */
9e52ba61 1791 coherence_data_size = be32_to_cpup(prop) * 13;
9b53a9e2
YS		 1792 coherence_data_size /= 8;
1793
1794 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f 1795 if (prop == NULL) {
154152ae
TT		 1796 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1797 "in 'cpu' node\n");
5394ba0f 1798 of_node_put(np);
9b53a9e2 1799 return -ENODEV;
5394ba0f 1800 }
9e52ba61 1801 d_cache_line_size = be32_to_cpup(prop);
9b53a9e2
YS		 1802
1803 of_node_put(np);
1804 coherence_data = vmalloc(coherence_data_size);
1805 if (!coherence_data)
1806 return -ENOMEM;
1807#endif
4a85dc8b 1808
28541d0f 1809 ret = platform_driver_register(&fsl_diu_driver);
9b53a9e2 1810 if (ret) {
154152ae 1811 pr_err("fsl-diu-fb: failed to register platform driver\n");
9b53a9e2
YS		 1812#if defined(CONFIG_NOT_COHERENT_CACHE)
1813 vfree(coherence_data);
1814#endif
1815 iounmap(dr.diu_reg);
1816 }
1817 return ret;
1818}
1819
1820static void __exit fsl_diu_exit(void)
1821{
28541d0f 1822 platform_driver_unregister(&fsl_diu_driver);
9b53a9e2
YS		 1823#if defined(CONFIG_NOT_COHERENT_CACHE)
1824 vfree(coherence_data);
1825#endif
1826}
1827
1828module_init(fsl_diu_init);
1829module_exit(fsl_diu_exit);
1830
1831MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1832MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1833MODULE_LICENSE("GPL");
1834
1835module_param_named(mode, fb_mode, charp, 0);
1836MODULE_PARM_DESC(mode,
1837 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1838module_param_named(bpp, default_bpp, ulong, 0);
154152ae 1839MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
7653aaab
TT		 1840module_param_named(monitor, monitor_string, charp, 0);
1841MODULE_PARM_DESC(monitor, "Specify the monitor port "
1842 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
9b53a9e2 1843
Linux 6.x block layer and io_uring tree(s)