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drivers/video: fsl-diu-fb: remove unused 'cursor_reset' variable
[linux-2.6-block.git] / drivers / video / fsl-diu-fb.c
CommitLineData
9b53a9e2
YS		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Freescale DIU Frame Buffer device driver
5 *
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
10 *
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 *
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/string.h>
24#include <linux/slab.h>
25#include <linux/fb.h>
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/interrupt.h>
30#include <linux/clk.h>
31#include <linux/uaccess.h>
32#include <linux/vmalloc.h>
b715f9f0 33#include <linux/spinlock.h>
9b53a9e2 34
9b53a9e2 35#include <sysdev/fsl_soc.h>
0814a979 36#include <linux/fsl-diu-fb.h>
8b856f04 37#include "edid.h"
9b53a9e2 38
ddd3d905 39#define NUM_AOIS 5 /* 1 for plane 0, 2 for planes 1 & 2 each */
b715f9f0
TT		 40
41/* HW cursor parameters */
42#define MAX_CURS 32
43
44/* INT_STATUS/INT_MASK field descriptions */
45#define INT_VSYNC 0x01 /* Vsync interrupt */
46#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
47#define INT_UNDRUN 0x04 /* Under run exception interrupt */
48#define INT_PARERR 0x08 /* Display parameters error interrupt */
49#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
50
9b53a9e2 51/*
63cf8df4
TT		 52 * List of supported video modes
53 *
760af8f8
TT		 54 * The first entry is the default video mode. The remain entries are in
55 * order if increasing resolution and frequency. The 320x240-60 mode is
56 * the initial AOI for the second and third planes.
9b53a9e2 57 */
9b53a9e2
YS		 58static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
59 {
9b53a9e2
YS		 60 .refresh = 60,
61 .xres = 1024,
62 .yres = 768,
63 .pixclock = 15385,
64 .left_margin = 160,
65 .right_margin = 24,
66 .upper_margin = 29,
67 .lower_margin = 3,
68 .hsync_len = 136,
69 .vsync_len = 6,
70 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
71 .vmode = FB_VMODE_NONINTERLACED
72 },
73 {
760af8f8
TT		 74 .refresh = 60,
75 .xres = 320,
76 .yres = 240,
77 .pixclock = 79440,
78 .left_margin = 16,
79 .right_margin = 16,
80 .upper_margin = 16,
81 .lower_margin = 5,
82 .hsync_len = 48,
83 .vsync_len = 1,
84 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
85 .vmode = FB_VMODE_NONINTERLACED
86 },
87 {
88 .refresh = 60,
89 .xres = 640,
90 .yres = 480,
91 .pixclock = 39722,
92 .left_margin = 48,
93 .right_margin = 16,
94 .upper_margin = 33,
95 .lower_margin = 10,
96 .hsync_len = 96,
97 .vsync_len = 2,
98 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
99 .vmode = FB_VMODE_NONINTERLACED
100 },
101 {
102 .refresh = 72,
103 .xres = 640,
104 .yres = 480,
105 .pixclock = 32052,
106 .left_margin = 128,
107 .right_margin = 24,
108 .upper_margin = 28,
109 .lower_margin = 9,
110 .hsync_len = 40,
111 .vsync_len = 3,
112 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
113 .vmode = FB_VMODE_NONINTERLACED
114 },
115 {
116 .refresh = 75,
117 .xres = 640,
118 .yres = 480,
119 .pixclock = 31747,
120 .left_margin = 120,
121 .right_margin = 16,
122 .upper_margin = 16,
123 .lower_margin = 1,
124 .hsync_len = 64,
125 .vsync_len = 3,
126 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
127 .vmode = FB_VMODE_NONINTERLACED
128 },
129 {
130 .refresh = 90,
131 .xres = 640,
132 .yres = 480,
133 .pixclock = 25057,
134 .left_margin = 120,
135 .right_margin = 32,
136 .upper_margin = 14,
137 .lower_margin = 25,
138 .hsync_len = 40,
139 .vsync_len = 14,
140 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
141 .vmode = FB_VMODE_NONINTERLACED
142 },
143 {
144 .refresh = 100,
145 .xres = 640,
146 .yres = 480,
147 .pixclock = 22272,
148 .left_margin = 48,
149 .right_margin = 32,
150 .upper_margin = 17,
151 .lower_margin = 22,
152 .hsync_len = 128,
153 .vsync_len = 12,
154 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
155 .vmode = FB_VMODE_NONINTERLACED
156 },
157 {
158 .refresh = 60,
159 .xres = 800,
160 .yres = 480,
161 .pixclock = 33805,
162 .left_margin = 96,
163 .right_margin = 24,
164 .upper_margin = 10,
165 .lower_margin = 3,
166 .hsync_len = 72,
167 .vsync_len = 7,
168 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
169 .vmode = FB_VMODE_NONINTERLACED
170 },
171 {
172 .refresh = 60,
173 .xres = 800,
174 .yres = 600,
175 .pixclock = 25000,
176 .left_margin = 88,
177 .right_margin = 40,
178 .upper_margin = 23,
179 .lower_margin = 1,
180 .hsync_len = 128,
181 .vsync_len = 4,
182 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
183 .vmode = FB_VMODE_NONINTERLACED
184 },
185 {
186 .refresh = 60,
187 .xres = 854,
188 .yres = 480,
189 .pixclock = 31518,
190 .left_margin = 104,
191 .right_margin = 16,
192 .upper_margin = 13,
193 .lower_margin = 1,
194 .hsync_len = 88,
195 .vsync_len = 3,
196 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
197 .vmode = FB_VMODE_NONINTERLACED
198 },
199 {
9b53a9e2
YS		 200 .refresh = 70,
201 .xres = 1024,
202 .yres = 768,
203 .pixclock = 16886,
204 .left_margin = 3,
205 .right_margin = 3,
206 .upper_margin = 2,
207 .lower_margin = 2,
208 .hsync_len = 40,
209 .vsync_len = 18,
210 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
211 .vmode = FB_VMODE_NONINTERLACED
212 },
213 {
9b53a9e2
YS		 214 .refresh = 75,
215 .xres = 1024,
216 .yres = 768,
217 .pixclock = 15009,
218 .left_margin = 3,
219 .right_margin = 3,
220 .upper_margin = 2,
221 .lower_margin = 2,
222 .hsync_len = 80,
223 .vsync_len = 32,
224 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
225 .vmode = FB_VMODE_NONINTERLACED
226 },
227 {
760af8f8
TT		 228 .refresh = 60,
229 .xres = 1280,
230 .yres = 480,
231 .pixclock = 18939,
232 .left_margin = 353,
233 .right_margin = 47,
234 .upper_margin = 39,
235 .lower_margin = 4,
236 .hsync_len = 8,
237 .vsync_len = 2,
238 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
239 .vmode = FB_VMODE_NONINTERLACED
240 },
241 {
242 .refresh = 60,
243 .xres = 1280,
244 .yres = 720,
245 .pixclock = 13426,
246 .left_margin = 192,
247 .right_margin = 64,
248 .upper_margin = 22,
249 .lower_margin = 1,
250 .hsync_len = 136,
251 .vsync_len = 3,
252 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
253 .vmode = FB_VMODE_NONINTERLACED
254 },
255 {
9b53a9e2
YS		 256 .refresh = 60,
257 .xres = 1280,
258 .yres = 1024,
259 .pixclock = 9375,
260 .left_margin = 38,
261 .right_margin = 128,
262 .upper_margin = 2,
263 .lower_margin = 7,
264 .hsync_len = 216,
265 .vsync_len = 37,
266 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
267 .vmode = FB_VMODE_NONINTERLACED
268 },
269 {
9b53a9e2
YS		 270 .refresh = 70,
271 .xres = 1280,
272 .yres = 1024,
273 .pixclock = 9380,
274 .left_margin = 6,
275 .right_margin = 6,
276 .upper_margin = 4,
277 .lower_margin = 4,
278 .hsync_len = 60,
279 .vsync_len = 94,
280 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
281 .vmode = FB_VMODE_NONINTERLACED
282 },
283 {
9b53a9e2
YS		 284 .refresh = 75,
285 .xres = 1280,
286 .yres = 1024,
287 .pixclock = 9380,
288 .left_margin = 6,
289 .right_margin = 6,
290 .upper_margin = 4,
291 .lower_margin = 4,
292 .hsync_len = 60,
293 .vsync_len = 15,
294 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
295 .vmode = FB_VMODE_NONINTERLACED
296 },
297 {
9b53a9e2 298 .refresh = 60,
760af8f8
TT		 299 .xres = 1920,
300 .yres = 1080,
301 .pixclock = 5787,
302 .left_margin = 328,
303 .right_margin = 120,
304 .upper_margin = 34,
305 .lower_margin = 1,
306 .hsync_len = 208,
307 .vsync_len = 3,
9b53a9e2
YS		 308 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
309 .vmode = FB_VMODE_NONINTERLACED
310 },
311};
312
760af8f8 313static char *fb_mode;
9b53a9e2 314static unsigned long default_bpp = 32;
7653aaab
TT		 315static enum fsl_diu_monitor_port monitor_port;
316static char *monitor_string;
9b53a9e2
YS		 317
318#if defined(CONFIG_NOT_COHERENT_CACHE)
319static u8 *coherence_data;
320static size_t coherence_data_size;
321static unsigned int d_cache_line_size;
322#endif
323
324static DEFINE_SPINLOCK(diu_lock);
325
2572df91
TT		 326enum mfb_index {
327 PLANE0 = 0, /* Plane 0, only one AOI that fills the screen */
328 PLANE1_AOI0, /* Plane 1, first AOI */
329 PLANE1_AOI1, /* Plane 1, second AOI */
330 PLANE2_AOI0, /* Plane 2, first AOI */
331 PLANE2_AOI1, /* Plane 2, second AOI */
332};
333
9b53a9e2 334struct mfb_info {
2572df91 335 enum mfb_index index;
9b53a9e2
YS		 336 char *id;
337 int registered;
9b53a9e2
YS		 338 unsigned long pseudo_palette[16];
339 struct diu_ad *ad;
9b53a9e2
YS		 340 unsigned char g_alpha;
341 unsigned int count;
342 int x_aoi_d; /* aoi display x offset to physical screen */
343 int y_aoi_d; /* aoi display y offset to physical screen */
344 struct fsl_diu_data *parent;
8b856f04 345 u8 *edid_data;
9b53a9e2
YS		 346};
347
ddd3d905
TT		 348/**
349 * struct fsl_diu_data - per-DIU data structure
350 * @dma_addr: DMA address of this structure
351 * @fsl_diu_info: fb_info objects, one per AOI
352 * @dev_attr: sysfs structure
353 * @irq: IRQ
ddd3d905
TT		 354 * @monitor_port: the monitor port this DIU is connected to
355 * @diu_reg: pointer to the DIU hardware registers
356 * @reg_lock: spinlock for register access
357 * @dummy_aoi: video buffer for the 4x4 32-bit dummy AOI
358 * dummy_ad: DIU Area Descriptor for the dummy AOI
359 * @ad[]: Area Descriptors for each real AOI
360 * @gamma: gamma color table
361 * @cursor: hardware cursor data
362 *
363 * This data structure must be allocated with 32-byte alignment, so that the
364 * internal fields can be aligned properly.
365 */
366struct fsl_diu_data {
367 dma_addr_t dma_addr;
368 struct fb_info fsl_diu_info[NUM_AOIS];
369 struct mfb_info mfb[NUM_AOIS];
370 struct device_attribute dev_attr;
371 unsigned int irq;
ddd3d905
TT		 372 enum fsl_diu_monitor_port monitor_port;
373 struct diu __iomem *diu_reg;
374 spinlock_t reg_lock;
375 u8 dummy_aoi[4 * 4 * 4];
376 struct diu_ad dummy_ad __aligned(8);
377 struct diu_ad ad[NUM_AOIS] __aligned(8);
378 u8 gamma[256 * 3] __aligned(32);
379 u8 cursor[MAX_CURS * MAX_CURS * 2] __aligned(32);
380} __aligned(32);
381
382/* Determine the DMA address of a member of the fsl_diu_data structure */
383#define DMA_ADDR(p, f) ((p)->dma_addr + offsetof(struct fsl_diu_data, f))
9b53a9e2
YS		 384
385static struct mfb_info mfb_template[] = {
2572df91
TT		 386 {
387 .index = PLANE0,
4a85dc8b
TT		 388 .id = "Panel0",
389 .registered = 0,
390 .count = 0,
391 .x_aoi_d = 0,
392 .y_aoi_d = 0,
9b53a9e2 393 },
2572df91
TT		 394 {
395 .index = PLANE1_AOI0,
4a85dc8b
TT		 396 .id = "Panel1 AOI0",
397 .registered = 0,
398 .g_alpha = 0xff,
399 .count = 0,
400 .x_aoi_d = 0,
401 .y_aoi_d = 0,
9b53a9e2 402 },
2572df91
TT		 403 {
404 .index = PLANE1_AOI1,
4a85dc8b
TT		 405 .id = "Panel1 AOI1",
406 .registered = 0,
407 .g_alpha = 0xff,
408 .count = 0,
409 .x_aoi_d = 0,
410 .y_aoi_d = 480,
9b53a9e2 411 },
2572df91
TT		 412 {
413 .index = PLANE2_AOI0,
4a85dc8b
TT		 414 .id = "Panel2 AOI0",
415 .registered = 0,
416 .g_alpha = 0xff,
417 .count = 0,
418 .x_aoi_d = 640,
419 .y_aoi_d = 0,
9b53a9e2 420 },
2572df91
TT		 421 {
422 .index = PLANE2_AOI1,
4a85dc8b
TT		 423 .id = "Panel2 AOI1",
424 .registered = 0,
425 .g_alpha = 0xff,
426 .count = 0,
427 .x_aoi_d = 640,
428 .y_aoi_d = 480,
9b53a9e2
YS		 429 },
430};
431
5cc2a36f
TT		 432#ifdef DEBUG
433static void __attribute__ ((unused)) fsl_diu_dump(struct diu __iomem *hw)
434{
435 mb();
436 pr_debug("DIU: desc=%08x,%08x,%08x, gamma=%08x pallete=%08x "
437 "cursor=%08x curs_pos=%08x diu_mode=%08x bgnd=%08x "
438 "disp_size=%08x hsyn_para=%08x vsyn_para=%08x syn_pol=%08x "
439 "thresholds=%08x int_mask=%08x plut=%08x\n",
440 hw->desc[0], hw->desc[1], hw->desc[2], hw->gamma,
441 hw->pallete, hw->cursor, hw->curs_pos, hw->diu_mode,
442 hw->bgnd, hw->disp_size, hw->hsyn_para, hw->vsyn_para,
443 hw->syn_pol, hw->thresholds, hw->int_mask, hw->plut);
444 rmb();
445}
446#endif
447
7653aaab
TT		 448/**
449 * fsl_diu_name_to_port - convert a port name to a monitor port enum
450 *
451 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
452 * the enum fsl_diu_monitor_port that corresponds to that string.
453 *
454 * For compatibility with older versions, a number ("0", "1", or "2") is also
455 * supported.
456 *
457 * If the string is unknown, DVI is assumed.
458 *
459 * If the particular port is not supported by the platform, another port
460 * (platform-specific) is chosen instead.
461 */
462static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s)
463{
464 enum fsl_diu_monitor_port port = FSL_DIU_PORT_DVI;
465 unsigned long val;
466
467 if (s) {
468 if (!strict_strtoul(s, 10, &val) && (val <= 2))
469 port = (enum fsl_diu_monitor_port) val;
470 else if (strncmp(s, "lvds", 4) == 0)
471 port = FSL_DIU_PORT_LVDS;
472 else if (strncmp(s, "dlvds", 5) == 0)
473 port = FSL_DIU_PORT_DLVDS;
474 }
475
476 return diu_ops.valid_monitor_port(port);
477}
478
0d9dab39
AG		 479/*
480 * Workaround for failed writing desc register of planes.
481 * Needed with MPC5121 DIU rev 2.0 silicon.
482 */
483void wr_reg_wa(u32 *reg, u32 val)
484{
485 do {
486 out_be32(reg, val);
487 } while (in_be32(reg) != val);
488}
489
7e47c211 490static void fsl_diu_enable_panel(struct fb_info *info)
9b53a9e2
YS		 491{
492 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
9b53a9e2 493 struct diu_ad *ad = mfbi->ad;
b7795052
TT		 494 struct fsl_diu_data *data = mfbi->parent;
495 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 496
7e47c211
TT		 497 switch (mfbi->index) {
498 case PLANE0:
499 if (hw->desc[0] != ad->paddr)
500 wr_reg_wa(&hw->desc[0], ad->paddr);
501 break;
502 case PLANE1_AOI0:
b7795052 503 cmfbi = &data->mfb[2];
7e47c211
TT		 504 if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
505 if (cmfbi->count > 0) /* AOI1 open */
506 ad->next_ad =
507 cpu_to_le32(cmfbi->ad->paddr);
508 else
509 ad->next_ad = 0;
510 wr_reg_wa(&hw->desc[1], ad->paddr);
9b53a9e2 511 }
7e47c211
TT		 512 break;
513 case PLANE2_AOI0:
b7795052 514 cmfbi = &data->mfb[4];
7e47c211
TT		 515 if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
516 if (cmfbi->count > 0) /* AOI1 open */
517 ad->next_ad =
518 cpu_to_le32(cmfbi->ad->paddr);
519 else
520 ad->next_ad = 0;
521 wr_reg_wa(&hw->desc[2], ad->paddr);
522 }
523 break;
524 case PLANE1_AOI1:
b7795052 525 pmfbi = &data->mfb[1];
7e47c211 526 ad->next_ad = 0;
b7795052 527 if (hw->desc[1] == data->dummy_ad.paddr)
7e47c211
TT		 528 wr_reg_wa(&hw->desc[1], ad->paddr);
529 else /* AOI0 open */
530 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
531 break;
532 case PLANE2_AOI1:
b7795052 533 pmfbi = &data->mfb[3];
7e47c211 534 ad->next_ad = 0;
b7795052 535 if (hw->desc[2] == data->dummy_ad.paddr)
7e47c211
TT		 536 wr_reg_wa(&hw->desc[2], ad->paddr);
537 else /* AOI0 was open */
538 pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
539 break;
540 }
9b53a9e2
YS		 541}
542
2572df91 543static void fsl_diu_disable_panel(struct fb_info *info)
9b53a9e2
YS		 544{
545 struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
9b53a9e2 546 struct diu_ad *ad = mfbi->ad;
b7795052
TT		 547 struct fsl_diu_data *data = mfbi->parent;
548 struct diu __iomem *hw = data->diu_reg;
9b53a9e2
YS		 549
550 switch (mfbi->index) {
2572df91 551 case PLANE0:
b7795052
TT		 552 if (hw->desc[0] != data->dummy_ad.paddr)
553 wr_reg_wa(&hw->desc[0], data->dummy_ad.paddr);
9b53a9e2 554 break;
2572df91 555 case PLANE1_AOI0:
b7795052 556 cmfbi = &data->mfb[2];
9b53a9e2 557 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 558 wr_reg_wa(&hw->desc[1], cmfbi->ad->paddr);
9b53a9e2
YS		 559 /* move AOI1 to the first */
560 else /* AOI1 was closed */
b7795052 561 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
9b53a9e2
YS		 562 /* close AOI 0 */
563 break;
2572df91 564 case PLANE2_AOI0:
b7795052 565 cmfbi = &data->mfb[4];
9b53a9e2 566 if (cmfbi->count > 0) /* AOI1 is open */
0d9dab39 567 wr_reg_wa(&hw->desc[2], cmfbi->ad->paddr);
9b53a9e2
YS		 568 /* move AOI1 to the first */
569 else /* AOI1 was closed */
b7795052 570 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
9b53a9e2
YS		 571 /* close AOI 0 */
572 break;
2572df91 573 case PLANE1_AOI1:
b7795052 574 pmfbi = &data->mfb[1];
9b53a9e2
YS		 575 if (hw->desc[1] != ad->paddr) {
576 /* AOI1 is not the first in the chain */
577 if (pmfbi->count > 0)
578 /* AOI0 is open, must be the first */
579 pmfbi->ad->next_ad = 0;
580 } else /* AOI1 is the first in the chain */
b7795052 581 wr_reg_wa(&hw->desc[1], data->dummy_ad.paddr);
9b53a9e2
YS		 582 /* close AOI 1 */
583 break;
2572df91 584 case PLANE2_AOI1:
b7795052 585 pmfbi = &data->mfb[3];
9b53a9e2
YS		 586 if (hw->desc[2] != ad->paddr) {
587 /* AOI1 is not the first in the chain */
588 if (pmfbi->count > 0)
589 /* AOI0 is open, must be the first */
590 pmfbi->ad->next_ad = 0;
591 } else /* AOI1 is the first in the chain */
b7795052 592 wr_reg_wa(&hw->desc[2], data->dummy_ad.paddr);
9b53a9e2
YS		 593 /* close AOI 1 */
594 break;
9b53a9e2 595 }
9b53a9e2
YS		 596}
597
598static void enable_lcdc(struct fb_info *info)
599{
9b53a9e2 600 struct mfb_info *mfbi = info->par;
b7795052
TT		 601 struct fsl_diu_data *data = mfbi->parent;
602 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 603
d397e916 604 out_be32(&hw->diu_mode, MFB_MODE1);
9b53a9e2
YS		 605}
606
607static void disable_lcdc(struct fb_info *info)
608{
9b53a9e2 609 struct mfb_info *mfbi = info->par;
b7795052
TT		 610 struct fsl_diu_data *data = mfbi->parent;
611 struct diu __iomem *hw = data->diu_reg;
9b53a9e2 612
d397e916 613 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 614}
615
616static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
617 struct fb_info *info)
618{
619 struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
b7795052 620 struct fsl_diu_data *data = mfbi->parent;
2572df91
TT		 621 int available_height, upper_aoi_bottom;
622 enum mfb_index index = mfbi->index;
9b53a9e2
YS		 623 int lower_aoi_is_open, upper_aoi_is_open;
624 __u32 base_plane_width, base_plane_height, upper_aoi_height;
625
b7795052
TT		 626 base_plane_width = data->fsl_diu_info[0].var.xres;
627 base_plane_height = data->fsl_diu_info[0].var.yres;
9b53a9e2 628
fdfaa483
YS		 629 if (mfbi->x_aoi_d < 0)
630 mfbi->x_aoi_d = 0;
631 if (mfbi->y_aoi_d < 0)
632 mfbi->y_aoi_d = 0;
9b53a9e2 633 switch (index) {
2572df91 634 case PLANE0:
9b53a9e2
YS		 635 if (mfbi->x_aoi_d != 0)
636 mfbi->x_aoi_d = 0;
637 if (mfbi->y_aoi_d != 0)
638 mfbi->y_aoi_d = 0;
639 break;
2572df91
TT		 640 case PLANE1_AOI0:
641 case PLANE2_AOI0:
b7795052 642 lower_aoi_mfbi = data->fsl_diu_info[index+1].par;
9b53a9e2
YS		 643 lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
644 if (var->xres > base_plane_width)
645 var->xres = base_plane_width;
646 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
647 mfbi->x_aoi_d = base_plane_width - var->xres;
648
649 if (lower_aoi_is_open)
650 available_height = lower_aoi_mfbi->y_aoi_d;
651 else
652 available_height = base_plane_height;
653 if (var->yres > available_height)
654 var->yres = available_height;
655 if ((mfbi->y_aoi_d + var->yres) > available_height)
656 mfbi->y_aoi_d = available_height - var->yres;
657 break;
2572df91
TT		 658 case PLANE1_AOI1:
659 case PLANE2_AOI1:
b7795052
TT		 660 upper_aoi_mfbi = data->fsl_diu_info[index-1].par;
661 upper_aoi_height = data->fsl_diu_info[index-1].var.yres;
9b53a9e2
YS		 662 upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
663 upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
664 if (var->xres > base_plane_width)
665 var->xres = base_plane_width;
666 if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
667 mfbi->x_aoi_d = base_plane_width - var->xres;
668 if (mfbi->y_aoi_d < 0)
669 mfbi->y_aoi_d = 0;
670 if (upper_aoi_is_open) {
671 if (mfbi->y_aoi_d < upper_aoi_bottom)
672 mfbi->y_aoi_d = upper_aoi_bottom;
673 available_height = base_plane_height
674 - upper_aoi_bottom;
675 } else
676 available_height = base_plane_height;
677 if (var->yres > available_height)
678 var->yres = available_height;
679 if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
680 mfbi->y_aoi_d = base_plane_height - var->yres;
681 break;
682 }
683}
684/*
685 * Checks to see if the hardware supports the state requested by var passed
686 * in. This function does not alter the hardware state! If the var passed in
687 * is slightly off by what the hardware can support then we alter the var
688 * PASSED in to what we can do. If the hardware doesn't support mode change
689 * a -EINVAL will be returned by the upper layers.
690 */
691static int fsl_diu_check_var(struct fb_var_screeninfo *var,
692 struct fb_info *info)
693{
9b53a9e2
YS		 694 if (var->xres_virtual < var->xres)
695 var->xres_virtual = var->xres;
696 if (var->yres_virtual < var->yres)
697 var->yres_virtual = var->yres;
698
699 if (var->xoffset < 0)
700 var->xoffset = 0;
701
702 if (var->yoffset < 0)
703 var->yoffset = 0;
704
705 if (var->xoffset + info->var.xres > info->var.xres_virtual)
706 var->xoffset = info->var.xres_virtual - info->var.xres;
707
708 if (var->yoffset + info->var.yres > info->var.yres_virtual)
709 var->yoffset = info->var.yres_virtual - info->var.yres;
710
711 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
712 (var->bits_per_pixel != 16))
713 var->bits_per_pixel = default_bpp;
714
715 switch (var->bits_per_pixel) {
716 case 16:
717 var->red.length = 5;
718 var->red.offset = 11;
719 var->red.msb_right = 0;
720
721 var->green.length = 6;
722 var->green.offset = 5;
723 var->green.msb_right = 0;
724
725 var->blue.length = 5;
726 var->blue.offset = 0;
727 var->blue.msb_right = 0;
728
729 var->transp.length = 0;
730 var->transp.offset = 0;
731 var->transp.msb_right = 0;
732 break;
733 case 24:
734 var->red.length = 8;
735 var->red.offset = 0;
736 var->red.msb_right = 0;
737
738 var->green.length = 8;
739 var->green.offset = 8;
740 var->green.msb_right = 0;
741
742 var->blue.length = 8;
743 var->blue.offset = 16;
744 var->blue.msb_right = 0;
745
746 var->transp.length = 0;
747 var->transp.offset = 0;
748 var->transp.msb_right = 0;
749 break;
750 case 32:
751 var->red.length = 8;
752 var->red.offset = 16;
753 var->red.msb_right = 0;
754
755 var->green.length = 8;
756 var->green.offset = 8;
757 var->green.msb_right = 0;
758
759 var->blue.length = 8;
760 var->blue.offset = 0;
761 var->blue.msb_right = 0;
762
763 var->transp.length = 8;
764 var->transp.offset = 24;
765 var->transp.msb_right = 0;
766
767 break;
768 }
9b53a9e2
YS		 769
770 var->height = -1;
771 var->width = -1;
772 var->grayscale = 0;
773
774 /* Copy nonstd field to/from sync for fbset usage */
775 var->sync |= var->nonstd;
776 var->nonstd |= var->sync;
777
778 adjust_aoi_size_position(var, info);
779 return 0;
780}
781
782static void set_fix(struct fb_info *info)
783{
784 struct fb_fix_screeninfo *fix = &info->fix;
785 struct fb_var_screeninfo *var = &info->var;
786 struct mfb_info *mfbi = info->par;
787
ec02dd23 788 strncpy(fix->id, mfbi->id, sizeof(fix->id));
9b53a9e2
YS		 789 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
790 fix->type = FB_TYPE_PACKED_PIXELS;
791 fix->accel = FB_ACCEL_NONE;
792 fix->visual = FB_VISUAL_TRUECOLOR;
793 fix->xpanstep = 1;
794 fix->ypanstep = 1;
795}
796
797static void update_lcdc(struct fb_info *info)
798{
799 struct fb_var_screeninfo *var = &info->var;
800 struct mfb_info *mfbi = info->par;
b7795052 801 struct fsl_diu_data *data = mfbi->parent;
3c755b7c 802 struct diu __iomem *hw;
9b53a9e2 803 int i, j;
ddd3d905 804 u8 *gamma_table_base;
9b53a9e2
YS		 805
806 u32 temp;
807
b7795052 808 hw = data->diu_reg;
9b53a9e2 809
28671735
TT		 810 if (diu_ops.set_monitor_port)
811 diu_ops.set_monitor_port(data->monitor_port);
b7795052 812 gamma_table_base = data->gamma;
ddd3d905 813
9b53a9e2
YS		 814 /* Prep for DIU init - gamma table, cursor table */
815
816 for (i = 0; i <= 2; i++)
4a85dc8b
TT		 817 for (j = 0; j <= 255; j++)
818 *gamma_table_base++ = j;
9b53a9e2 819
e09a8c3a
TT		 820 if (diu_ops.set_gamma_table)
821 diu_ops.set_gamma_table(data->monitor_port, data->gamma);
9b53a9e2 822
9b53a9e2
YS		 823 disable_lcdc(info);
824
825 /* Program DIU registers */
826
b7795052
TT		 827 out_be32(&hw->gamma, DMA_ADDR(data, gamma));
828 out_be32(&hw->cursor, DMA_ADDR(data, cursor));
9b53a9e2
YS		 829
830 out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
831 out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
832 out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
833 /* DISP SIZE */
9b53a9e2
YS		 834 out_be32(&hw->wb_size, 0); /* WB SIZE */
835 out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
836
837 /* Horizontal and vertical configuration register */
838 temp = var->left_margin << 22 | /* BP_H */
839 var->hsync_len << 11 | /* PW_H */
840 var->right_margin; /* FP_H */
841
842 out_be32(&hw->hsyn_para, temp);
843
844 temp = var->upper_margin << 22 | /* BP_V */
845 var->vsync_len << 11 | /* PW_V */
846 var->lower_margin; /* FP_V */
847
848 out_be32(&hw->vsyn_para, temp);
849
9b53a9e2
YS		 850 diu_ops.set_pixel_clock(var->pixclock);
851
852 out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
9b53a9e2
YS		 853 out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
854 out_be32(&hw->plut, 0x01F5F666);
855
856 /* Enable the DIU */
857 enable_lcdc(info);
858}
859
860static int map_video_memory(struct fb_info *info)
861{
537a1bf0 862 u32 smem_len = info->fix.line_length * info->var.yres_virtual;
05342c0b 863 void *p;
9b53a9e2 864
05342c0b
TT		 865 p = alloc_pages_exact(smem_len, GFP_DMA | __GFP_ZERO);
866 if (!p) {
154152ae 867 dev_err(info->dev, "unable to allocate fb memory\n");
9b53a9e2
YS		 868 return -ENOMEM;
869 }
537a1bf0 870 mutex_lock(&info->mm_lock);
05342c0b
TT		 871 info->screen_base = p;
872 info->fix.smem_start = virt_to_phys(info->screen_base);
537a1bf0
KH		 873 info->fix.smem_len = smem_len;
874 mutex_unlock(&info->mm_lock);
9b53a9e2
YS		 875 info->screen_size = info->fix.smem_len;
876
9b53a9e2
YS		 877 return 0;
878}
879
880static void unmap_video_memory(struct fb_info *info)
881{
05342c0b
TT		 882 void *p = info->screen_base;
883 size_t l = info->fix.smem_len;
884
537a1bf0 885 mutex_lock(&info->mm_lock);
05946bce 886 info->screen_base = NULL;
9b53a9e2
YS		 887 info->fix.smem_start = 0;
888 info->fix.smem_len = 0;
537a1bf0 889 mutex_unlock(&info->mm_lock);
05342c0b
TT		 890
891 if (p)
892 free_pages_exact(p, l);
9b53a9e2
YS		 893}
894
ae5591e3
YS		 895/*
896 * Using the fb_var_screeninfo in fb_info we set the aoi of this
897 * particular framebuffer. It is a light version of fsl_diu_set_par.
898 */
899static int fsl_diu_set_aoi(struct fb_info *info)
900{
901 struct fb_var_screeninfo *var = &info->var;
902 struct mfb_info *mfbi = info->par;
903 struct diu_ad *ad = mfbi->ad;
904
905 /* AOI should not be greater than display size */
906 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
907 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
908 return 0;
909}
910
e09a8c3a
TT		 911/**
912 * fsl_diu_get_pixel_format: return the pixel format for a given color depth
913 *
914 * The pixel format is a 32-bit value that determine which bits in each
915 * pixel are to be used for each color. This is the default function used
916 * if the platform does not define its own version.
917 */
918static u32 fsl_diu_get_pixel_format(unsigned int bits_per_pixel)
919{
920#define PF_BYTE_F 0x10000000
921#define PF_ALPHA_C_MASK 0x0E000000
922#define PF_ALPHA_C_SHIFT 25
923#define PF_BLUE_C_MASK 0x01800000
924#define PF_BLUE_C_SHIFT 23
925#define PF_GREEN_C_MASK 0x00600000
926#define PF_GREEN_C_SHIFT 21
927#define PF_RED_C_MASK 0x00180000
928#define PF_RED_C_SHIFT 19
929#define PF_PALETTE 0x00040000
930#define PF_PIXEL_S_MASK 0x00030000
931#define PF_PIXEL_S_SHIFT 16
932#define PF_COMP_3_MASK 0x0000F000
933#define PF_COMP_3_SHIFT 12
934#define PF_COMP_2_MASK 0x00000F00
935#define PF_COMP_2_SHIFT 8
936#define PF_COMP_1_MASK 0x000000F0
937#define PF_COMP_1_SHIFT 4
938#define PF_COMP_0_MASK 0x0000000F
939#define PF_COMP_0_SHIFT 0
940
941#define MAKE_PF(alpha, red, blue, green, size, c0, c1, c2, c3) \
942 cpu_to_le32(PF_BYTE_F | (alpha << PF_ALPHA_C_SHIFT) | \
943 (blue << PF_BLUE_C_SHIFT) | (green << PF_GREEN_C_SHIFT) | \
944 (red << PF_RED_C_SHIFT) | (c3 << PF_COMP_3_SHIFT) | \
945 (c2 << PF_COMP_2_SHIFT) | (c1 << PF_COMP_1_SHIFT) | \
946 (c0 << PF_COMP_0_SHIFT) | (size << PF_PIXEL_S_SHIFT))
947
948 switch (bits_per_pixel) {
949 case 32:
950 /* 0x88883316 */
951 return MAKE_PF(3, 2, 0, 1, 3, 8, 8, 8, 8);
952 case 24:
953 /* 0x88082219 */
954 return MAKE_PF(4, 0, 1, 2, 2, 0, 8, 8, 8);
955 case 16:
956 /* 0x65053118 */
957 return MAKE_PF(4, 2, 1, 0, 1, 5, 6, 5, 0);
958 default:
959 pr_err("fsl-diu: unsupported color depth %u\n", bits_per_pixel);
960 return 0;
961 }
962}
963
9b53a9e2
YS		 964/*
965 * Using the fb_var_screeninfo in fb_info we set the resolution of this
966 * particular framebuffer. This function alters the fb_fix_screeninfo stored
967 * in fb_info. It does not alter var in fb_info since we are using that
968 * data. This means we depend on the data in var inside fb_info to be
969 * supported by the hardware. fsl_diu_check_var is always called before
970 * fsl_diu_set_par to ensure this.
971 */
972static int fsl_diu_set_par(struct fb_info *info)
973{
974 unsigned long len;
975 struct fb_var_screeninfo *var = &info->var;
976 struct mfb_info *mfbi = info->par;
b7795052 977 struct fsl_diu_data *data = mfbi->parent;
9b53a9e2 978 struct diu_ad *ad = mfbi->ad;
3c755b7c 979 struct diu __iomem *hw;
9b53a9e2 980
b7795052 981 hw = data->diu_reg;
9b53a9e2
YS		 982
983 set_fix(info);
9b53a9e2
YS		 984
985 len = info->var.yres_virtual * info->fix.line_length;
986 /* Alloc & dealloc each time resolution/bpp change */
987 if (len != info->fix.smem_len) {
988 if (info->fix.smem_start)
989 unmap_video_memory(info);
9b53a9e2
YS		 990
991 /* Memory allocation for framebuffer */
992 if (map_video_memory(info)) {
154152ae 993 dev_err(info->dev, "unable to allocate fb memory 1\n");
9b53a9e2
YS		 994 return -ENOMEM;
995 }
996 }
997
e09a8c3a
TT		 998 if (diu_ops.get_pixel_format)
999 ad->pix_fmt = diu_ops.get_pixel_format(data->monitor_port,
1000 var->bits_per_pixel);
1001 else
1002 ad->pix_fmt = fsl_diu_get_pixel_format(var->bits_per_pixel);
1003
9b53a9e2 1004 ad->addr = cpu_to_le32(info->fix.smem_start);
ae5591e3
YS		 1005 ad->src_size_g_alpha = cpu_to_le32((var->yres_virtual << 12) |
1006 var->xres_virtual) | mfbi->g_alpha;
1007 /* AOI should not be greater than display size */
9b53a9e2 1008 ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
ae5591e3 1009 ad->offset_xyi = cpu_to_le32((var->yoffset << 16) | var->xoffset);
9b53a9e2
YS		 1010 ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
1011
1012 /* Disable chroma keying function */
1013 ad->ckmax_r = 0;
1014 ad->ckmax_g = 0;
1015 ad->ckmax_b = 0;
1016
1017 ad->ckmin_r = 255;
1018 ad->ckmin_g = 255;
1019 ad->ckmin_b = 255;
1020
2572df91 1021 if (mfbi->index == PLANE0)
9b53a9e2
YS		 1022 update_lcdc(info);
1023 return 0;
1024}
1025
1026static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
1027{
4a85dc8b 1028 return ((val << width) + 0x7FFF - val) >> 16;
9b53a9e2
YS		 1029}
1030
1031/*
1032 * Set a single color register. The values supplied have a 16 bit magnitude
1033 * which needs to be scaled in this function for the hardware. Things to take
1034 * into consideration are how many color registers, if any, are supported with
1035 * the current color visual. With truecolor mode no color palettes are
25985edc 1036 * supported. Here a pseudo palette is created which we store the value in
9b53a9e2
YS		 1037 * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
1038 * color palette.
1039 */
4a85dc8b
TT		 1040static int fsl_diu_setcolreg(unsigned int regno, unsigned int red,
1041 unsigned int green, unsigned int blue,
1042 unsigned int transp, struct fb_info *info)
9b53a9e2
YS		 1043{
1044 int ret = 1;
1045
1046 /*
1047 * If greyscale is true, then we convert the RGB value
1048 * to greyscale no matter what visual we are using.
1049 */
1050 if (info->var.grayscale)
1051 red = green = blue = (19595 * red + 38470 * green +
1052 7471 * blue) >> 16;
1053 switch (info->fix.visual) {
1054 case FB_VISUAL_TRUECOLOR:
1055 /*
1056 * 16-bit True Colour. We encode the RGB value
1057 * according to the RGB bitfield information.
1058 */
1059 if (regno < 16) {
1060 u32 *pal = info->pseudo_palette;
1061 u32 v;
1062
1063 red = CNVT_TOHW(red, info->var.red.length);
1064 green = CNVT_TOHW(green, info->var.green.length);
1065 blue = CNVT_TOHW(blue, info->var.blue.length);
1066 transp = CNVT_TOHW(transp, info->var.transp.length);
1067
1068 v = (red << info->var.red.offset) |
1069 (green << info->var.green.offset) |
1070 (blue << info->var.blue.offset) |
1071 (transp << info->var.transp.offset);
1072
1073 pal[regno] = v;
1074 ret = 0;
1075 }
1076 break;
9b53a9e2
YS		 1077 }
1078
1079 return ret;
1080}
1081
1082/*
1083 * Pan (or wrap, depending on the `vmode' field) the display using the
1084 * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
1085 * don't fit, return -EINVAL.
1086 */
1087static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
1088 struct fb_info *info)
1089{
1090 if ((info->var.xoffset == var->xoffset) &&
1091 (info->var.yoffset == var->yoffset))
1092 return 0; /* No change, do nothing */
1093
1094 if (var->xoffset < 0 || var->yoffset < 0
1095 || var->xoffset + info->var.xres > info->var.xres_virtual
1096 || var->yoffset + info->var.yres > info->var.yres_virtual)
1097 return -EINVAL;
1098
1099 info->var.xoffset = var->xoffset;
1100 info->var.yoffset = var->yoffset;
1101
1102 if (var->vmode & FB_VMODE_YWRAP)
1103 info->var.vmode |= FB_VMODE_YWRAP;
1104 else
1105 info->var.vmode &= ~FB_VMODE_YWRAP;
1106
ae5591e3
YS		 1107 fsl_diu_set_aoi(info);
1108
9b53a9e2
YS		 1109 return 0;
1110}
1111
9b53a9e2
YS		 1112static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
1113 unsigned long arg)
1114{
1115 struct mfb_info *mfbi = info->par;
1116 struct diu_ad *ad = mfbi->ad;
1117 struct mfb_chroma_key ck;
1118 unsigned char global_alpha;
1119 struct aoi_display_offset aoi_d;
1120 __u32 pix_fmt;
1121 void __user *buf = (void __user *)arg;
1122
1123 if (!arg)
1124 return -EINVAL;
5cc2a36f
TT		 1125
1126 dev_dbg(info->dev, "ioctl %08x (dir=%s%s type=%u nr=%u size=%u)\n", cmd,
1127 _IOC_DIR(cmd) & _IOC_READ ? "R" : "",
1128 _IOC_DIR(cmd) & _IOC_WRITE ? "W" : "",
1129 _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
1130
9b53a9e2 1131 switch (cmd) {
36b0b1d4
TT		 1132 case MFB_SET_PIXFMT_OLD:
1133 dev_warn(info->dev,
1134 "MFB_SET_PIXFMT value of 0x%08x is deprecated.\n",
1135 MFB_SET_PIXFMT_OLD);
9b53a9e2
YS		 1136 case MFB_SET_PIXFMT:
1137 if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
1138 return -EFAULT;
1139 ad->pix_fmt = pix_fmt;
9b53a9e2 1140 break;
36b0b1d4
TT		 1141 case MFB_GET_PIXFMT_OLD:
1142 dev_warn(info->dev,
1143 "MFB_GET_PIXFMT value of 0x%08x is deprecated.\n",
1144 MFB_GET_PIXFMT_OLD);
9b53a9e2
YS		 1145 case MFB_GET_PIXFMT:
1146 pix_fmt = ad->pix_fmt;
1147 if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
1148 return -EFAULT;
9b53a9e2
YS		 1149 break;
1150 case MFB_SET_AOID:
1151 if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
1152 return -EFAULT;
1153 mfbi->x_aoi_d = aoi_d.x_aoi_d;
1154 mfbi->y_aoi_d = aoi_d.y_aoi_d;
9b53a9e2 1155 fsl_diu_check_var(&info->var, info);
ae5591e3 1156 fsl_diu_set_aoi(info);
9b53a9e2
YS		 1157 break;
1158 case MFB_GET_AOID:
1159 aoi_d.x_aoi_d = mfbi->x_aoi_d;
1160 aoi_d.y_aoi_d = mfbi->y_aoi_d;
1161 if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
1162 return -EFAULT;
9b53a9e2
YS		 1163 break;
1164 case MFB_GET_ALPHA:
1165 global_alpha = mfbi->g_alpha;
1166 if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
1167 return -EFAULT;
9b53a9e2
YS		 1168 break;
1169 case MFB_SET_ALPHA:
1170 /* set panel information */
1171 if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
1172 return -EFAULT;
1173 ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
1174 (global_alpha & 0xff);
1175 mfbi->g_alpha = global_alpha;
9b53a9e2
YS		 1176 break;
1177 case MFB_SET_CHROMA_KEY:
1178 /* set panel winformation */
1179 if (copy_from_user(&ck, buf, sizeof(ck)))
1180 return -EFAULT;
1181
1182 if (ck.enable &&
1183 (ck.red_max < ck.red_min ||
1184 ck.green_max < ck.green_min ||
1185 ck.blue_max < ck.blue_min))
1186 return -EINVAL;
1187
1188 if (!ck.enable) {
1189 ad->ckmax_r = 0;
1190 ad->ckmax_g = 0;
1191 ad->ckmax_b = 0;
1192 ad->ckmin_r = 255;
1193 ad->ckmin_g = 255;
1194 ad->ckmin_b = 255;
1195 } else {
1196 ad->ckmax_r = ck.red_max;
1197 ad->ckmax_g = ck.green_max;
1198 ad->ckmax_b = ck.blue_max;
1199 ad->ckmin_r = ck.red_min;
1200 ad->ckmin_g = ck.green_min;
1201 ad->ckmin_b = ck.blue_min;
1202 }
9b53a9e2 1203 break;
e95c17e9
TT		 1204#ifdef CONFIG_PPC_MPC512x
1205 case MFB_SET_GAMMA: {
1206 struct fsl_diu_data *data = mfbi->parent;
1207
1208 if (copy_from_user(data->gamma, buf, sizeof(data->gamma)))
1209 return -EFAULT;
1210 setbits32(&data->diu_reg->gamma, 0); /* Force table reload */
1211 break;
1212 }
1213 case MFB_GET_GAMMA: {
1214 struct fsl_diu_data *data = mfbi->parent;
1215
1216 if (copy_to_user(buf, data->gamma, sizeof(data->gamma)))
1217 return -EFAULT;
1218 break;
1219 }
1220#endif
9b53a9e2 1221 default:
154152ae 1222 dev_err(info->dev, "unknown ioctl command (0x%08X)\n", cmd);
9b53a9e2
YS		 1223 return -ENOIOCTLCMD;
1224 }
1225
1226 return 0;
1227}
1228
1229/* turn on fb if count == 1
1230 */
1231static int fsl_diu_open(struct fb_info *info, int user)
1232{
1233 struct mfb_info *mfbi = info->par;
1234 int res = 0;
1235
4b5006ec 1236 /* free boot splash memory on first /dev/fb0 open */
2572df91 1237 if ((mfbi->index == PLANE0) && diu_ops.release_bootmem)
4b5006ec
AG		 1238 diu_ops.release_bootmem();
1239
9b53a9e2
YS		 1240 spin_lock(&diu_lock);
1241 mfbi->count++;
1242 if (mfbi->count == 1) {
9b53a9e2
YS		 1243 fsl_diu_check_var(&info->var, info);
1244 res = fsl_diu_set_par(info);
1245 if (res < 0)
1246 mfbi->count--;
f74de500
TT		 1247 else {
1248 struct fsl_diu_data *data = mfbi->parent;
1249
1250#ifdef CONFIG_NOT_COHERENT_CACHE
1251 /*
1252 * Enable underrun detection and vertical sync
1253 * interrupts.
1254 */
1255 clrbits32(&data->diu_reg->int_mask,
1256 INT_UNDRUN | INT_VSYNC);
1257#else
1258 /* Enable underrun detection */
1259 clrbits32(&data->diu_reg->int_mask, INT_UNDRUN);
1260#endif
7e47c211 1261 fsl_diu_enable_panel(info);
f74de500 1262 }
9b53a9e2
YS		 1263 }
1264
1265 spin_unlock(&diu_lock);
1266 return res;
1267}
1268
1269/* turn off fb if count == 0
1270 */
1271static int fsl_diu_release(struct fb_info *info, int user)
1272{
1273 struct mfb_info *mfbi = info->par;
1274 int res = 0;
1275
1276 spin_lock(&diu_lock);
1277 mfbi->count--;
f74de500
TT		 1278 if (mfbi->count == 0) {
1279 struct fsl_diu_data *data = mfbi->parent;
1280
1281 /* Disable interrupts */
1282 out_be32(&data->diu_reg->int_mask, 0xffffffff);
2572df91 1283 fsl_diu_disable_panel(info);
f74de500 1284 }
2572df91 1285
9b53a9e2
YS		 1286 spin_unlock(&diu_lock);
1287 return res;
1288}
1289
1290static struct fb_ops fsl_diu_ops = {
1291 .owner = THIS_MODULE,
1292 .fb_check_var = fsl_diu_check_var,
1293 .fb_set_par = fsl_diu_set_par,
1294 .fb_setcolreg = fsl_diu_setcolreg,
9b53a9e2
YS		 1295 .fb_pan_display = fsl_diu_pan_display,
1296 .fb_fillrect = cfb_fillrect,
1297 .fb_copyarea = cfb_copyarea,
1298 .fb_imageblit = cfb_imageblit,
1299 .fb_ioctl = fsl_diu_ioctl,
1300 .fb_open = fsl_diu_open,
1301 .fb_release = fsl_diu_release,
1302};
1303
05946bce 1304static int __devinit install_fb(struct fb_info *info)
9b53a9e2
YS		 1305{
1306 int rc;
1307 struct mfb_info *mfbi = info->par;
1308 const char *aoi_mode, *init_aoi_mode = "320x240";
8b856f04
AG		 1309 struct fb_videomode *db = fsl_diu_mode_db;
1310 unsigned int dbsize = ARRAY_SIZE(fsl_diu_mode_db);
1311 int has_default_mode = 1;
9b53a9e2 1312
f934fbd6
TT		 1313 info->var.activate = FB_ACTIVATE_NOW;
1314 info->fbops = &fsl_diu_ops;
934dbeeb
TT		 1315 info->flags = FBINFO_DEFAULT | FBINFO_VIRTFB | FBINFO_PARTIAL_PAN_OK |
1316 FBINFO_READS_FAST;
f934fbd6
TT		 1317 info->pseudo_palette = mfbi->pseudo_palette;
1318
1319 rc = fb_alloc_cmap(&info->cmap, 16, 0);
1320 if (rc)
1321 return rc;
9b53a9e2 1322
2572df91 1323 if (mfbi->index == PLANE0) {
8b856f04
AG		 1324 if (mfbi->edid_data) {
1325 /* Now build modedb from EDID */
1326 fb_edid_to_monspecs(mfbi->edid_data, &info->monspecs);
1327 fb_videomode_to_modelist(info->monspecs.modedb,
1328 info->monspecs.modedb_len,
1329 &info->modelist);
1330 db = info->monspecs.modedb;
1331 dbsize = info->monspecs.modedb_len;
1332 }
9b53a9e2 1333 aoi_mode = fb_mode;
8b856f04 1334 } else {
9b53a9e2 1335 aoi_mode = init_aoi_mode;
8b856f04 1336 }
63cf8df4
TT		 1337 rc = fb_find_mode(&info->var, info, aoi_mode, db, dbsize, NULL,
1338 default_bpp);
154152ae 1339 if (!rc) {
8b856f04
AG		 1340 /*
1341 * For plane 0 we continue and look into
1342 * driver's internal modedb.
1343 */
2572df91 1344 if ((mfbi->index == PLANE0) && mfbi->edid_data)
8b856f04
AG		 1345 has_default_mode = 0;
1346 else
1347 return -EINVAL;
9b53a9e2
YS		 1348 }
1349
8b856f04
AG		 1350 if (!has_default_mode) {
1351 rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
63cf8df4
TT		 1352 ARRAY_SIZE(fsl_diu_mode_db), NULL, default_bpp);
1353 if (rc)
8b856f04
AG		 1354 has_default_mode = 1;
1355 }
1356
1357 /* Still not found, use preferred mode from database if any */
1358 if (!has_default_mode && info->monspecs.modedb) {
1359 struct fb_monspecs *specs = &info->monspecs;
1360 struct fb_videomode *modedb = &specs->modedb[0];
1361
1362 /*
1363 * Get preferred timing. If not found,
1364 * first mode in database will be used.
1365 */
1366 if (specs->misc & FB_MISC_1ST_DETAIL) {
1367 int i;
1368
1369 for (i = 0; i < specs->modedb_len; i++) {
1370 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1371 modedb = &specs->modedb[i];
1372 break;
1373 }
1374 }
1375 }
1376
1377 info->var.bits_per_pixel = default_bpp;
1378 fb_videomode_to_var(&info->var, modedb);
1379 }
1380
9b53a9e2 1381 if (fsl_diu_check_var(&info->var, info)) {
154152ae 1382 dev_err(info->dev, "fsl_diu_check_var failed\n");
589c7971 1383 unmap_video_memory(info);
9b53a9e2
YS		 1384 fb_dealloc_cmap(&info->cmap);
1385 return -EINVAL;
1386 }
1387
9b53a9e2 1388 if (register_framebuffer(info) < 0) {
154152ae 1389 dev_err(info->dev, "register_framebuffer failed\n");
9b53a9e2
YS		 1390 unmap_video_memory(info);
1391 fb_dealloc_cmap(&info->cmap);
1392 return -EINVAL;
1393 }
1394
1395 mfbi->registered = 1;
154152ae 1396 dev_info(info->dev, "%s registered successfully\n", mfbi->id);
9b53a9e2
YS		 1397
1398 return 0;
1399}
1400
05946bce 1401static void uninstall_fb(struct fb_info *info)
9b53a9e2
YS		 1402{
1403 struct mfb_info *mfbi = info->par;
1404
1405 if (!mfbi->registered)
1406 return;
1407
2572df91 1408 if (mfbi->index == PLANE0)
8b856f04
AG		 1409 kfree(mfbi->edid_data);
1410
9b53a9e2
YS		 1411 unregister_framebuffer(info);
1412 unmap_video_memory(info);
1413 if (&info->cmap)
1414 fb_dealloc_cmap(&info->cmap);
1415
1416 mfbi->registered = 0;
1417}
1418
1419static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
1420{
3c755b7c 1421 struct diu __iomem *hw = dev_id;
f74de500 1422 uint32_t status = in_be32(&hw->int_status);
9b53a9e2
YS		 1423
1424 if (status) {
1425 /* This is the workaround for underrun */
1426 if (status & INT_UNDRUN) {
1427 out_be32(&hw->diu_mode, 0);
9b53a9e2
YS		 1428 udelay(1);
1429 out_be32(&hw->diu_mode, 1);
1430 }
1431#if defined(CONFIG_NOT_COHERENT_CACHE)
1432 else if (status & INT_VSYNC) {
1433 unsigned int i;
4a85dc8b 1434
9b53a9e2
YS		 1435 for (i = 0; i < coherence_data_size;
1436 i += d_cache_line_size)
1437 __asm__ __volatile__ (
1438 "dcbz 0, %[input]"
1439 ::[input]"r"(&coherence_data[i]));
1440 }
1441#endif
1442 return IRQ_HANDLED;
1443 }
1444 return IRQ_NONE;
1445}
1446
9b53a9e2
YS		 1447#ifdef CONFIG_PM
1448/*
1449 * Power management hooks. Note that we won't be called from IRQ context,
1450 * unlike the blank functions above, so we may sleep.
1451 */
2dc11581 1452static int fsl_diu_suspend(struct platform_device *ofdev, pm_message_t state)
9b53a9e2 1453{
b7795052 1454 struct fsl_diu_data *data;
9b53a9e2 1455
b7795052 1456 data = dev_get_drvdata(&ofdev->dev);
f7f5ef0a 1457 disable_lcdc(data->fsl_diu_info);
9b53a9e2
YS		 1458
1459 return 0;
1460}
1461
2dc11581 1462static int fsl_diu_resume(struct platform_device *ofdev)
9b53a9e2 1463{
b7795052 1464 struct fsl_diu_data *data;
9b53a9e2 1465
b7795052 1466 data = dev_get_drvdata(&ofdev->dev);
f7f5ef0a 1467 enable_lcdc(data->fsl_diu_info);
9b53a9e2
YS		 1468
1469 return 0;
1470}
1471
1472#else
1473#define fsl_diu_suspend NULL
1474#define fsl_diu_resume NULL
1475#endif /* CONFIG_PM */
1476
9b53a9e2
YS		 1477static ssize_t store_monitor(struct device *device,
1478 struct device_attribute *attr, const char *buf, size_t count)
1479{
7653aaab 1480 enum fsl_diu_monitor_port old_monitor_port;
b7795052 1481 struct fsl_diu_data *data =
9b53a9e2
YS		 1482 container_of(attr, struct fsl_diu_data, dev_attr);
1483
b7795052
TT		 1484 old_monitor_port = data->monitor_port;
1485 data->monitor_port = fsl_diu_name_to_port(buf);
9b53a9e2 1486
b7795052 1487 if (old_monitor_port != data->monitor_port) {
9b53a9e2
YS		 1488 /* All AOIs need adjust pixel format
1489 * fsl_diu_set_par only change the pixsel format here
1490 * unlikely to fail. */
ddd3d905
TT		 1491 unsigned int i;
1492
1493 for (i=0; i < NUM_AOIS; i++)
b7795052 1494 fsl_diu_set_par(&data->fsl_diu_info[i]);
9b53a9e2
YS		 1495 }
1496 return count;
1497}
1498
1499static ssize_t show_monitor(struct device *device,
1500 struct device_attribute *attr, char *buf)
1501{
b7795052 1502 struct fsl_diu_data *data =
9b53a9e2 1503 container_of(attr, struct fsl_diu_data, dev_attr);
7653aaab 1504
b7795052 1505 switch (data->monitor_port) {
7653aaab
TT		 1506 case FSL_DIU_PORT_DVI:
1507 return sprintf(buf, "DVI\n");
1508 case FSL_DIU_PORT_LVDS:
1509 return sprintf(buf, "Single-link LVDS\n");
1510 case FSL_DIU_PORT_DLVDS:
1511 return sprintf(buf, "Dual-link LVDS\n");
1512 }
1513
1514 return 0;
9b53a9e2
YS		 1515}
1516
9e52ba61 1517static int __devinit fsl_diu_probe(struct platform_device *pdev)
9b53a9e2 1518{
9e52ba61 1519 struct device_node *np = pdev->dev.of_node;
9b53a9e2 1520 struct mfb_info *mfbi;
b7795052 1521 struct fsl_diu_data *data;
4b5006ec 1522 int diu_mode;
b7795052 1523 dma_addr_t dma_addr; /* DMA addr of fsl_diu_data struct */
ddd3d905
TT		 1524 unsigned int i;
1525 int ret;
9b53a9e2 1526
c1f383d9
DC		 1527 data = dmam_alloc_coherent(&pdev->dev, sizeof(struct fsl_diu_data),
1528 &dma_addr, GFP_DMA | __GFP_ZERO);
b7795052 1529 if (!data)
9b53a9e2 1530 return -ENOMEM;
b7795052 1531 data->dma_addr = dma_addr;
ddd3d905
TT		 1532
1533 /*
1534 * dma_alloc_coherent() uses a page allocator, so the address is
1535 * always page-aligned. We need the memory to be 32-byte aligned,
1536 * so that's good. However, if one day the allocator changes, we
1537 * need to catch that. It's not worth the effort to handle unaligned
1538 * alloctions now because it's highly unlikely to ever be a problem.
1539 */
b7795052 1540 if ((unsigned long)data & 31) {
ddd3d905
TT		 1541 dev_err(&pdev->dev, "misaligned allocation");
1542 ret = -ENOMEM;
1543 goto error;
1544 }
9b53a9e2 1545
b7795052 1546 spin_lock_init(&data->reg_lock);
3c755b7c 1547
ddd3d905 1548 for (i = 0; i < NUM_AOIS; i++) {
b7795052 1549 struct fb_info *info = &data->fsl_diu_info[i];
ddd3d905
TT		 1550
1551 info->device = &pdev->dev;
b7795052 1552 info->par = &data->mfb[i];
ddd3d905
TT		 1553
1554 /*
1555 * We store the physical address of the AD in the reserved
1556 * 'paddr' field of the AD itself.
1557 */
b7795052 1558 data->ad[i].paddr = DMA_ADDR(data, ad[i]);
ddd3d905
TT		 1559
1560 info->fix.smem_start = 0;
1561
1562 /* Initialize the AOI data structure */
1563 mfbi = info->par;
9b53a9e2 1564 memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
b7795052
TT		 1565 mfbi->parent = data;
1566 mfbi->ad = &data->ad[i];
8b856f04 1567
2572df91 1568 if (mfbi->index == PLANE0) {
8b856f04
AG		 1569 const u8 *prop;
1570 int len;
1571
1572 /* Get EDID */
1573 prop = of_get_property(np, "edid", &len);
1574 if (prop && len == EDID_LENGTH)
1575 mfbi->edid_data = kmemdup(prop, EDID_LENGTH,
1576 GFP_KERNEL);
1577 }
9b53a9e2
YS		 1578 }
1579
b7795052
TT		 1580 data->diu_reg = of_iomap(np, 0);
1581 if (!data->diu_reg) {
9e52ba61 1582 dev_err(&pdev->dev, "cannot map DIU registers\n");
9b53a9e2 1583 ret = -EFAULT;
ddd3d905 1584 goto error;
9b53a9e2
YS		 1585 }
1586
b7795052 1587 diu_mode = in_be32(&data->diu_reg->diu_mode);
c4e5a023 1588 if (diu_mode == MFB_MODE0)
b7795052 1589 out_be32(&data->diu_reg->diu_mode, 0); /* disable DIU */
9b53a9e2
YS		 1590
1591 /* Get the IRQ of the DIU */
b7795052 1592 data->irq = irq_of_parse_and_map(np, 0);
9b53a9e2 1593
b7795052 1594 if (!data->irq) {
9e52ba61 1595 dev_err(&pdev->dev, "could not get DIU IRQ\n");
9b53a9e2
YS		 1596 ret = -EINVAL;
1597 goto error;
1598 }
b7795052 1599 data->monitor_port = monitor_port;
9b53a9e2 1600
ddd3d905 1601 /* Initialize the dummy Area Descriptor */
b7795052
TT		 1602 data->dummy_ad.addr = cpu_to_le32(DMA_ADDR(data, dummy_aoi));
1603 data->dummy_ad.pix_fmt = 0x88882317;
1604 data->dummy_ad.src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
1605 data->dummy_ad.aoi_size = cpu_to_le32((4 << 16) | 2);
1606 data->dummy_ad.offset_xyi = 0;
1607 data->dummy_ad.offset_xyd = 0;
1608 data->dummy_ad.next_ad = 0;
1609 data->dummy_ad.paddr = DMA_ADDR(data, dummy_ad);
9b53a9e2 1610
4b5006ec
AG		 1611 /*
1612 * Let DIU display splash screen if it was pre-initialized
1613 * by the bootloader, set dummy area descriptor otherwise.
1614 */
c4e5a023 1615 if (diu_mode == MFB_MODE0)
b7795052 1616 out_be32(&data->diu_reg->desc[0], data->dummy_ad.paddr);
ddd3d905 1617
b7795052
TT		 1618 out_be32(&data->diu_reg->desc[1], data->dummy_ad.paddr);
1619 out_be32(&data->diu_reg->desc[2], data->dummy_ad.paddr);
ddd3d905
TT		 1620
1621 for (i = 0; i < NUM_AOIS; i++) {
b7795052 1622 ret = install_fb(&data->fsl_diu_info[i]);
9b53a9e2 1623 if (ret) {
9e52ba61 1624 dev_err(&pdev->dev, "could not register fb %d\n", i);
9b53a9e2
YS		 1625 goto error;
1626 }
1627 }
1628
f74de500
TT		 1629 /*
1630 * Older versions of U-Boot leave interrupts enabled, so disable
1631 * all of them and clear the status register.
1632 */
1633 out_be32(&data->diu_reg->int_mask, 0xffffffff);
1634 in_be32(&data->diu_reg->int_status);
1635
1636 ret = request_irq(data->irq, fsl_diu_isr, 0, "fsl-diu-fb",
1637 &data->diu_reg);
1638 if (ret) {
9e52ba61 1639 dev_err(&pdev->dev, "could not claim irq\n");
9b53a9e2
YS		 1640 goto error;
1641 }
1642
b7795052
TT		 1643 sysfs_attr_init(&data->dev_attr.attr);
1644 data->dev_attr.attr.name = "monitor";
1645 data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
1646 data->dev_attr.show = show_monitor;
1647 data->dev_attr.store = store_monitor;
1648 ret = device_create_file(&pdev->dev, &data->dev_attr);
ddd3d905 1649 if (ret) {
9e52ba61 1650 dev_err(&pdev->dev, "could not create sysfs file %s\n",
b7795052 1651 data->dev_attr.attr.name);
9b53a9e2
YS		 1652 }
1653
b7795052 1654 dev_set_drvdata(&pdev->dev, data);
9b53a9e2
YS		 1655 return 0;
1656
1657error:
ddd3d905 1658 for (i = 0; i < NUM_AOIS; i++)
b7795052 1659 uninstall_fb(&data->fsl_diu_info[i]);
ddd3d905 1660
b7795052 1661 iounmap(data->diu_reg);
9b53a9e2 1662
9b53a9e2
YS		 1663 return ret;
1664}
1665
9e52ba61 1666static int fsl_diu_remove(struct platform_device *pdev)
9b53a9e2 1667{
b7795052 1668 struct fsl_diu_data *data;
9b53a9e2
YS		 1669 int i;
1670
b7795052
TT		 1671 data = dev_get_drvdata(&pdev->dev);
1672 disable_lcdc(&data->fsl_diu_info[0]);
f74de500
TT		 1673
1674 free_irq(data->irq, &data->diu_reg);
ddd3d905
TT		 1675
1676 for (i = 0; i < NUM_AOIS; i++)
b7795052 1677 uninstall_fb(&data->fsl_diu_info[i]);
ddd3d905 1678
b7795052 1679 iounmap(data->diu_reg);
ddd3d905 1680
9b53a9e2
YS		 1681 return 0;
1682}
1683
1684#ifndef MODULE
1685static int __init fsl_diu_setup(char *options)
1686{
1687 char *opt;
1688 unsigned long val;
1689
1690 if (!options || !*options)
1691 return 0;
1692
1693 while ((opt = strsep(&options, ",")) != NULL) {
1694 if (!*opt)
1695 continue;
1696 if (!strncmp(opt, "monitor=", 8)) {
7653aaab 1697 monitor_port = fsl_diu_name_to_port(opt + 8);
9b53a9e2
YS		 1698 } else if (!strncmp(opt, "bpp=", 4)) {
1699 if (!strict_strtoul(opt + 4, 10, &val))
1700 default_bpp = val;
1701 } else
1702 fb_mode = opt;
1703 }
1704
1705 return 0;
1706}
1707#endif
1708
1709static struct of_device_id fsl_diu_match[] = {
d24720a4
AG		 1710#ifdef CONFIG_PPC_MPC512x
1711 {
1712 .compatible = "fsl,mpc5121-diu",
1713 },
1714#endif
9b53a9e2
YS		 1715 {
1716 .compatible = "fsl,diu",
1717 },
1718 {}
1719};
1720MODULE_DEVICE_TABLE(of, fsl_diu_match);
1721
28541d0f 1722static struct platform_driver fsl_diu_driver = {
4018294b 1723 .driver = {
f8c6bf6a 1724 .name = "fsl-diu-fb",
4018294b
GL		 1725 .owner = THIS_MODULE,
1726 .of_match_table = fsl_diu_match,
1727 },
9b53a9e2
YS		 1728 .probe = fsl_diu_probe,
1729 .remove = fsl_diu_remove,
1730 .suspend = fsl_diu_suspend,
1731 .resume = fsl_diu_resume,
1732};
1733
1734static int __init fsl_diu_init(void)
1735{
1736#ifdef CONFIG_NOT_COHERENT_CACHE
1737 struct device_node *np;
1738 const u32 *prop;
1739#endif
1740 int ret;
1741#ifndef MODULE
1742 char *option;
1743
1744 /*
1745 * For kernel boot options (in 'video=xxxfb:<options>' format)
1746 */
1747 if (fb_get_options("fslfb", &option))
1748 return -ENODEV;
1749 fsl_diu_setup(option);
7653aaab
TT		 1750#else
1751 monitor_port = fsl_diu_name_to_port(monitor_string);
9b53a9e2 1752#endif
154152ae 1753 pr_info("Freescale Display Interface Unit (DIU) framebuffer driver\n");
9b53a9e2
YS		 1754
1755#ifdef CONFIG_NOT_COHERENT_CACHE
1756 np = of_find_node_by_type(NULL, "cpu");
1757 if (!np) {
154152ae 1758 pr_err("fsl-diu-fb: can't find 'cpu' device node\n");
9b53a9e2
YS		 1759 return -ENODEV;
1760 }
1761
1762 prop = of_get_property(np, "d-cache-size", NULL);
5394ba0f 1763 if (prop == NULL) {
154152ae
TT		 1764 pr_err("fsl-diu-fb: missing 'd-cache-size' property' "
1765 "in 'cpu' node\n");
5394ba0f 1766 of_node_put(np);
9b53a9e2 1767 return -ENODEV;
5394ba0f 1768 }
9b53a9e2 1769
4a85dc8b
TT		 1770 /*
1771 * Freescale PLRU requires 13/8 times the cache size to do a proper
1772 * displacement flush
9b53a9e2 1773 */
9e52ba61 1774 coherence_data_size = be32_to_cpup(prop) * 13;
9b53a9e2
YS		 1775 coherence_data_size /= 8;
1776
5cc2a36f
TT		 1777 pr_debug("fsl-diu-fb: coherence data size is %zu bytes\n",
1778 coherence_data_size);
1779
9b53a9e2 1780 prop = of_get_property(np, "d-cache-line-size", NULL);
5394ba0f 1781 if (prop == NULL) {
154152ae
TT		 1782 pr_err("fsl-diu-fb: missing 'd-cache-line-size' property' "
1783 "in 'cpu' node\n");
5394ba0f 1784 of_node_put(np);
9b53a9e2 1785 return -ENODEV;
5394ba0f 1786 }
9e52ba61 1787 d_cache_line_size = be32_to_cpup(prop);
9b53a9e2 1788
5cc2a36f
TT		 1789 pr_debug("fsl-diu-fb: cache lines size is %u bytes\n",
1790 d_cache_line_size);
1791
9b53a9e2
YS		 1792 of_node_put(np);
1793 coherence_data = vmalloc(coherence_data_size);
5cc2a36f
TT		 1794 if (!coherence_data) {
1795 pr_err("fsl-diu-fb: could not allocate coherence data "
1796 "(size=%zu)\n", coherence_data_size);
9b53a9e2 1797 return -ENOMEM;
5cc2a36f
TT		 1798 }
1799
9b53a9e2 1800#endif
4a85dc8b 1801
28541d0f 1802 ret = platform_driver_register(&fsl_diu_driver);
9b53a9e2 1803 if (ret) {
154152ae 1804 pr_err("fsl-diu-fb: failed to register platform driver\n");
9b53a9e2
YS		 1805#if defined(CONFIG_NOT_COHERENT_CACHE)
1806 vfree(coherence_data);
1807#endif
9b53a9e2
YS		 1808 }
1809 return ret;
1810}
1811
1812static void __exit fsl_diu_exit(void)
1813{
28541d0f 1814 platform_driver_unregister(&fsl_diu_driver);
9b53a9e2
YS		 1815#if defined(CONFIG_NOT_COHERENT_CACHE)
1816 vfree(coherence_data);
1817#endif
1818}
1819
1820module_init(fsl_diu_init);
1821module_exit(fsl_diu_exit);
1822
1823MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
1824MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
1825MODULE_LICENSE("GPL");
1826
1827module_param_named(mode, fb_mode, charp, 0);
1828MODULE_PARM_DESC(mode,
1829 "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
1830module_param_named(bpp, default_bpp, ulong, 0);
154152ae 1831MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified in 'mode'");
7653aaab
TT		 1832module_param_named(monitor, monitor_string, charp, 0);
1833MODULE_PARM_DESC(monitor, "Specify the monitor port "
1834 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
9b53a9e2 1835
Linux 6.x block layer and io_uring tree(s)