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1da177e4 LT |
1 | /* ffb.c: Creator/Elite3D frame buffer driver |
2 | * | |
3 | * Copyright (C) 2003 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz) | |
5 | * | |
6 | * Driver layout based loosely on tgafb.c, see that file for credits. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/fb.h> | |
17 | #include <linux/mm.h> | |
18 | #include <linux/timer.h> | |
19 | ||
20 | #include <asm/io.h> | |
21 | #include <asm/upa.h> | |
22 | #include <asm/oplib.h> | |
23 | #include <asm/fbio.h> | |
24 | ||
25 | #include "sbuslib.h" | |
26 | ||
27 | /* | |
28 | * Local functions. | |
29 | */ | |
30 | ||
31 | static int ffb_setcolreg(unsigned, unsigned, unsigned, unsigned, | |
32 | unsigned, struct fb_info *); | |
33 | static int ffb_blank(int, struct fb_info *); | |
34 | static void ffb_init_fix(struct fb_info *); | |
35 | ||
36 | static void ffb_imageblit(struct fb_info *, const struct fb_image *); | |
37 | static void ffb_fillrect(struct fb_info *, const struct fb_fillrect *); | |
38 | static void ffb_copyarea(struct fb_info *, const struct fb_copyarea *); | |
39 | static int ffb_sync(struct fb_info *); | |
216d526c | 40 | static int ffb_mmap(struct fb_info *, struct vm_area_struct *); |
67a6680d | 41 | static int ffb_ioctl(struct fb_info *, unsigned int, unsigned long); |
1da177e4 LT |
42 | static int ffb_pan_display(struct fb_var_screeninfo *, struct fb_info *); |
43 | ||
44 | /* | |
45 | * Frame buffer operations | |
46 | */ | |
47 | ||
48 | static struct fb_ops ffb_ops = { | |
49 | .owner = THIS_MODULE, | |
50 | .fb_setcolreg = ffb_setcolreg, | |
51 | .fb_blank = ffb_blank, | |
52 | .fb_pan_display = ffb_pan_display, | |
53 | .fb_fillrect = ffb_fillrect, | |
54 | .fb_copyarea = ffb_copyarea, | |
55 | .fb_imageblit = ffb_imageblit, | |
56 | .fb_sync = ffb_sync, | |
57 | .fb_mmap = ffb_mmap, | |
58 | .fb_ioctl = ffb_ioctl, | |
9ffb83bc CH |
59 | #ifdef CONFIG_COMPAT |
60 | .fb_compat_ioctl = sbusfb_compat_ioctl, | |
61 | #endif | |
1da177e4 LT |
62 | }; |
63 | ||
64 | /* Register layout and definitions */ | |
65 | #define FFB_SFB8R_VOFF 0x00000000 | |
66 | #define FFB_SFB8G_VOFF 0x00400000 | |
67 | #define FFB_SFB8B_VOFF 0x00800000 | |
68 | #define FFB_SFB8X_VOFF 0x00c00000 | |
69 | #define FFB_SFB32_VOFF 0x01000000 | |
70 | #define FFB_SFB64_VOFF 0x02000000 | |
71 | #define FFB_FBC_REGS_VOFF 0x04000000 | |
72 | #define FFB_BM_FBC_REGS_VOFF 0x04002000 | |
73 | #define FFB_DFB8R_VOFF 0x04004000 | |
74 | #define FFB_DFB8G_VOFF 0x04404000 | |
75 | #define FFB_DFB8B_VOFF 0x04804000 | |
76 | #define FFB_DFB8X_VOFF 0x04c04000 | |
77 | #define FFB_DFB24_VOFF 0x05004000 | |
78 | #define FFB_DFB32_VOFF 0x06004000 | |
79 | #define FFB_DFB422A_VOFF 0x07004000 /* DFB 422 mode write to A */ | |
80 | #define FFB_DFB422AD_VOFF 0x07804000 /* DFB 422 mode with line doubling */ | |
81 | #define FFB_DFB24B_VOFF 0x08004000 /* DFB 24bit mode write to B */ | |
82 | #define FFB_DFB422B_VOFF 0x09004000 /* DFB 422 mode write to B */ | |
83 | #define FFB_DFB422BD_VOFF 0x09804000 /* DFB 422 mode with line doubling */ | |
84 | #define FFB_SFB16Z_VOFF 0x0a004000 /* 16bit mode Z planes */ | |
85 | #define FFB_SFB8Z_VOFF 0x0a404000 /* 8bit mode Z planes */ | |
86 | #define FFB_SFB422_VOFF 0x0ac04000 /* SFB 422 mode write to A/B */ | |
87 | #define FFB_SFB422D_VOFF 0x0b404000 /* SFB 422 mode with line doubling */ | |
88 | #define FFB_FBC_KREGS_VOFF 0x0bc04000 | |
89 | #define FFB_DAC_VOFF 0x0bc06000 | |
90 | #define FFB_PROM_VOFF 0x0bc08000 | |
91 | #define FFB_EXP_VOFF 0x0bc18000 | |
92 | ||
93 | #define FFB_SFB8R_POFF 0x04000000UL | |
94 | #define FFB_SFB8G_POFF 0x04400000UL | |
95 | #define FFB_SFB8B_POFF 0x04800000UL | |
96 | #define FFB_SFB8X_POFF 0x04c00000UL | |
97 | #define FFB_SFB32_POFF 0x05000000UL | |
98 | #define FFB_SFB64_POFF 0x06000000UL | |
99 | #define FFB_FBC_REGS_POFF 0x00600000UL | |
100 | #define FFB_BM_FBC_REGS_POFF 0x00600000UL | |
101 | #define FFB_DFB8R_POFF 0x01000000UL | |
102 | #define FFB_DFB8G_POFF 0x01400000UL | |
103 | #define FFB_DFB8B_POFF 0x01800000UL | |
104 | #define FFB_DFB8X_POFF 0x01c00000UL | |
105 | #define FFB_DFB24_POFF 0x02000000UL | |
106 | #define FFB_DFB32_POFF 0x03000000UL | |
107 | #define FFB_FBC_KREGS_POFF 0x00610000UL | |
108 | #define FFB_DAC_POFF 0x00400000UL | |
109 | #define FFB_PROM_POFF 0x00000000UL | |
110 | #define FFB_EXP_POFF 0x00200000UL | |
111 | #define FFB_DFB422A_POFF 0x09000000UL | |
112 | #define FFB_DFB422AD_POFF 0x09800000UL | |
113 | #define FFB_DFB24B_POFF 0x0a000000UL | |
114 | #define FFB_DFB422B_POFF 0x0b000000UL | |
115 | #define FFB_DFB422BD_POFF 0x0b800000UL | |
116 | #define FFB_SFB16Z_POFF 0x0c800000UL | |
117 | #define FFB_SFB8Z_POFF 0x0c000000UL | |
118 | #define FFB_SFB422_POFF 0x0d000000UL | |
119 | #define FFB_SFB422D_POFF 0x0d800000UL | |
120 | ||
121 | /* Draw operations */ | |
122 | #define FFB_DRAWOP_DOT 0x00 | |
123 | #define FFB_DRAWOP_AADOT 0x01 | |
124 | #define FFB_DRAWOP_BRLINECAP 0x02 | |
125 | #define FFB_DRAWOP_BRLINEOPEN 0x03 | |
126 | #define FFB_DRAWOP_DDLINE 0x04 | |
127 | #define FFB_DRAWOP_AALINE 0x05 | |
128 | #define FFB_DRAWOP_TRIANGLE 0x06 | |
129 | #define FFB_DRAWOP_POLYGON 0x07 | |
130 | #define FFB_DRAWOP_RECTANGLE 0x08 | |
131 | #define FFB_DRAWOP_FASTFILL 0x09 | |
132 | #define FFB_DRAWOP_BCOPY 0x0a | |
133 | #define FFB_DRAWOP_VSCROLL 0x0b | |
134 | ||
135 | /* Pixel processor control */ | |
136 | /* Force WID */ | |
137 | #define FFB_PPC_FW_DISABLE 0x800000 | |
138 | #define FFB_PPC_FW_ENABLE 0xc00000 | |
139 | /* Auxiliary clip */ | |
140 | #define FFB_PPC_ACE_DISABLE 0x040000 | |
141 | #define FFB_PPC_ACE_AUX_SUB 0x080000 | |
142 | #define FFB_PPC_ACE_AUX_ADD 0x0c0000 | |
143 | /* Depth cue */ | |
144 | #define FFB_PPC_DCE_DISABLE 0x020000 | |
145 | #define FFB_PPC_DCE_ENABLE 0x030000 | |
146 | /* Alpha blend */ | |
147 | #define FFB_PPC_ABE_DISABLE 0x008000 | |
148 | #define FFB_PPC_ABE_ENABLE 0x00c000 | |
149 | /* View clip */ | |
150 | #define FFB_PPC_VCE_DISABLE 0x001000 | |
151 | #define FFB_PPC_VCE_2D 0x002000 | |
152 | #define FFB_PPC_VCE_3D 0x003000 | |
153 | /* Area pattern */ | |
154 | #define FFB_PPC_APE_DISABLE 0x000800 | |
155 | #define FFB_PPC_APE_ENABLE 0x000c00 | |
156 | /* Transparent background */ | |
157 | #define FFB_PPC_TBE_OPAQUE 0x000200 | |
158 | #define FFB_PPC_TBE_TRANSPARENT 0x000300 | |
159 | /* Z source */ | |
160 | #define FFB_PPC_ZS_VAR 0x000080 | |
161 | #define FFB_PPC_ZS_CONST 0x0000c0 | |
162 | /* Y source */ | |
163 | #define FFB_PPC_YS_VAR 0x000020 | |
164 | #define FFB_PPC_YS_CONST 0x000030 | |
165 | /* X source */ | |
166 | #define FFB_PPC_XS_WID 0x000004 | |
167 | #define FFB_PPC_XS_VAR 0x000008 | |
168 | #define FFB_PPC_XS_CONST 0x00000c | |
169 | /* Color (BGR) source */ | |
170 | #define FFB_PPC_CS_VAR 0x000002 | |
171 | #define FFB_PPC_CS_CONST 0x000003 | |
172 | ||
173 | #define FFB_ROP_NEW 0x83 | |
174 | #define FFB_ROP_OLD 0x85 | |
175 | #define FFB_ROP_NEW_XOR_OLD 0x86 | |
176 | ||
177 | #define FFB_UCSR_FIFO_MASK 0x00000fff | |
178 | #define FFB_UCSR_FB_BUSY 0x01000000 | |
179 | #define FFB_UCSR_RP_BUSY 0x02000000 | |
180 | #define FFB_UCSR_ALL_BUSY (FFB_UCSR_RP_BUSY|FFB_UCSR_FB_BUSY) | |
181 | #define FFB_UCSR_READ_ERR 0x40000000 | |
182 | #define FFB_UCSR_FIFO_OVFL 0x80000000 | |
183 | #define FFB_UCSR_ALL_ERRORS (FFB_UCSR_READ_ERR|FFB_UCSR_FIFO_OVFL) | |
184 | ||
185 | struct ffb_fbc { | |
186 | /* Next vertex registers */ | |
187 | u32 xxx1[3]; | |
188 | volatile u32 alpha; | |
189 | volatile u32 red; | |
190 | volatile u32 green; | |
191 | volatile u32 blue; | |
192 | volatile u32 depth; | |
193 | volatile u32 y; | |
194 | volatile u32 x; | |
195 | u32 xxx2[2]; | |
196 | volatile u32 ryf; | |
197 | volatile u32 rxf; | |
198 | u32 xxx3[2]; | |
199 | ||
200 | volatile u32 dmyf; | |
201 | volatile u32 dmxf; | |
202 | u32 xxx4[2]; | |
203 | volatile u32 ebyi; | |
204 | volatile u32 ebxi; | |
205 | u32 xxx5[2]; | |
206 | volatile u32 by; | |
207 | volatile u32 bx; | |
208 | u32 dy; | |
209 | u32 dx; | |
210 | volatile u32 bh; | |
211 | volatile u32 bw; | |
212 | u32 xxx6[2]; | |
213 | ||
214 | u32 xxx7[32]; | |
215 | ||
216 | /* Setup unit vertex state register */ | |
217 | volatile u32 suvtx; | |
218 | u32 xxx8[63]; | |
219 | ||
220 | /* Control registers */ | |
221 | volatile u32 ppc; | |
222 | volatile u32 wid; | |
223 | volatile u32 fg; | |
224 | volatile u32 bg; | |
225 | volatile u32 consty; | |
226 | volatile u32 constz; | |
227 | volatile u32 xclip; | |
228 | volatile u32 dcss; | |
229 | volatile u32 vclipmin; | |
230 | volatile u32 vclipmax; | |
231 | volatile u32 vclipzmin; | |
232 | volatile u32 vclipzmax; | |
233 | volatile u32 dcsf; | |
234 | volatile u32 dcsb; | |
235 | volatile u32 dczf; | |
236 | volatile u32 dczb; | |
237 | ||
238 | u32 xxx9; | |
239 | volatile u32 blendc; | |
240 | volatile u32 blendc1; | |
241 | volatile u32 blendc2; | |
242 | volatile u32 fbramitc; | |
243 | volatile u32 fbc; | |
244 | volatile u32 rop; | |
245 | volatile u32 cmp; | |
246 | volatile u32 matchab; | |
247 | volatile u32 matchc; | |
248 | volatile u32 magnab; | |
249 | volatile u32 magnc; | |
250 | volatile u32 fbcfg0; | |
251 | volatile u32 fbcfg1; | |
252 | volatile u32 fbcfg2; | |
253 | volatile u32 fbcfg3; | |
254 | ||
255 | u32 ppcfg; | |
256 | volatile u32 pick; | |
257 | volatile u32 fillmode; | |
258 | volatile u32 fbramwac; | |
259 | volatile u32 pmask; | |
260 | volatile u32 xpmask; | |
261 | volatile u32 ypmask; | |
262 | volatile u32 zpmask; | |
263 | volatile u32 clip0min; | |
264 | volatile u32 clip0max; | |
265 | volatile u32 clip1min; | |
266 | volatile u32 clip1max; | |
267 | volatile u32 clip2min; | |
268 | volatile u32 clip2max; | |
269 | volatile u32 clip3min; | |
270 | volatile u32 clip3max; | |
271 | ||
272 | /* New 3dRAM III support regs */ | |
273 | volatile u32 rawblend2; | |
274 | volatile u32 rawpreblend; | |
275 | volatile u32 rawstencil; | |
276 | volatile u32 rawstencilctl; | |
277 | volatile u32 threedram1; | |
278 | volatile u32 threedram2; | |
279 | volatile u32 passin; | |
280 | volatile u32 rawclrdepth; | |
281 | volatile u32 rawpmask; | |
282 | volatile u32 rawcsrc; | |
283 | volatile u32 rawmatch; | |
284 | volatile u32 rawmagn; | |
285 | volatile u32 rawropblend; | |
286 | volatile u32 rawcmp; | |
287 | volatile u32 rawwac; | |
288 | volatile u32 fbramid; | |
289 | ||
290 | volatile u32 drawop; | |
291 | u32 xxx10[2]; | |
292 | volatile u32 fontlpat; | |
293 | u32 xxx11; | |
294 | volatile u32 fontxy; | |
295 | volatile u32 fontw; | |
296 | volatile u32 fontinc; | |
297 | volatile u32 font; | |
298 | u32 xxx12[3]; | |
299 | volatile u32 blend2; | |
300 | volatile u32 preblend; | |
301 | volatile u32 stencil; | |
302 | volatile u32 stencilctl; | |
303 | ||
304 | u32 xxx13[4]; | |
305 | volatile u32 dcss1; | |
306 | volatile u32 dcss2; | |
307 | volatile u32 dcss3; | |
308 | volatile u32 widpmask; | |
309 | volatile u32 dcs2; | |
310 | volatile u32 dcs3; | |
311 | volatile u32 dcs4; | |
312 | u32 xxx14; | |
313 | volatile u32 dcd2; | |
314 | volatile u32 dcd3; | |
315 | volatile u32 dcd4; | |
316 | u32 xxx15; | |
317 | ||
318 | volatile u32 pattern[32]; | |
319 | ||
320 | u32 xxx16[256]; | |
321 | ||
322 | volatile u32 devid; | |
323 | u32 xxx17[63]; | |
324 | ||
325 | volatile u32 ucsr; | |
326 | u32 xxx18[31]; | |
327 | ||
328 | volatile u32 mer; | |
329 | }; | |
330 | ||
331 | struct ffb_dac { | |
332 | volatile u32 type; | |
333 | volatile u32 value; | |
334 | volatile u32 type2; | |
335 | volatile u32 value2; | |
336 | }; | |
337 | ||
338 | struct ffb_par { | |
339 | spinlock_t lock; | |
340 | struct ffb_fbc *fbc; | |
341 | struct ffb_dac *dac; | |
342 | ||
343 | u32 flags; | |
344 | #define FFB_FLAG_AFB 0x00000001 | |
345 | #define FFB_FLAG_BLANKED 0x00000002 | |
346 | ||
347 | u32 fg_cache __attribute__((aligned (8))); | |
348 | u32 bg_cache; | |
349 | u32 rop_cache; | |
350 | ||
351 | int fifo_cache; | |
352 | ||
353 | unsigned long physbase; | |
354 | unsigned long fbsize; | |
355 | ||
356 | char name[64]; | |
357 | int prom_node; | |
358 | int prom_parent_node; | |
359 | int dac_rev; | |
360 | int board_type; | |
1da177e4 LT |
361 | }; |
362 | ||
363 | static void FFBFifo(struct ffb_par *par, int n) | |
364 | { | |
365 | struct ffb_fbc *fbc; | |
366 | int cache = par->fifo_cache; | |
367 | ||
368 | if (cache - n < 0) { | |
369 | fbc = par->fbc; | |
370 | do { cache = (upa_readl(&fbc->ucsr) & FFB_UCSR_FIFO_MASK) - 8; | |
371 | } while (cache - n < 0); | |
372 | } | |
373 | par->fifo_cache = cache - n; | |
374 | } | |
375 | ||
376 | static void FFBWait(struct ffb_par *par) | |
377 | { | |
378 | struct ffb_fbc *fbc; | |
379 | int limit = 10000; | |
380 | ||
381 | fbc = par->fbc; | |
382 | do { | |
383 | if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_BUSY) == 0) | |
384 | break; | |
385 | if ((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) { | |
386 | upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr); | |
387 | } | |
388 | udelay(10); | |
389 | } while(--limit > 0); | |
390 | } | |
391 | ||
392 | static int ffb_sync(struct fb_info *p) | |
393 | { | |
394 | struct ffb_par *par = (struct ffb_par *) p->par; | |
395 | ||
396 | FFBWait(par); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | static __inline__ void ffb_rop(struct ffb_par *par, u32 rop) | |
401 | { | |
402 | if (par->rop_cache != rop) { | |
403 | FFBFifo(par, 1); | |
404 | upa_writel(rop, &par->fbc->rop); | |
405 | par->rop_cache = rop; | |
406 | } | |
407 | } | |
408 | ||
409 | static void ffb_switch_from_graph(struct ffb_par *par) | |
410 | { | |
411 | struct ffb_fbc *fbc = par->fbc; | |
412 | struct ffb_dac *dac = par->dac; | |
413 | unsigned long flags; | |
414 | ||
415 | spin_lock_irqsave(&par->lock, flags); | |
416 | FFBWait(par); | |
417 | par->fifo_cache = 0; | |
418 | FFBFifo(par, 7); | |
419 | upa_writel(FFB_PPC_VCE_DISABLE|FFB_PPC_TBE_OPAQUE| | |
420 | FFB_PPC_APE_DISABLE|FFB_PPC_CS_CONST, | |
421 | &fbc->ppc); | |
422 | upa_writel(0x2000707f, &fbc->fbc); | |
423 | upa_writel(par->rop_cache, &fbc->rop); | |
424 | upa_writel(0xffffffff, &fbc->pmask); | |
425 | upa_writel((1 << 16) | (0 << 0), &fbc->fontinc); | |
426 | upa_writel(par->fg_cache, &fbc->fg); | |
427 | upa_writel(par->bg_cache, &fbc->bg); | |
428 | FFBWait(par); | |
429 | ||
430 | /* Disable cursor. */ | |
431 | upa_writel(0x100, &dac->type2); | |
432 | if (par->dac_rev <= 2) | |
433 | upa_writel(0, &dac->value2); | |
434 | else | |
435 | upa_writel(3, &dac->value2); | |
436 | ||
437 | spin_unlock_irqrestore(&par->lock, flags); | |
438 | } | |
439 | ||
440 | static int ffb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
441 | { | |
442 | struct ffb_par *par = (struct ffb_par *) info->par; | |
443 | ||
444 | /* We just use this to catch switches out of | |
445 | * graphics mode. | |
446 | */ | |
447 | ffb_switch_from_graph(par); | |
448 | ||
449 | if (var->xoffset || var->yoffset || var->vmode) | |
450 | return -EINVAL; | |
451 | return 0; | |
452 | } | |
453 | ||
454 | /** | |
455 | * ffb_fillrect - REQUIRED function. Can use generic routines if | |
456 | * non acclerated hardware and packed pixel based. | |
457 | * Draws a rectangle on the screen. | |
458 | * | |
459 | * @info: frame buffer structure that represents a single frame buffer | |
460 | * @rect: structure defining the rectagle and operation. | |
461 | */ | |
462 | static void ffb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
463 | { | |
464 | struct ffb_par *par = (struct ffb_par *) info->par; | |
465 | struct ffb_fbc *fbc = par->fbc; | |
466 | unsigned long flags; | |
467 | u32 fg; | |
468 | ||
232443e2 | 469 | BUG_ON(rect->rop != ROP_COPY && rect->rop != ROP_XOR); |
1da177e4 LT |
470 | |
471 | fg = ((u32 *)info->pseudo_palette)[rect->color]; | |
472 | ||
473 | spin_lock_irqsave(&par->lock, flags); | |
474 | ||
475 | if (fg != par->fg_cache) { | |
476 | FFBFifo(par, 1); | |
477 | upa_writel(fg, &fbc->fg); | |
478 | par->fg_cache = fg; | |
479 | } | |
480 | ||
481 | ffb_rop(par, (rect->rop == ROP_COPY ? | |
482 | FFB_ROP_NEW : | |
483 | FFB_ROP_NEW_XOR_OLD)); | |
484 | ||
485 | FFBFifo(par, 5); | |
486 | upa_writel(FFB_DRAWOP_RECTANGLE, &fbc->drawop); | |
487 | upa_writel(rect->dy, &fbc->by); | |
488 | upa_writel(rect->dx, &fbc->bx); | |
489 | upa_writel(rect->height, &fbc->bh); | |
490 | upa_writel(rect->width, &fbc->bw); | |
491 | ||
492 | spin_unlock_irqrestore(&par->lock, flags); | |
493 | } | |
494 | ||
495 | /** | |
496 | * ffb_copyarea - REQUIRED function. Can use generic routines if | |
497 | * non acclerated hardware and packed pixel based. | |
498 | * Copies on area of the screen to another area. | |
499 | * | |
500 | * @info: frame buffer structure that represents a single frame buffer | |
501 | * @area: structure defining the source and destination. | |
502 | */ | |
503 | ||
504 | static void | |
505 | ffb_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |
506 | { | |
507 | struct ffb_par *par = (struct ffb_par *) info->par; | |
508 | struct ffb_fbc *fbc = par->fbc; | |
509 | unsigned long flags; | |
510 | ||
511 | if (area->dx != area->sx || | |
512 | area->dy == area->sy) { | |
513 | cfb_copyarea(info, area); | |
514 | return; | |
515 | } | |
516 | ||
517 | spin_lock_irqsave(&par->lock, flags); | |
518 | ||
519 | ffb_rop(par, FFB_ROP_OLD); | |
520 | ||
521 | FFBFifo(par, 7); | |
522 | upa_writel(FFB_DRAWOP_VSCROLL, &fbc->drawop); | |
523 | upa_writel(area->sy, &fbc->by); | |
524 | upa_writel(area->sx, &fbc->bx); | |
525 | upa_writel(area->dy, &fbc->dy); | |
526 | upa_writel(area->dx, &fbc->dx); | |
527 | upa_writel(area->height, &fbc->bh); | |
528 | upa_writel(area->width, &fbc->bw); | |
529 | ||
530 | spin_unlock_irqrestore(&par->lock, flags); | |
531 | } | |
532 | ||
533 | /** | |
534 | * ffb_imageblit - REQUIRED function. Can use generic routines if | |
535 | * non acclerated hardware and packed pixel based. | |
536 | * Copies a image from system memory to the screen. | |
537 | * | |
538 | * @info: frame buffer structure that represents a single frame buffer | |
539 | * @image: structure defining the image. | |
540 | */ | |
541 | static void ffb_imageblit(struct fb_info *info, const struct fb_image *image) | |
542 | { | |
543 | struct ffb_par *par = (struct ffb_par *) info->par; | |
544 | struct ffb_fbc *fbc = par->fbc; | |
545 | const u8 *data = image->data; | |
546 | unsigned long flags; | |
547 | u32 fg, bg, xy; | |
548 | u64 fgbg; | |
549 | int i, width, stride; | |
550 | ||
551 | if (image->depth > 1) { | |
552 | cfb_imageblit(info, image); | |
553 | return; | |
554 | } | |
555 | ||
556 | fg = ((u32 *)info->pseudo_palette)[image->fg_color]; | |
557 | bg = ((u32 *)info->pseudo_palette)[image->bg_color]; | |
558 | fgbg = ((u64) fg << 32) | (u64) bg; | |
559 | xy = (image->dy << 16) | image->dx; | |
560 | width = image->width; | |
561 | stride = ((width + 7) >> 3); | |
562 | ||
563 | spin_lock_irqsave(&par->lock, flags); | |
564 | ||
565 | if (fgbg != *(u64 *)&par->fg_cache) { | |
566 | FFBFifo(par, 2); | |
567 | upa_writeq(fgbg, &fbc->fg); | |
568 | *(u64 *)&par->fg_cache = fgbg; | |
569 | } | |
570 | ||
571 | if (width >= 32) { | |
572 | FFBFifo(par, 1); | |
573 | upa_writel(32, &fbc->fontw); | |
574 | } | |
575 | ||
576 | while (width >= 32) { | |
577 | const u8 *next_data = data + 4; | |
578 | ||
579 | FFBFifo(par, 1); | |
580 | upa_writel(xy, &fbc->fontxy); | |
581 | xy += (32 << 0); | |
582 | ||
583 | for (i = 0; i < image->height; i++) { | |
584 | u32 val = (((u32)data[0] << 24) | | |
585 | ((u32)data[1] << 16) | | |
586 | ((u32)data[2] << 8) | | |
587 | ((u32)data[3] << 0)); | |
588 | FFBFifo(par, 1); | |
589 | upa_writel(val, &fbc->font); | |
590 | ||
591 | data += stride; | |
592 | } | |
593 | ||
594 | data = next_data; | |
595 | width -= 32; | |
596 | } | |
597 | ||
598 | if (width) { | |
599 | FFBFifo(par, 2); | |
600 | upa_writel(width, &fbc->fontw); | |
601 | upa_writel(xy, &fbc->fontxy); | |
602 | ||
603 | for (i = 0; i < image->height; i++) { | |
604 | u32 val = (((u32)data[0] << 24) | | |
605 | ((u32)data[1] << 16) | | |
606 | ((u32)data[2] << 8) | | |
607 | ((u32)data[3] << 0)); | |
608 | FFBFifo(par, 1); | |
609 | upa_writel(val, &fbc->font); | |
610 | ||
611 | data += stride; | |
612 | } | |
613 | } | |
614 | ||
615 | spin_unlock_irqrestore(&par->lock, flags); | |
616 | } | |
617 | ||
618 | static void ffb_fixup_var_rgb(struct fb_var_screeninfo *var) | |
619 | { | |
620 | var->red.offset = 0; | |
621 | var->red.length = 8; | |
622 | var->green.offset = 8; | |
623 | var->green.length = 8; | |
624 | var->blue.offset = 16; | |
625 | var->blue.length = 8; | |
626 | var->transp.offset = 0; | |
627 | var->transp.length = 0; | |
628 | } | |
629 | ||
630 | /** | |
631 | * ffb_setcolreg - Optional function. Sets a color register. | |
632 | * @regno: boolean, 0 copy local, 1 get_user() function | |
633 | * @red: frame buffer colormap structure | |
634 | * @green: The green value which can be up to 16 bits wide | |
635 | * @blue: The blue value which can be up to 16 bits wide. | |
636 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
637 | * @info: frame buffer info structure | |
638 | */ | |
639 | static int ffb_setcolreg(unsigned regno, | |
640 | unsigned red, unsigned green, unsigned blue, | |
641 | unsigned transp, struct fb_info *info) | |
642 | { | |
643 | u32 value; | |
644 | ||
645 | if (regno >= 256) | |
646 | return 1; | |
647 | ||
648 | red >>= 8; | |
649 | green >>= 8; | |
650 | blue >>= 8; | |
651 | ||
652 | value = (blue << 16) | (green << 8) | red; | |
653 | ((u32 *)info->pseudo_palette)[regno] = value; | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
658 | /** | |
659 | * ffb_blank - Optional function. Blanks the display. | |
660 | * @blank_mode: the blank mode we want. | |
661 | * @info: frame buffer structure that represents a single frame buffer | |
662 | */ | |
663 | static int | |
664 | ffb_blank(int blank, struct fb_info *info) | |
665 | { | |
666 | struct ffb_par *par = (struct ffb_par *) info->par; | |
667 | struct ffb_dac *dac = par->dac; | |
668 | unsigned long flags; | |
669 | u32 tmp; | |
670 | ||
671 | spin_lock_irqsave(&par->lock, flags); | |
672 | ||
673 | FFBWait(par); | |
674 | ||
675 | switch (blank) { | |
676 | case FB_BLANK_UNBLANK: /* Unblanking */ | |
677 | upa_writel(0x6000, &dac->type); | |
678 | tmp = (upa_readl(&dac->value) | 0x1); | |
679 | upa_writel(0x6000, &dac->type); | |
680 | upa_writel(tmp, &dac->value); | |
681 | par->flags &= ~FFB_FLAG_BLANKED; | |
682 | break; | |
683 | ||
684 | case FB_BLANK_NORMAL: /* Normal blanking */ | |
685 | case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ | |
686 | case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ | |
687 | case FB_BLANK_POWERDOWN: /* Poweroff */ | |
688 | upa_writel(0x6000, &dac->type); | |
689 | tmp = (upa_readl(&dac->value) & ~0x1); | |
690 | upa_writel(0x6000, &dac->type); | |
691 | upa_writel(tmp, &dac->value); | |
692 | par->flags |= FFB_FLAG_BLANKED; | |
693 | break; | |
694 | } | |
695 | ||
696 | spin_unlock_irqrestore(&par->lock, flags); | |
697 | ||
698 | return 0; | |
699 | } | |
700 | ||
701 | static struct sbus_mmap_map ffb_mmap_map[] = { | |
702 | { | |
703 | .voff = FFB_SFB8R_VOFF, | |
704 | .poff = FFB_SFB8R_POFF, | |
705 | .size = 0x0400000 | |
706 | }, | |
707 | { | |
708 | .voff = FFB_SFB8G_VOFF, | |
709 | .poff = FFB_SFB8G_POFF, | |
710 | .size = 0x0400000 | |
711 | }, | |
712 | { | |
713 | .voff = FFB_SFB8B_VOFF, | |
714 | .poff = FFB_SFB8B_POFF, | |
715 | .size = 0x0400000 | |
716 | }, | |
717 | { | |
718 | .voff = FFB_SFB8X_VOFF, | |
719 | .poff = FFB_SFB8X_POFF, | |
720 | .size = 0x0400000 | |
721 | }, | |
722 | { | |
723 | .voff = FFB_SFB32_VOFF, | |
724 | .poff = FFB_SFB32_POFF, | |
725 | .size = 0x1000000 | |
726 | }, | |
727 | { | |
728 | .voff = FFB_SFB64_VOFF, | |
729 | .poff = FFB_SFB64_POFF, | |
730 | .size = 0x2000000 | |
731 | }, | |
732 | { | |
733 | .voff = FFB_FBC_REGS_VOFF, | |
734 | .poff = FFB_FBC_REGS_POFF, | |
735 | .size = 0x0002000 | |
736 | }, | |
737 | { | |
738 | .voff = FFB_BM_FBC_REGS_VOFF, | |
739 | .poff = FFB_BM_FBC_REGS_POFF, | |
740 | .size = 0x0002000 | |
741 | }, | |
742 | { | |
743 | .voff = FFB_DFB8R_VOFF, | |
744 | .poff = FFB_DFB8R_POFF, | |
745 | .size = 0x0400000 | |
746 | }, | |
747 | { | |
748 | .voff = FFB_DFB8G_VOFF, | |
749 | .poff = FFB_DFB8G_POFF, | |
750 | .size = 0x0400000 | |
751 | }, | |
752 | { | |
753 | .voff = FFB_DFB8B_VOFF, | |
754 | .poff = FFB_DFB8B_POFF, | |
755 | .size = 0x0400000 | |
756 | }, | |
757 | { | |
758 | .voff = FFB_DFB8X_VOFF, | |
759 | .poff = FFB_DFB8X_POFF, | |
760 | .size = 0x0400000 | |
761 | }, | |
762 | { | |
763 | .voff = FFB_DFB24_VOFF, | |
764 | .poff = FFB_DFB24_POFF, | |
765 | .size = 0x1000000 | |
766 | }, | |
767 | { | |
768 | .voff = FFB_DFB32_VOFF, | |
769 | .poff = FFB_DFB32_POFF, | |
770 | .size = 0x1000000 | |
771 | }, | |
772 | { | |
773 | .voff = FFB_FBC_KREGS_VOFF, | |
774 | .poff = FFB_FBC_KREGS_POFF, | |
775 | .size = 0x0002000 | |
776 | }, | |
777 | { | |
778 | .voff = FFB_DAC_VOFF, | |
779 | .poff = FFB_DAC_POFF, | |
780 | .size = 0x0002000 | |
781 | }, | |
782 | { | |
783 | .voff = FFB_PROM_VOFF, | |
784 | .poff = FFB_PROM_POFF, | |
785 | .size = 0x0010000 | |
786 | }, | |
787 | { | |
788 | .voff = FFB_EXP_VOFF, | |
789 | .poff = FFB_EXP_POFF, | |
790 | .size = 0x0002000 | |
791 | }, | |
792 | { | |
793 | .voff = FFB_DFB422A_VOFF, | |
794 | .poff = FFB_DFB422A_POFF, | |
795 | .size = 0x0800000 | |
796 | }, | |
797 | { | |
798 | .voff = FFB_DFB422AD_VOFF, | |
799 | .poff = FFB_DFB422AD_POFF, | |
800 | .size = 0x0800000 | |
801 | }, | |
802 | { | |
803 | .voff = FFB_DFB24B_VOFF, | |
804 | .poff = FFB_DFB24B_POFF, | |
805 | .size = 0x1000000 | |
806 | }, | |
807 | { | |
808 | .voff = FFB_DFB422B_VOFF, | |
809 | .poff = FFB_DFB422B_POFF, | |
810 | .size = 0x0800000 | |
811 | }, | |
812 | { | |
813 | .voff = FFB_DFB422BD_VOFF, | |
814 | .poff = FFB_DFB422BD_POFF, | |
815 | .size = 0x0800000 | |
816 | }, | |
817 | { | |
818 | .voff = FFB_SFB16Z_VOFF, | |
819 | .poff = FFB_SFB16Z_POFF, | |
820 | .size = 0x0800000 | |
821 | }, | |
822 | { | |
823 | .voff = FFB_SFB8Z_VOFF, | |
824 | .poff = FFB_SFB8Z_POFF, | |
825 | .size = 0x0800000 | |
826 | }, | |
827 | { | |
828 | .voff = FFB_SFB422_VOFF, | |
829 | .poff = FFB_SFB422_POFF, | |
830 | .size = 0x0800000 | |
831 | }, | |
832 | { | |
833 | .voff = FFB_SFB422D_VOFF, | |
834 | .poff = FFB_SFB422D_POFF, | |
835 | .size = 0x0800000 | |
836 | }, | |
837 | { .size = 0 } | |
838 | }; | |
839 | ||
216d526c | 840 | static int ffb_mmap(struct fb_info *info, struct vm_area_struct *vma) |
1da177e4 LT |
841 | { |
842 | struct ffb_par *par = (struct ffb_par *)info->par; | |
843 | ||
844 | return sbusfb_mmap_helper(ffb_mmap_map, | |
845 | par->physbase, par->fbsize, | |
846 | 0, vma); | |
847 | } | |
848 | ||
67a6680d | 849 | static int ffb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
850 | { |
851 | struct ffb_par *par = (struct ffb_par *) info->par; | |
852 | ||
853 | return sbusfb_ioctl_helper(cmd, arg, info, | |
854 | FBTYPE_CREATOR, 24, par->fbsize); | |
855 | } | |
856 | ||
857 | /* | |
858 | * Initialisation | |
859 | */ | |
860 | ||
861 | static void | |
862 | ffb_init_fix(struct fb_info *info) | |
863 | { | |
864 | struct ffb_par *par = (struct ffb_par *)info->par; | |
865 | const char *ffb_type_name; | |
866 | ||
867 | if (!(par->flags & FFB_FLAG_AFB)) { | |
868 | if ((par->board_type & 0x7) == 0x3) | |
869 | ffb_type_name = "Creator 3D"; | |
870 | else | |
871 | ffb_type_name = "Creator"; | |
872 | } else | |
873 | ffb_type_name = "Elite 3D"; | |
874 | ||
875 | strlcpy(info->fix.id, ffb_type_name, sizeof(info->fix.id)); | |
876 | ||
877 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
878 | info->fix.visual = FB_VISUAL_TRUECOLOR; | |
879 | ||
880 | /* Framebuffer length is the same regardless of resolution. */ | |
881 | info->fix.line_length = 8192; | |
882 | ||
883 | info->fix.accel = FB_ACCEL_SUN_CREATOR; | |
884 | } | |
885 | ||
886 | static int ffb_apply_upa_parent_ranges(int parent, | |
887 | struct linux_prom64_registers *regs) | |
888 | { | |
889 | struct linux_prom64_ranges ranges[PROMREG_MAX]; | |
890 | char name[128]; | |
891 | int len, i; | |
892 | ||
893 | prom_getproperty(parent, "name", name, sizeof(name)); | |
894 | if (strcmp(name, "upa") != 0) | |
895 | return 0; | |
896 | ||
897 | len = prom_getproperty(parent, "ranges", (void *) ranges, sizeof(ranges)); | |
898 | if (len <= 0) | |
899 | return 1; | |
900 | ||
901 | len /= sizeof(struct linux_prom64_ranges); | |
902 | for (i = 0; i < len; i++) { | |
903 | struct linux_prom64_ranges *rng = &ranges[i]; | |
904 | u64 phys_addr = regs->phys_addr; | |
905 | ||
906 | if (phys_addr >= rng->ot_child_base && | |
907 | phys_addr < (rng->ot_child_base + rng->or_size)) { | |
908 | regs->phys_addr -= rng->ot_child_base; | |
909 | regs->phys_addr += rng->ot_parent_base; | |
910 | return 0; | |
911 | } | |
912 | } | |
913 | ||
914 | return 1; | |
915 | } | |
916 | ||
917 | struct all_info { | |
918 | struct fb_info info; | |
919 | struct ffb_par par; | |
920 | u32 pseudo_palette[256]; | |
921 | struct list_head list; | |
922 | }; | |
923 | static LIST_HEAD(ffb_list); | |
924 | ||
925 | static void ffb_init_one(int node, int parent) | |
926 | { | |
927 | struct linux_prom64_registers regs[2*PROMREG_MAX]; | |
928 | struct ffb_fbc *fbc; | |
929 | struct ffb_dac *dac; | |
930 | struct all_info *all; | |
931 | ||
932 | if (prom_getproperty(node, "reg", (void *) regs, sizeof(regs)) <= 0) { | |
933 | printk("ffb: Cannot get reg device node property.\n"); | |
934 | return; | |
935 | } | |
936 | ||
937 | if (ffb_apply_upa_parent_ranges(parent, ®s[0])) { | |
938 | printk("ffb: Cannot apply parent ranges to regs.\n"); | |
939 | return; | |
940 | } | |
941 | ||
942 | all = kmalloc(sizeof(*all), GFP_KERNEL); | |
943 | if (!all) { | |
944 | printk(KERN_ERR "ffb: Cannot allocate memory.\n"); | |
945 | return; | |
946 | } | |
947 | memset(all, 0, sizeof(*all)); | |
948 | ||
949 | INIT_LIST_HEAD(&all->list); | |
950 | ||
951 | spin_lock_init(&all->par.lock); | |
952 | all->par.fbc = (struct ffb_fbc *)(regs[0].phys_addr + FFB_FBC_REGS_POFF); | |
953 | all->par.dac = (struct ffb_dac *)(regs[0].phys_addr + FFB_DAC_POFF); | |
954 | all->par.rop_cache = FFB_ROP_NEW; | |
955 | all->par.physbase = regs[0].phys_addr; | |
956 | all->par.prom_node = node; | |
957 | all->par.prom_parent_node = parent; | |
958 | ||
959 | /* Don't mention copyarea, so SCROLL_REDRAW is always | |
960 | * used. It is the fastest on this chip. | |
961 | */ | |
962 | all->info.flags = (FBINFO_DEFAULT | | |
963 | /* FBINFO_HWACCEL_COPYAREA | */ | |
964 | FBINFO_HWACCEL_FILLRECT | | |
965 | FBINFO_HWACCEL_IMAGEBLIT); | |
966 | all->info.fbops = &ffb_ops; | |
967 | all->info.screen_base = (char *) all->par.physbase + FFB_DFB24_POFF; | |
968 | all->info.par = &all->par; | |
969 | all->info.pseudo_palette = all->pseudo_palette; | |
970 | ||
971 | sbusfb_fill_var(&all->info.var, all->par.prom_node, 32); | |
972 | all->par.fbsize = PAGE_ALIGN(all->info.var.xres * | |
973 | all->info.var.yres * | |
974 | 4); | |
975 | ffb_fixup_var_rgb(&all->info.var); | |
976 | ||
977 | all->info.var.accel_flags = FB_ACCELF_TEXT; | |
978 | ||
979 | prom_getstring(node, "name", all->par.name, sizeof(all->par.name)); | |
980 | if (!strcmp(all->par.name, "SUNW,afb")) | |
981 | all->par.flags |= FFB_FLAG_AFB; | |
982 | ||
983 | all->par.board_type = prom_getintdefault(node, "board_type", 0); | |
984 | ||
985 | fbc = all->par.fbc; | |
986 | if((upa_readl(&fbc->ucsr) & FFB_UCSR_ALL_ERRORS) != 0) | |
987 | upa_writel(FFB_UCSR_ALL_ERRORS, &fbc->ucsr); | |
988 | ||
989 | ffb_switch_from_graph(&all->par); | |
990 | ||
991 | dac = all->par.dac; | |
992 | upa_writel(0x8000, &dac->type); | |
993 | all->par.dac_rev = upa_readl(&dac->value) >> 0x1c; | |
994 | ||
995 | /* Elite3D has different DAC revision numbering, and no DAC revisions | |
996 | * have the reversed meaning of cursor enable. | |
997 | */ | |
998 | if (all->par.flags & FFB_FLAG_AFB) | |
999 | all->par.dac_rev = 10; | |
1000 | ||
1001 | /* Unblank it just to be sure. When there are multiple | |
1002 | * FFB/AFB cards in the system, or it is not the OBP | |
1003 | * chosen console, it will have video outputs off in | |
1004 | * the DAC. | |
1005 | */ | |
1006 | ffb_blank(0, &all->info); | |
1007 | ||
1008 | if (fb_alloc_cmap(&all->info.cmap, 256, 0)) { | |
1009 | printk(KERN_ERR "ffb: Could not allocate color map.\n"); | |
1010 | kfree(all); | |
1011 | return; | |
1012 | } | |
1013 | ||
1014 | ffb_init_fix(&all->info); | |
1015 | ||
1016 | if (register_framebuffer(&all->info) < 0) { | |
1017 | printk(KERN_ERR "ffb: Could not register framebuffer.\n"); | |
1018 | fb_dealloc_cmap(&all->info.cmap); | |
1019 | kfree(all); | |
1020 | return; | |
1021 | } | |
1022 | ||
1023 | list_add(&all->list, &ffb_list); | |
1024 | ||
1025 | printk("ffb: %s at %016lx type %d DAC %d\n", | |
1026 | ((all->par.flags & FFB_FLAG_AFB) ? "AFB" : "FFB"), | |
1027 | regs[0].phys_addr, all->par.board_type, all->par.dac_rev); | |
1028 | } | |
1029 | ||
1030 | static void ffb_scan_siblings(int root) | |
1031 | { | |
1032 | int node, child; | |
1033 | ||
1034 | child = prom_getchild(root); | |
1035 | for (node = prom_searchsiblings(child, "SUNW,ffb"); node; | |
1036 | node = prom_searchsiblings(prom_getsibling(node), "SUNW,ffb")) | |
1037 | ffb_init_one(node, root); | |
1038 | for (node = prom_searchsiblings(child, "SUNW,afb"); node; | |
1039 | node = prom_searchsiblings(prom_getsibling(node), "SUNW,afb")) | |
1040 | ffb_init_one(node, root); | |
1041 | } | |
1042 | ||
1043 | int __init ffb_init(void) | |
1044 | { | |
1045 | int root; | |
1046 | ||
1047 | if (fb_get_options("ffb", NULL)) | |
1048 | return -ENODEV; | |
1049 | ||
1050 | ffb_scan_siblings(prom_root_node); | |
1051 | ||
1052 | root = prom_getchild(prom_root_node); | |
1053 | for (root = prom_searchsiblings(root, "upa"); root; | |
1054 | root = prom_searchsiblings(prom_getsibling(root), "upa")) | |
1055 | ffb_scan_siblings(root); | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | void __exit ffb_exit(void) | |
1061 | { | |
1062 | struct list_head *pos, *tmp; | |
1063 | ||
1064 | list_for_each_safe(pos, tmp, &ffb_list) { | |
1065 | struct all_info *all = list_entry(pos, typeof(*all), list); | |
1066 | ||
1067 | unregister_framebuffer(&all->info); | |
1068 | fb_dealloc_cmap(&all->info.cmap); | |
1069 | kfree(all); | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | int __init | |
1074 | ffb_setup(char *arg) | |
1075 | { | |
1076 | /* No cmdline options yet... */ | |
1077 | return 0; | |
1078 | } | |
1079 | ||
1080 | module_init(ffb_init); | |
1081 | ||
1082 | #ifdef MODULE | |
1083 | module_exit(ffb_exit); | |
1084 | #endif | |
1085 | ||
1086 | MODULE_DESCRIPTION("framebuffer driver for Creator/Elite3D chipsets"); | |
1087 | MODULE_AUTHOR("David S. Miller <davem@redhat.com>"); | |
1088 | MODULE_LICENSE("GPL"); |