Commit | Line | Data |
---|---|---|
147394c8 | 1 | /* |
dac4ccfb | 2 | * Xilinx TFT frame buffer driver |
147394c8 AK |
3 | * |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
31e8d460 GL |
7 | * 2002-2007 (c) MontaVista Software, Inc. |
8 | * 2007 (c) Secret Lab Technologies, Ltd. | |
dac4ccfb | 9 | * 2009 (c) Xilinx Inc. |
31e8d460 GL |
10 | * |
11 | * This file is licensed under the terms of the GNU General Public License | |
12 | * version 2. This program is licensed "as is" without any warranty of any | |
13 | * kind, whether express or implied. | |
147394c8 AK |
14 | */ |
15 | ||
16 | /* | |
17 | * This driver was based on au1100fb.c by MontaVista rewritten for 2.6 | |
18 | * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn | |
19 | * was based on skeletonfb.c, Skeleton for a frame buffer device by | |
20 | * Geert Uytterhoeven. | |
21 | */ | |
22 | ||
3cb3ec2c | 23 | #include <linux/device.h> |
147394c8 AK |
24 | #include <linux/module.h> |
25 | #include <linux/kernel.h> | |
147394c8 AK |
26 | #include <linux/errno.h> |
27 | #include <linux/string.h> | |
28 | #include <linux/mm.h> | |
29 | #include <linux/fb.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/dma-mapping.h> | |
31e8d460 GL |
32 | #include <linux/of_device.h> |
33 | #include <linux/of_platform.h> | |
a1dfe9c7 | 34 | #include <linux/of_address.h> |
dac4ccfb | 35 | #include <linux/io.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
a1dfe9c7 MS |
37 | |
38 | #ifdef CONFIG_PPC_DCR | |
dac4ccfb | 39 | #include <asm/dcr.h> |
a1dfe9c7 | 40 | #endif |
147394c8 AK |
41 | |
42 | #define DRIVER_NAME "xilinxfb" | |
dac4ccfb | 43 | |
147394c8 AK |
44 | |
45 | /* | |
5130af35 | 46 | * Xilinx calls it "TFT LCD Controller" though it can also be used for |
dac4ccfb JL |
47 | * the VGA port on the Xilinx ML40x board. This is a hardware display |
48 | * controller for a 640x480 resolution TFT or VGA screen. | |
147394c8 AK |
49 | * |
50 | * The interface to the framebuffer is nice and simple. There are two | |
51 | * control registers. The first tells the LCD interface where in memory | |
52 | * the frame buffer is (only the 11 most significant bits are used, so | |
53 | * don't start thinking about scrolling). The second allows the LCD to | |
54 | * be turned on or off as well as rotated 180 degrees. | |
dac4ccfb | 55 | * |
5130af35 | 56 | * In case of direct BUS access the second control register will be at |
dac4ccfb JL |
57 | * an offset of 4 as compared to the DCR access where the offset is 1 |
58 | * i.e. REG_CTRL. So this is taken care in the function | |
ec05e7a8 | 59 | * xilinx_fb_out32 where it left shifts the offset 2 times in case of |
5130af35 | 60 | * direct BUS access. |
147394c8 AK |
61 | */ |
62 | #define NUM_REGS 2 | |
63 | #define REG_FB_ADDR 0 | |
64 | #define REG_CTRL 1 | |
65 | #define REG_CTRL_ENABLE 0x0001 | |
66 | #define REG_CTRL_ROTATE 0x0002 | |
67 | ||
68 | /* | |
69 | * The hardware only handles a single mode: 640x480 24 bit true | |
70 | * color. Each pixel gets a word (32 bits) of memory. Within each word, | |
71 | * the 8 most significant bits are ignored, the next 8 bits are the red | |
72 | * level, the next 8 bits are the green level and the 8 least | |
73 | * significant bits are the blue level. Each row of the LCD uses 1024 | |
74 | * words, but only the first 640 pixels are displayed with the other 384 | |
75 | * words being ignored. There are 480 rows. | |
76 | */ | |
77 | #define BYTES_PER_PIXEL 4 | |
78 | #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8) | |
147394c8 AK |
79 | |
80 | #define RED_SHIFT 16 | |
81 | #define GREEN_SHIFT 8 | |
82 | #define BLUE_SHIFT 0 | |
83 | ||
84 | #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */ | |
85 | ||
c4a41bcc MS |
86 | /* ML300/403 reference design framebuffer driver platform data struct */ |
87 | struct xilinxfb_platform_data { | |
88 | u32 rotate_screen; /* Flag to rotate display 180 degrees */ | |
89 | u32 screen_height_mm; /* Physical dimensions of screen in mm */ | |
90 | u32 screen_width_mm; | |
91 | u32 xres, yres; /* resolution of screen in pixels */ | |
92 | u32 xvirt, yvirt; /* resolution of memory buffer */ | |
93 | ||
94 | /* Physical address of framebuffer memory; If non-zero, driver | |
95 | * will use provided memory address instead of allocating one from | |
96 | * the consistent pool. */ | |
97 | u32 fb_phys; | |
98 | }; | |
99 | ||
01ba1e9d GL |
100 | /* |
101 | * Default xilinxfb configuration | |
102 | */ | |
103 | static struct xilinxfb_platform_data xilinx_fb_default_pdata = { | |
b4d6a726 GL |
104 | .xres = 640, |
105 | .yres = 480, | |
106 | .xvirt = 1024, | |
86a2249d | 107 | .yvirt = 480, |
01ba1e9d GL |
108 | }; |
109 | ||
147394c8 AK |
110 | /* |
111 | * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures | |
112 | */ | |
3f5b85d1 | 113 | static struct fb_fix_screeninfo xilinx_fb_fix = { |
147394c8 AK |
114 | .id = "Xilinx", |
115 | .type = FB_TYPE_PACKED_PIXELS, | |
116 | .visual = FB_VISUAL_TRUECOLOR, | |
147394c8 AK |
117 | .accel = FB_ACCEL_NONE |
118 | }; | |
119 | ||
3f5b85d1 | 120 | static struct fb_var_screeninfo xilinx_fb_var = { |
147394c8 AK |
121 | .bits_per_pixel = BITS_PER_PIXEL, |
122 | ||
123 | .red = { RED_SHIFT, 8, 0 }, | |
124 | .green = { GREEN_SHIFT, 8, 0 }, | |
125 | .blue = { BLUE_SHIFT, 8, 0 }, | |
126 | .transp = { 0, 0, 0 }, | |
127 | ||
128 | .activate = FB_ACTIVATE_NOW | |
129 | }; | |
130 | ||
dac4ccfb | 131 | |
5130af35 | 132 | #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */ |
2121c339 | 133 | #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */ |
dac4ccfb | 134 | |
147394c8 AK |
135 | struct xilinxfb_drvdata { |
136 | ||
137 | struct fb_info info; /* FB driver info record */ | |
138 | ||
dac4ccfb JL |
139 | phys_addr_t regs_phys; /* phys. address of the control |
140 | registers */ | |
141 | void __iomem *regs; /* virt. address of the control | |
142 | registers */ | |
a1dfe9c7 | 143 | #ifdef CONFIG_PPC_DCR |
dac4ccfb | 144 | dcr_host_t dcr_host; |
dac4ccfb | 145 | unsigned int dcr_len; |
a1dfe9c7 | 146 | #endif |
b9a22794 | 147 | void *fb_virt; /* virt. address of the frame buffer */ |
147394c8 | 148 | dma_addr_t fb_phys; /* phys. address of the frame buffer */ |
287e5d6f | 149 | int fb_alloced; /* Flag, was the fb memory alloced? */ |
147394c8 | 150 | |
dac4ccfb JL |
151 | u8 flags; /* features of the driver */ |
152 | ||
147394c8 AK |
153 | u32 reg_ctrl_default; |
154 | ||
155 | u32 pseudo_palette[PALETTE_ENTRIES_NO]; | |
156 | /* Fake palette of 16 colors */ | |
157 | }; | |
158 | ||
159 | #define to_xilinxfb_drvdata(_info) \ | |
160 | container_of(_info, struct xilinxfb_drvdata, info) | |
161 | ||
162 | /* | |
5130af35 | 163 | * The XPS TFT Controller can be accessed through BUS or DCR interface. |
dac4ccfb JL |
164 | * To perform the read/write on the registers we need to check on |
165 | * which bus its connected and call the appropriate write API. | |
147394c8 | 166 | */ |
ec05e7a8 | 167 | static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset, |
dac4ccfb JL |
168 | u32 val) |
169 | { | |
2121c339 MS |
170 | if (drvdata->flags & BUS_ACCESS_FLAG) { |
171 | if (drvdata->flags & LITTLE_ENDIAN_ACCESS) | |
172 | iowrite32(val, drvdata->regs + (offset << 2)); | |
173 | else | |
174 | iowrite32be(val, drvdata->regs + (offset << 2)); | |
175 | } | |
a1dfe9c7 | 176 | #ifdef CONFIG_PPC_DCR |
dac4ccfb JL |
177 | else |
178 | dcr_write(drvdata->dcr_host, offset, val); | |
a1dfe9c7 | 179 | #endif |
dac4ccfb | 180 | } |
147394c8 | 181 | |
2121c339 MS |
182 | static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset) |
183 | { | |
184 | if (drvdata->flags & BUS_ACCESS_FLAG) { | |
185 | if (drvdata->flags & LITTLE_ENDIAN_ACCESS) | |
186 | return ioread32(drvdata->regs + (offset << 2)); | |
187 | else | |
188 | return ioread32be(drvdata->regs + (offset << 2)); | |
189 | } | |
190 | #ifdef CONFIG_PPC_DCR | |
191 | else | |
192 | return dcr_read(drvdata->dcr_host, offset); | |
193 | #endif | |
194 | return 0; | |
195 | } | |
196 | ||
147394c8 AK |
197 | static int |
198 | xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, | |
199 | unsigned transp, struct fb_info *fbi) | |
200 | { | |
201 | u32 *palette = fbi->pseudo_palette; | |
202 | ||
203 | if (regno >= PALETTE_ENTRIES_NO) | |
204 | return -EINVAL; | |
205 | ||
206 | if (fbi->var.grayscale) { | |
207 | /* Convert color to grayscale. | |
208 | * grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
209 | red = green = blue = | |
210 | (red * 77 + green * 151 + blue * 28 + 127) >> 8; | |
211 | } | |
212 | ||
213 | /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */ | |
214 | ||
215 | /* We only handle 8 bits of each color. */ | |
216 | red >>= 8; | |
217 | green >>= 8; | |
218 | blue >>= 8; | |
219 | palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) | | |
220 | (blue << BLUE_SHIFT); | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | static int | |
226 | xilinx_fb_blank(int blank_mode, struct fb_info *fbi) | |
227 | { | |
228 | struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi); | |
229 | ||
230 | switch (blank_mode) { | |
231 | case FB_BLANK_UNBLANK: | |
232 | /* turn on panel */ | |
ec05e7a8 | 233 | xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default); |
147394c8 AK |
234 | break; |
235 | ||
236 | case FB_BLANK_NORMAL: | |
237 | case FB_BLANK_VSYNC_SUSPEND: | |
238 | case FB_BLANK_HSYNC_SUSPEND: | |
239 | case FB_BLANK_POWERDOWN: | |
240 | /* turn off panel */ | |
ec05e7a8 | 241 | xilinx_fb_out32(drvdata, REG_CTRL, 0); |
147394c8 AK |
242 | default: |
243 | break; | |
244 | ||
245 | } | |
246 | return 0; /* success */ | |
247 | } | |
248 | ||
249 | static struct fb_ops xilinxfb_ops = | |
250 | { | |
251 | .owner = THIS_MODULE, | |
252 | .fb_setcolreg = xilinx_fb_setcolreg, | |
253 | .fb_blank = xilinx_fb_blank, | |
254 | .fb_fillrect = cfb_fillrect, | |
255 | .fb_copyarea = cfb_copyarea, | |
256 | .fb_imageblit = cfb_imageblit, | |
257 | }; | |
258 | ||
26477622 GL |
259 | /* --------------------------------------------------------------------- |
260 | * Bus independent setup/teardown | |
261 | */ | |
147394c8 | 262 | |
a8f045aa | 263 | static int xilinxfb_assign(struct platform_device *pdev, |
dac4ccfb | 264 | struct xilinxfb_drvdata *drvdata, |
01ba1e9d | 265 | struct xilinxfb_platform_data *pdata) |
147394c8 | 266 | { |
26477622 | 267 | int rc; |
a8f045aa | 268 | struct device *dev = &pdev->dev; |
b4d6a726 | 269 | int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL; |
147394c8 | 270 | |
5130af35 | 271 | if (drvdata->flags & BUS_ACCESS_FLAG) { |
a8f045aa | 272 | struct resource *res; |
dac4ccfb | 273 | |
a8f045aa | 274 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b1a9329c | 275 | drvdata->regs = devm_ioremap_resource(&pdev->dev, res); |
718b90ac MS |
276 | if (IS_ERR(drvdata->regs)) |
277 | return PTR_ERR(drvdata->regs); | |
278 | ||
b1a9329c | 279 | drvdata->regs_phys = res->start; |
147394c8 | 280 | } |
147394c8 AK |
281 | |
282 | /* Allocate the framebuffer memory */ | |
287e5d6f GL |
283 | if (pdata->fb_phys) { |
284 | drvdata->fb_phys = pdata->fb_phys; | |
285 | drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize); | |
286 | } else { | |
287 | drvdata->fb_alloced = 1; | |
288 | drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize), | |
289 | &drvdata->fb_phys, GFP_KERNEL); | |
290 | } | |
291 | ||
147394c8 | 292 | if (!drvdata->fb_virt) { |
3cb3ec2c | 293 | dev_err(dev, "Could not allocate frame buffer memory\n"); |
718b90ac | 294 | return -ENOMEM; |
147394c8 AK |
295 | } |
296 | ||
297 | /* Clear (turn to black) the framebuffer */ | |
b4d6a726 | 298 | memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize); |
147394c8 AK |
299 | |
300 | /* Tell the hardware where the frame buffer is */ | |
ec05e7a8 | 301 | xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); |
2121c339 MS |
302 | rc = xilinx_fb_in32(drvdata, REG_FB_ADDR); |
303 | /* Endianess detection */ | |
304 | if (rc != drvdata->fb_phys) { | |
305 | drvdata->flags |= LITTLE_ENDIAN_ACCESS; | |
306 | xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys); | |
307 | } | |
147394c8 AK |
308 | |
309 | /* Turn on the display */ | |
f53161d1 | 310 | drvdata->reg_ctrl_default = REG_CTRL_ENABLE; |
01ba1e9d | 311 | if (pdata->rotate_screen) |
f53161d1 | 312 | drvdata->reg_ctrl_default |= REG_CTRL_ROTATE; |
ec05e7a8 | 313 | xilinx_fb_out32(drvdata, REG_CTRL, |
dac4ccfb | 314 | drvdata->reg_ctrl_default); |
147394c8 AK |
315 | |
316 | /* Fill struct fb_info */ | |
317 | drvdata->info.device = dev; | |
b9a22794 | 318 | drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt; |
147394c8 AK |
319 | drvdata->info.fbops = &xilinxfb_ops; |
320 | drvdata->info.fix = xilinx_fb_fix; | |
321 | drvdata->info.fix.smem_start = drvdata->fb_phys; | |
b4d6a726 GL |
322 | drvdata->info.fix.smem_len = fbsize; |
323 | drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL; | |
324 | ||
147394c8 | 325 | drvdata->info.pseudo_palette = drvdata->pseudo_palette; |
26477622 GL |
326 | drvdata->info.flags = FBINFO_DEFAULT; |
327 | drvdata->info.var = xilinx_fb_var; | |
b4d6a726 GL |
328 | drvdata->info.var.height = pdata->screen_height_mm; |
329 | drvdata->info.var.width = pdata->screen_width_mm; | |
330 | drvdata->info.var.xres = pdata->xres; | |
331 | drvdata->info.var.yres = pdata->yres; | |
332 | drvdata->info.var.xres_virtual = pdata->xvirt; | |
333 | drvdata->info.var.yres_virtual = pdata->yvirt; | |
147394c8 | 334 | |
26477622 GL |
335 | /* Allocate a colour map */ |
336 | rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0); | |
337 | if (rc) { | |
3cb3ec2c | 338 | dev_err(dev, "Fail to allocate colormap (%d entries)\n", |
147394c8 | 339 | PALETTE_ENTRIES_NO); |
3fb99ce4 | 340 | goto err_cmap; |
147394c8 AK |
341 | } |
342 | ||
147394c8 | 343 | /* Register new frame buffer */ |
26477622 GL |
344 | rc = register_framebuffer(&drvdata->info); |
345 | if (rc) { | |
3cb3ec2c | 346 | dev_err(dev, "Could not register frame buffer\n"); |
3fb99ce4 | 347 | goto err_regfb; |
147394c8 AK |
348 | } |
349 | ||
5130af35 | 350 | if (drvdata->flags & BUS_ACCESS_FLAG) { |
dac4ccfb | 351 | /* Put a banner in the log (for DEBUG) */ |
bf265c84 MS |
352 | dev_dbg(dev, "regs: phys=%pa, virt=%p\n", |
353 | &drvdata->regs_phys, drvdata->regs); | |
dac4ccfb | 354 | } |
258de4ba | 355 | /* Put a banner in the log (for DEBUG) */ |
aa296a89 GL |
356 | dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n", |
357 | (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize); | |
b4d6a726 | 358 | |
147394c8 AK |
359 | return 0; /* success */ |
360 | ||
3fb99ce4 | 361 | err_regfb: |
147394c8 AK |
362 | fb_dealloc_cmap(&drvdata->info.cmap); |
363 | ||
3fb99ce4 | 364 | err_cmap: |
287e5d6f GL |
365 | if (drvdata->fb_alloced) |
366 | dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt, | |
367 | drvdata->fb_phys); | |
dac4ccfb JL |
368 | else |
369 | iounmap(drvdata->fb_virt); | |
370 | ||
147394c8 | 371 | /* Turn off the display */ |
ec05e7a8 | 372 | xilinx_fb_out32(drvdata, REG_CTRL, 0); |
147394c8 | 373 | |
26477622 | 374 | return rc; |
147394c8 AK |
375 | } |
376 | ||
26477622 | 377 | static int xilinxfb_release(struct device *dev) |
147394c8 | 378 | { |
26477622 | 379 | struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev); |
147394c8 AK |
380 | |
381 | #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO) | |
382 | xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info); | |
383 | #endif | |
384 | ||
385 | unregister_framebuffer(&drvdata->info); | |
386 | ||
387 | fb_dealloc_cmap(&drvdata->info.cmap); | |
388 | ||
287e5d6f GL |
389 | if (drvdata->fb_alloced) |
390 | dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len), | |
391 | drvdata->fb_virt, drvdata->fb_phys); | |
dac4ccfb JL |
392 | else |
393 | iounmap(drvdata->fb_virt); | |
147394c8 AK |
394 | |
395 | /* Turn off the display */ | |
ec05e7a8 | 396 | xilinx_fb_out32(drvdata, REG_CTRL, 0); |
147394c8 | 397 | |
a1dfe9c7 | 398 | #ifdef CONFIG_PPC_DCR |
718b90ac MS |
399 | /* Release the resources, as allocated based on interface */ |
400 | if (!(drvdata->flags & BUS_ACCESS_FLAG)) | |
dac4ccfb | 401 | dcr_unmap(drvdata->dcr_host, drvdata->dcr_len); |
a1dfe9c7 | 402 | #endif |
147394c8 | 403 | |
147394c8 AK |
404 | return 0; |
405 | } | |
406 | ||
31e8d460 GL |
407 | /* --------------------------------------------------------------------- |
408 | * OF bus binding | |
409 | */ | |
410 | ||
353846fb | 411 | static int xilinxfb_of_probe(struct platform_device *pdev) |
31e8d460 | 412 | { |
31e8d460 | 413 | const u32 *prop; |
0f5e17c5 | 414 | u32 tft_access = 0; |
01ba1e9d | 415 | struct xilinxfb_platform_data pdata; |
a8f045aa | 416 | int size; |
dac4ccfb | 417 | struct xilinxfb_drvdata *drvdata; |
31e8d460 | 418 | |
01ba1e9d GL |
419 | /* Copy with the default pdata (not a ptr reference!) */ |
420 | pdata = xilinx_fb_default_pdata; | |
421 | ||
aa296a89 | 422 | /* Allocate the driver data region */ |
5c128df7 MS |
423 | drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); |
424 | if (!drvdata) | |
aa296a89 | 425 | return -ENOMEM; |
aa296a89 | 426 | |
dac4ccfb | 427 | /* |
5130af35 | 428 | * To check whether the core is connected directly to DCR or BUS |
dac4ccfb JL |
429 | * interface and initialize the tft_access accordingly. |
430 | */ | |
353846fb | 431 | of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if", |
0f5e17c5 | 432 | &tft_access); |
dac4ccfb JL |
433 | |
434 | /* | |
5130af35 | 435 | * Fill the resource structure if its direct BUS interface |
dac4ccfb JL |
436 | * otherwise fill the dcr_host structure. |
437 | */ | |
438 | if (tft_access) { | |
5130af35 | 439 | drvdata->flags |= BUS_ACCESS_FLAG; |
a1dfe9c7 MS |
440 | } |
441 | #ifdef CONFIG_PPC_DCR | |
442 | else { | |
443 | int start; | |
33826d01 SR |
444 | start = dcr_resource_start(pdev->dev.of_node, 0); |
445 | drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0); | |
446 | drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len); | |
aa296a89 | 447 | if (!DCR_MAP_OK(drvdata->dcr_host)) { |
33826d01 | 448 | dev_err(&pdev->dev, "invalid DCR address\n"); |
a8f045aa | 449 | return -ENODEV; |
dac4ccfb | 450 | } |
31e8d460 | 451 | } |
a1dfe9c7 | 452 | #endif |
31e8d460 | 453 | |
353846fb | 454 | prop = of_get_property(pdev->dev.of_node, "phys-size", &size); |
31e8d460 | 455 | if ((prop) && (size >= sizeof(u32)*2)) { |
01ba1e9d GL |
456 | pdata.screen_width_mm = prop[0]; |
457 | pdata.screen_height_mm = prop[1]; | |
31e8d460 GL |
458 | } |
459 | ||
353846fb | 460 | prop = of_get_property(pdev->dev.of_node, "resolution", &size); |
b4d6a726 GL |
461 | if ((prop) && (size >= sizeof(u32)*2)) { |
462 | pdata.xres = prop[0]; | |
463 | pdata.yres = prop[1]; | |
464 | } | |
465 | ||
353846fb | 466 | prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size); |
b4d6a726 GL |
467 | if ((prop) && (size >= sizeof(u32)*2)) { |
468 | pdata.xvirt = prop[0]; | |
469 | pdata.yvirt = prop[1]; | |
470 | } | |
471 | ||
353846fb | 472 | if (of_find_property(pdev->dev.of_node, "rotate-display", NULL)) |
01ba1e9d | 473 | pdata.rotate_screen = 1; |
31e8d460 | 474 | |
353846fb MS |
475 | dev_set_drvdata(&pdev->dev, drvdata); |
476 | return xilinxfb_assign(pdev, drvdata, &pdata); | |
31e8d460 GL |
477 | } |
478 | ||
48c68c4f | 479 | static int xilinxfb_of_remove(struct platform_device *op) |
31e8d460 GL |
480 | { |
481 | return xilinxfb_release(&op->dev); | |
482 | } | |
483 | ||
484 | /* Match table for of_platform binding */ | |
48c68c4f | 485 | static struct of_device_id xilinxfb_of_match[] = { |
dac4ccfb | 486 | { .compatible = "xlnx,xps-tft-1.00.a", }, |
652078ba AA |
487 | { .compatible = "xlnx,xps-tft-2.00.a", }, |
488 | { .compatible = "xlnx,xps-tft-2.01.a", }, | |
0e349b0e | 489 | { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", }, |
dac4ccfb | 490 | { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", }, |
31e8d460 GL |
491 | {}, |
492 | }; | |
493 | MODULE_DEVICE_TABLE(of, xilinxfb_of_match); | |
494 | ||
28541d0f | 495 | static struct platform_driver xilinxfb_of_driver = { |
31e8d460 | 496 | .probe = xilinxfb_of_probe, |
48c68c4f | 497 | .remove = xilinxfb_of_remove, |
31e8d460 GL |
498 | .driver = { |
499 | .name = DRIVER_NAME, | |
4018294b | 500 | .of_match_table = xilinxfb_of_match, |
31e8d460 GL |
501 | }, |
502 | }; | |
503 | ||
4277f2c4 | 504 | module_platform_driver(xilinxfb_of_driver); |
147394c8 AK |
505 | |
506 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); | |
dac4ccfb | 507 | MODULE_DESCRIPTION("Xilinx TFT frame buffer driver"); |
147394c8 | 508 | MODULE_LICENSE("GPL"); |