Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
49b1f4b4 | 2 | * Frame buffer driver for Trident TGUI, Blade and Image series |
1da177e4 | 3 | * |
245a2c2c | 4 | * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro> |
ddb53d48 | 5 | * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl> |
1da177e4 LT |
6 | * |
7 | * CREDITS:(in order of appearance) | |
245a2c2c KH |
8 | * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video |
9 | * Special thanks ;) to Mattia Crivellini <tia@mclink.it> | |
10 | * much inspired by the XFree86 4.x Trident driver sources | |
11 | * by Alan Hourihane the FreeVGA project | |
12 | * Francesco Salvestrini <salvestrini@users.sf.net> XP support, | |
13 | * code, suggestions | |
1da177e4 | 14 | * TODO: |
245a2c2c | 15 | * timing value tweaking so it looks good on every monitor in every mode |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | #include <linux/module.h> |
19 | #include <linux/fb.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/pci.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
1da177e4 LT |
23 | |
24 | #include <linux/delay.h> | |
10172ed6 | 25 | #include <video/vga.h> |
1da177e4 LT |
26 | #include <video/trident.h> |
27 | ||
6a5e3bd0 OZ |
28 | #include <linux/i2c.h> |
29 | #include <linux/i2c-algo-bit.h> | |
30 | ||
1da177e4 | 31 | struct tridentfb_par { |
245a2c2c | 32 | void __iomem *io_virt; /* iospace virtual memory address */ |
ea8ee55c | 33 | u32 pseudo_pal[16]; |
122e8ad3 | 34 | int chip_id; |
6eed8e1e | 35 | int flatpanel; |
d9cad04b KH |
36 | void (*init_accel) (struct tridentfb_par *, int, int); |
37 | void (*wait_engine) (struct tridentfb_par *); | |
38 | void (*fill_rect) | |
39 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
40 | void (*copy_rect) | |
41 | (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32); | |
0292be4a KH |
42 | void (*image_blit) |
43 | (struct tridentfb_par *par, const char*, | |
44 | u32, u32, u32, u32, u32, u32); | |
5cf13845 | 45 | unsigned char eng_oper; /* engine operation... */ |
6a5e3bd0 OZ |
46 | bool ddc_registered; |
47 | struct i2c_adapter ddc_adapter; | |
48 | struct i2c_algo_bit_data ddc_algo; | |
1da177e4 LT |
49 | }; |
50 | ||
1da177e4 | 51 | static struct fb_fix_screeninfo tridentfb_fix = { |
245a2c2c | 52 | .id = "Trident", |
1da177e4 LT |
53 | .type = FB_TYPE_PACKED_PIXELS, |
54 | .ypanstep = 1, | |
55 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
56 | .accel = FB_ACCEL_NONE, | |
57 | }; | |
58 | ||
1da177e4 LT |
59 | /* defaults which are normally overriden by user values */ |
60 | ||
61 | /* video mode */ | |
6a5e3bd0 | 62 | static char *mode_option; |
48c68c4f | 63 | static int bpp = 8; |
1da177e4 | 64 | |
48c68c4f | 65 | static int noaccel; |
1da177e4 LT |
66 | |
67 | static int center; | |
68 | static int stretch; | |
69 | ||
48c68c4f GKH |
70 | static int fp; |
71 | static int crt; | |
1da177e4 | 72 | |
48c68c4f GKH |
73 | static int memsize; |
74 | static int memdiff; | |
1da177e4 LT |
75 | static int nativex; |
76 | ||
07f41e45 KH |
77 | module_param(mode_option, charp, 0); |
78 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
9e3f0ca8 KH |
79 | module_param_named(mode, mode_option, charp, 0); |
80 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
1da177e4 LT |
81 | module_param(bpp, int, 0); |
82 | module_param(center, int, 0); | |
83 | module_param(stretch, int, 0); | |
84 | module_param(noaccel, int, 0); | |
85 | module_param(memsize, int, 0); | |
86 | module_param(memdiff, int, 0); | |
87 | module_param(nativex, int, 0); | |
88 | module_param(fp, int, 0); | |
6eed8e1e | 89 | MODULE_PARM_DESC(fp, "Define if flatpanel is connected"); |
1da177e4 | 90 | module_param(crt, int, 0); |
6eed8e1e | 91 | MODULE_PARM_DESC(crt, "Define if CRT is connected"); |
1da177e4 | 92 | |
5cf13845 | 93 | static inline int is_oldclock(int id) |
6bdf1035 | 94 | { |
a0d92256 KH |
95 | return (id == TGUI9440) || |
96 | (id == TGUI9660) || | |
0e73a47f KH |
97 | (id == CYBER9320); |
98 | } | |
99 | ||
5cf13845 | 100 | static inline int is_oldprotect(int id) |
0e73a47f | 101 | { |
5cf13845 | 102 | return is_oldclock(id) || |
0e73a47f | 103 | (id == PROVIDIA9685) || |
0e73a47f KH |
104 | (id == CYBER9382) || |
105 | (id == CYBER9385); | |
6bdf1035 KH |
106 | } |
107 | ||
5cf13845 | 108 | static inline int is_blade(int id) |
e0759a5f KH |
109 | { |
110 | return (id == BLADE3D) || | |
111 | (id == CYBERBLADEE4) || | |
112 | (id == CYBERBLADEi7) || | |
113 | (id == CYBERBLADEi7D) || | |
114 | (id == CYBERBLADEi1) || | |
115 | (id == CYBERBLADEi1D) || | |
116 | (id == CYBERBLADEAi1) || | |
117 | (id == CYBERBLADEAi1D); | |
118 | } | |
119 | ||
5cf13845 | 120 | static inline int is_xp(int id) |
e0759a5f KH |
121 | { |
122 | return (id == CYBERBLADEXPAi1) || | |
123 | (id == CYBERBLADEXPm8) || | |
124 | (id == CYBERBLADEXPm16); | |
125 | } | |
126 | ||
5cf13845 | 127 | static inline int is3Dchip(int id) |
1da177e4 | 128 | { |
5cf13845 | 129 | return is_blade(id) || is_xp(id) || |
245a2c2c KH |
130 | (id == CYBER9397) || (id == CYBER9397DVD) || |
131 | (id == CYBER9520) || (id == CYBER9525DVD) || | |
5cf13845 | 132 | (id == IMAGE975) || (id == IMAGE985); |
1da177e4 LT |
133 | } |
134 | ||
5cf13845 | 135 | static inline int iscyber(int id) |
1da177e4 LT |
136 | { |
137 | switch (id) { | |
245a2c2c KH |
138 | case CYBER9388: |
139 | case CYBER9382: | |
140 | case CYBER9385: | |
141 | case CYBER9397: | |
142 | case CYBER9397DVD: | |
143 | case CYBER9520: | |
144 | case CYBER9525DVD: | |
145 | case CYBERBLADEE4: | |
146 | case CYBERBLADEi7D: | |
147 | case CYBERBLADEi1: | |
148 | case CYBERBLADEi1D: | |
149 | case CYBERBLADEAi1: | |
150 | case CYBERBLADEAi1D: | |
151 | case CYBERBLADEXPAi1: | |
152 | return 1; | |
1da177e4 | 153 | |
245a2c2c | 154 | case CYBER9320: |
245a2c2c | 155 | case CYBERBLADEi7: /* VIA MPV4 integrated version */ |
245a2c2c KH |
156 | default: |
157 | /* case CYBERBLDAEXPm8: Strange */ | |
158 | /* case CYBERBLDAEXPm16: Strange */ | |
159 | return 0; | |
1da177e4 LT |
160 | } |
161 | } | |
162 | ||
306fa6f6 KH |
163 | static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg) |
164 | { | |
165 | fb_writeb(val, p->io_virt + reg); | |
166 | } | |
1da177e4 | 167 | |
306fa6f6 KH |
168 | static inline u8 t_inb(struct tridentfb_par *p, u16 reg) |
169 | { | |
170 | return fb_readb(p->io_virt + reg); | |
171 | } | |
1da177e4 | 172 | |
306fa6f6 KH |
173 | static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v) |
174 | { | |
175 | fb_writel(v, par->io_virt + r); | |
176 | } | |
177 | ||
178 | static inline u32 readmmr(struct tridentfb_par *par, u16 r) | |
179 | { | |
180 | return fb_readl(par->io_virt + r); | |
181 | } | |
1da177e4 | 182 | |
6a5e3bd0 OZ |
183 | #define DDC_SDA_TGUI BIT(0) |
184 | #define DDC_SCL_TGUI BIT(1) | |
185 | #define DDC_SCL_DRIVE_TGUI BIT(2) | |
186 | #define DDC_SDA_DRIVE_TGUI BIT(3) | |
187 | #define DDC_MASK_TGUI (DDC_SCL_DRIVE_TGUI | DDC_SDA_DRIVE_TGUI) | |
188 | ||
189 | static void tridentfb_ddc_setscl_tgui(void *data, int val) | |
190 | { | |
191 | struct tridentfb_par *par = data; | |
192 | u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; | |
193 | ||
194 | if (val) | |
195 | reg &= ~DDC_SCL_DRIVE_TGUI; /* disable drive - don't drive hi */ | |
196 | else | |
197 | reg |= DDC_SCL_DRIVE_TGUI; /* drive low */ | |
198 | ||
199 | vga_mm_wcrt(par->io_virt, I2C, reg); | |
200 | } | |
201 | ||
202 | static void tridentfb_ddc_setsda_tgui(void *data, int val) | |
203 | { | |
204 | struct tridentfb_par *par = data; | |
205 | u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI; | |
206 | ||
207 | if (val) | |
208 | reg &= ~DDC_SDA_DRIVE_TGUI; /* disable drive - don't drive hi */ | |
209 | else | |
210 | reg |= DDC_SDA_DRIVE_TGUI; /* drive low */ | |
211 | ||
212 | vga_mm_wcrt(par->io_virt, I2C, reg); | |
213 | } | |
214 | ||
215 | static int tridentfb_ddc_getsda_tgui(void *data) | |
216 | { | |
217 | struct tridentfb_par *par = data; | |
218 | ||
219 | return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI); | |
220 | } | |
221 | ||
222 | #define DDC_SDA_IN BIT(0) | |
223 | #define DDC_SCL_OUT BIT(1) | |
224 | #define DDC_SDA_OUT BIT(3) | |
225 | #define DDC_SCL_IN BIT(6) | |
226 | #define DDC_MASK (DDC_SCL_OUT | DDC_SDA_OUT) | |
227 | ||
228 | static void tridentfb_ddc_setscl(void *data, int val) | |
229 | { | |
230 | struct tridentfb_par *par = data; | |
231 | unsigned char reg; | |
232 | ||
233 | reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK; | |
234 | if (val) | |
235 | reg |= DDC_SCL_OUT; | |
236 | else | |
237 | reg &= ~DDC_SCL_OUT; | |
238 | vga_mm_wcrt(par->io_virt, I2C, reg); | |
239 | } | |
240 | ||
241 | static void tridentfb_ddc_setsda(void *data, int val) | |
242 | { | |
243 | struct tridentfb_par *par = data; | |
244 | unsigned char reg; | |
245 | ||
246 | reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK; | |
247 | if (!val) | |
248 | reg |= DDC_SDA_OUT; | |
249 | else | |
250 | reg &= ~DDC_SDA_OUT; | |
251 | vga_mm_wcrt(par->io_virt, I2C, reg); | |
252 | } | |
253 | ||
254 | static int tridentfb_ddc_getscl(void *data) | |
255 | { | |
256 | struct tridentfb_par *par = data; | |
257 | ||
258 | return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN); | |
259 | } | |
260 | ||
261 | static int tridentfb_ddc_getsda(void *data) | |
262 | { | |
263 | struct tridentfb_par *par = data; | |
264 | ||
265 | return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN); | |
266 | } | |
267 | ||
268 | static int tridentfb_setup_ddc_bus(struct fb_info *info) | |
269 | { | |
270 | struct tridentfb_par *par = info->par; | |
271 | ||
272 | strlcpy(par->ddc_adapter.name, info->fix.id, | |
273 | sizeof(par->ddc_adapter.name)); | |
274 | par->ddc_adapter.owner = THIS_MODULE; | |
275 | par->ddc_adapter.class = I2C_CLASS_DDC; | |
276 | par->ddc_adapter.algo_data = &par->ddc_algo; | |
277 | par->ddc_adapter.dev.parent = info->device; | |
278 | if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */ | |
279 | par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui; | |
280 | par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui; | |
281 | par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui; | |
282 | /* no getscl */ | |
283 | } else { | |
284 | par->ddc_algo.setsda = tridentfb_ddc_setsda; | |
285 | par->ddc_algo.setscl = tridentfb_ddc_setscl; | |
286 | par->ddc_algo.getsda = tridentfb_ddc_getsda; | |
287 | par->ddc_algo.getscl = tridentfb_ddc_getscl; | |
288 | } | |
289 | par->ddc_algo.udelay = 10; | |
290 | par->ddc_algo.timeout = 20; | |
291 | par->ddc_algo.data = par; | |
292 | ||
293 | i2c_set_adapdata(&par->ddc_adapter, par); | |
294 | ||
295 | return i2c_bit_add_bus(&par->ddc_adapter); | |
296 | } | |
297 | ||
1da177e4 LT |
298 | /* |
299 | * Blade specific acceleration. | |
300 | */ | |
301 | ||
245a2c2c | 302 | #define point(x, y) ((y) << 16 | (x)) |
1da177e4 | 303 | |
306fa6f6 | 304 | static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 305 | { |
245a2c2c | 306 | int v1 = (pitch >> 3) << 20; |
49b1f4b4 KH |
307 | int tmp = bpp == 24 ? 2 : (bpp >> 4); |
308 | int v2 = v1 | (tmp << 29); | |
309 | ||
306fa6f6 KH |
310 | writemmr(par, 0x21C0, v2); |
311 | writemmr(par, 0x21C4, v2); | |
312 | writemmr(par, 0x21B8, v2); | |
313 | writemmr(par, 0x21BC, v2); | |
314 | writemmr(par, 0x21D0, v1); | |
315 | writemmr(par, 0x21D4, v1); | |
316 | writemmr(par, 0x21C8, v1); | |
317 | writemmr(par, 0x21CC, v1); | |
318 | writemmr(par, 0x216C, 0); | |
1da177e4 LT |
319 | } |
320 | ||
306fa6f6 | 321 | static void blade_wait_engine(struct tridentfb_par *par) |
1da177e4 | 322 | { |
49b1f4b4 KH |
323 | while (readmmr(par, STATUS) & 0xFA800000) |
324 | cpu_relax(); | |
1da177e4 LT |
325 | } |
326 | ||
306fa6f6 KH |
327 | static void blade_fill_rect(struct tridentfb_par *par, |
328 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 329 | { |
49b1f4b4 KH |
330 | writemmr(par, COLOR, c); |
331 | writemmr(par, ROP, rop ? ROP_X : ROP_S); | |
306fa6f6 | 332 | writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2); |
1da177e4 | 333 | |
49b1f4b4 KH |
334 | writemmr(par, DST1, point(x, y)); |
335 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 LT |
336 | } |
337 | ||
0292be4a KH |
338 | static void blade_image_blit(struct tridentfb_par *par, const char *data, |
339 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 b) | |
340 | { | |
341 | unsigned size = ((w + 31) >> 5) * h; | |
342 | ||
343 | writemmr(par, COLOR, c); | |
344 | writemmr(par, BGCOLOR, b); | |
345 | writemmr(par, CMD, 0xa0000000 | 3 << 19); | |
346 | ||
347 | writemmr(par, DST1, point(x, y)); | |
348 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
349 | ||
7f2ea957 | 350 | iowrite32_rep(par->io_virt + 0x10000, data, size); |
0292be4a KH |
351 | } |
352 | ||
306fa6f6 KH |
353 | static void blade_copy_rect(struct tridentfb_par *par, |
354 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 355 | { |
1da177e4 | 356 | int direction = 2; |
49b1f4b4 KH |
357 | u32 s1 = point(x1, y1); |
358 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
359 | u32 d1 = point(x2, y2); | |
360 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 LT |
361 | |
362 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) | |
245a2c2c | 363 | direction = 0; |
1da177e4 | 364 | |
306fa6f6 KH |
365 | writemmr(par, ROP, ROP_S); |
366 | writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction); | |
1da177e4 | 367 | |
49b1f4b4 KH |
368 | writemmr(par, SRC1, direction ? s2 : s1); |
369 | writemmr(par, SRC2, direction ? s1 : s2); | |
370 | writemmr(par, DST1, direction ? d2 : d1); | |
371 | writemmr(par, DST2, direction ? d1 : d2); | |
1da177e4 LT |
372 | } |
373 | ||
1da177e4 LT |
374 | /* |
375 | * BladeXP specific acceleration functions | |
376 | */ | |
377 | ||
306fa6f6 | 378 | static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 379 | { |
49b1f4b4 KH |
380 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
381 | int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); | |
1da177e4 LT |
382 | |
383 | switch (pitch << (bpp >> 3)) { | |
245a2c2c KH |
384 | case 8192: |
385 | case 512: | |
386 | x |= 0x00; | |
387 | break; | |
388 | case 1024: | |
389 | x |= 0x04; | |
390 | break; | |
391 | case 2048: | |
392 | x |= 0x08; | |
393 | break; | |
394 | case 4096: | |
395 | x |= 0x0C; | |
396 | break; | |
1da177e4 LT |
397 | } |
398 | ||
306fa6f6 | 399 | t_outb(par, x, 0x2125); |
1da177e4 | 400 | |
5cf13845 | 401 | par->eng_oper = x | 0x40; |
1da177e4 | 402 | |
306fa6f6 KH |
403 | writemmr(par, 0x2154, v1); |
404 | writemmr(par, 0x2150, v1); | |
405 | t_outb(par, 3, 0x2126); | |
1da177e4 LT |
406 | } |
407 | ||
306fa6f6 | 408 | static void xp_wait_engine(struct tridentfb_par *par) |
1da177e4 | 409 | { |
5cf13845 KH |
410 | int count = 0; |
411 | int timeout = 0; | |
1da177e4 | 412 | |
49b1f4b4 | 413 | while (t_inb(par, STATUS) & 0x80) { |
1da177e4 LT |
414 | count++; |
415 | if (count == 10000000) { | |
416 | /* Timeout */ | |
417 | count = 9990000; | |
418 | timeout++; | |
419 | if (timeout == 8) { | |
420 | /* Reset engine */ | |
49b1f4b4 | 421 | t_outb(par, 0x00, STATUS); |
1da177e4 LT |
422 | return; |
423 | } | |
424 | } | |
49b1f4b4 | 425 | cpu_relax(); |
1da177e4 LT |
426 | } |
427 | } | |
428 | ||
306fa6f6 KH |
429 | static void xp_fill_rect(struct tridentfb_par *par, |
430 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 431 | { |
306fa6f6 KH |
432 | writemmr(par, 0x2127, ROP_P); |
433 | writemmr(par, 0x2158, c); | |
49b1f4b4 KH |
434 | writemmr(par, DRAWFL, 0x4000); |
435 | writemmr(par, OLDDIM, point(h, w)); | |
436 | writemmr(par, OLDDST, point(y, x)); | |
437 | t_outb(par, 0x01, OLDCMD); | |
5cf13845 | 438 | t_outb(par, par->eng_oper, 0x2125); |
1da177e4 LT |
439 | } |
440 | ||
306fa6f6 KH |
441 | static void xp_copy_rect(struct tridentfb_par *par, |
442 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 443 | { |
245a2c2c | 444 | u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp; |
5cf13845 | 445 | int direction = 0x0004; |
245a2c2c | 446 | |
1da177e4 LT |
447 | if ((x1 < x2) && (y1 == y2)) { |
448 | direction |= 0x0200; | |
449 | x1_tmp = x1 + w - 1; | |
450 | x2_tmp = x2 + w - 1; | |
451 | } else { | |
452 | x1_tmp = x1; | |
453 | x2_tmp = x2; | |
454 | } | |
245a2c2c | 455 | |
1da177e4 LT |
456 | if (y1 < y2) { |
457 | direction |= 0x0100; | |
458 | y1_tmp = y1 + h - 1; | |
459 | y2_tmp = y2 + h - 1; | |
245a2c2c | 460 | } else { |
1da177e4 LT |
461 | y1_tmp = y1; |
462 | y2_tmp = y2; | |
463 | } | |
464 | ||
49b1f4b4 | 465 | writemmr(par, DRAWFL, direction); |
306fa6f6 | 466 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
467 | writemmr(par, OLDSRC, point(y1_tmp, x1_tmp)); |
468 | writemmr(par, OLDDST, point(y2_tmp, x2_tmp)); | |
469 | writemmr(par, OLDDIM, point(h, w)); | |
470 | t_outb(par, 0x01, OLDCMD); | |
1da177e4 LT |
471 | } |
472 | ||
1da177e4 LT |
473 | /* |
474 | * Image specific acceleration functions | |
475 | */ | |
306fa6f6 | 476 | static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) |
1da177e4 | 477 | { |
49b1f4b4 KH |
478 | int tmp = bpp == 24 ? 2: (bpp >> 4); |
479 | ||
306fa6f6 KH |
480 | writemmr(par, 0x2120, 0xF0000000); |
481 | writemmr(par, 0x2120, 0x40000000 | tmp); | |
482 | writemmr(par, 0x2120, 0x80000000); | |
483 | writemmr(par, 0x2144, 0x00000000); | |
484 | writemmr(par, 0x2148, 0x00000000); | |
485 | writemmr(par, 0x2150, 0x00000000); | |
486 | writemmr(par, 0x2154, 0x00000000); | |
487 | writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch); | |
488 | writemmr(par, 0x216C, 0x00000000); | |
489 | writemmr(par, 0x2170, 0x00000000); | |
490 | writemmr(par, 0x217C, 0x00000000); | |
491 | writemmr(par, 0x2120, 0x10000000); | |
492 | writemmr(par, 0x2130, (2047 << 16) | 2047); | |
1da177e4 LT |
493 | } |
494 | ||
306fa6f6 | 495 | static void image_wait_engine(struct tridentfb_par *par) |
1da177e4 | 496 | { |
49b1f4b4 KH |
497 | while (readmmr(par, 0x2164) & 0xF0000000) |
498 | cpu_relax(); | |
1da177e4 LT |
499 | } |
500 | ||
306fa6f6 KH |
501 | static void image_fill_rect(struct tridentfb_par *par, |
502 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
1da177e4 | 503 | { |
306fa6f6 KH |
504 | writemmr(par, 0x2120, 0x80000000); |
505 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
1da177e4 | 506 | |
306fa6f6 | 507 | writemmr(par, 0x2144, c); |
1da177e4 | 508 | |
49b1f4b4 KH |
509 | writemmr(par, DST1, point(x, y)); |
510 | writemmr(par, DST2, point(x + w - 1, y + h - 1)); | |
1da177e4 | 511 | |
306fa6f6 | 512 | writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9); |
1da177e4 LT |
513 | } |
514 | ||
306fa6f6 KH |
515 | static void image_copy_rect(struct tridentfb_par *par, |
516 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
1da177e4 | 517 | { |
2c86a0c2 | 518 | int direction = 0x4; |
49b1f4b4 KH |
519 | u32 s1 = point(x1, y1); |
520 | u32 s2 = point(x1 + w - 1, y1 + h - 1); | |
521 | u32 d1 = point(x2, y2); | |
522 | u32 d2 = point(x2 + w - 1, y2 + h - 1); | |
1da177e4 | 523 | |
245a2c2c KH |
524 | if ((y1 > y2) || ((y1 == y2) && (x1 > x2))) |
525 | direction = 0; | |
526 | ||
306fa6f6 KH |
527 | writemmr(par, 0x2120, 0x80000000); |
528 | writemmr(par, 0x2120, 0x90000000 | ROP_S); | |
245a2c2c | 529 | |
49b1f4b4 KH |
530 | writemmr(par, SRC1, direction ? s2 : s1); |
531 | writemmr(par, SRC2, direction ? s1 : s2); | |
532 | writemmr(par, DST1, direction ? d2 : d1); | |
533 | writemmr(par, DST2, direction ? d1 : d2); | |
306fa6f6 KH |
534 | writemmr(par, 0x2124, |
535 | 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction); | |
245a2c2c | 536 | } |
1da177e4 | 537 | |
bcac2d5f KH |
538 | /* |
539 | * TGUI 9440/96XX acceleration | |
540 | */ | |
541 | ||
542 | static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) | |
543 | { | |
49b1f4b4 | 544 | unsigned char x = bpp == 24 ? 3 : (bpp >> 4); |
bcac2d5f KH |
545 | |
546 | /* disable clipping */ | |
547 | writemmr(par, 0x2148, 0); | |
548 | writemmr(par, 0x214C, point(4095, 2047)); | |
549 | ||
bcac2d5f KH |
550 | switch ((pitch * bpp) / 8) { |
551 | case 8192: | |
552 | case 512: | |
553 | x |= 0x00; | |
554 | break; | |
555 | case 1024: | |
556 | x |= 0x04; | |
557 | break; | |
558 | case 2048: | |
559 | x |= 0x08; | |
560 | break; | |
561 | case 4096: | |
562 | x |= 0x0C; | |
563 | break; | |
564 | } | |
565 | ||
566 | fb_writew(x, par->io_virt + 0x2122); | |
567 | } | |
568 | ||
569 | static void tgui_fill_rect(struct tridentfb_par *par, | |
570 | u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop) | |
571 | { | |
572 | t_outb(par, ROP_P, 0x2127); | |
49b1f4b4 KH |
573 | writemmr(par, OLDCLR, c); |
574 | writemmr(par, DRAWFL, 0x4020); | |
575 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
576 | writemmr(par, OLDDST, point(x, y)); | |
577 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
578 | } |
579 | ||
580 | static void tgui_copy_rect(struct tridentfb_par *par, | |
581 | u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h) | |
582 | { | |
583 | int flags = 0; | |
584 | u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp; | |
585 | ||
586 | if ((x1 < x2) && (y1 == y2)) { | |
587 | flags |= 0x0200; | |
588 | x1_tmp = x1 + w - 1; | |
589 | x2_tmp = x2 + w - 1; | |
590 | } else { | |
591 | x1_tmp = x1; | |
592 | x2_tmp = x2; | |
593 | } | |
594 | ||
595 | if (y1 < y2) { | |
596 | flags |= 0x0100; | |
597 | y1_tmp = y1 + h - 1; | |
598 | y2_tmp = y2 + h - 1; | |
599 | } else { | |
600 | y1_tmp = y1; | |
601 | y2_tmp = y2; | |
602 | } | |
603 | ||
49b1f4b4 | 604 | writemmr(par, DRAWFL, 0x4 | flags); |
bcac2d5f | 605 | t_outb(par, ROP_S, 0x2127); |
49b1f4b4 KH |
606 | writemmr(par, OLDSRC, point(x1_tmp, y1_tmp)); |
607 | writemmr(par, OLDDST, point(x2_tmp, y2_tmp)); | |
608 | writemmr(par, OLDDIM, point(w - 1, h - 1)); | |
609 | t_outb(par, 1, OLDCMD); | |
bcac2d5f KH |
610 | } |
611 | ||
1da177e4 LT |
612 | /* |
613 | * Accel functions called by the upper layers | |
614 | */ | |
245a2c2c KH |
615 | static void tridentfb_fillrect(struct fb_info *info, |
616 | const struct fb_fillrect *fr) | |
1da177e4 | 617 | { |
306fa6f6 | 618 | struct tridentfb_par *par = info->par; |
49b1f4b4 | 619 | int col; |
245a2c2c | 620 | |
01a2d9ed KH |
621 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
622 | cfb_fillrect(info, fr); | |
623 | return; | |
624 | } | |
49b1f4b4 KH |
625 | if (info->var.bits_per_pixel == 8) { |
626 | col = fr->color; | |
245a2c2c KH |
627 | col |= col << 8; |
628 | col |= col << 16; | |
49b1f4b4 | 629 | } else |
245a2c2c | 630 | col = ((u32 *)(info->pseudo_palette))[fr->color]; |
245a2c2c | 631 | |
49b1f4b4 | 632 | par->wait_engine(par); |
d9cad04b | 633 | par->fill_rect(par, fr->dx, fr->dy, fr->width, |
306fa6f6 | 634 | fr->height, col, fr->rop); |
1da177e4 | 635 | } |
49b1f4b4 | 636 | |
0292be4a KH |
637 | static void tridentfb_imageblit(struct fb_info *info, |
638 | const struct fb_image *img) | |
639 | { | |
640 | struct tridentfb_par *par = info->par; | |
641 | int col, bgcol; | |
642 | ||
643 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) { | |
644 | cfb_imageblit(info, img); | |
645 | return; | |
646 | } | |
647 | if (info->var.bits_per_pixel == 8) { | |
648 | col = img->fg_color; | |
649 | col |= col << 8; | |
650 | col |= col << 16; | |
651 | bgcol = img->bg_color; | |
652 | bgcol |= bgcol << 8; | |
653 | bgcol |= bgcol << 16; | |
654 | } else { | |
655 | col = ((u32 *)(info->pseudo_palette))[img->fg_color]; | |
656 | bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color]; | |
657 | } | |
658 | ||
659 | par->wait_engine(par); | |
660 | if (par->image_blit) | |
661 | par->image_blit(par, img->data, img->dx, img->dy, | |
662 | img->width, img->height, col, bgcol); | |
663 | else | |
664 | cfb_imageblit(info, img); | |
665 | } | |
666 | ||
245a2c2c KH |
667 | static void tridentfb_copyarea(struct fb_info *info, |
668 | const struct fb_copyarea *ca) | |
1da177e4 | 669 | { |
306fa6f6 KH |
670 | struct tridentfb_par *par = info->par; |
671 | ||
01a2d9ed KH |
672 | if (info->flags & FBINFO_HWACCEL_DISABLED) { |
673 | cfb_copyarea(info, ca); | |
674 | return; | |
675 | } | |
49b1f4b4 | 676 | par->wait_engine(par); |
d9cad04b | 677 | par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy, |
306fa6f6 | 678 | ca->width, ca->height); |
49b1f4b4 KH |
679 | } |
680 | ||
681 | static int tridentfb_sync(struct fb_info *info) | |
682 | { | |
683 | struct tridentfb_par *par = info->par; | |
684 | ||
01a2d9ed KH |
685 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) |
686 | par->wait_engine(par); | |
49b1f4b4 | 687 | return 0; |
1da177e4 | 688 | } |
1da177e4 | 689 | |
1da177e4 LT |
690 | /* |
691 | * Hardware access functions | |
692 | */ | |
693 | ||
306fa6f6 | 694 | static inline unsigned char read3X4(struct tridentfb_par *par, int reg) |
1da177e4 | 695 | { |
10172ed6 | 696 | return vga_mm_rcrt(par->io_virt, reg); |
1da177e4 LT |
697 | } |
698 | ||
306fa6f6 KH |
699 | static inline void write3X4(struct tridentfb_par *par, int reg, |
700 | unsigned char val) | |
1da177e4 | 701 | { |
10172ed6 | 702 | vga_mm_wcrt(par->io_virt, reg, val); |
1da177e4 LT |
703 | } |
704 | ||
10172ed6 KH |
705 | static inline unsigned char read3CE(struct tridentfb_par *par, |
706 | unsigned char reg) | |
1da177e4 | 707 | { |
10172ed6 | 708 | return vga_mm_rgfx(par->io_virt, reg); |
1da177e4 LT |
709 | } |
710 | ||
306fa6f6 KH |
711 | static inline void writeAttr(struct tridentfb_par *par, int reg, |
712 | unsigned char val) | |
1da177e4 | 713 | { |
10172ed6 KH |
714 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
715 | vga_mm_wattr(par->io_virt, reg, val); | |
1da177e4 LT |
716 | } |
717 | ||
306fa6f6 KH |
718 | static inline void write3CE(struct tridentfb_par *par, int reg, |
719 | unsigned char val) | |
1da177e4 | 720 | { |
10172ed6 | 721 | vga_mm_wgfx(par->io_virt, reg, val); |
1da177e4 LT |
722 | } |
723 | ||
13b0de49 | 724 | static void enable_mmio(struct tridentfb_par *par) |
1da177e4 LT |
725 | { |
726 | /* Goto New Mode */ | |
10172ed6 | 727 | vga_io_rseq(0x0B); |
1da177e4 LT |
728 | |
729 | /* Unprotect registers */ | |
10172ed6 | 730 | vga_io_wseq(NewMode1, 0x80); |
13b0de49 KH |
731 | if (!is_oldprotect(par->chip_id)) |
732 | vga_io_wseq(Protection, 0x92); | |
245a2c2c | 733 | |
1da177e4 | 734 | /* Enable MMIO */ |
245a2c2c | 735 | outb(PCIReg, 0x3D4); |
1da177e4 | 736 | outb(inb(0x3D5) | 0x01, 0x3D5); |
e8ed857c KH |
737 | } |
738 | ||
306fa6f6 | 739 | static void disable_mmio(struct tridentfb_par *par) |
e8ed857c | 740 | { |
e8ed857c | 741 | /* Goto New Mode */ |
10172ed6 | 742 | vga_mm_rseq(par->io_virt, 0x0B); |
e8ed857c KH |
743 | |
744 | /* Unprotect registers */ | |
10172ed6 | 745 | vga_mm_wseq(par->io_virt, NewMode1, 0x80); |
13b0de49 KH |
746 | if (!is_oldprotect(par->chip_id)) |
747 | vga_mm_wseq(par->io_virt, Protection, 0x92); | |
e8ed857c KH |
748 | |
749 | /* Disable MMIO */ | |
306fa6f6 KH |
750 | t_outb(par, PCIReg, 0x3D4); |
751 | t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5); | |
1da177e4 LT |
752 | } |
753 | ||
5cf13845 | 754 | static inline void crtc_unlock(struct tridentfb_par *par) |
306fa6f6 | 755 | { |
10172ed6 KH |
756 | write3X4(par, VGA_CRTC_V_SYNC_END, |
757 | read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F); | |
306fa6f6 | 758 | } |
1da177e4 LT |
759 | |
760 | /* Return flat panel's maximum x resolution */ | |
48c68c4f | 761 | static int get_nativex(struct tridentfb_par *par) |
1da177e4 | 762 | { |
245a2c2c | 763 | int x, y, tmp; |
1da177e4 LT |
764 | |
765 | if (nativex) | |
766 | return nativex; | |
767 | ||
306fa6f6 | 768 | tmp = (read3CE(par, VertStretch) >> 4) & 3; |
1da177e4 LT |
769 | |
770 | switch (tmp) { | |
245a2c2c KH |
771 | case 0: |
772 | x = 1280; y = 1024; | |
773 | break; | |
774 | case 2: | |
775 | x = 1024; y = 768; | |
776 | break; | |
777 | case 3: | |
778 | x = 800; y = 600; | |
779 | break; | |
245a2c2c KH |
780 | case 1: |
781 | default: | |
782 | x = 640; y = 480; | |
783 | break; | |
1da177e4 LT |
784 | } |
785 | ||
786 | output("%dx%d flat panel found\n", x, y); | |
787 | return x; | |
788 | } | |
789 | ||
790 | /* Set pitch */ | |
5cf13845 | 791 | static inline void set_lwidth(struct tridentfb_par *par, int width) |
1da177e4 | 792 | { |
10172ed6 | 793 | write3X4(par, VGA_CRTC_OFFSET, width & 0xFF); |
23aa4db7 OZ |
794 | /* chips older than TGUI9660 have only 1 width bit in AddColReg */ |
795 | /* touching the other one breaks I2C/DDC */ | |
796 | if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320) | |
797 | write3X4(par, AddColReg, | |
798 | (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4)); | |
799 | else | |
800 | write3X4(par, AddColReg, | |
801 | (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4)); | |
1da177e4 LT |
802 | } |
803 | ||
804 | /* For resolutions smaller than FP resolution stretch */ | |
306fa6f6 | 805 | static void screen_stretch(struct tridentfb_par *par) |
1da177e4 | 806 | { |
122e8ad3 | 807 | if (par->chip_id != CYBERBLADEXPAi1) |
306fa6f6 | 808 | write3CE(par, BiosReg, 0); |
245a2c2c | 809 | else |
306fa6f6 KH |
810 | write3CE(par, BiosReg, 8); |
811 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1); | |
812 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1); | |
1da177e4 LT |
813 | } |
814 | ||
815 | /* For resolutions smaller than FP resolution center */ | |
5cf13845 | 816 | static inline void screen_center(struct tridentfb_par *par) |
1da177e4 | 817 | { |
306fa6f6 KH |
818 | write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80); |
819 | write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80); | |
1da177e4 LT |
820 | } |
821 | ||
822 | /* Address of first shown pixel in display memory */ | |
306fa6f6 | 823 | static void set_screen_start(struct tridentfb_par *par, int base) |
1da177e4 | 824 | { |
306fa6f6 | 825 | u8 tmp; |
10172ed6 KH |
826 | write3X4(par, VGA_CRTC_START_LO, base & 0xFF); |
827 | write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8); | |
306fa6f6 KH |
828 | tmp = read3X4(par, CRTCModuleTest) & 0xDF; |
829 | write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11)); | |
830 | tmp = read3X4(par, CRTHiOrd) & 0xF8; | |
831 | write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17)); | |
1da177e4 LT |
832 | } |
833 | ||
1da177e4 | 834 | /* Set dotclock frequency */ |
306fa6f6 | 835 | static void set_vclk(struct tridentfb_par *par, unsigned long freq) |
1da177e4 | 836 | { |
245a2c2c | 837 | int m, n, k; |
6bdf1035 KH |
838 | unsigned long fi, d, di; |
839 | unsigned char best_m = 0, best_n = 0, best_k = 0; | |
840 | unsigned char hi, lo; | |
6280fd4f | 841 | unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1; |
1da177e4 | 842 | |
3f275ea3 | 843 | d = 20000; |
6280fd4f KH |
844 | for (k = shift; k >= 0; k--) |
845 | for (m = 1; m < 32; m++) { | |
846 | n = ((m + 2) << shift) - 8; | |
34dec243 | 847 | for (n = (n < 0 ? 0 : n); n < 122; n++) { |
3f275ea3 | 848 | fi = ((14318l * (n + 8)) / (m + 2)) >> k; |
34dec243 | 849 | di = abs(fi - freq); |
6280fd4f | 850 | if (di < d || (di == d && k == best_k)) { |
245a2c2c | 851 | d = di; |
6bdf1035 KH |
852 | best_n = n; |
853 | best_m = m; | |
854 | best_k = k; | |
245a2c2c | 855 | } |
3f275ea3 KH |
856 | if (fi > freq) |
857 | break; | |
245a2c2c | 858 | } |
34dec243 | 859 | } |
6bdf1035 KH |
860 | |
861 | if (is_oldclock(par->chip_id)) { | |
862 | lo = best_n | (best_m << 7); | |
863 | hi = (best_m >> 1) | (best_k << 4); | |
864 | } else { | |
865 | lo = best_n; | |
866 | hi = best_m | (best_k << 6); | |
867 | } | |
868 | ||
122e8ad3 | 869 | if (is3Dchip(par->chip_id)) { |
10172ed6 KH |
870 | vga_mm_wseq(par->io_virt, ClockHigh, hi); |
871 | vga_mm_wseq(par->io_virt, ClockLow, lo); | |
1da177e4 | 872 | } else { |
c1724fec KH |
873 | t_outb(par, lo, 0x43C8); |
874 | t_outb(par, hi, 0x43C9); | |
1da177e4 | 875 | } |
245a2c2c | 876 | debug("VCLK = %X %X\n", hi, lo); |
1da177e4 LT |
877 | } |
878 | ||
879 | /* Set number of lines for flat panels*/ | |
306fa6f6 | 880 | static void set_number_of_lines(struct tridentfb_par *par, int lines) |
1da177e4 | 881 | { |
306fa6f6 | 882 | int tmp = read3CE(par, CyberEnhance) & 0x8F; |
1da177e4 LT |
883 | if (lines > 1024) |
884 | tmp |= 0x50; | |
885 | else if (lines > 768) | |
886 | tmp |= 0x30; | |
887 | else if (lines > 600) | |
888 | tmp |= 0x20; | |
889 | else if (lines > 480) | |
890 | tmp |= 0x10; | |
306fa6f6 | 891 | write3CE(par, CyberEnhance, tmp); |
1da177e4 LT |
892 | } |
893 | ||
894 | /* | |
895 | * If we see that FP is active we assume we have one. | |
6eed8e1e | 896 | * Otherwise we have a CRT display. User can override. |
1da177e4 | 897 | */ |
48c68c4f | 898 | static int is_flatpanel(struct tridentfb_par *par) |
1da177e4 LT |
899 | { |
900 | if (fp) | |
6eed8e1e | 901 | return 1; |
122e8ad3 | 902 | if (crt || !iscyber(par->chip_id)) |
6eed8e1e KH |
903 | return 0; |
904 | return (read3CE(par, FPConfig) & 0x10) ? 1 : 0; | |
1da177e4 LT |
905 | } |
906 | ||
907 | /* Try detecting the video memory size */ | |
48c68c4f | 908 | static unsigned int get_memsize(struct tridentfb_par *par) |
1da177e4 LT |
909 | { |
910 | unsigned char tmp, tmp2; | |
911 | unsigned int k; | |
912 | ||
913 | /* If memory size provided by user */ | |
914 | if (memsize) | |
915 | k = memsize * Kb; | |
916 | else | |
122e8ad3 | 917 | switch (par->chip_id) { |
245a2c2c KH |
918 | case CYBER9525DVD: |
919 | k = 2560 * Kb; | |
920 | break; | |
1da177e4 | 921 | default: |
306fa6f6 | 922 | tmp = read3X4(par, SPR) & 0x0F; |
1da177e4 LT |
923 | switch (tmp) { |
924 | ||
245a2c2c | 925 | case 0x01: |
b614ce8b | 926 | k = 512 * Kb; |
245a2c2c KH |
927 | break; |
928 | case 0x02: | |
929 | k = 6 * Mb; /* XP */ | |
930 | break; | |
931 | case 0x03: | |
932 | k = 1 * Mb; | |
933 | break; | |
934 | case 0x04: | |
935 | k = 8 * Mb; | |
936 | break; | |
937 | case 0x06: | |
938 | k = 10 * Mb; /* XP */ | |
939 | break; | |
940 | case 0x07: | |
941 | k = 2 * Mb; | |
942 | break; | |
943 | case 0x08: | |
944 | k = 12 * Mb; /* XP */ | |
945 | break; | |
946 | case 0x0A: | |
947 | k = 14 * Mb; /* XP */ | |
948 | break; | |
949 | case 0x0C: | |
950 | k = 16 * Mb; /* XP */ | |
951 | break; | |
952 | case 0x0E: /* XP */ | |
953 | ||
10172ed6 | 954 | tmp2 = vga_mm_rseq(par->io_virt, 0xC1); |
245a2c2c KH |
955 | switch (tmp2) { |
956 | case 0x00: | |
957 | k = 20 * Mb; | |
958 | break; | |
959 | case 0x01: | |
960 | k = 24 * Mb; | |
961 | break; | |
962 | case 0x10: | |
963 | k = 28 * Mb; | |
964 | break; | |
965 | case 0x11: | |
966 | k = 32 * Mb; | |
967 | break; | |
968 | default: | |
969 | k = 1 * Mb; | |
970 | break; | |
971 | } | |
972 | break; | |
973 | ||
974 | case 0x0F: | |
975 | k = 4 * Mb; | |
976 | break; | |
977 | default: | |
978 | k = 1 * Mb; | |
1da177e4 | 979 | break; |
1da177e4 | 980 | } |
245a2c2c | 981 | } |
1da177e4 LT |
982 | |
983 | k -= memdiff * Kb; | |
245a2c2c | 984 | output("framebuffer size = %d Kb\n", k / Kb); |
1da177e4 LT |
985 | return k; |
986 | } | |
987 | ||
988 | /* See if we can handle the video mode described in var */ | |
245a2c2c KH |
989 | static int tridentfb_check_var(struct fb_var_screeninfo *var, |
990 | struct fb_info *info) | |
1da177e4 | 991 | { |
6eed8e1e | 992 | struct tridentfb_par *par = info->par; |
1da177e4 | 993 | int bpp = var->bits_per_pixel; |
bcac2d5f | 994 | int line_length; |
74a933fe | 995 | int ramdac = 230000; /* 230MHz for most 3D chips */ |
1da177e4 LT |
996 | debug("enter\n"); |
997 | ||
998 | /* check color depth */ | |
245a2c2c | 999 | if (bpp == 24) |
1da177e4 | 1000 | bpp = var->bits_per_pixel = 32; |
49b1f4b4 KH |
1001 | if (bpp != 8 && bpp != 16 && bpp != 32) |
1002 | return -EINVAL; | |
54f019e5 KH |
1003 | if (par->chip_id == TGUI9440 && bpp == 32) |
1004 | return -EINVAL; | |
245a2c2c | 1005 | /* check whether resolution fits on panel and in memory */ |
6eed8e1e | 1006 | if (par->flatpanel && nativex && var->xres > nativex) |
1da177e4 | 1007 | return -EINVAL; |
74a933fe KH |
1008 | /* various resolution checks */ |
1009 | var->xres = (var->xres + 7) & ~0x7; | |
49b1f4b4 | 1010 | if (var->xres > var->xres_virtual) |
74a933fe | 1011 | var->xres_virtual = var->xres; |
49b1f4b4 KH |
1012 | if (var->yres > var->yres_virtual) |
1013 | var->yres_virtual = var->yres; | |
1014 | if (var->xres_virtual > 4095 || var->yres > 2048) | |
1015 | return -EINVAL; | |
1016 | /* prevent from position overflow for acceleration */ | |
1017 | if (var->yres_virtual > 0xffff) | |
1018 | return -EINVAL; | |
bcac2d5f | 1019 | line_length = var->xres_virtual * bpp / 8; |
01a2d9ed KH |
1020 | |
1021 | if (!is3Dchip(par->chip_id) && | |
1022 | !(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
bcac2d5f KH |
1023 | /* acceleration requires line length to be power of 2 */ |
1024 | if (line_length <= 512) | |
1025 | var->xres_virtual = 512 * 8 / bpp; | |
1026 | else if (line_length <= 1024) | |
1027 | var->xres_virtual = 1024 * 8 / bpp; | |
1028 | else if (line_length <= 2048) | |
1029 | var->xres_virtual = 2048 * 8 / bpp; | |
1030 | else if (line_length <= 4096) | |
1031 | var->xres_virtual = 4096 * 8 / bpp; | |
1032 | else if (line_length <= 8192) | |
1033 | var->xres_virtual = 8192 * 8 / bpp; | |
49b1f4b4 KH |
1034 | else |
1035 | return -EINVAL; | |
bcac2d5f KH |
1036 | |
1037 | line_length = var->xres_virtual * bpp / 8; | |
1038 | } | |
01a2d9ed | 1039 | |
f330c4b1 KH |
1040 | /* datasheet specifies how to set panning only up to 4 MB */ |
1041 | if (line_length * (var->yres_virtual - var->yres) > (4 << 20)) | |
1042 | var->yres_virtual = ((4 << 20) / line_length) + var->yres; | |
1043 | ||
bcac2d5f | 1044 | if (line_length * var->yres_virtual > info->fix.smem_len) |
1da177e4 LT |
1045 | return -EINVAL; |
1046 | ||
1047 | switch (bpp) { | |
245a2c2c KH |
1048 | case 8: |
1049 | var->red.offset = 0; | |
a4af1798 KH |
1050 | var->red.length = 8; |
1051 | var->green = var->red; | |
1052 | var->blue = var->red; | |
245a2c2c KH |
1053 | break; |
1054 | case 16: | |
1055 | var->red.offset = 11; | |
1056 | var->green.offset = 5; | |
1057 | var->blue.offset = 0; | |
1058 | var->red.length = 5; | |
1059 | var->green.length = 6; | |
1060 | var->blue.length = 5; | |
1061 | break; | |
1062 | case 32: | |
1063 | var->red.offset = 16; | |
1064 | var->green.offset = 8; | |
1065 | var->blue.offset = 0; | |
1066 | var->red.length = 8; | |
1067 | var->green.length = 8; | |
1068 | var->blue.length = 8; | |
1069 | break; | |
1070 | default: | |
1071 | return -EINVAL; | |
1da177e4 | 1072 | } |
74a933fe KH |
1073 | |
1074 | if (is_xp(par->chip_id)) | |
1075 | ramdac = 350000; | |
1076 | ||
1077 | switch (par->chip_id) { | |
1078 | case TGUI9440: | |
54f019e5 | 1079 | ramdac = (bpp >= 16) ? 45000 : 90000; |
74a933fe KH |
1080 | break; |
1081 | case CYBER9320: | |
1082 | case TGUI9660: | |
1083 | ramdac = 135000; | |
1084 | break; | |
1085 | case PROVIDIA9685: | |
1086 | case CYBER9388: | |
1087 | case CYBER9382: | |
1088 | case CYBER9385: | |
1089 | ramdac = 170000; | |
1090 | break; | |
1091 | } | |
1092 | ||
1093 | /* The clock is doubled for 32 bpp */ | |
1094 | if (bpp == 32) | |
1095 | ramdac /= 2; | |
1096 | ||
1097 | if (PICOS2KHZ(var->pixclock) > ramdac) | |
1098 | return -EINVAL; | |
1099 | ||
1da177e4 LT |
1100 | debug("exit\n"); |
1101 | ||
1102 | return 0; | |
1103 | ||
1104 | } | |
245a2c2c | 1105 | |
1da177e4 LT |
1106 | /* Pan the display */ |
1107 | static int tridentfb_pan_display(struct fb_var_screeninfo *var, | |
245a2c2c | 1108 | struct fb_info *info) |
1da177e4 | 1109 | { |
306fa6f6 | 1110 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1111 | unsigned int offset; |
1112 | ||
1113 | debug("enter\n"); | |
4541dbe1 LP |
1114 | offset = (var->xoffset + (var->yoffset * info->var.xres_virtual)) |
1115 | * info->var.bits_per_pixel / 32; | |
306fa6f6 | 1116 | set_screen_start(par, offset); |
1da177e4 LT |
1117 | debug("exit\n"); |
1118 | return 0; | |
1119 | } | |
1120 | ||
5cf13845 | 1121 | static inline void shadowmode_on(struct tridentfb_par *par) |
306fa6f6 KH |
1122 | { |
1123 | write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81); | |
1124 | } | |
1125 | ||
5cf13845 | 1126 | static inline void shadowmode_off(struct tridentfb_par *par) |
306fa6f6 KH |
1127 | { |
1128 | write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E); | |
1129 | } | |
1da177e4 LT |
1130 | |
1131 | /* Set the hardware to the requested video mode */ | |
1132 | static int tridentfb_set_par(struct fb_info *info) | |
1133 | { | |
5cf13845 | 1134 | struct tridentfb_par *par = info->par; |
245a2c2c KH |
1135 | u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend; |
1136 | u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend; | |
1137 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 LT |
1138 | int bpp = var->bits_per_pixel; |
1139 | unsigned char tmp; | |
3f275ea3 KH |
1140 | unsigned long vclk; |
1141 | ||
1da177e4 | 1142 | debug("enter\n"); |
245a2c2c | 1143 | hdispend = var->xres / 8 - 1; |
34dec243 KH |
1144 | hsyncstart = (var->xres + var->right_margin) / 8; |
1145 | hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8; | |
7f762d23 KH |
1146 | htotal = (var->xres + var->left_margin + var->right_margin + |
1147 | var->hsync_len) / 8 - 5; | |
0e73a47f | 1148 | hblankstart = hdispend + 1; |
7f762d23 | 1149 | hblankend = htotal + 3; |
1da177e4 | 1150 | |
1da177e4 LT |
1151 | vdispend = var->yres - 1; |
1152 | vsyncstart = var->yres + var->lower_margin; | |
7f762d23 KH |
1153 | vsyncend = vsyncstart + var->vsync_len; |
1154 | vtotal = var->upper_margin + vsyncend - 2; | |
0e73a47f | 1155 | vblankstart = vdispend + 1; |
7f762d23 | 1156 | vblankend = vtotal; |
1da177e4 | 1157 | |
34dec243 KH |
1158 | if (info->var.vmode & FB_VMODE_INTERLACED) { |
1159 | vtotal /= 2; | |
1160 | vdispend /= 2; | |
1161 | vsyncstart /= 2; | |
1162 | vsyncend /= 2; | |
1163 | vblankstart /= 2; | |
1164 | vblankend /= 2; | |
1165 | } | |
1166 | ||
13b0de49 | 1167 | enable_mmio(par); |
306fa6f6 KH |
1168 | crtc_unlock(par); |
1169 | write3CE(par, CyberControl, 8); | |
34dec243 KH |
1170 | tmp = 0xEB; |
1171 | if (var->sync & FB_SYNC_HOR_HIGH_ACT) | |
1172 | tmp &= ~0x40; | |
1173 | if (var->sync & FB_SYNC_VERT_HIGH_ACT) | |
1174 | tmp &= ~0x80; | |
1da177e4 | 1175 | |
6eed8e1e | 1176 | if (par->flatpanel && var->xres < nativex) { |
1da177e4 LT |
1177 | /* |
1178 | * on flat panels with native size larger | |
1179 | * than requested resolution decide whether | |
1180 | * we stretch or center | |
1181 | */ | |
34dec243 | 1182 | t_outb(par, tmp | 0xC0, VGA_MIS_W); |
1da177e4 | 1183 | |
306fa6f6 | 1184 | shadowmode_on(par); |
1da177e4 | 1185 | |
245a2c2c | 1186 | if (center) |
306fa6f6 | 1187 | screen_center(par); |
1da177e4 | 1188 | else if (stretch) |
306fa6f6 | 1189 | screen_stretch(par); |
1da177e4 LT |
1190 | |
1191 | } else { | |
34dec243 | 1192 | t_outb(par, tmp, VGA_MIS_W); |
306fa6f6 | 1193 | write3CE(par, CyberControl, 8); |
1da177e4 LT |
1194 | } |
1195 | ||
1196 | /* vertical timing values */ | |
10172ed6 KH |
1197 | write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF); |
1198 | write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF); | |
1199 | write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF); | |
1200 | write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F)); | |
1201 | write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF); | |
7f762d23 | 1202 | write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF); |
1da177e4 LT |
1203 | |
1204 | /* horizontal timing values */ | |
10172ed6 KH |
1205 | write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF); |
1206 | write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF); | |
1207 | write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF); | |
1208 | write3X4(par, VGA_CRTC_H_SYNC_END, | |
306fa6f6 | 1209 | (hsyncend & 0x1F) | ((hblankend & 0x20) << 2)); |
10172ed6 | 1210 | write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF); |
7f762d23 | 1211 | write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F); |
1da177e4 LT |
1212 | |
1213 | /* higher bits of vertical timing values */ | |
1214 | tmp = 0x10; | |
1215 | if (vtotal & 0x100) tmp |= 0x01; | |
1216 | if (vdispend & 0x100) tmp |= 0x02; | |
1217 | if (vsyncstart & 0x100) tmp |= 0x04; | |
1218 | if (vblankstart & 0x100) tmp |= 0x08; | |
1219 | ||
1220 | if (vtotal & 0x200) tmp |= 0x20; | |
1221 | if (vdispend & 0x200) tmp |= 0x40; | |
1222 | if (vsyncstart & 0x200) tmp |= 0x80; | |
10172ed6 | 1223 | write3X4(par, VGA_CRTC_OVERFLOW, tmp); |
1da177e4 | 1224 | |
7f762d23 KH |
1225 | tmp = read3X4(par, CRTHiOrd) & 0x07; |
1226 | tmp |= 0x08; /* line compare bit 10 */ | |
1da177e4 LT |
1227 | if (vtotal & 0x400) tmp |= 0x80; |
1228 | if (vblankstart & 0x400) tmp |= 0x40; | |
1229 | if (vsyncstart & 0x400) tmp |= 0x20; | |
1230 | if (vdispend & 0x400) tmp |= 0x10; | |
306fa6f6 | 1231 | write3X4(par, CRTHiOrd, tmp); |
1da177e4 | 1232 | |
7f762d23 KH |
1233 | tmp = (htotal >> 8) & 0x01; |
1234 | tmp |= (hdispend >> 7) & 0x02; | |
1235 | tmp |= (hsyncstart >> 5) & 0x08; | |
1236 | tmp |= (hblankstart >> 4) & 0x10; | |
306fa6f6 | 1237 | write3X4(par, HorizOverflow, tmp); |
245a2c2c | 1238 | |
1da177e4 LT |
1239 | tmp = 0x40; |
1240 | if (vblankstart & 0x200) tmp |= 0x20; | |
245a2c2c | 1241 | //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */ |
10172ed6 | 1242 | write3X4(par, VGA_CRTC_MAX_SCAN, tmp); |
1da177e4 | 1243 | |
10172ed6 KH |
1244 | write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF); |
1245 | write3X4(par, VGA_CRTC_PRESET_ROW, 0); | |
1246 | write3X4(par, VGA_CRTC_MODE, 0xC3); | |
1da177e4 | 1247 | |
306fa6f6 | 1248 | write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */ |
1da177e4 | 1249 | |
245a2c2c | 1250 | tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80; |
306fa6f6 KH |
1251 | /* enable access extended memory */ |
1252 | write3X4(par, CRTCModuleTest, tmp); | |
34dec243 KH |
1253 | tmp = read3CE(par, MiscIntContReg) & ~0x4; |
1254 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
1255 | tmp |= 0x4; | |
1256 | write3CE(par, MiscIntContReg, tmp); | |
1da177e4 | 1257 | |
306fa6f6 KH |
1258 | /* enable GE for text acceleration */ |
1259 | write3X4(par, GraphEngReg, 0x80); | |
1da177e4 | 1260 | |
1da177e4 | 1261 | switch (bpp) { |
245a2c2c KH |
1262 | case 8: |
1263 | tmp = 0x00; | |
1264 | break; | |
1265 | case 16: | |
1266 | tmp = 0x05; | |
1267 | break; | |
1268 | case 24: | |
1269 | tmp = 0x29; | |
1270 | break; | |
1271 | case 32: | |
1272 | tmp = 0x09; | |
1273 | break; | |
1da177e4 LT |
1274 | } |
1275 | ||
306fa6f6 | 1276 | write3X4(par, PixelBusReg, tmp); |
1da177e4 | 1277 | |
0e73a47f KH |
1278 | tmp = read3X4(par, DRAMControl); |
1279 | if (!is_oldprotect(par->chip_id)) | |
1280 | tmp |= 0x10; | |
122e8ad3 | 1281 | if (iscyber(par->chip_id)) |
245a2c2c | 1282 | tmp |= 0x20; |
306fa6f6 | 1283 | write3X4(par, DRAMControl, tmp); /* both IO, linear enable */ |
1da177e4 | 1284 | |
306fa6f6 | 1285 | write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40); |
0e73a47f KH |
1286 | if (!is_xp(par->chip_id)) |
1287 | write3X4(par, Performance, read3X4(par, Performance) | 0x10); | |
306fa6f6 | 1288 | /* MMIO & PCI read and write burst enable */ |
13b0de49 | 1289 | if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975) |
a0d92256 | 1290 | write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06); |
1da177e4 | 1291 | |
10172ed6 KH |
1292 | vga_mm_wseq(par->io_virt, 0, 3); |
1293 | vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */ | |
306fa6f6 | 1294 | /* enable 4 maps because needed in chain4 mode */ |
10172ed6 KH |
1295 | vga_mm_wseq(par->io_virt, 2, 0x0F); |
1296 | vga_mm_wseq(par->io_virt, 3, 0); | |
1297 | vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */ | |
1da177e4 | 1298 | |
54f019e5 KH |
1299 | /* convert from picoseconds to kHz */ |
1300 | vclk = PICOS2KHZ(info->var.pixclock); | |
1301 | ||
306fa6f6 | 1302 | /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ |
65e93e03 | 1303 | tmp = read3CE(par, MiscExtFunc) & 0xF0; |
54f019e5 | 1304 | if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { |
65e93e03 | 1305 | tmp |= 8; |
54f019e5 KH |
1306 | vclk *= 2; |
1307 | } | |
1308 | set_vclk(par, vclk); | |
65e93e03 | 1309 | write3CE(par, MiscExtFunc, tmp | 0x12); |
306fa6f6 KH |
1310 | write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */ |
1311 | write3CE(par, 0x6, 0x05); /* graphics mode */ | |
1312 | write3CE(par, 0x7, 0x0F); /* planes? */ | |
1da177e4 | 1313 | |
306fa6f6 KH |
1314 | /* graphics mode and support 256 color modes */ |
1315 | writeAttr(par, 0x10, 0x41); | |
1316 | writeAttr(par, 0x12, 0x0F); /* planes */ | |
1317 | writeAttr(par, 0x13, 0); /* horizontal pel panning */ | |
1da177e4 | 1318 | |
245a2c2c KH |
1319 | /* colors */ |
1320 | for (tmp = 0; tmp < 0x10; tmp++) | |
306fa6f6 | 1321 | writeAttr(par, tmp, tmp); |
10172ed6 KH |
1322 | fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */ |
1323 | t_outb(par, 0x20, VGA_ATT_W); /* enable attr */ | |
1da177e4 LT |
1324 | |
1325 | switch (bpp) { | |
245a2c2c KH |
1326 | case 8: |
1327 | tmp = 0; | |
1328 | break; | |
245a2c2c KH |
1329 | case 16: |
1330 | tmp = 0x30; | |
1331 | break; | |
1332 | case 24: | |
1333 | case 32: | |
1334 | tmp = 0xD0; | |
1335 | break; | |
1da177e4 LT |
1336 | } |
1337 | ||
10172ed6 KH |
1338 | t_inb(par, VGA_PEL_IW); |
1339 | t_inb(par, VGA_PEL_MSK); | |
1340 | t_inb(par, VGA_PEL_MSK); | |
1341 | t_inb(par, VGA_PEL_MSK); | |
1342 | t_inb(par, VGA_PEL_MSK); | |
1343 | t_outb(par, tmp, VGA_PEL_MSK); | |
1344 | t_inb(par, VGA_PEL_IW); | |
1da177e4 | 1345 | |
6eed8e1e | 1346 | if (par->flatpanel) |
306fa6f6 | 1347 | set_number_of_lines(par, info->var.yres); |
bcac2d5f KH |
1348 | info->fix.line_length = info->var.xres_virtual * bpp / 8; |
1349 | set_lwidth(par, info->fix.line_length / 8); | |
01a2d9ed KH |
1350 | |
1351 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1352 | par->init_accel(par, info->var.xres_virtual, bpp); | |
2c86a0c2 | 1353 | |
1da177e4 | 1354 | info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; |
245a2c2c | 1355 | info->cmap.len = (bpp == 8) ? 256 : 16; |
1da177e4 LT |
1356 | debug("exit\n"); |
1357 | return 0; | |
1358 | } | |
1359 | ||
1360 | /* Set one color register */ | |
1361 | static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
245a2c2c KH |
1362 | unsigned blue, unsigned transp, |
1363 | struct fb_info *info) | |
1da177e4 LT |
1364 | { |
1365 | int bpp = info->var.bits_per_pixel; | |
306fa6f6 | 1366 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1367 | |
1368 | if (regno >= info->cmap.len) | |
1369 | return 1; | |
1370 | ||
973d9ab2 | 1371 | if (bpp == 8) { |
10172ed6 KH |
1372 | t_outb(par, 0xFF, VGA_PEL_MSK); |
1373 | t_outb(par, regno, VGA_PEL_IW); | |
1da177e4 | 1374 | |
10172ed6 KH |
1375 | t_outb(par, red >> 10, VGA_PEL_D); |
1376 | t_outb(par, green >> 10, VGA_PEL_D); | |
1377 | t_outb(par, blue >> 10, VGA_PEL_D); | |
1da177e4 | 1378 | |
973d9ab2 AD |
1379 | } else if (regno < 16) { |
1380 | if (bpp == 16) { /* RGB 565 */ | |
1381 | u32 col; | |
1382 | ||
1383 | col = (red & 0xF800) | ((green & 0xFC00) >> 5) | | |
1384 | ((blue & 0xF800) >> 11); | |
1385 | col |= col << 16; | |
1386 | ((u32 *)(info->pseudo_palette))[regno] = col; | |
1387 | } else if (bpp == 32) /* ARGB 8888 */ | |
5cf13845 | 1388 | ((u32 *)info->pseudo_palette)[regno] = |
245a2c2c KH |
1389 | ((transp & 0xFF00) << 16) | |
1390 | ((red & 0xFF00) << 8) | | |
973d9ab2 | 1391 | ((green & 0xFF00)) | |
245a2c2c | 1392 | ((blue & 0xFF00) >> 8); |
973d9ab2 | 1393 | } |
1da177e4 | 1394 | |
1da177e4 LT |
1395 | return 0; |
1396 | } | |
1397 | ||
5cf13845 | 1398 | /* Try blanking the screen. For flat panels it does nothing */ |
1da177e4 LT |
1399 | static int tridentfb_blank(int blank_mode, struct fb_info *info) |
1400 | { | |
245a2c2c | 1401 | unsigned char PMCont, DPMSCont; |
306fa6f6 | 1402 | struct tridentfb_par *par = info->par; |
1da177e4 LT |
1403 | |
1404 | debug("enter\n"); | |
6eed8e1e | 1405 | if (par->flatpanel) |
1da177e4 | 1406 | return 0; |
306fa6f6 KH |
1407 | t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */ |
1408 | PMCont = t_inb(par, 0x83C6) & 0xFC; | |
1409 | DPMSCont = read3CE(par, PowerStatus) & 0xFC; | |
245a2c2c | 1410 | switch (blank_mode) { |
1da177e4 LT |
1411 | case FB_BLANK_UNBLANK: |
1412 | /* Screen: On, HSync: On, VSync: On */ | |
1413 | case FB_BLANK_NORMAL: | |
1414 | /* Screen: Off, HSync: On, VSync: On */ | |
1415 | PMCont |= 0x03; | |
1416 | DPMSCont |= 0x00; | |
1417 | break; | |
1418 | case FB_BLANK_HSYNC_SUSPEND: | |
1419 | /* Screen: Off, HSync: Off, VSync: On */ | |
1420 | PMCont |= 0x02; | |
1421 | DPMSCont |= 0x01; | |
1422 | break; | |
1423 | case FB_BLANK_VSYNC_SUSPEND: | |
1424 | /* Screen: Off, HSync: On, VSync: Off */ | |
1425 | PMCont |= 0x02; | |
1426 | DPMSCont |= 0x02; | |
1427 | break; | |
1428 | case FB_BLANK_POWERDOWN: | |
1429 | /* Screen: Off, HSync: Off, VSync: Off */ | |
1430 | PMCont |= 0x00; | |
1431 | DPMSCont |= 0x03; | |
1432 | break; | |
245a2c2c | 1433 | } |
1da177e4 | 1434 | |
306fa6f6 KH |
1435 | write3CE(par, PowerStatus, DPMSCont); |
1436 | t_outb(par, 4, 0x83C8); | |
1437 | t_outb(par, PMCont, 0x83C6); | |
1da177e4 LT |
1438 | |
1439 | debug("exit\n"); | |
1440 | ||
1441 | /* let fbcon do a softblank for us */ | |
1442 | return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; | |
1443 | } | |
1444 | ||
245a2c2c KH |
1445 | static struct fb_ops tridentfb_ops = { |
1446 | .owner = THIS_MODULE, | |
1447 | .fb_setcolreg = tridentfb_setcolreg, | |
1448 | .fb_pan_display = tridentfb_pan_display, | |
1449 | .fb_blank = tridentfb_blank, | |
1450 | .fb_check_var = tridentfb_check_var, | |
1451 | .fb_set_par = tridentfb_set_par, | |
1452 | .fb_fillrect = tridentfb_fillrect, | |
1453 | .fb_copyarea = tridentfb_copyarea, | |
0292be4a | 1454 | .fb_imageblit = tridentfb_imageblit, |
49b1f4b4 | 1455 | .fb_sync = tridentfb_sync, |
245a2c2c KH |
1456 | }; |
1457 | ||
48c68c4f GKH |
1458 | static int trident_pci_probe(struct pci_dev *dev, |
1459 | const struct pci_device_id *id) | |
1da177e4 LT |
1460 | { |
1461 | int err; | |
1462 | unsigned char revision; | |
e09ed099 KH |
1463 | struct fb_info *info; |
1464 | struct tridentfb_par *default_par; | |
122e8ad3 KH |
1465 | int chip3D; |
1466 | int chip_id; | |
6a5e3bd0 | 1467 | bool found = false; |
1da177e4 LT |
1468 | |
1469 | err = pci_enable_device(dev); | |
1470 | if (err) | |
1471 | return err; | |
1472 | ||
e09ed099 KH |
1473 | info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev); |
1474 | if (!info) | |
1475 | return -ENOMEM; | |
1476 | default_par = info->par; | |
1477 | ||
1da177e4 LT |
1478 | chip_id = id->device; |
1479 | ||
1480 | /* If PCI id is 0x9660 then further detect chip type */ | |
245a2c2c | 1481 | |
1da177e4 | 1482 | if (chip_id == TGUI9660) { |
10172ed6 | 1483 | revision = vga_io_rseq(RevisionID); |
245a2c2c | 1484 | |
1da177e4 | 1485 | switch (revision) { |
0e73a47f KH |
1486 | case 0x21: |
1487 | chip_id = PROVIDIA9685; | |
1488 | break; | |
245a2c2c KH |
1489 | case 0x22: |
1490 | case 0x23: | |
1491 | chip_id = CYBER9397; | |
1492 | break; | |
1493 | case 0x2A: | |
1494 | chip_id = CYBER9397DVD; | |
1495 | break; | |
1496 | case 0x30: | |
1497 | case 0x33: | |
1498 | case 0x34: | |
1499 | case 0x35: | |
1500 | case 0x38: | |
1501 | case 0x3A: | |
1502 | case 0xB3: | |
1503 | chip_id = CYBER9385; | |
1504 | break; | |
1505 | case 0x40 ... 0x43: | |
1506 | chip_id = CYBER9382; | |
1507 | break; | |
1508 | case 0x4A: | |
1509 | chip_id = CYBER9388; | |
1510 | break; | |
1511 | default: | |
1512 | break; | |
1da177e4 LT |
1513 | } |
1514 | } | |
1515 | ||
1516 | chip3D = is3Dchip(chip_id); | |
1da177e4 LT |
1517 | |
1518 | if (is_xp(chip_id)) { | |
d9cad04b KH |
1519 | default_par->init_accel = xp_init_accel; |
1520 | default_par->wait_engine = xp_wait_engine; | |
1521 | default_par->fill_rect = xp_fill_rect; | |
1522 | default_par->copy_rect = xp_copy_rect; | |
01a2d9ed | 1523 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP; |
245a2c2c | 1524 | } else if (is_blade(chip_id)) { |
d9cad04b KH |
1525 | default_par->init_accel = blade_init_accel; |
1526 | default_par->wait_engine = blade_wait_engine; | |
1527 | default_par->fill_rect = blade_fill_rect; | |
1528 | default_par->copy_rect = blade_copy_rect; | |
0292be4a | 1529 | default_par->image_blit = blade_image_blit; |
01a2d9ed | 1530 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D; |
bcac2d5f | 1531 | } else if (chip3D) { /* 3DImage family left */ |
d9cad04b KH |
1532 | default_par->init_accel = image_init_accel; |
1533 | default_par->wait_engine = image_wait_engine; | |
1534 | default_par->fill_rect = image_fill_rect; | |
1535 | default_par->copy_rect = image_copy_rect; | |
01a2d9ed | 1536 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE; |
bcac2d5f KH |
1537 | } else { /* TGUI 9440/96XX family */ |
1538 | default_par->init_accel = tgui_init_accel; | |
1539 | default_par->wait_engine = xp_wait_engine; | |
1540 | default_par->fill_rect = tgui_fill_rect; | |
1541 | default_par->copy_rect = tgui_copy_rect; | |
01a2d9ed | 1542 | tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI; |
1da177e4 LT |
1543 | } |
1544 | ||
122e8ad3 KH |
1545 | default_par->chip_id = chip_id; |
1546 | ||
1da177e4 | 1547 | /* setup MMIO region */ |
245a2c2c | 1548 | tridentfb_fix.mmio_start = pci_resource_start(dev, 1); |
5cf13845 | 1549 | tridentfb_fix.mmio_len = pci_resource_len(dev, 1); |
1da177e4 | 1550 | |
5cf13845 KH |
1551 | if (!request_mem_region(tridentfb_fix.mmio_start, |
1552 | tridentfb_fix.mmio_len, "tridentfb")) { | |
1da177e4 | 1553 | debug("request_region failed!\n"); |
3876ae8b | 1554 | framebuffer_release(info); |
1da177e4 LT |
1555 | return -1; |
1556 | } | |
1557 | ||
e09ed099 KH |
1558 | default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start, |
1559 | tridentfb_fix.mmio_len); | |
1da177e4 | 1560 | |
e09ed099 | 1561 | if (!default_par->io_virt) { |
1da177e4 | 1562 | debug("ioremap failed\n"); |
e8ed857c KH |
1563 | err = -1; |
1564 | goto out_unmap1; | |
1da177e4 LT |
1565 | } |
1566 | ||
13b0de49 | 1567 | enable_mmio(default_par); |
bcac2d5f | 1568 | |
1da177e4 | 1569 | /* setup framebuffer memory */ |
245a2c2c | 1570 | tridentfb_fix.smem_start = pci_resource_start(dev, 0); |
e09ed099 | 1571 | tridentfb_fix.smem_len = get_memsize(default_par); |
245a2c2c | 1572 | |
5cf13845 KH |
1573 | if (!request_mem_region(tridentfb_fix.smem_start, |
1574 | tridentfb_fix.smem_len, "tridentfb")) { | |
1da177e4 | 1575 | debug("request_mem_region failed!\n"); |
e09ed099 | 1576 | disable_mmio(info->par); |
a02f6402 | 1577 | err = -1; |
e8ed857c | 1578 | goto out_unmap1; |
1da177e4 LT |
1579 | } |
1580 | ||
e09ed099 KH |
1581 | info->screen_base = ioremap_nocache(tridentfb_fix.smem_start, |
1582 | tridentfb_fix.smem_len); | |
1da177e4 | 1583 | |
e09ed099 | 1584 | if (!info->screen_base) { |
1da177e4 | 1585 | debug("ioremap failed\n"); |
a02f6402 | 1586 | err = -1; |
e8ed857c | 1587 | goto out_unmap2; |
1da177e4 LT |
1588 | } |
1589 | ||
6eed8e1e | 1590 | default_par->flatpanel = is_flatpanel(default_par); |
1da177e4 | 1591 | |
6eed8e1e | 1592 | if (default_par->flatpanel) |
e09ed099 | 1593 | nativex = get_nativex(default_par); |
1da177e4 | 1594 | |
e09ed099 KH |
1595 | info->fix = tridentfb_fix; |
1596 | info->fbops = &tridentfb_ops; | |
aa0aa8ab | 1597 | info->pseudo_palette = default_par->pseudo_pal; |
1da177e4 | 1598 | |
e09ed099 | 1599 | info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN; |
01a2d9ed KH |
1600 | if (!noaccel && default_par->init_accel) { |
1601 | info->flags &= ~FBINFO_HWACCEL_DISABLED; | |
1602 | info->flags |= FBINFO_HWACCEL_COPYAREA; | |
1603 | info->flags |= FBINFO_HWACCEL_FILLRECT; | |
1604 | } else | |
1605 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1606 | ||
ddb53d48 KH |
1607 | if (is_blade(chip_id) && chip_id != BLADE3D) |
1608 | info->flags |= FBINFO_READS_FAST; | |
1609 | ||
0292be4a KH |
1610 | info->pixmap.addr = kmalloc(4096, GFP_KERNEL); |
1611 | if (!info->pixmap.addr) { | |
1612 | err = -ENOMEM; | |
1613 | goto out_unmap2; | |
1614 | } | |
1615 | ||
1616 | info->pixmap.size = 4096; | |
1617 | info->pixmap.buf_align = 4; | |
1618 | info->pixmap.scan_align = 1; | |
1619 | info->pixmap.access_align = 32; | |
1620 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
6a5e3bd0 | 1621 | info->var.bits_per_pixel = 8; |
0292be4a KH |
1622 | |
1623 | if (default_par->image_blit) { | |
1624 | info->flags |= FBINFO_HWACCEL_IMAGEBLIT; | |
1625 | info->pixmap.scan_align = 4; | |
1626 | } | |
1627 | ||
1628 | if (noaccel) { | |
1629 | printk(KERN_DEBUG "disabling acceleration\n"); | |
1630 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1631 | info->pixmap.scan_align = 1; | |
1632 | } | |
1633 | ||
6a5e3bd0 OZ |
1634 | if (tridentfb_setup_ddc_bus(info) == 0) { |
1635 | u8 *edid = fb_ddc_read(&default_par->ddc_adapter); | |
1636 | ||
1637 | default_par->ddc_registered = true; | |
1638 | if (edid) { | |
1639 | fb_edid_to_monspecs(edid, &info->monspecs); | |
1640 | kfree(edid); | |
1641 | if (!info->monspecs.modedb) | |
1642 | dev_err(info->device, "error getting mode database\n"); | |
1643 | else { | |
1644 | const struct fb_videomode *m; | |
1645 | ||
1646 | fb_videomode_to_modelist(info->monspecs.modedb, | |
1647 | info->monspecs.modedb_len, | |
1648 | &info->modelist); | |
1649 | m = fb_find_best_display(&info->monspecs, | |
1650 | &info->modelist); | |
1651 | if (m) { | |
1652 | fb_videomode_to_var(&info->var, m); | |
1653 | /* fill all other info->var's fields */ | |
1654 | if (tridentfb_check_var(&info->var, | |
1655 | info) == 0) | |
1656 | found = true; | |
1657 | } | |
1658 | } | |
1659 | } | |
a02f6402 | 1660 | } |
6a5e3bd0 OZ |
1661 | |
1662 | if (!mode_option && !found) | |
1663 | mode_option = "640x480-8@60"; | |
1664 | ||
1665 | /* Prepare startup mode */ | |
1666 | if (mode_option) { | |
1667 | err = fb_find_mode(&info->var, info, mode_option, | |
1668 | info->monspecs.modedb, | |
1669 | info->monspecs.modedb_len, | |
1670 | NULL, info->var.bits_per_pixel); | |
1671 | if (!err || err == 4) { | |
1672 | err = -EINVAL; | |
1673 | dev_err(info->device, "mode %s not found\n", | |
1674 | mode_option); | |
1675 | fb_destroy_modedb(info->monspecs.modedb); | |
1676 | info->monspecs.modedb = NULL; | |
1677 | goto out_unmap2; | |
1678 | } | |
1679 | } | |
1680 | ||
1681 | fb_destroy_modedb(info->monspecs.modedb); | |
1682 | info->monspecs.modedb = NULL; | |
1683 | ||
e09ed099 | 1684 | err = fb_alloc_cmap(&info->cmap, 256, 0); |
e8ed857c KH |
1685 | if (err < 0) |
1686 | goto out_unmap2; | |
1687 | ||
ea8ee55c | 1688 | info->var.activate |= FB_ACTIVATE_NOW; |
e09ed099 KH |
1689 | info->device = &dev->dev; |
1690 | if (register_framebuffer(info) < 0) { | |
5cf13845 | 1691 | printk(KERN_ERR "tridentfb: could not register framebuffer\n"); |
e09ed099 | 1692 | fb_dealloc_cmap(&info->cmap); |
a02f6402 | 1693 | err = -EINVAL; |
e8ed857c | 1694 | goto out_unmap2; |
1da177e4 LT |
1695 | } |
1696 | output("fb%d: %s frame buffer device %dx%d-%dbpp\n", | |
ea8ee55c KH |
1697 | info->node, info->fix.id, info->var.xres, |
1698 | info->var.yres, info->var.bits_per_pixel); | |
e09ed099 KH |
1699 | |
1700 | pci_set_drvdata(dev, info); | |
1da177e4 | 1701 | return 0; |
a02f6402 | 1702 | |
e8ed857c | 1703 | out_unmap2: |
6a5e3bd0 OZ |
1704 | if (default_par->ddc_registered) |
1705 | i2c_del_adapter(&default_par->ddc_adapter); | |
0292be4a | 1706 | kfree(info->pixmap.addr); |
e09ed099 KH |
1707 | if (info->screen_base) |
1708 | iounmap(info->screen_base); | |
e8ed857c | 1709 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e09ed099 | 1710 | disable_mmio(info->par); |
e8ed857c | 1711 | out_unmap1: |
e09ed099 KH |
1712 | if (default_par->io_virt) |
1713 | iounmap(default_par->io_virt); | |
e8ed857c | 1714 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
e09ed099 | 1715 | framebuffer_release(info); |
a02f6402 | 1716 | return err; |
1da177e4 LT |
1717 | } |
1718 | ||
48c68c4f | 1719 | static void trident_pci_remove(struct pci_dev *dev) |
1da177e4 | 1720 | { |
e09ed099 KH |
1721 | struct fb_info *info = pci_get_drvdata(dev); |
1722 | struct tridentfb_par *par = info->par; | |
1723 | ||
1724 | unregister_framebuffer(info); | |
6a5e3bd0 OZ |
1725 | if (par->ddc_registered) |
1726 | i2c_del_adapter(&par->ddc_adapter); | |
1da177e4 | 1727 | iounmap(par->io_virt); |
e09ed099 | 1728 | iounmap(info->screen_base); |
1da177e4 | 1729 | release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len); |
e8ed857c | 1730 | release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len); |
0292be4a | 1731 | kfree(info->pixmap.addr); |
07b39b49 | 1732 | fb_dealloc_cmap(&info->cmap); |
e09ed099 | 1733 | framebuffer_release(info); |
1da177e4 LT |
1734 | } |
1735 | ||
1736 | /* List of boards that we are trying to support */ | |
bb6a1818 | 1737 | static const struct pci_device_id trident_devices[] = { |
245a2c2c KH |
1738 | {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1739 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1740 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1741 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1742 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1743 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1744 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1745 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
a0d92256 | 1746 | {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
245a2c2c KH |
1747 | {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, |
1748 | {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1749 | {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1750 | {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1751 | {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1752 | {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1753 | {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1754 | {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1755 | {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1756 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1757 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1758 | {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, | |
1da177e4 | 1759 | {0,} |
245a2c2c KH |
1760 | }; |
1761 | ||
1762 | MODULE_DEVICE_TABLE(pci, trident_devices); | |
1da177e4 LT |
1763 | |
1764 | static struct pci_driver tridentfb_pci_driver = { | |
245a2c2c KH |
1765 | .name = "tridentfb", |
1766 | .id_table = trident_devices, | |
1767 | .probe = trident_pci_probe, | |
48c68c4f | 1768 | .remove = trident_pci_remove, |
1da177e4 LT |
1769 | }; |
1770 | ||
1771 | /* | |
1772 | * Parse user specified options (`video=trident:') | |
1773 | * example: | |
245a2c2c | 1774 | * video=trident:800x600,bpp=16,noaccel |
1da177e4 LT |
1775 | */ |
1776 | #ifndef MODULE | |
07f41e45 | 1777 | static int __init tridentfb_setup(char *options) |
1da177e4 | 1778 | { |
245a2c2c | 1779 | char *opt; |
1da177e4 LT |
1780 | if (!options || !*options) |
1781 | return 0; | |
245a2c2c KH |
1782 | while ((opt = strsep(&options, ",")) != NULL) { |
1783 | if (!*opt) | |
1784 | continue; | |
1785 | if (!strncmp(opt, "noaccel", 7)) | |
1da177e4 | 1786 | noaccel = 1; |
245a2c2c | 1787 | else if (!strncmp(opt, "fp", 2)) |
6eed8e1e | 1788 | fp = 1; |
245a2c2c | 1789 | else if (!strncmp(opt, "crt", 3)) |
6eed8e1e | 1790 | fp = 0; |
245a2c2c KH |
1791 | else if (!strncmp(opt, "bpp=", 4)) |
1792 | bpp = simple_strtoul(opt + 4, NULL, 0); | |
1793 | else if (!strncmp(opt, "center", 6)) | |
1da177e4 | 1794 | center = 1; |
245a2c2c | 1795 | else if (!strncmp(opt, "stretch", 7)) |
1da177e4 | 1796 | stretch = 1; |
245a2c2c KH |
1797 | else if (!strncmp(opt, "memsize=", 8)) |
1798 | memsize = simple_strtoul(opt + 8, NULL, 0); | |
1799 | else if (!strncmp(opt, "memdiff=", 8)) | |
1800 | memdiff = simple_strtoul(opt + 8, NULL, 0); | |
1801 | else if (!strncmp(opt, "nativex=", 8)) | |
1802 | nativex = simple_strtoul(opt + 8, NULL, 0); | |
1da177e4 | 1803 | else |
07f41e45 | 1804 | mode_option = opt; |
1da177e4 LT |
1805 | } |
1806 | return 0; | |
1807 | } | |
1808 | #endif | |
1809 | ||
1810 | static int __init tridentfb_init(void) | |
1811 | { | |
1812 | #ifndef MODULE | |
1813 | char *option = NULL; | |
1814 | ||
1815 | if (fb_get_options("tridentfb", &option)) | |
1816 | return -ENODEV; | |
1817 | tridentfb_setup(option); | |
1818 | #endif | |
1da177e4 LT |
1819 | return pci_register_driver(&tridentfb_pci_driver); |
1820 | } | |
1821 | ||
1822 | static void __exit tridentfb_exit(void) | |
1823 | { | |
1824 | pci_unregister_driver(&tridentfb_pci_driver); | |
1825 | } | |
1826 | ||
1da177e4 LT |
1827 | module_init(tridentfb_init); |
1828 | module_exit(tridentfb_exit); | |
1829 | ||
1830 | MODULE_AUTHOR("Jani Monoses <jani@iv.ro>"); | |
1831 | MODULE_DESCRIPTION("Framebuffer driver for Trident cards"); | |
1832 | MODULE_LICENSE("GPL"); | |
ddb53d48 | 1833 | MODULE_ALIAS("cyblafb"); |
1da177e4 | 1834 |