Commit | Line | Data |
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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer | |
4 | * | |
5 | * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net> | |
6 | * | |
7 | * Created 15 Jan 2000 by Ghozlane Toumi | |
8 | * | |
9 | * Contributions (and many thanks) : | |
10 | * | |
11 | * 03/2001 James Simmons <jsimmons@infradead.org> | |
12 | * 04/2001 Paul Mundt <lethal@chaoticdreams.org> | |
13 | * 05/2001 Urs Ganse <ursg@uni.de> | |
14 | * (initial work on voodoo2 port, interlace) | |
15 | * 09/2002 Helge Deller <deller@gmx.de> | |
16 | * (enable driver on big-endian machines (hppa), ioctl fixes) | |
17 | * 12/2002 Helge Deller <deller@gmx.de> | |
18 | * (port driver to new frambuffer infrastructure) | |
19 | * 01/2003 Helge Deller <deller@gmx.de> | |
20 | * (initial work on fb hardware acceleration for voodoo2) | |
b98fc9a3 AC |
21 | * 08/2006 Alan Cox <alan@redhat.com> |
22 | * Remove never finished and bogus 24/32bit support | |
23 | * Clean up macro abuse | |
24 | * Minor tidying for format. | |
0743b868 HD |
25 | * 12/2006 Helge Deller <deller@gmx.de> |
26 | * add /sys/class/graphics/fbX/vgapass sysfs-interface | |
27 | * add module option "mode_option" to set initial screen mode | |
28 | * use fbdev default videomode database | |
29 | * remove debug functions from ioctl | |
1da177e4 LT |
30 | */ |
31 | ||
32 | /* | |
33 | * The voodoo1 has the following memory mapped address space: | |
34 | * 0x000000 - 0x3fffff : registers (4MB) | |
35 | * 0x400000 - 0x7fffff : linear frame buffer (4MB) | |
36 | * 0x800000 - 0xffffff : texture memory (8MB) | |
37 | */ | |
38 | ||
39 | /* | |
40 | * misc notes, TODOs, toASKs, and deep thoughts | |
41 | ||
42 | -TODO: at one time or another test that the mode is acceptable by the monitor | |
43 | -ASK: Can I choose different ordering for the color bitfields (rgba argb ...) | |
c30fe7f7 | 44 | which one should i use ? is there any preferred one ? It seems ARGB is |
1da177e4 LT |
45 | the one ... |
46 | -TODO: in set_var check the validity of timings (hsync vsync)... | |
47 | -TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via | |
48 | a nop command. so it's ok as long as the commands we pass don't go | |
49 | through the fifo. warning: issuing a nop command seems to need pci_fifo | |
50 | -FIXME: in case of failure in the init sequence, be sure we return to a safe | |
51 | state. | |
b98fc9a3 | 52 | - FIXME: Use accelerator for 2D scroll |
1da177e4 LT |
53 | -FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20) |
54 | */ | |
55 | ||
56 | /* | |
57 | * debug info | |
58 | * SST_DEBUG : enable debugging | |
59 | * SST_DEBUG_REG : debug registers | |
60 | * 0 : no debug | |
61 | * 1 : dac calls, [un]set_bits, FbiInit | |
62 | * 2 : insane debug level (log every register read/write) | |
63 | * SST_DEBUG_FUNC : functions | |
64 | * 0 : no debug | |
65 | * 1 : function call / debug ioctl | |
66 | * 2 : variables | |
67 | * 3 : flood . you don't want to do that. trust me. | |
68 | * SST_DEBUG_VAR : debug display/var structs | |
69 | * 0 : no debug | |
70 | * 1 : dumps display, fb_var | |
71 | * | |
72 | * sstfb specific ioctls: | |
73 | * toggle vga (0x46db) : toggle vga_pass_through | |
1da177e4 LT |
74 | */ |
75 | ||
76 | #undef SST_DEBUG | |
77 | ||
1da177e4 LT |
78 | |
79 | /* | |
80 | * Includes | |
81 | */ | |
82 | ||
145eed48 | 83 | #include <linux/aperture.h> |
1da177e4 LT |
84 | #include <linux/string.h> |
85 | #include <linux/kernel.h> | |
86 | #include <linux/module.h> | |
87 | #include <linux/fb.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/delay.h> | |
90 | #include <linux/init.h> | |
1da177e4 | 91 | #include <asm/io.h> |
84902b7a | 92 | #include <linux/uaccess.h> |
1da177e4 LT |
93 | #include <video/sstfb.h> |
94 | ||
95 | ||
96 | /* initialized by setup */ | |
97 | ||
90ab5ee9 | 98 | static bool vgapass; /* enable VGA passthrough cable */ |
1da177e4 | 99 | static int mem; /* mem size in MB, 0 = autodetect */ |
90ab5ee9 | 100 | static bool clipping = 1; /* use clipping (slower, safer) */ |
1da177e4 | 101 | static int gfxclk; /* force FBI freq in Mhz . Dangerous */ |
90ab5ee9 | 102 | static bool slowpci; /* slow PCI settings */ |
1da177e4 | 103 | |
0743b868 HD |
104 | /* |
105 | Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60 | |
106 | */ | |
107 | #define DEFAULT_VIDEO_MODE "640x480@60" | |
108 | ||
48c68c4f | 109 | static char *mode_option = DEFAULT_VIDEO_MODE; |
1da177e4 LT |
110 | |
111 | enum { | |
112 | ID_VOODOO1 = 0, | |
113 | ID_VOODOO2 = 1, | |
114 | }; | |
115 | ||
116 | #define IS_VOODOO2(par) ((par)->type == ID_VOODOO2) | |
117 | ||
48c68c4f | 118 | static struct sst_spec voodoo_spec[] = { |
1da177e4 LT |
119 | { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 }, |
120 | { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 }, | |
121 | }; | |
122 | ||
1da177e4 LT |
123 | |
124 | /* | |
125 | * debug functions | |
126 | */ | |
127 | ||
1da177e4 LT |
128 | #if (SST_DEBUG_REG > 0) |
129 | static void sst_dbg_print_read_reg(u32 reg, u32 val) { | |
130 | const char *regname; | |
131 | switch (reg) { | |
132 | case FBIINIT0: regname = "FbiInit0"; break; | |
133 | case FBIINIT1: regname = "FbiInit1"; break; | |
134 | case FBIINIT2: regname = "FbiInit2"; break; | |
135 | case FBIINIT3: regname = "FbiInit3"; break; | |
136 | case FBIINIT4: regname = "FbiInit4"; break; | |
137 | case FBIINIT5: regname = "FbiInit5"; break; | |
138 | case FBIINIT6: regname = "FbiInit6"; break; | |
139 | default: regname = NULL; break; | |
140 | } | |
141 | if (regname == NULL) | |
142 | r_ddprintk("sst_read(%#x): %#x\n", reg, val); | |
143 | else | |
144 | r_dprintk(" sst_read(%s): %#x\n", regname, val); | |
145 | } | |
146 | ||
147 | static void sst_dbg_print_write_reg(u32 reg, u32 val) { | |
148 | const char *regname; | |
149 | switch (reg) { | |
150 | case FBIINIT0: regname = "FbiInit0"; break; | |
151 | case FBIINIT1: regname = "FbiInit1"; break; | |
152 | case FBIINIT2: regname = "FbiInit2"; break; | |
153 | case FBIINIT3: regname = "FbiInit3"; break; | |
154 | case FBIINIT4: regname = "FbiInit4"; break; | |
155 | case FBIINIT5: regname = "FbiInit5"; break; | |
156 | case FBIINIT6: regname = "FbiInit6"; break; | |
157 | default: regname = NULL; break; | |
158 | } | |
159 | if (regname == NULL) | |
160 | r_ddprintk("sst_write(%#x, %#x)\n", reg, val); | |
161 | else | |
162 | r_dprintk(" sst_write(%s, %#x)\n", regname, val); | |
163 | } | |
164 | #else /* (SST_DEBUG_REG > 0) */ | |
165 | # define sst_dbg_print_read_reg(reg, val) do {} while(0) | |
166 | # define sst_dbg_print_write_reg(reg, val) do {} while(0) | |
167 | #endif /* (SST_DEBUG_REG > 0) */ | |
168 | ||
169 | /* | |
170 | * hardware access functions | |
171 | */ | |
172 | ||
173 | /* register access */ | |
174 | #define sst_read(reg) __sst_read(par->mmio_vbase, reg) | |
175 | #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val) | |
176 | #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val) | |
177 | #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val) | |
178 | #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg) | |
179 | #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val) | |
180 | #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg) | |
181 | #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val) | |
182 | ||
183 | static inline u32 __sst_read(u8 __iomem *vbase, u32 reg) | |
184 | { | |
185 | u32 ret = readl(vbase + reg); | |
186 | sst_dbg_print_read_reg(reg, ret); | |
187 | return ret; | |
188 | } | |
189 | ||
190 | static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val) | |
191 | { | |
192 | sst_dbg_print_write_reg(reg, val); | |
193 | writel(val, vbase + reg); | |
194 | } | |
195 | ||
196 | static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val) | |
197 | { | |
198 | r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val); | |
199 | __sst_write(vbase, reg, __sst_read(vbase, reg) | val); | |
200 | } | |
201 | ||
202 | static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val) | |
203 | { | |
204 | r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val); | |
205 | __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val); | |
206 | } | |
207 | ||
208 | /* | |
209 | * wait for the fbi chip. ASK: what happens if the fbi is stuck ? | |
210 | * | |
211 | * the FBI is supposed to be ready if we receive 5 time | |
212 | * in a row a "idle" answer to our requests | |
213 | */ | |
214 | ||
215 | #define sst_wait_idle() __sst_wait_idle(par->mmio_vbase) | |
216 | ||
217 | static int __sst_wait_idle(u8 __iomem *vbase) | |
218 | { | |
219 | int count = 0; | |
220 | ||
221 | /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */ | |
222 | ||
223 | while(1) { | |
224 | if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) { | |
225 | f_dddprintk("status: busy\n"); | |
25985edc | 226 | /* FIXME basically, this is a busy wait. maybe not that good. oh well; |
1da177e4 LT |
227 | * this is a small loop after all. |
228 | * Or maybe we should use mdelay() or udelay() here instead ? */ | |
229 | count = 0; | |
230 | } else { | |
231 | count++; | |
232 | f_dddprintk("status: idle(%d)\n", count); | |
233 | } | |
234 | if (count >= 5) return 1; | |
235 | /* XXX do something to avoid hanging the machine if the voodoo is out */ | |
236 | } | |
237 | } | |
238 | ||
239 | ||
240 | /* dac access */ | |
241 | /* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */ | |
242 | static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg) | |
243 | { | |
244 | u8 ret; | |
245 | ||
246 | reg &= 0x07; | |
247 | __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD ); | |
248 | __sst_wait_idle(vbase); | |
249 | /* udelay(10); */ | |
250 | ret = __sst_read(vbase, DAC_READ) & 0xff; | |
251 | r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret); | |
252 | ||
253 | return ret; | |
254 | } | |
255 | ||
256 | static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val) | |
257 | { | |
258 | r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val); | |
259 | reg &= 0x07; | |
260 | __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val); | |
e52e15d3 | 261 | __sst_wait_idle(vbase); |
1da177e4 LT |
262 | } |
263 | ||
264 | /* indexed access to ti/att dacs */ | |
265 | static u32 __dac_i_read(u8 __iomem *vbase, u8 reg) | |
266 | { | |
267 | u32 ret; | |
268 | ||
269 | __sst_dac_write(vbase, DACREG_ADDR_I, reg); | |
270 | ret = __sst_dac_read(vbase, DACREG_DATA_I); | |
271 | r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret); | |
272 | return ret; | |
273 | } | |
274 | static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val) | |
275 | { | |
276 | r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val); | |
277 | __sst_dac_write(vbase, DACREG_ADDR_I, reg); | |
278 | __sst_dac_write(vbase, DACREG_DATA_I, val); | |
279 | } | |
280 | ||
281 | /* compute the m,n,p , returns the real freq | |
282 | * (ics datasheet : N <-> N1 , P <-> N2) | |
283 | * | |
284 | * Fout= Fref * (M+2)/( 2^P * (N+2)) | |
285 | * we try to get close to the asked freq | |
286 | * with P as high, and M as low as possible | |
287 | * range: | |
288 | * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63 | |
289 | * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31 | |
290 | * we'll use the lowest limitation, should be precise enouth | |
291 | */ | |
292 | static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t) | |
293 | { | |
294 | int m, m2, n, p, best_err, fout; | |
295 | int best_n = -1; | |
296 | int best_m = -1; | |
297 | ||
298 | best_err = freq; | |
299 | p = 3; | |
300 | /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/ | |
301 | while (((1 << p) * freq > VCO_MAX) && (p >= 0)) | |
302 | p--; | |
303 | if (p == -1) | |
304 | return -EINVAL; | |
305 | for (n = 1; n < 32; n++) { | |
306 | /* calc 2 * m so we can round it later*/ | |
307 | m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ; | |
308 | ||
309 | m = (m2 % 2 ) ? m2/2+1 : m2/2 ; | |
310 | if (m >= 128) | |
311 | break; | |
312 | fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2)); | |
313 | if ((abs(fout - freq) < best_err) && (m > 0)) { | |
314 | best_n = n; | |
315 | best_m = m; | |
316 | best_err = abs(fout - freq); | |
317 | /* we get the lowest m , allowing 0.5% error in freq*/ | |
318 | if (200*best_err < freq) break; | |
319 | } | |
320 | } | |
321 | if (best_n == -1) /* unlikely, but who knows ? */ | |
322 | return -EINVAL; | |
323 | t->p = p; | |
324 | t->n = best_n; | |
325 | t->m = best_m; | |
326 | *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2)); | |
327 | f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n", | |
328 | t->m, t->n, t->p, *freq_out); | |
329 | return 0; | |
330 | } | |
331 | ||
332 | /* | |
333 | * clear lfb screen | |
334 | */ | |
335 | static void sstfb_clear_screen(struct fb_info *info) | |
336 | { | |
337 | /* clear screen */ | |
20d54e48 | 338 | fb_memset_io(info->screen_base, 0, info->fix.smem_len); |
1da177e4 LT |
339 | } |
340 | ||
341 | ||
342 | /** | |
343 | * sstfb_check_var - Optional function. Validates a var passed in. | |
344 | * @var: frame buffer variable screen structure | |
345 | * @info: frame buffer structure that represents a single frame buffer | |
b98fc9a3 AC |
346 | * |
347 | * Limit to the abilities of a single chip as SLI is not supported | |
348 | * by this driver. | |
1da177e4 | 349 | */ |
b98fc9a3 | 350 | |
1da177e4 LT |
351 | static int sstfb_check_var(struct fb_var_screeninfo *var, |
352 | struct fb_info *info) | |
353 | { | |
7227576f | 354 | struct sstfb_par *par = info->par; |
1da177e4 LT |
355 | int hSyncOff = var->xres + var->right_margin + var->left_margin; |
356 | int vSyncOff = var->yres + var->lower_margin + var->upper_margin; | |
357 | int vBackPorch = var->left_margin, yDim = var->yres; | |
358 | int vSyncOn = var->vsync_len; | |
359 | int tiles_in_X, real_length; | |
360 | unsigned int freq; | |
361 | ||
362 | if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) { | |
b98fc9a3 | 363 | printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n", |
1da177e4 LT |
364 | PICOS2KHZ(var->pixclock)); |
365 | return -EINVAL; | |
366 | } | |
367 | var->pixclock = KHZ2PICOS(freq); | |
729d6872 | 368 | |
1da177e4 LT |
369 | if (var->vmode & FB_VMODE_INTERLACED) |
370 | vBackPorch += (vBackPorch % 2); | |
371 | if (var->vmode & FB_VMODE_DOUBLE) { | |
372 | vBackPorch <<= 1; | |
373 | yDim <<=1; | |
374 | vSyncOn <<=1; | |
375 | vSyncOff <<=1; | |
376 | } | |
377 | ||
378 | switch (var->bits_per_pixel) { | |
379 | case 0 ... 16 : | |
380 | var->bits_per_pixel = 16; | |
381 | break; | |
1da177e4 | 382 | default : |
b98fc9a3 | 383 | printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel); |
1da177e4 LT |
384 | return -EINVAL; |
385 | } | |
729d6872 | 386 | |
1da177e4 | 387 | /* validity tests */ |
b98fc9a3 AC |
388 | if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 || |
389 | hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 || | |
390 | vSyncOff <= 0 || vBackPorch <= 0) { | |
1da177e4 LT |
391 | return -EINVAL; |
392 | } | |
393 | ||
394 | if (IS_VOODOO2(par)) { | |
395 | /* Voodoo 2 limits */ | |
729d6872 | 396 | tiles_in_X = (var->xres + 63 ) / 64 * 2; |
1da177e4 | 397 | |
b98fc9a3 AC |
398 | if (var->xres > POW2(11) || yDim >= POW2(11)) { |
399 | printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", | |
1da177e4 LT |
400 | var->xres, var->yres); |
401 | return -EINVAL; | |
402 | } | |
403 | ||
b98fc9a3 AC |
404 | if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) || |
405 | var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) || | |
406 | vSyncOff >= POW2(13) || vBackPorch >= POW2(9) || | |
407 | tiles_in_X >= POW2(6) || tiles_in_X <= 0) { | |
408 | printk(KERN_ERR "sstfb: Unsupported timings\n"); | |
1da177e4 LT |
409 | return -EINVAL; |
410 | } | |
411 | } else { | |
412 | /* Voodoo limits */ | |
413 | tiles_in_X = (var->xres + 63 ) / 64; | |
414 | ||
415 | if (var->vmode) { | |
b98fc9a3 | 416 | printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n", |
1da177e4 LT |
417 | var->vmode); |
418 | return -EINVAL; | |
419 | } | |
b98fc9a3 AC |
420 | if (var->xres > POW2(10) || var->yres >= POW2(10)) { |
421 | printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n", | |
1da177e4 LT |
422 | var->xres, var->yres); |
423 | return -EINVAL; | |
424 | } | |
b98fc9a3 AC |
425 | if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) || |
426 | var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) || | |
427 | vSyncOff >= POW2(12) || vBackPorch >= POW2(8) || | |
428 | tiles_in_X >= POW2(4) || tiles_in_X <= 0) { | |
429 | printk(KERN_ERR "sstfb: Unsupported timings\n"); | |
1da177e4 LT |
430 | return -EINVAL; |
431 | } | |
432 | } | |
433 | ||
434 | /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */ | |
435 | /* FIXME: i don't like this... looks wrong */ | |
436 | real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 ) | |
437 | * ((var->bits_per_pixel == 16) ? 2 : 4); | |
438 | ||
b98fc9a3 AC |
439 | if (real_length * yDim > info->fix.smem_len) { |
440 | printk(KERN_ERR "sstfb: Not enough video memory\n"); | |
1da177e4 LT |
441 | return -ENOMEM; |
442 | } | |
443 | ||
444 | var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT); | |
445 | var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE); | |
446 | var->xoffset = 0; | |
447 | var->yoffset = 0; | |
448 | var->height = -1; | |
449 | var->width = -1; | |
450 | ||
451 | /* | |
452 | * correct the color bit fields | |
453 | */ | |
454 | /* var->{red|green|blue}.msb_right = 0; */ | |
455 | ||
456 | switch (var->bits_per_pixel) { | |
457 | case 16: /* RGB 565 LfbMode 0 */ | |
458 | var->red.length = 5; | |
459 | var->green.length = 6; | |
460 | var->blue.length = 5; | |
461 | var->transp.length = 0; | |
462 | ||
463 | var->red.offset = 11; | |
464 | var->green.offset = 5; | |
465 | var->blue.offset = 0; | |
466 | var->transp.offset = 0; | |
467 | break; | |
1da177e4 LT |
468 | default: |
469 | return -EINVAL; | |
470 | } | |
471 | return 0; | |
472 | } | |
473 | ||
474 | /** | |
475 | * sstfb_set_par - Optional function. Alters the hardware state. | |
476 | * @info: frame buffer structure that represents a single frame buffer | |
477 | */ | |
478 | static int sstfb_set_par(struct fb_info *info) | |
479 | { | |
7227576f | 480 | struct sstfb_par *par = info->par; |
1da177e4 LT |
481 | u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0; |
482 | struct pci_dev *sst_dev = par->dev; | |
483 | unsigned int freq; | |
484 | int ntiles; | |
485 | ||
486 | par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin; | |
487 | ||
488 | par->yDim = info->var.yres; | |
489 | par->vSyncOn = info->var.vsync_len; | |
490 | par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin; | |
491 | par->vBackPorch = info->var.upper_margin; | |
492 | ||
493 | /* We need par->pll */ | |
494 | sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll); | |
495 | ||
496 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
497 | par->vBackPorch += (par->vBackPorch % 2); | |
498 | if (info->var.vmode & FB_VMODE_DOUBLE) { | |
499 | par->vBackPorch <<= 1; | |
500 | par->yDim <<=1; | |
501 | par->vSyncOn <<=1; | |
502 | par->vSyncOff <<=1; | |
503 | } | |
504 | ||
505 | if (IS_VOODOO2(par)) { | |
25985edc | 506 | /* voodoo2 has 32 pixel wide tiles , BUT strange things |
1da177e4 LT |
507 | happen with odd number of tiles */ |
508 | par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2; | |
509 | } else { | |
510 | /* voodoo1 has 64 pixels wide tiles. */ | |
511 | par->tiles_in_X = (info->var.xres + 63 ) / 64; | |
512 | } | |
513 | ||
514 | f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n"); | |
515 | f_ddprintk("%-7d %-8d %-7d %-8d\n", | |
516 | info->var.hsync_len, par->hSyncOff, | |
517 | par->vSyncOn, par->vSyncOff); | |
518 | f_ddprintk("left_margin upper_margin xres yres Freq\n"); | |
519 | f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n", | |
520 | info->var.left_margin, info->var.upper_margin, | |
521 | info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock)); | |
522 | ||
523 | sst_write(NOPCMD, 0); | |
524 | sst_wait_idle(); | |
525 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
526 | sst_set_bits(FBIINIT1, VIDEO_RESET); | |
527 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
528 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
529 | sst_wait_idle(); | |
530 | ||
531 | /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */ | |
532 | ||
533 | sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2)); | |
534 | sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1)); | |
535 | sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); | |
536 | sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn); | |
537 | ||
538 | fbiinit2 = sst_read(FBIINIT2); | |
539 | fbiinit3 = sst_read(FBIINIT3); | |
540 | ||
b595076a | 541 | /* everything is reset. we enable fbiinit2/3 remap : dac access ok */ |
1da177e4 LT |
542 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, |
543 | PCI_EN_INIT_WR | PCI_REMAP_DAC ); | |
544 | ||
545 | par->dac_sw.set_vidmod(info, info->var.bits_per_pixel); | |
546 | ||
547 | /* set video clock */ | |
548 | par->dac_sw.set_pll(info, &par->pll, VID_CLOCK); | |
549 | ||
550 | /* disable fbiinit2/3 remap */ | |
551 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, | |
552 | PCI_EN_INIT_WR); | |
553 | ||
554 | /* restore fbiinit2/3 */ | |
555 | sst_write(FBIINIT2,fbiinit2); | |
556 | sst_write(FBIINIT3,fbiinit3); | |
557 | ||
558 | fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK) | |
559 | | EN_DATA_OE | |
560 | | EN_BLANK_OE | |
561 | | EN_HVSYNC_OE | |
562 | | EN_DCLK_OE | |
563 | /* | (15 << TILES_IN_X_SHIFT) */ | |
564 | | SEL_INPUT_VCLK_2X | |
565 | /* | (2 << VCLK_2X_SEL_DEL_SHIFT) | |
566 | | (2 << VCLK_DEL_SHIFT) */; | |
567 | /* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28) | |
568 | in (near) future set them accordingly to revision + resolution (cf glide) | |
569 | first understand what it stands for :) | |
570 | FIXME: there are some artefacts... check for the vclk_in_delay | |
571 | lets try with 6ns delay in both vclk_out & in... | |
572 | doh... they're still there :\ | |
573 | */ | |
574 | ||
575 | ntiles = par->tiles_in_X; | |
576 | if (IS_VOODOO2(par)) { | |
577 | fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT | |
578 | | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT; | |
579 | /* as the only value of importance for us in fbiinit6 is tiles in X (lsb), | |
580 | and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just | |
581 | write our value. BTW due to the dac unable to read odd number of tiles, this | |
582 | field is always null ... */ | |
583 | fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT; | |
584 | } | |
585 | else | |
586 | fbiinit1 |= ntiles << TILES_IN_X_SHIFT; | |
587 | ||
588 | switch (info->var.bits_per_pixel) { | |
589 | case 16: | |
590 | fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL; | |
591 | break; | |
1da177e4 LT |
592 | default: |
593 | return -EINVAL; | |
594 | } | |
595 | sst_write(FBIINIT1, fbiinit1); | |
596 | if (IS_VOODOO2(par)) { | |
597 | sst_write(FBIINIT6, fbiinit6); | |
598 | fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ; | |
599 | if (info->var.vmode & FB_VMODE_INTERLACED) | |
600 | fbiinit5 |= INTERLACE; | |
601 | if (info->var.vmode & FB_VMODE_DOUBLE) | |
602 | fbiinit5 |= VDOUBLESCAN; | |
603 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) | |
604 | fbiinit5 |= HSYNC_HIGH; | |
605 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) | |
606 | fbiinit5 |= VSYNC_HIGH; | |
607 | sst_write(FBIINIT5, fbiinit5); | |
608 | } | |
609 | sst_wait_idle(); | |
610 | sst_unset_bits(FBIINIT1, VIDEO_RESET); | |
611 | sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
612 | sst_set_bits(FBIINIT2, EN_DRAM_REFRESH); | |
613 | /* disables fbiinit writes */ | |
614 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); | |
615 | ||
616 | /* set lfbmode : set mode + front buffer for reads/writes | |
617 | + disable pipeline */ | |
618 | switch (info->var.bits_per_pixel) { | |
619 | case 16: | |
620 | lfbmode = LFB_565; | |
621 | break; | |
1da177e4 LT |
622 | default: |
623 | return -EINVAL; | |
624 | } | |
625 | ||
626 | #if defined(__BIG_ENDIAN) | |
627 | /* Enable byte-swizzle functionality in hardware. | |
628 | * With this enabled, all our read- and write-accesses to | |
629 | * the voodoo framebuffer can be done in native format, and | |
630 | * the hardware will automatically convert it to little-endian. | |
631 | * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */ | |
632 | lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR | | |
633 | LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD ); | |
634 | #endif | |
729d6872 | 635 | |
1da177e4 LT |
636 | if (clipping) { |
637 | sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE); | |
638 | /* | |
639 | * Set "clipping" dimensions. If clipping is disabled and | |
640 | * writes to offscreen areas of the framebuffer are performed, | |
641 | * the "behaviour is undefined" (_very_ undefined) - Urs | |
642 | */ | |
643 | /* btw, it requires enabling pixel pipeline in LFBMODE . | |
644 | off screen read/writes will just wrap and read/print pixels | |
645 | on screen. Ugly but not that dangerous */ | |
646 | f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n", | |
647 | info->var.xres - 1, par->yDim - 1); | |
648 | ||
649 | sst_write(CLIP_LEFT_RIGHT, info->var.xres); | |
650 | sst_write(CLIP_LOWY_HIGHY, par->yDim); | |
651 | sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE); | |
652 | } else { | |
653 | /* no clipping : direct access, no pipeline */ | |
654 | sst_write(LFBMODE, lfbmode); | |
655 | } | |
656 | return 0; | |
657 | } | |
658 | ||
659 | /** | |
660 | * sstfb_setcolreg - Optional function. Sets a color register. | |
661 | * @regno: hardware colormap register | |
662 | * @red: frame buffer colormap structure | |
663 | * @green: The green value which can be up to 16 bits wide | |
664 | * @blue: The blue value which can be up to 16 bits wide. | |
665 | * @transp: If supported the alpha value which can be up to 16 bits wide. | |
666 | * @info: frame buffer info structure | |
667 | */ | |
668 | static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
669 | u_int transp, struct fb_info *info) | |
670 | { | |
7227576f | 671 | struct sstfb_par *par = info->par; |
1da177e4 LT |
672 | u32 col; |
673 | ||
674 | f_dddprintk("sstfb_setcolreg\n"); | |
675 | f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n", | |
676 | regno, red, green, blue, transp); | |
7227576f AD |
677 | if (regno > 15) |
678 | return 0; | |
1da177e4 LT |
679 | |
680 | red >>= (16 - info->var.red.length); | |
681 | green >>= (16 - info->var.green.length); | |
682 | blue >>= (16 - info->var.blue.length); | |
683 | transp >>= (16 - info->var.transp.length); | |
684 | col = (red << info->var.red.offset) | |
685 | | (green << info->var.green.offset) | |
686 | | (blue << info->var.blue.offset) | |
687 | | (transp << info->var.transp.offset); | |
729d6872 | 688 | |
7227576f | 689 | par->palette[regno] = col; |
1da177e4 LT |
690 | |
691 | return 0; | |
692 | } | |
693 | ||
0743b868 | 694 | static void sstfb_setvgapass( struct fb_info *info, int enable ) |
1da177e4 | 695 | { |
7227576f | 696 | struct sstfb_par *par = info->par; |
1da177e4 | 697 | struct pci_dev *sst_dev = par->dev; |
0743b868 HD |
698 | u32 fbiinit0, tmp; |
699 | ||
700 | enable = enable ? 1:0; | |
701 | if (par->vgapass == enable) | |
702 | return; | |
703 | par->vgapass = enable; | |
704 | ||
705 | pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp); | |
706 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, | |
707 | tmp | PCI_EN_INIT_WR ); | |
708 | fbiinit0 = sst_read (FBIINIT0); | |
709 | if (par->vgapass) { | |
710 | sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH); | |
31b6780c | 711 | fb_info(info, "Enabling VGA pass-through\n"); |
0743b868 HD |
712 | } else { |
713 | sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH); | |
31b6780c | 714 | fb_info(info, "Disabling VGA pass-through\n"); |
0743b868 HD |
715 | } |
716 | pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp); | |
717 | } | |
718 | ||
719 | static ssize_t store_vgapass(struct device *device, struct device_attribute *attr, | |
720 | const char *buf, size_t count) | |
721 | { | |
722 | struct fb_info *info = dev_get_drvdata(device); | |
723 | char ** last = NULL; | |
724 | int val; | |
725 | ||
726 | val = simple_strtoul(buf, last, 0); | |
727 | sstfb_setvgapass(info, val); | |
728 | ||
729 | return count; | |
730 | } | |
731 | ||
732 | static ssize_t show_vgapass(struct device *device, struct device_attribute *attr, | |
733 | char *buf) | |
734 | { | |
735 | struct fb_info *info = dev_get_drvdata(device); | |
736 | struct sstfb_par *par = info->par; | |
3f614236 | 737 | return sprintf(buf, "%d\n", par->vgapass); |
0743b868 HD |
738 | } |
739 | ||
740 | static struct device_attribute device_attrs[] = { | |
741 | __ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass) | |
742 | }; | |
743 | ||
744 | static int sstfb_ioctl(struct fb_info *info, unsigned int cmd, | |
745 | unsigned long arg) | |
746 | { | |
747 | struct sstfb_par *par; | |
748 | u32 val; | |
1da177e4 LT |
749 | |
750 | switch (cmd) { | |
0743b868 HD |
751 | /* set/get VGA pass_through mode */ |
752 | case SSTFB_SET_VGAPASS: | |
1da177e4 LT |
753 | if (copy_from_user(&val, (void __user *)arg, sizeof(val))) |
754 | return -EFAULT; | |
0743b868 | 755 | sstfb_setvgapass(info, val); |
1da177e4 | 756 | return 0; |
0743b868 HD |
757 | case SSTFB_GET_VGAPASS: |
758 | par = info->par; | |
759 | val = par->vgapass; | |
760 | if (copy_to_user((void __user *)arg, &val, sizeof(val))) | |
1da177e4 | 761 | return -EFAULT; |
1da177e4 LT |
762 | return 0; |
763 | } | |
0743b868 | 764 | |
1da177e4 LT |
765 | return -EINVAL; |
766 | } | |
767 | ||
768 | ||
769 | /* | |
770 | * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only | |
771 | */ | |
772 | #if 0 | |
773 | static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area) | |
774 | { | |
7227576f | 775 | struct sstfb_par *par = info->par; |
1da177e4 | 776 | u32 stride = info->fix.line_length; |
729d6872 | 777 | |
1da177e4 LT |
778 | if (!IS_VOODOO2(par)) |
779 | return; | |
780 | ||
781 | sst_write(BLTSRCBASEADDR, 0); | |
782 | sst_write(BLTDSTBASEADDR, 0); | |
783 | sst_write(BLTROP, BLTROP_COPY); | |
784 | sst_write(BLTXYSTRIDES, stride | (stride << 16)); | |
785 | sst_write(BLTSRCXY, area->sx | (area->sy << 16)); | |
786 | sst_write(BLTDSTXY, area->dx | (area->dy << 16)); | |
787 | sst_write(BLTSIZE, area->width | (area->height << 16)); | |
788 | sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT | | |
789 | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) ); | |
790 | sst_wait_idle(); | |
791 | } | |
792 | #endif | |
793 | ||
794 | ||
795 | /* | |
796 | * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only | |
797 | */ | |
0743b868 | 798 | #if 0 |
729d6872 | 799 | static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) |
1da177e4 | 800 | { |
7227576f | 801 | struct sstfb_par *par = info->par; |
1da177e4 LT |
802 | u32 stride = info->fix.line_length; |
803 | ||
804 | if (!IS_VOODOO2(par)) | |
805 | return; | |
729d6872 | 806 | |
1da177e4 LT |
807 | sst_write(BLTCLIPX, info->var.xres); |
808 | sst_write(BLTCLIPY, info->var.yres); | |
729d6872 | 809 | |
1da177e4 LT |
810 | sst_write(BLTDSTBASEADDR, 0); |
811 | sst_write(BLTCOLOR, rect->color); | |
812 | sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR); | |
813 | sst_write(BLTXYSTRIDES, stride | (stride << 16)); | |
814 | sst_write(BLTDSTXY, rect->dx | (rect->dy << 16)); | |
815 | sst_write(BLTSIZE, rect->width | (rect->height << 16)); | |
816 | sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT | |
817 | | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) ); | |
818 | sst_wait_idle(); | |
819 | } | |
0743b868 | 820 | #endif |
1da177e4 LT |
821 | |
822 | ||
823 | ||
729d6872 TZ |
824 | /* |
825 | * get lfb size | |
1da177e4 | 826 | */ |
48c68c4f | 827 | static int sst_get_memsize(struct fb_info *info, __u32 *memsize) |
1da177e4 LT |
828 | { |
829 | u8 __iomem *fbbase_virt = info->screen_base; | |
830 | ||
831 | /* force memsize */ | |
b98fc9a3 | 832 | if (mem >= 1 && mem <= 4) { |
1da177e4 | 833 | *memsize = (mem * 0x100000); |
b98fc9a3 | 834 | printk(KERN_INFO "supplied memsize: %#x\n", *memsize); |
1da177e4 LT |
835 | return 1; |
836 | } | |
837 | ||
838 | writel(0xdeadbeef, fbbase_virt); | |
839 | writel(0xdeadbeef, fbbase_virt+0x100000); | |
840 | writel(0xdeadbeef, fbbase_virt+0x200000); | |
841 | f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", | |
842 | readl(fbbase_virt), readl(fbbase_virt + 0x100000), | |
843 | readl(fbbase_virt + 0x200000)); | |
844 | ||
845 | writel(0xabcdef01, fbbase_virt); | |
846 | ||
847 | f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n", | |
848 | readl(fbbase_virt), readl(fbbase_virt + 0x100000), | |
849 | readl(fbbase_virt + 0x200000)); | |
850 | ||
851 | /* checks for 4mb lfb, then 2, then defaults to 1 */ | |
852 | if (readl(fbbase_virt + 0x200000) == 0xdeadbeef) | |
853 | *memsize = 0x400000; | |
854 | else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef) | |
855 | *memsize = 0x200000; | |
856 | else | |
857 | *memsize = 0x100000; | |
858 | f_ddprintk("detected memsize: %dMB\n", *memsize >> 20); | |
859 | return 1; | |
860 | } | |
861 | ||
862 | ||
729d6872 TZ |
863 | /* |
864 | * DAC detection routines | |
1da177e4 LT |
865 | */ |
866 | ||
867 | /* fbi should be idle, and fifo emty and mem disabled */ | |
868 | /* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */ | |
869 | ||
48c68c4f | 870 | static int sst_detect_att(struct fb_info *info) |
1da177e4 | 871 | { |
7227576f | 872 | struct sstfb_par *par = info->par; |
1da177e4 LT |
873 | int i, mir, dir; |
874 | ||
b98fc9a3 | 875 | for (i = 0; i < 3; i++) { |
1da177e4 LT |
876 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ |
877 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
878 | sst_dac_read(DACREG_RMR); | |
879 | sst_dac_read(DACREG_RMR); | |
880 | sst_dac_read(DACREG_RMR); | |
881 | /* the fifth time, CR0 is read */ | |
882 | sst_dac_read(DACREG_RMR); | |
883 | /* the 6th, manufacturer id register */ | |
884 | mir = sst_dac_read(DACREG_RMR); | |
885 | /*the 7th, device ID register */ | |
886 | dir = sst_dac_read(DACREG_RMR); | |
887 | f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); | |
b98fc9a3 | 888 | if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) { |
1da177e4 LT |
889 | return 1; |
890 | } | |
891 | } | |
892 | return 0; | |
893 | } | |
894 | ||
48c68c4f | 895 | static int sst_detect_ti(struct fb_info *info) |
1da177e4 | 896 | { |
7227576f | 897 | struct sstfb_par *par = info->par; |
1da177e4 LT |
898 | int i, mir, dir; |
899 | ||
900 | for (i = 0; i<3; i++) { | |
901 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
902 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
903 | sst_dac_read(DACREG_RMR); | |
904 | sst_dac_read(DACREG_RMR); | |
905 | sst_dac_read(DACREG_RMR); | |
906 | /* the fifth time, CR0 is read */ | |
907 | sst_dac_read(DACREG_RMR); | |
908 | /* the 6th, manufacturer id register */ | |
909 | mir = sst_dac_read(DACREG_RMR); | |
910 | /*the 7th, device ID register */ | |
911 | dir = sst_dac_read(DACREG_RMR); | |
912 | f_ddprintk("mir: %#x, dir: %#x\n", mir, dir); | |
913 | if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) { | |
914 | return 1; | |
915 | } | |
916 | } | |
917 | return 0; | |
918 | } | |
919 | ||
920 | /* | |
921 | * try to detect ICS5342 ramdac | |
922 | * we get the 1st byte (M value) of preset f1,f7 and fB | |
923 | * why those 3 ? mmmh... for now, i'll do it the glide way... | |
924 | * and ask questions later. anyway, it seems that all the freq registers are | |
25985edc | 925 | * really at their default state (cf specs) so i ask again, why those 3 regs ? |
1da177e4 LT |
926 | * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for |
927 | * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be | |
928 | * touched... | |
25985edc | 929 | * is it really safe ? how can i reset this ramdac ? geee... |
1da177e4 | 930 | */ |
48c68c4f | 931 | static int sst_detect_ics(struct fb_info *info) |
1da177e4 | 932 | { |
7227576f | 933 | struct sstfb_par *par = info->par; |
1da177e4 LT |
934 | int m_clk0_1, m_clk0_7, m_clk1_b; |
935 | int n_clk0_1, n_clk0_7, n_clk1_b; | |
936 | int i; | |
937 | ||
938 | for (i = 0; i<5; i++ ) { | |
939 | sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */ | |
940 | m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); | |
941 | n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA); | |
942 | sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */ | |
943 | m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); | |
944 | n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA); | |
945 | sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */ | |
946 | m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); | |
947 | n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA); | |
948 | f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n", | |
949 | m_clk0_1, m_clk0_7, m_clk1_b); | |
950 | f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n", | |
951 | n_clk0_1, n_clk0_7, n_clk1_b); | |
952 | if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI) | |
953 | && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI) | |
954 | && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) { | |
955 | return 1; | |
956 | } | |
957 | } | |
958 | return 0; | |
959 | } | |
960 | ||
961 | ||
962 | /* | |
963 | * gfx, video, pci fifo should be reset, dram refresh disabled | |
964 | * see detect_dac | |
965 | */ | |
966 | ||
729d6872 | 967 | static int sst_set_pll_att_ti(struct fb_info *info, |
1da177e4 LT |
968 | const struct pll_timing *t, const int clock) |
969 | { | |
7227576f | 970 | struct sstfb_par *par = info->par; |
1da177e4 LT |
971 | u8 cr0, cc; |
972 | ||
973 | /* enable indexed mode */ | |
974 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
975 | sst_dac_read(DACREG_RMR); /* 1 time: RMR */ | |
976 | sst_dac_read(DACREG_RMR); /* 2 RMR */ | |
977 | sst_dac_read(DACREG_RMR); /* 3 // */ | |
978 | sst_dac_read(DACREG_RMR); /* 4 // */ | |
979 | cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */ | |
980 | ||
981 | sst_dac_write(DACREG_WMA, 0); | |
982 | sst_dac_read(DACREG_RMR); | |
983 | sst_dac_read(DACREG_RMR); | |
984 | sst_dac_read(DACREG_RMR); | |
985 | sst_dac_read(DACREG_RMR); | |
986 | sst_dac_write(DACREG_RMR, (cr0 & 0xf0) | |
987 | | DACREG_CR0_EN_INDEXED | |
988 | | DACREG_CR0_8BIT | |
989 | | DACREG_CR0_PWDOWN ); | |
990 | /* so, now we are in indexed mode . dunno if its common, but | |
991 | i find this way of doing things a little bit weird :p */ | |
992 | ||
993 | udelay(300); | |
994 | cc = dac_i_read(DACREG_CC_I); | |
995 | switch (clock) { | |
996 | case VID_CLOCK: | |
997 | dac_i_write(DACREG_AC0_I, t->m); | |
998 | dac_i_write(DACREG_AC1_I, t->p << 6 | t->n); | |
999 | dac_i_write(DACREG_CC_I, | |
1000 | (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C); | |
1001 | break; | |
1002 | case GFX_CLOCK: | |
1003 | dac_i_write(DACREG_BD0_I, t->m); | |
1004 | dac_i_write(DACREG_BD1_I, t->p << 6 | t->n); | |
1005 | dac_i_write(DACREG_CC_I, | |
1006 | (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D); | |
1007 | break; | |
1008 | default: | |
1009 | dprintk("%s: wrong clock code '%d'\n", | |
5ae12170 | 1010 | __func__, clock); |
1da177e4 LT |
1011 | return 0; |
1012 | } | |
1013 | udelay(300); | |
1014 | ||
1015 | /* power up the dac & return to "normal" non-indexed mode */ | |
1016 | dac_i_write(DACREG_CR0_I, | |
1017 | cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED); | |
1018 | return 1; | |
1019 | } | |
1020 | ||
1021 | static int sst_set_pll_ics(struct fb_info *info, | |
1022 | const struct pll_timing *t, const int clock) | |
1023 | { | |
7227576f | 1024 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1025 | u8 pll_ctrl; |
1026 | ||
1027 | sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL); | |
1028 | pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); | |
1029 | switch(clock) { | |
1030 | case VID_CLOCK: | |
1031 | sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */ | |
1032 | sst_dac_write(DACREG_ICS_PLLDATA, t->m); | |
1033 | sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); | |
1034 | /* selects freq f0 for clock 0 */ | |
1035 | sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); | |
1036 | sst_dac_write(DACREG_ICS_PLLDATA, | |
1037 | (pll_ctrl & 0xd8) | |
1038 | | DACREG_ICS_CLK0 | |
1039 | | DACREG_ICS_CLK0_0); | |
1040 | break; | |
1041 | case GFX_CLOCK : | |
1042 | sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */ | |
1043 | sst_dac_write(DACREG_ICS_PLLDATA, t->m); | |
1044 | sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n); | |
1045 | /* selects freq fA for clock 1 */ | |
1046 | sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL); | |
1047 | sst_dac_write(DACREG_ICS_PLLDATA, | |
1048 | (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); | |
1049 | break; | |
1050 | default: | |
1051 | dprintk("%s: wrong clock code '%d'\n", | |
5ae12170 | 1052 | __func__, clock); |
1da177e4 LT |
1053 | return 0; |
1054 | } | |
1055 | udelay(300); | |
1056 | return 1; | |
1057 | } | |
1058 | ||
1059 | static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp) | |
1060 | { | |
7227576f | 1061 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1062 | u8 cr0; |
1063 | ||
1064 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
1065 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
1066 | sst_dac_read(DACREG_RMR); | |
1067 | sst_dac_read(DACREG_RMR); | |
1068 | sst_dac_read(DACREG_RMR); | |
1069 | /* the fifth time, CR0 is read */ | |
1070 | cr0 = sst_dac_read(DACREG_RMR); | |
1071 | ||
1072 | sst_dac_write(DACREG_WMA, 0); /* backdoor */ | |
1073 | sst_dac_read(DACREG_RMR); /* read 4 times RMR */ | |
1074 | sst_dac_read(DACREG_RMR); | |
1075 | sst_dac_read(DACREG_RMR); | |
1076 | sst_dac_read(DACREG_RMR); | |
1077 | /* cr0 */ | |
1078 | switch(bpp) { | |
1079 | case 16: | |
1080 | sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP); | |
1081 | break; | |
1da177e4 | 1082 | default: |
5ae12170 | 1083 | dprintk("%s: bad depth '%u'\n", __func__, bpp); |
1da177e4 LT |
1084 | break; |
1085 | } | |
1086 | } | |
1087 | ||
1088 | static void sst_set_vidmod_ics(struct fb_info *info, const int bpp) | |
1089 | { | |
7227576f | 1090 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1091 | |
1092 | switch(bpp) { | |
1093 | case 16: | |
1094 | sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP); | |
1095 | break; | |
1da177e4 | 1096 | default: |
5ae12170 | 1097 | dprintk("%s: bad depth '%u'\n", __func__, bpp); |
1da177e4 LT |
1098 | break; |
1099 | } | |
1100 | } | |
1101 | ||
1102 | /* | |
1103 | * detect dac type | |
1104 | * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset, | |
1105 | * dram refresh disabled, FbiInit remaped. | |
c9404c9c | 1106 | * TODO: mmh.. maybe i should put the "prerequisite" in the func ... |
1da177e4 LT |
1107 | */ |
1108 | ||
1109 | ||
48c68c4f | 1110 | static struct dac_switch dacs[] = { |
1da177e4 LT |
1111 | { .name = "TI TVP3409", |
1112 | .detect = sst_detect_ti, | |
1113 | .set_pll = sst_set_pll_att_ti, | |
1114 | .set_vidmod = sst_set_vidmod_att_ti }, | |
1115 | ||
1116 | { .name = "AT&T ATT20C409", | |
1117 | .detect = sst_detect_att, | |
1118 | .set_pll = sst_set_pll_att_ti, | |
1119 | .set_vidmod = sst_set_vidmod_att_ti }, | |
1120 | { .name = "ICS ICS5342", | |
1121 | .detect = sst_detect_ics, | |
1122 | .set_pll = sst_set_pll_ics, | |
1123 | .set_vidmod = sst_set_vidmod_ics }, | |
1124 | }; | |
1125 | ||
48c68c4f | 1126 | static int sst_detect_dactype(struct fb_info *info, struct sstfb_par *par) |
1da177e4 LT |
1127 | { |
1128 | int i, ret = 0; | |
d1ae418e TK |
1129 | |
1130 | for (i = 0; i < ARRAY_SIZE(dacs); i++) { | |
1da177e4 | 1131 | ret = dacs[i].detect(info); |
d1ae418e TK |
1132 | if (ret) |
1133 | break; | |
1da177e4 LT |
1134 | } |
1135 | if (!ret) | |
1136 | return 0; | |
5ae12170 | 1137 | f_dprintk("%s found %s\n", __func__, dacs[i].name); |
1da177e4 LT |
1138 | par->dac_sw = dacs[i]; |
1139 | return 1; | |
1140 | } | |
1141 | ||
1142 | /* | |
1143 | * Internal Routines | |
1144 | */ | |
48c68c4f | 1145 | static int sst_init(struct fb_info *info, struct sstfb_par *par) |
1da177e4 LT |
1146 | { |
1147 | u32 fbiinit0, fbiinit1, fbiinit4; | |
1148 | struct pci_dev *dev = par->dev; | |
1149 | struct pll_timing gfx_timings; | |
1150 | struct sst_spec *spec; | |
1151 | int Fout; | |
0743b868 | 1152 | int gfx_clock; |
1da177e4 LT |
1153 | |
1154 | spec = &voodoo_spec[par->type]; | |
1155 | f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 " | |
1156 | " fbiinit6\n"); | |
1157 | f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n", | |
1158 | sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2), | |
1159 | sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6)); | |
1160 | /* disable video clock */ | |
1161 | pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0); | |
1162 | ||
1163 | /* enable writing to init registers, disable pci fifo */ | |
1164 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
1165 | /* reset video */ | |
1166 | sst_set_bits(FBIINIT1, VIDEO_RESET); | |
1167 | sst_wait_idle(); | |
1168 | /* reset gfx + pci fifo */ | |
1169 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
1170 | sst_wait_idle(); | |
1171 | ||
1172 | /* unreset fifo */ | |
1173 | /*sst_unset_bits(FBIINIT0, FIFO_RESET); | |
1174 | sst_wait_idle();*/ | |
1175 | /* unreset FBI */ | |
1176 | /*sst_unset_bits(FBIINIT0, FBI_RESET); | |
1177 | sst_wait_idle();*/ | |
1178 | ||
1179 | /* disable dram refresh */ | |
1180 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
1181 | sst_wait_idle(); | |
1182 | /* remap fbinit2/3 to dac */ | |
1183 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1184 | PCI_EN_INIT_WR | PCI_REMAP_DAC ); | |
1185 | /* detect dac type */ | |
1186 | if (!sst_detect_dactype(info, par)) { | |
b98fc9a3 | 1187 | printk(KERN_ERR "sstfb: unknown dac type.\n"); |
1da177e4 LT |
1188 | //FIXME watch it: we are not in a safe state, bad bad bad. |
1189 | return 0; | |
1190 | } | |
1191 | ||
1192 | /* set graphic clock */ | |
0743b868 | 1193 | gfx_clock = spec->default_gfx_clock; |
1da177e4 | 1194 | if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) { |
b98fc9a3 | 1195 | printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk); |
0743b868 | 1196 | gfx_clock = gfxclk *1000; |
1da177e4 | 1197 | } else if (gfxclk) { |
b98fc9a3 | 1198 | printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk); |
1da177e4 LT |
1199 | } |
1200 | ||
0743b868 | 1201 | sst_calc_pll(gfx_clock, &Fout, &gfx_timings); |
1da177e4 LT |
1202 | par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); |
1203 | ||
1204 | /* disable fbiinit remap */ | |
1205 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1206 | PCI_EN_INIT_WR| PCI_EN_FIFO_WR ); | |
1207 | /* defaults init registers */ | |
1208 | /* FbiInit0: unreset gfx, unreset fifo */ | |
1209 | fbiinit0 = FBIINIT0_DEFAULT; | |
1210 | fbiinit1 = FBIINIT1_DEFAULT; | |
1211 | fbiinit4 = FBIINIT4_DEFAULT; | |
0743b868 HD |
1212 | par->vgapass = vgapass; |
1213 | if (par->vgapass) | |
1214 | fbiinit0 &= ~DIS_VGA_PASSTHROUGH; | |
1da177e4 | 1215 | else |
0743b868 | 1216 | fbiinit0 |= DIS_VGA_PASSTHROUGH; |
1da177e4 LT |
1217 | if (slowpci) { |
1218 | fbiinit1 |= SLOW_PCI_WRITES; | |
1219 | fbiinit4 |= SLOW_PCI_READS; | |
1220 | } else { | |
1221 | fbiinit1 &= ~SLOW_PCI_WRITES; | |
1222 | fbiinit4 &= ~SLOW_PCI_READS; | |
1223 | } | |
1224 | sst_write(FBIINIT0, fbiinit0); | |
1225 | sst_wait_idle(); | |
1226 | sst_write(FBIINIT1, fbiinit1); | |
1227 | sst_wait_idle(); | |
1228 | sst_write(FBIINIT2, FBIINIT2_DEFAULT); | |
1229 | sst_wait_idle(); | |
1230 | sst_write(FBIINIT3, FBIINIT3_DEFAULT); | |
1231 | sst_wait_idle(); | |
1232 | sst_write(FBIINIT4, fbiinit4); | |
1233 | sst_wait_idle(); | |
1234 | if (IS_VOODOO2(par)) { | |
1235 | sst_write(FBIINIT6, FBIINIT6_DEFAULT); | |
1236 | sst_wait_idle(); | |
1237 | } | |
1238 | ||
1239 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR); | |
1240 | pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0); | |
1241 | return 1; | |
1242 | } | |
1243 | ||
48c68c4f | 1244 | static void sst_shutdown(struct fb_info *info) |
1da177e4 | 1245 | { |
7227576f | 1246 | struct sstfb_par *par = info->par; |
1da177e4 LT |
1247 | struct pci_dev *dev = par->dev; |
1248 | struct pll_timing gfx_timings; | |
1249 | int Fout; | |
1250 | ||
1251 | /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */ | |
1252 | pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR); | |
1253 | sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING); | |
1254 | sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH); | |
1255 | sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET); | |
1256 | sst_wait_idle(); | |
1257 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1258 | PCI_EN_INIT_WR | PCI_REMAP_DAC); | |
1259 | /* set 20Mhz gfx clock */ | |
1260 | sst_calc_pll(20000, &Fout, &gfx_timings); | |
1261 | par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK); | |
1262 | /* TODO maybe shutdown the dac, vrefresh and so on... */ | |
1263 | pci_write_config_dword(dev, PCI_INIT_ENABLE, | |
1264 | PCI_EN_INIT_WR); | |
0743b868 | 1265 | sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH); |
1da177e4 LT |
1266 | pci_write_config_dword(dev, PCI_VCLK_DISABLE,0); |
1267 | /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct | |
1268 | * from start ? */ | |
1269 | pci_write_config_dword(dev, PCI_INIT_ENABLE, 0); | |
1270 | ||
1271 | } | |
1272 | ||
1273 | /* | |
1274 | * Interface to the world | |
1275 | */ | |
48c68c4f | 1276 | static int sstfb_setup(char *options) |
1da177e4 LT |
1277 | { |
1278 | char *this_opt; | |
1279 | ||
1280 | if (!options || !*options) | |
1281 | return 0; | |
1282 | ||
1283 | while ((this_opt = strsep(&options, ",")) != NULL) { | |
1284 | if (!*this_opt) continue; | |
1285 | ||
1286 | f_ddprintk("option %s\n", this_opt); | |
1287 | ||
1288 | if (!strcmp(this_opt, "vganopass")) | |
1289 | vgapass = 0; | |
1290 | else if (!strcmp(this_opt, "vgapass")) | |
1291 | vgapass = 1; | |
1292 | else if (!strcmp(this_opt, "clipping")) | |
1293 | clipping = 1; | |
1294 | else if (!strcmp(this_opt, "noclipping")) | |
1295 | clipping = 0; | |
1296 | else if (!strcmp(this_opt, "fastpci")) | |
1297 | slowpci = 0; | |
1298 | else if (!strcmp(this_opt, "slowpci")) | |
1299 | slowpci = 1; | |
1300 | else if (!strncmp(this_opt, "mem:",4)) | |
1301 | mem = simple_strtoul (this_opt+4, NULL, 0); | |
1302 | else if (!strncmp(this_opt, "gfxclk:",7)) | |
1303 | gfxclk = simple_strtoul (this_opt+7, NULL, 0); | |
1304 | else | |
1305 | mode_option = this_opt; | |
1306 | } | |
1307 | return 0; | |
1308 | } | |
0743b868 | 1309 | |
1da177e4 | 1310 | |
8a48ac33 | 1311 | static const struct fb_ops sstfb_ops = { |
1da177e4 | 1312 | .owner = THIS_MODULE, |
99df80c7 | 1313 | FB_DEFAULT_IOMEM_OPS, |
1da177e4 LT |
1314 | .fb_check_var = sstfb_check_var, |
1315 | .fb_set_par = sstfb_set_par, | |
1316 | .fb_setcolreg = sstfb_setcolreg, | |
1da177e4 LT |
1317 | .fb_ioctl = sstfb_ioctl, |
1318 | }; | |
1319 | ||
48c68c4f | 1320 | static int sstfb_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1da177e4 LT |
1321 | { |
1322 | struct fb_info *info; | |
1323 | struct fb_fix_screeninfo *fix; | |
1324 | struct sstfb_par *par; | |
1325 | struct sst_spec *spec; | |
1326 | int err; | |
1327 | ||
145eed48 TZ |
1328 | err = aperture_remove_conflicting_pci_devices(pdev, "sstfb"); |
1329 | if (err) | |
1330 | return err; | |
1331 | ||
1da177e4 LT |
1332 | /* Enable device in PCI config. */ |
1333 | if ((err=pci_enable_device(pdev))) { | |
b98fc9a3 | 1334 | printk(KERN_ERR "cannot enable device\n"); |
1da177e4 LT |
1335 | return err; |
1336 | } | |
1337 | ||
1338 | /* Allocate the fb and par structures. */ | |
7227576f AD |
1339 | info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev); |
1340 | if (!info) | |
1da177e4 | 1341 | return -ENOMEM; |
7227576f AD |
1342 | |
1343 | pci_set_drvdata(pdev, info); | |
729d6872 | 1344 | |
7227576f | 1345 | par = info->par; |
1da177e4 | 1346 | fix = &info->fix; |
729d6872 | 1347 | |
1da177e4 LT |
1348 | par->type = id->driver_data; |
1349 | spec = &voodoo_spec[par->type]; | |
1350 | f_ddprintk("found device : %s\n", spec->name); | |
1351 | ||
1352 | par->dev = pdev; | |
44c10138 | 1353 | par->revision = pdev->revision; |
1da177e4 LT |
1354 | |
1355 | fix->mmio_start = pci_resource_start(pdev,0); | |
1356 | fix->mmio_len = 0x400000; | |
1357 | fix->smem_start = fix->mmio_start + 0x400000; | |
1358 | ||
1359 | if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) { | |
b98fc9a3 | 1360 | printk(KERN_ERR "sstfb: cannot reserve mmio memory\n"); |
1da177e4 LT |
1361 | goto fail_mmio_mem; |
1362 | } | |
1363 | ||
1364 | if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) { | |
b98fc9a3 | 1365 | printk(KERN_ERR "sstfb: cannot reserve fb memory\n"); |
1da177e4 LT |
1366 | goto fail_fb_mem; |
1367 | } | |
1368 | ||
4bdc0d67 | 1369 | par->mmio_vbase = ioremap(fix->mmio_start, |
1da177e4 LT |
1370 | fix->mmio_len); |
1371 | if (!par->mmio_vbase) { | |
b98fc9a3 | 1372 | printk(KERN_ERR "sstfb: cannot remap register area %#lx\n", |
1da177e4 LT |
1373 | fix->mmio_start); |
1374 | goto fail_mmio_remap; | |
1375 | } | |
4bdc0d67 | 1376 | info->screen_base = ioremap(fix->smem_start, 0x400000); |
1da177e4 | 1377 | if (!info->screen_base) { |
b98fc9a3 | 1378 | printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n", |
1da177e4 LT |
1379 | fix->smem_start); |
1380 | goto fail_fb_remap; | |
1381 | } | |
1382 | ||
1383 | if (!sst_init(info, par)) { | |
b98fc9a3 | 1384 | printk(KERN_ERR "sstfb: Init failed\n"); |
1da177e4 LT |
1385 | goto fail; |
1386 | } | |
1387 | sst_get_memsize(info, &fix->smem_len); | |
8d026858 | 1388 | strscpy(fix->id, spec->name, sizeof(fix->id)); |
1da177e4 | 1389 | |
b98fc9a3 | 1390 | printk(KERN_INFO "%s (revision %d) with %s dac\n", |
1da177e4 | 1391 | fix->id, par->revision, par->dac_sw.name); |
b98fc9a3 | 1392 | printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n", |
1da177e4 LT |
1393 | fix->smem_start, info->screen_base, |
1394 | fix->smem_len >> 20); | |
1395 | ||
57e4bc8a | 1396 | f_ddprintk("regbase_virt: %p\n", par->mmio_vbase); |
1da177e4 LT |
1397 | f_ddprintk("membase_phys: %#lx\n", fix->smem_start); |
1398 | f_ddprintk("fbbase_virt: %p\n", info->screen_base); | |
1399 | ||
1da177e4 | 1400 | info->fbops = &sstfb_ops; |
7227576f | 1401 | info->pseudo_palette = par->palette; |
1da177e4 LT |
1402 | |
1403 | fix->type = FB_TYPE_PACKED_PIXELS; | |
1404 | fix->visual = FB_VISUAL_TRUECOLOR; | |
1405 | fix->accel = FB_ACCEL_NONE; /* FIXME */ | |
1406 | /* | |
1407 | * According to the specs, the linelength must be of 1024 *pixels* | |
b98fc9a3 AC |
1408 | * and the 24bpp mode is in fact a 32 bpp mode (and both are in |
1409 | * fact dithered to 16bit). | |
1da177e4 LT |
1410 | */ |
1411 | fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */ | |
729d6872 | 1412 | |
0743b868 | 1413 | fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16); |
1da177e4 LT |
1414 | |
1415 | if (sstfb_check_var(&info->var, info)) { | |
0743b868 | 1416 | printk(KERN_ERR "sstfb: invalid video mode.\n"); |
1da177e4 LT |
1417 | goto fail; |
1418 | } | |
1419 | ||
1420 | if (sstfb_set_par(info)) { | |
b98fc9a3 | 1421 | printk(KERN_ERR "sstfb: can't set default video mode.\n"); |
1da177e4 LT |
1422 | goto fail; |
1423 | } | |
729d6872 | 1424 | |
c2312427 AS |
1425 | if (fb_alloc_cmap(&info->cmap, 256, 0)) { |
1426 | printk(KERN_ERR "sstfb: can't alloc cmap memory.\n"); | |
1427 | goto fail; | |
1428 | } | |
1da177e4 LT |
1429 | |
1430 | /* register fb */ | |
1431 | info->device = &pdev->dev; | |
1432 | if (register_framebuffer(info) < 0) { | |
b98fc9a3 | 1433 | printk(KERN_ERR "sstfb: can't register framebuffer.\n"); |
c2312427 | 1434 | goto fail_register; |
1da177e4 LT |
1435 | } |
1436 | ||
0743b868 HD |
1437 | sstfb_clear_screen(info); |
1438 | ||
1439 | if (device_create_file(info->dev, &device_attrs[0])) | |
1440 | printk(KERN_WARNING "sstfb: can't create sysfs entry.\n"); | |
1441 | ||
1da177e4 | 1442 | |
31b6780c JP |
1443 | fb_info(info, "%s frame buffer device at 0x%p\n", |
1444 | fix->id, info->screen_base); | |
1da177e4 LT |
1445 | |
1446 | return 0; | |
1447 | ||
c2312427 | 1448 | fail_register: |
0743b868 | 1449 | fb_dealloc_cmap(&info->cmap); |
c2312427 | 1450 | fail: |
1da177e4 LT |
1451 | iounmap(info->screen_base); |
1452 | fail_fb_remap: | |
1453 | iounmap(par->mmio_vbase); | |
1454 | fail_mmio_remap: | |
1455 | release_mem_region(fix->smem_start, 0x400000); | |
1456 | fail_fb_mem: | |
1457 | release_mem_region(fix->mmio_start, info->fix.mmio_len); | |
1458 | fail_mmio_mem: | |
7227576f | 1459 | framebuffer_release(info); |
1da177e4 LT |
1460 | return -ENXIO; /* no voodoo detected */ |
1461 | } | |
1462 | ||
48c68c4f | 1463 | static void sstfb_remove(struct pci_dev *pdev) |
1da177e4 LT |
1464 | { |
1465 | struct sstfb_par *par; | |
1466 | struct fb_info *info; | |
1467 | ||
1468 | info = pci_get_drvdata(pdev); | |
7227576f | 1469 | par = info->par; |
729d6872 | 1470 | |
0743b868 | 1471 | device_remove_file(info->dev, &device_attrs[0]); |
1da177e4 | 1472 | sst_shutdown(info); |
1da177e4 LT |
1473 | iounmap(info->screen_base); |
1474 | iounmap(par->mmio_vbase); | |
1475 | release_mem_region(info->fix.smem_start, 0x400000); | |
1476 | release_mem_region(info->fix.mmio_start, info->fix.mmio_len); | |
0743b868 HD |
1477 | fb_dealloc_cmap(&info->cmap); |
1478 | unregister_framebuffer(info); | |
7227576f | 1479 | framebuffer_release(info); |
1da177e4 LT |
1480 | } |
1481 | ||
1482 | ||
0743b868 HD |
1483 | static const struct pci_device_id sstfb_id_tbl[] = { |
1484 | { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ), | |
1485 | .driver_data = ID_VOODOO1, }, | |
1486 | { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2), | |
1487 | .driver_data = ID_VOODOO2, }, | |
1da177e4 LT |
1488 | { 0 }, |
1489 | }; | |
1490 | ||
1491 | static struct pci_driver sstfb_driver = { | |
1492 | .name = "sstfb", | |
1493 | .id_table = sstfb_id_tbl, | |
1494 | .probe = sstfb_probe, | |
48c68c4f | 1495 | .remove = sstfb_remove, |
1da177e4 LT |
1496 | }; |
1497 | ||
1498 | ||
48c68c4f | 1499 | static int sstfb_init(void) |
1da177e4 | 1500 | { |
1da177e4 LT |
1501 | char *option = NULL; |
1502 | ||
0ba2fa8c TZ |
1503 | if (fb_modesetting_disabled("sstfb")) |
1504 | return -ENODEV; | |
1505 | ||
1da177e4 LT |
1506 | if (fb_get_options("sstfb", &option)) |
1507 | return -ENODEV; | |
1508 | sstfb_setup(option); | |
0743b868 | 1509 | |
1da177e4 LT |
1510 | return pci_register_driver(&sstfb_driver); |
1511 | } | |
1512 | ||
48c68c4f | 1513 | static void sstfb_exit(void) |
1da177e4 LT |
1514 | { |
1515 | pci_unregister_driver(&sstfb_driver); | |
1516 | } | |
1da177e4 LT |
1517 | |
1518 | ||
1da177e4 | 1519 | module_init(sstfb_init); |
1da177e4 | 1520 | module_exit(sstfb_exit); |
1da177e4 LT |
1521 | |
1522 | MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>"); | |
1523 | MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards"); | |
1524 | MODULE_LICENSE("GPL"); | |
1525 | ||
1526 | module_param(mem, int, 0); | |
1527 | MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)"); | |
1528 | module_param(vgapass, bool, 0); | |
1529 | MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)"); | |
1530 | module_param(clipping, bool, 0); | |
1531 | MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)"); | |
1532 | module_param(gfxclk, int, 0); | |
1533 | MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)"); | |
1534 | module_param(slowpci, bool, 0); | |
1535 | MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)"); | |
0743b868 HD |
1536 | module_param(mode_option, charp, 0); |
1537 | MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")"); | |
1538 |