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video: fbdev: sh_mobile_lcdcfb: Remove sh_mobile_lcdc_check_var() declaration
[linux-2.6-block.git] / drivers / video / fbdev / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
f1f60b5f
LP		 11#include <linux/atomic.h>
12#include <linux/backlight.h>
cfb4f5d1 13#include <linux/clk.h>
f1f60b5f 14#include <linux/console.h>
c5deac3c 15#include <linux/ctype.h>
cfb4f5d1 16#include <linux/dma-mapping.h>
f1f60b5f 17#include <linux/delay.h>
9e146700 18#include <linux/fbcon.h>
f1f60b5f 19#include <linux/init.h>
8564557a 20#include <linux/interrupt.h>
40331b21 21#include <linux/ioctl.h>
f1f60b5f
LP		 22#include <linux/kernel.h>
23#include <linux/mm.h>
355b200b 24#include <linux/module.h>
f1f60b5f
LP		 25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/videodev2.h>
29#include <linux/vmalloc.h>
30
225c9a8d 31#include <video/sh_mobile_lcdc.h>
cfb4f5d1 32
6de9edd5
GL		 33#include "sh_mobile_lcdcfb.h"
34
c5deac3c
LP		 35/* ----------------------------------------------------------------------------
36 * Overlay register definitions
37 */
38
39#define LDBCR 0xb00
40#define LDBCR_UPC(n) (1 << ((n) + 16))
41#define LDBCR_UPF(n) (1 << ((n) + 8))
42#define LDBCR_UPD(n) (1 << ((n) + 0))
43#define LDBnBSIFR(n) (0xb20 + (n) * 0x20 + 0x00)
44#define LDBBSIFR_EN (1 << 31)
45#define LDBBSIFR_VS (1 << 29)
46#define LDBBSIFR_BRSEL (1 << 28)
47#define LDBBSIFR_MX (1 << 27)
48#define LDBBSIFR_MY (1 << 26)
49#define LDBBSIFR_CV3 (3 << 24)
50#define LDBBSIFR_CV2 (2 << 24)
51#define LDBBSIFR_CV1 (1 << 24)
52#define LDBBSIFR_CV0 (0 << 24)
53#define LDBBSIFR_CV_MASK (3 << 24)
54#define LDBBSIFR_LAY_MASK (0xff << 16)
55#define LDBBSIFR_LAY_SHIFT 16
56#define LDBBSIFR_ROP3_MASK (0xff << 16)
57#define LDBBSIFR_ROP3_SHIFT 16
58#define LDBBSIFR_AL_PL8 (3 << 14)
59#define LDBBSIFR_AL_PL1 (2 << 14)
60#define LDBBSIFR_AL_PK (1 << 14)
61#define LDBBSIFR_AL_1 (0 << 14)
62#define LDBBSIFR_AL_MASK (3 << 14)
63#define LDBBSIFR_SWPL (1 << 10)
64#define LDBBSIFR_SWPW (1 << 9)
65#define LDBBSIFR_SWPB (1 << 8)
66#define LDBBSIFR_RY (1 << 7)
67#define LDBBSIFR_CHRR_420 (2 << 0)
68#define LDBBSIFR_CHRR_422 (1 << 0)
69#define LDBBSIFR_CHRR_444 (0 << 0)
70#define LDBBSIFR_RPKF_ARGB32 (0x00 << 0)
71#define LDBBSIFR_RPKF_RGB16 (0x03 << 0)
72#define LDBBSIFR_RPKF_RGB24 (0x0b << 0)
73#define LDBBSIFR_RPKF_MASK (0x1f << 0)
74#define LDBnBSSZR(n) (0xb20 + (n) * 0x20 + 0x04)
75#define LDBBSSZR_BVSS_MASK (0xfff << 16)
76#define LDBBSSZR_BVSS_SHIFT 16
77#define LDBBSSZR_BHSS_MASK (0xfff << 0)
78#define LDBBSSZR_BHSS_SHIFT 0
79#define LDBnBLOCR(n) (0xb20 + (n) * 0x20 + 0x08)
80#define LDBBLOCR_CVLC_MASK (0xfff << 16)
81#define LDBBLOCR_CVLC_SHIFT 16
82#define LDBBLOCR_CHLC_MASK (0xfff << 0)
83#define LDBBLOCR_CHLC_SHIFT 0
84#define LDBnBSMWR(n) (0xb20 + (n) * 0x20 + 0x0c)
85#define LDBBSMWR_BSMWA_MASK (0xffff << 16)
86#define LDBBSMWR_BSMWA_SHIFT 16
87#define LDBBSMWR_BSMW_MASK (0xffff << 0)
88#define LDBBSMWR_BSMW_SHIFT 0
89#define LDBnBSAYR(n) (0xb20 + (n) * 0x20 + 0x10)
90#define LDBBSAYR_FG1A_MASK (0xff << 24)
91#define LDBBSAYR_FG1A_SHIFT 24
92#define LDBBSAYR_FG1R_MASK (0xff << 16)
93#define LDBBSAYR_FG1R_SHIFT 16
94#define LDBBSAYR_FG1G_MASK (0xff << 8)
95#define LDBBSAYR_FG1G_SHIFT 8
96#define LDBBSAYR_FG1B_MASK (0xff << 0)
97#define LDBBSAYR_FG1B_SHIFT 0
98#define LDBnBSACR(n) (0xb20 + (n) * 0x20 + 0x14)
99#define LDBBSACR_FG2A_MASK (0xff << 24)
100#define LDBBSACR_FG2A_SHIFT 24
101#define LDBBSACR_FG2R_MASK (0xff << 16)
102#define LDBBSACR_FG2R_SHIFT 16
103#define LDBBSACR_FG2G_MASK (0xff << 8)
104#define LDBBSACR_FG2G_SHIFT 8
105#define LDBBSACR_FG2B_MASK (0xff << 0)
106#define LDBBSACR_FG2B_SHIFT 0
107#define LDBnBSAAR(n) (0xb20 + (n) * 0x20 + 0x18)
108#define LDBBSAAR_AP_MASK (0xff << 24)
109#define LDBBSAAR_AP_SHIFT 24
110#define LDBBSAAR_R_MASK (0xff << 16)
111#define LDBBSAAR_R_SHIFT 16
112#define LDBBSAAR_GY_MASK (0xff << 8)
113#define LDBBSAAR_GY_SHIFT 8
114#define LDBBSAAR_B_MASK (0xff << 0)
115#define LDBBSAAR_B_SHIFT 0
116#define LDBnBPPCR(n) (0xb20 + (n) * 0x20 + 0x1c)
117#define LDBBPPCR_AP_MASK (0xff << 24)
118#define LDBBPPCR_AP_SHIFT 24
119#define LDBBPPCR_R_MASK (0xff << 16)
120#define LDBBPPCR_R_SHIFT 16
121#define LDBBPPCR_GY_MASK (0xff << 8)
122#define LDBBPPCR_GY_SHIFT 8
123#define LDBBPPCR_B_MASK (0xff << 0)
124#define LDBBPPCR_B_SHIFT 0
125#define LDBnBBGCL(n) (0xb10 + (n) * 0x04)
126#define LDBBBGCL_BGA_MASK (0xff << 24)
127#define LDBBBGCL_BGA_SHIFT 24
128#define LDBBBGCL_BGR_MASK (0xff << 16)
129#define LDBBBGCL_BGR_SHIFT 16
130#define LDBBBGCL_BGG_MASK (0xff << 8)
131#define LDBBBGCL_BGG_SHIFT 8
132#define LDBBBGCL_BGB_MASK (0xff << 0)
133#define LDBBBGCL_BGB_SHIFT 0
134
a6f15ade
PE		 135#define SIDE_B_OFFSET 0x1000
136#define MIRROR_OFFSET 0x2000
cfb4f5d1 137
d2ecbab5
GL		 138#define MAX_XRES 1920
139#define MAX_YRES 1080
cfb4f5d1 140
c5deac3c
LP		 141enum sh_mobile_lcdc_overlay_mode {
142 LCDC_OVERLAY_BLEND,
143 LCDC_OVERLAY_ROP3,
144};
145
146/*
147 * struct sh_mobile_lcdc_overlay - LCDC display overlay
148 *
149 * @channel: LCDC channel this overlay belongs to
150 * @cfg: Overlay configuration
151 * @info: Frame buffer device
152 * @index: Overlay index (0-3)
153 * @base: Overlay registers base address
154 * @enabled: True if the overlay is enabled
155 * @mode: Overlay blending mode (alpha blend or ROP3)
156 * @alpha: Global alpha blending value (0-255, for alpha blending mode)
157 * @rop3: Raster operation (for ROP3 mode)
158 * @fb_mem: Frame buffer virtual memory address
159 * @fb_size: Frame buffer size in bytes
160 * @dma_handle: Frame buffer DMA address
161 * @base_addr_y: Overlay base address (RGB or luma component)
162 * @base_addr_c: Overlay base address (chroma component)
a4aa25f6 163 * @pan_y_offset: Panning linear offset in bytes (luma component)
c5deac3c
LP		 164 * @format: Current pixelf format
165 * @xres: Horizontal visible resolution
166 * @xres_virtual: Horizontal total resolution
167 * @yres: Vertical visible resolution
168 * @yres_virtual: Vertical total resolution
169 * @pitch: Overlay line pitch
170 * @pos_x: Horizontal overlay position
171 * @pos_y: Vertical overlay position
172 */
173struct sh_mobile_lcdc_overlay {
174 struct sh_mobile_lcdc_chan *channel;
175
176 const struct sh_mobile_lcdc_overlay_cfg *cfg;
177 struct fb_info *info;
178
179 unsigned int index;
180 unsigned long base;
181
182 bool enabled;
183 enum sh_mobile_lcdc_overlay_mode mode;
184 unsigned int alpha;
185 unsigned int rop3;
186
187 void *fb_mem;
188 unsigned long fb_size;
189
190 dma_addr_t dma_handle;
191 unsigned long base_addr_y;
192 unsigned long base_addr_c;
a4aa25f6 193 unsigned long pan_y_offset;
c5deac3c
LP		 194
195 const struct sh_mobile_lcdc_format_info *format;
196 unsigned int xres;
197 unsigned int xres_virtual;
198 unsigned int yres;
199 unsigned int yres_virtual;
200 unsigned int pitch;
201 int pos_x;
202 int pos_y;
203};
204
f1f60b5f
LP		 205struct sh_mobile_lcdc_priv {
206 void __iomem *base;
207 int irq;
208 atomic_t hw_usecnt;
209 struct device *dev;
210 struct clk *dot_clk;
211 unsigned long lddckr;
c5deac3c 212
f1f60b5f 213 struct sh_mobile_lcdc_chan ch[2];
c5deac3c
LP		 214 struct sh_mobile_lcdc_overlay overlays[4];
215
f1f60b5f
LP		 216 int started;
217 int forced_fourcc; /* 2 channel LCDC must share fourcc setting */
f1f60b5f
LP		 218};
219
220/* -----------------------------------------------------------------------------
221 * Registers access
222 */
223
0246c471 224static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 225 [LDDCKPAT1R] = 0x400,
226 [LDDCKPAT2R] = 0x404,
227 [LDMT1R] = 0x418,
228 [LDMT2R] = 0x41c,
229 [LDMT3R] = 0x420,
230 [LDDFR] = 0x424,
231 [LDSM1R] = 0x428,
8564557a 232 [LDSM2R] = 0x42c,
cfb4f5d1 233 [LDSA1R] = 0x430,
53b50314 234 [LDSA2R] = 0x434,
cfb4f5d1
MD		 235 [LDMLSR] = 0x438,
236 [LDHCNR] = 0x448,
237 [LDHSYNR] = 0x44c,
238 [LDVLNR] = 0x450,
239 [LDVSYNR] = 0x454,
240 [LDPMR] = 0x460,
6011bdea 241 [LDHAJR] = 0x4a0,
cfb4f5d1
MD		 242};
243
0246c471 244static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 245 [LDDCKPAT1R] = 0x408,
246 [LDDCKPAT2R] = 0x40c,
247 [LDMT1R] = 0x600,
248 [LDMT2R] = 0x604,
249 [LDMT3R] = 0x608,
250 [LDDFR] = 0x60c,
251 [LDSM1R] = 0x610,
8564557a 252 [LDSM2R] = 0x614,
cfb4f5d1
MD		 253 [LDSA1R] = 0x618,
254 [LDMLSR] = 0x620,
255 [LDHCNR] = 0x624,
256 [LDHSYNR] = 0x628,
257 [LDVLNR] = 0x62c,
258 [LDVSYNR] = 0x630,
259 [LDPMR] = 0x63c,
260};
261
a6f15ade
PE		 262static bool banked(int reg_nr)
263{
264 switch (reg_nr) {
265 case LDMT1R:
266 case LDMT2R:
267 case LDMT3R:
268 case LDDFR:
269 case LDSM1R:
270 case LDSA1R:
53b50314 271 case LDSA2R:
a6f15ade
PE		 272 case LDMLSR:
273 case LDHCNR:
274 case LDHSYNR:
275 case LDVLNR:
276 case LDVSYNR:
277 return true;
278 }
279 return false;
280}
281
f1f60b5f
LP		 282static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
283{
b5ef967d 284 return chan->cfg->chan == LCDC_CHAN_SUBLCD;
f1f60b5f
LP		 285}
286
cfb4f5d1
MD		 287static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
288 int reg_nr, unsigned long data)
289{
290 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 291 if (banked(reg_nr))
292 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
293 SIDE_B_OFFSET);
294}
295
296static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
297 int reg_nr, unsigned long data)
298{
299 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
300 MIRROR_OFFSET);
cfb4f5d1
MD		 301}
302
303static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
304 int reg_nr)
305{
306 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
307}
308
c5deac3c
LP		 309static void lcdc_write_overlay(struct sh_mobile_lcdc_overlay *ovl,
310 int reg, unsigned long data)
311{
312 iowrite32(data, ovl->channel->lcdc->base + reg);
313 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET);
314}
315
cfb4f5d1
MD		 316static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
317 unsigned long reg_offs, unsigned long data)
318{
319 iowrite32(data, priv->base + reg_offs);
320}
321
322static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
323 unsigned long reg_offs)
324{
325 return ioread32(priv->base + reg_offs);
326}
327
328static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
329 unsigned long reg_offs,
330 unsigned long mask, unsigned long until)
331{
332 while ((lcdc_read(priv, reg_offs) & mask) != until)
333 cpu_relax();
334}
335
f1f60b5f
LP		 336/* -----------------------------------------------------------------------------
337 * Clock management
338 */
339
340static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1 341{
f1f60b5f 342 if (atomic_inc_and_test(&priv->hw_usecnt)) {
5988c269 343 clk_prepare_enable(priv->dot_clk);
f1f60b5f 344 pm_runtime_get_sync(priv->dev);
f1f60b5f 345 }
cfb4f5d1
MD		 346}
347
f1f60b5f
LP		 348static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
349{
350 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
f1f60b5f 351 pm_runtime_put(priv->dev);
5988c269 352 clk_disable_unprepare(priv->dot_clk);
f1f60b5f
LP		 353 }
354}
355
0a7f17aa
LP		 356static int sh_mobile_lcdc_setup_clocks(struct sh_mobile_lcdc_priv *priv,
357 int clock_source)
f1f60b5f 358{
4774c12a 359 struct clk *clk;
f1f60b5f
LP		 360 char *str;
361
362 switch (clock_source) {
363 case LCDC_CLK_BUS:
364 str = "bus_clk";
365 priv->lddckr = LDDCKR_ICKSEL_BUS;
366 break;
367 case LCDC_CLK_PERIPHERAL:
368 str = "peripheral_clk";
369 priv->lddckr = LDDCKR_ICKSEL_MIPI;
370 break;
371 case LCDC_CLK_EXTERNAL:
372 str = NULL;
373 priv->lddckr = LDDCKR_ICKSEL_HDMI;
374 break;
375 default:
376 return -EINVAL;
377 }
378
4774c12a
LP		 379 if (str == NULL)
380 return 0;
381
0a7f17aa 382 clk = clk_get(priv->dev, str);
4774c12a 383 if (IS_ERR(clk)) {
0a7f17aa 384 dev_err(priv->dev, "cannot get dot clock %s\n", str);
4774c12a 385 return PTR_ERR(clk);
f1f60b5f
LP		 386 }
387
4774c12a 388 priv->dot_clk = clk;
f1f60b5f
LP		 389 return 0;
390}
391
392/* -----------------------------------------------------------------------------
37c5dcc2 393 * Display, panel and deferred I/O
f1f60b5f
LP		 394 */
395
cfb4f5d1
MD		 396static void lcdc_sys_write_index(void *handle, unsigned long data)
397{
398 struct sh_mobile_lcdc_chan *ch = handle;
399
ce1c0b08
LP		 400 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT);
401 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
402 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
403 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
404 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 405}
406
407static void lcdc_sys_write_data(void *handle, unsigned long data)
408{
409 struct sh_mobile_lcdc_chan *ch = handle;
410
ce1c0b08
LP		 411 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW);
412 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
413 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA |
414 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
415 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1
MD		 416}
417
418static unsigned long lcdc_sys_read_data(void *handle)
419{
420 struct sh_mobile_lcdc_chan *ch = handle;
421
ce1c0b08
LP		 422 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR);
423 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
424 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA |
425 (lcdc_chan_is_sublcd(ch) ? 2 : 0));
cfb4f5d1 426 udelay(1);
ce1c0b08 427 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0);
cfb4f5d1 428
ce1c0b08 429 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK;
cfb4f5d1
MD		 430}
431
d38d840a 432static struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
6895aff4
KC		 433 .write_index = lcdc_sys_write_index,
434 .write_data = lcdc_sys_write_data,
435 .read_data = lcdc_sys_read_data,
cfb4f5d1
MD		 436};
437
1c6a307a
PM		 438static int sh_mobile_lcdc_sginit(struct fb_info *info,
439 struct list_head *pagelist)
440{
441 struct sh_mobile_lcdc_chan *ch = info->par;
58f03d99 442 unsigned int nr_pages_max = ch->fb_size >> PAGE_SHIFT;
1c6a307a
PM		 443 struct page *page;
444 int nr_pages = 0;
445
446 sg_init_table(ch->sglist, nr_pages_max);
447
448 list_for_each_entry(page, pagelist, lru)
449 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
450
451 return nr_pages;
452}
453
8564557a
MD		 454static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
455 struct list_head *pagelist)
456{
457 struct sh_mobile_lcdc_chan *ch = info->par;
b5ef967d 458 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
8564557a
MD		 459
460 /* enable clocks before accessing hardware */
461 sh_mobile_lcdc_clk_on(ch->lcdc);
462
5c1a56b5
PM		 463 /*
464 * It's possible to get here without anything on the pagelist via
465 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
466 * invocation. In the former case, the acceleration routines are
467 * stepped in to when using the framebuffer console causing the
468 * workqueue to be scheduled without any dirty pages on the list.
469 *
470 * Despite this, a panel update is still needed given that the
471 * acceleration routines have their own methods for writing in
472 * that still need to be updated.
473 *
474 * The fsync() and empty pagelist case could be optimized for,
475 * but we don't bother, as any application exhibiting such
476 * behaviour is fundamentally broken anyways.
477 */
478 if (!list_empty(pagelist)) {
479 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
480
481 /* trigger panel update */
e8363140 482 dma_map_sg(ch->lcdc->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
afaad83b
LP		 483 if (panel->start_transfer)
484 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 485 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
e8363140
LP		 486 dma_unmap_sg(ch->lcdc->dev, ch->sglist, nr_pages,
487 DMA_TO_DEVICE);
ef61aae4 488 } else {
afaad83b
LP		 489 if (panel->start_transfer)
490 panel->start_transfer(ch, &sh_mobile_lcdc_sys_bus_ops);
ce1c0b08 491 lcdc_write_chan(ch, LDSM2R, LDSM2R_OSTRG);
ef61aae4 492 }
8564557a
MD		 493}
494
495static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
496{
497 struct fb_deferred_io *fbdefio = info->fbdefio;
498
499 if (fbdefio)
500 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
501}
502
37c5dcc2
LP		 503static void sh_mobile_lcdc_display_on(struct sh_mobile_lcdc_chan *ch)
504{
b5ef967d 505 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 506
9a2985e7 507 if (ch->tx_dev) {
458981c3
LP		 508 int ret;
509
510 ret = ch->tx_dev->ops->display_on(ch->tx_dev);
511 if (ret < 0)
9a2985e7 512 return;
458981c3
LP		 513
514 if (ret == SH_MOBILE_LCDC_DISPLAY_DISCONNECTED)
515 ch->info->state = FBINFO_STATE_SUSPENDED;
9a2985e7
LP		 516 }
517
37c5dcc2 518 /* HDMI must be enabled before LCDC configuration */
afaad83b
LP		 519 if (panel->display_on)
520 panel->display_on();
37c5dcc2
LP		 521}
522
523static void sh_mobile_lcdc_display_off(struct sh_mobile_lcdc_chan *ch)
524{
b5ef967d 525 const struct sh_mobile_lcdc_panel_cfg *panel = &ch->cfg->panel_cfg;
37c5dcc2 526
afaad83b
LP		 527 if (panel->display_off)
528 panel->display_off();
9a2985e7
LP		 529
530 if (ch->tx_dev)
531 ch->tx_dev->ops->display_off(ch->tx_dev);
37c5dcc2
LP		 532}
533
f1f60b5f
LP		 534/* -----------------------------------------------------------------------------
535 * Format helpers
536 */
537
105784bb
LP		 538struct sh_mobile_lcdc_format_info {
539 u32 fourcc;
540 unsigned int bpp;
541 bool yuv;
542 u32 lddfr;
543};
544
545static const struct sh_mobile_lcdc_format_info sh_mobile_format_infos[] = {
546 {
547 .fourcc = V4L2_PIX_FMT_RGB565,
548 .bpp = 16,
549 .yuv = false,
550 .lddfr = LDDFR_PKF_RGB16,
551 }, {
552 .fourcc = V4L2_PIX_FMT_BGR24,
553 .bpp = 24,
554 .yuv = false,
555 .lddfr = LDDFR_PKF_RGB24,
556 }, {
557 .fourcc = V4L2_PIX_FMT_BGR32,
558 .bpp = 32,
559 .yuv = false,
560 .lddfr = LDDFR_PKF_ARGB32,
561 }, {
562 .fourcc = V4L2_PIX_FMT_NV12,
563 .bpp = 12,
564 .yuv = true,
565 .lddfr = LDDFR_CC | LDDFR_YF_420,
566 }, {
567 .fourcc = V4L2_PIX_FMT_NV21,
568 .bpp = 12,
569 .yuv = true,
570 .lddfr = LDDFR_CC | LDDFR_YF_420,
571 }, {
572 .fourcc = V4L2_PIX_FMT_NV16,
573 .bpp = 16,
574 .yuv = true,
575 .lddfr = LDDFR_CC | LDDFR_YF_422,
576 }, {
577 .fourcc = V4L2_PIX_FMT_NV61,
578 .bpp = 16,
579 .yuv = true,
580 .lddfr = LDDFR_CC | LDDFR_YF_422,
581 }, {
582 .fourcc = V4L2_PIX_FMT_NV24,
583 .bpp = 24,
584 .yuv = true,
585 .lddfr = LDDFR_CC | LDDFR_YF_444,
586 }, {
587 .fourcc = V4L2_PIX_FMT_NV42,
588 .bpp = 24,
589 .yuv = true,
590 .lddfr = LDDFR_CC | LDDFR_YF_444,
591 },
592};
593
594static const struct sh_mobile_lcdc_format_info *
595sh_mobile_format_info(u32 fourcc)
596{
597 unsigned int i;
598
599 for (i = 0; i < ARRAY_SIZE(sh_mobile_format_infos); ++i) {
600 if (sh_mobile_format_infos[i].fourcc == fourcc)
601 return &sh_mobile_format_infos[i];
602 }
603
604 return NULL;
605}
606
f1f60b5f
LP		 607static int sh_mobile_format_fourcc(const struct fb_var_screeninfo *var)
608{
609 if (var->grayscale > 1)
610 return var->grayscale;
611
612 switch (var->bits_per_pixel) {
613 case 16:
614 return V4L2_PIX_FMT_RGB565;
615 case 24:
616 return V4L2_PIX_FMT_BGR24;
617 case 32:
618 return V4L2_PIX_FMT_BGR32;
619 default:
620 return 0;
621 }
622}
623
624static int sh_mobile_format_is_fourcc(const struct fb_var_screeninfo *var)
625{
626 return var->grayscale > 1;
627}
628
f1f60b5f
LP		 629/* -----------------------------------------------------------------------------
630 * Start, stop and IRQ
631 */
632
8564557a
MD		 633static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
634{
635 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 636 struct sh_mobile_lcdc_chan *ch;
9dd38819 637 unsigned long ldintr;
2feb075a
MD		 638 int is_sub;
639 int k;
8564557a 640
dc48665f
LP		 641 /* Acknowledge interrupts and disable further VSYNC End IRQs. */
642 ldintr = lcdc_read(priv, _LDINTR);
643 lcdc_write(priv, _LDINTR, (ldintr ^ LDINTR_STATUS_MASK) & ~LDINTR_VEE);
8564557a 644
2feb075a 645 /* figure out if this interrupt is for main or sub lcd */
ce1c0b08 646 is_sub = (lcdc_read(priv, _LDSR) & LDSR_MSS) ? 1 : 0;
2feb075a 647
9dd38819 648 /* wake up channel and disable clocks */
2feb075a
MD		 649 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
650 ch = &priv->ch[k];
651
652 if (!ch->enabled)
653 continue;
654
dc48665f 655 /* Frame End */
9dd38819
PE		 656 if (ldintr & LDINTR_FS) {
657 if (is_sub == lcdc_chan_is_sublcd(ch)) {
658 ch->frame_end = 1;
659 wake_up(&ch->frame_end_wait);
2feb075a 660
9dd38819
PE		 661 sh_mobile_lcdc_clk_off(priv);
662 }
663 }
664
665 /* VSYNC End */
40331b21
PE		 666 if (ldintr & LDINTR_VES)
667 complete(&ch->vsync_completion);
2feb075a
MD		 668 }
669
8564557a
MD		 670 return IRQ_HANDLED;
671}
672
d7ad3342 673static int sh_mobile_lcdc_wait_for_vsync(struct sh_mobile_lcdc_chan *ch)
4976677f
LP		 674{
675 unsigned long ldintr;
676 int ret;
677
678 /* Enable VSync End interrupt and be careful not to acknowledge any
679 * pending interrupt.
680 */
681 ldintr = lcdc_read(ch->lcdc, _LDINTR);
682 ldintr |= LDINTR_VEE | LDINTR_STATUS_MASK;
683 lcdc_write(ch->lcdc, _LDINTR, ldintr);
684
685 ret = wait_for_completion_interruptible_timeout(&ch->vsync_completion,
686 msecs_to_jiffies(100));
687 if (!ret)
688 return -ETIMEDOUT;
689
690 return 0;
691}
692
cfb4f5d1
MD		 693static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
694 int start)
695{
696 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
697 int k;
698
699 /* start or stop the lcdc */
700 if (start)
ce1c0b08 701 lcdc_write(priv, _LDCNT2R, tmp | LDCNT2R_DO);
cfb4f5d1 702 else
ce1c0b08 703 lcdc_write(priv, _LDCNT2R, tmp & ~LDCNT2R_DO);
cfb4f5d1
MD		 704
705 /* wait until power is applied/stopped on all channels */
706 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
707 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
708 while (1) {
ce1c0b08
LP		 709 tmp = lcdc_read_chan(&priv->ch[k], LDPMR)
710 & LDPMR_LPS;
711 if (start && tmp == LDPMR_LPS)
cfb4f5d1
MD		 712 break;
713 if (!start && tmp == 0)
714 break;
715 cpu_relax();
716 }
717
718 if (!start)
719 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
720}
721
6011bdea
GL		 722static void sh_mobile_lcdc_geometry(struct sh_mobile_lcdc_chan *ch)
723{
2d04559d
LP		 724 const struct fb_var_screeninfo *var = &ch->info->var;
725 const struct fb_videomode *mode = &ch->display.mode;
1c120deb 726 unsigned long h_total, hsync_pos, display_h_total;
6011bdea
GL		 727 u32 tmp;
728
729 tmp = ch->ldmt1r_value;
ce1c0b08
LP		 730 tmp |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : LDMT1R_VPOL;
731 tmp |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : LDMT1R_HPOL;
b5ef967d
LP		 732 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWPOL) ? LDMT1R_DWPOL : 0;
733 tmp |= (ch->cfg->flags & LCDC_FLAGS_DIPOL) ? LDMT1R_DIPOL : 0;
734 tmp |= (ch->cfg->flags & LCDC_FLAGS_DAPOL) ? LDMT1R_DAPOL : 0;
735 tmp |= (ch->cfg->flags & LCDC_FLAGS_HSCNT) ? LDMT1R_HSCNT : 0;
736 tmp |= (ch->cfg->flags & LCDC_FLAGS_DWCNT) ? LDMT1R_DWCNT : 0;
6011bdea
GL		 737 lcdc_write_chan(ch, LDMT1R, tmp);
738
739 /* setup SYS bus */
b5ef967d
LP		 740 lcdc_write_chan(ch, LDMT2R, ch->cfg->sys_bus_cfg.ldmt2r);
741 lcdc_write_chan(ch, LDMT3R, ch->cfg->sys_bus_cfg.ldmt3r);
6011bdea
GL		 742
743 /* horizontal configuration */
2d04559d
LP		 744 h_total = mode->xres + mode->hsync_len + mode->left_margin
745 + mode->right_margin;
6011bdea 746 tmp = h_total / 8; /* HTCN */
58f03d99 747 tmp |= (min(mode->xres, ch->xres) / 8) << 16; /* HDCN */
6011bdea
GL		 748 lcdc_write_chan(ch, LDHCNR, tmp);
749
2d04559d 750 hsync_pos = mode->xres + mode->right_margin;
6011bdea 751 tmp = hsync_pos / 8; /* HSYNP */
2d04559d 752 tmp |= (mode->hsync_len / 8) << 16; /* HSYNW */
6011bdea
GL		 753 lcdc_write_chan(ch, LDHSYNR, tmp);
754
755 /* vertical configuration */
2d04559d
LP		 756 tmp = mode->yres + mode->vsync_len + mode->upper_margin
757 + mode->lower_margin; /* VTLN */
58f03d99 758 tmp |= min(mode->yres, ch->yres) << 16; /* VDLN */
6011bdea
GL		 759 lcdc_write_chan(ch, LDVLNR, tmp);
760
2d04559d
LP		 761 tmp = mode->yres + mode->lower_margin; /* VSYNP */
762 tmp |= mode->vsync_len << 16; /* VSYNW */
6011bdea
GL		 763 lcdc_write_chan(ch, LDVSYNR, tmp);
764
765 /* Adjust horizontal synchronisation for HDMI */
2d04559d
LP		 766 display_h_total = mode->xres + mode->hsync_len + mode->left_margin
767 + mode->right_margin;
768 tmp = ((mode->xres & 7) << 24) | ((display_h_total & 7) << 16)
769 | ((mode->hsync_len & 7) << 8) | (hsync_pos & 7);
6011bdea 770 lcdc_write_chan(ch, LDHAJR, tmp);
9beb09f1 771 lcdc_write_chan_mirror(ch, LDHAJR, tmp);
6011bdea
GL		 772}
773
c5deac3c
LP		 774static void sh_mobile_lcdc_overlay_setup(struct sh_mobile_lcdc_overlay *ovl)
775{
776 u32 format = 0;
777
778 if (!ovl->enabled) {
779 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
780 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), 0);
781 lcdc_write(ovl->channel->lcdc, LDBCR,
782 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
783 return;
784 }
785
786 ovl->base_addr_y = ovl->dma_handle;
a4aa25f6
LP		 787 ovl->base_addr_c = ovl->dma_handle
788 + ovl->xres_virtual * ovl->yres_virtual;
c5deac3c
LP		 789
790 switch (ovl->mode) {
791 case LCDC_OVERLAY_BLEND:
792 format = LDBBSIFR_EN | (ovl->alpha << LDBBSIFR_LAY_SHIFT);
793 break;
794
795 case LCDC_OVERLAY_ROP3:
796 format = LDBBSIFR_EN | LDBBSIFR_BRSEL
797 | (ovl->rop3 << LDBBSIFR_ROP3_SHIFT);
798 break;
799 }
800
801 switch (ovl->format->fourcc) {
802 case V4L2_PIX_FMT_RGB565:
803 case V4L2_PIX_FMT_NV21:
804 case V4L2_PIX_FMT_NV61:
805 case V4L2_PIX_FMT_NV42:
806 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW;
807 break;
808 case V4L2_PIX_FMT_BGR24:
809 case V4L2_PIX_FMT_NV12:
810 case V4L2_PIX_FMT_NV16:
811 case V4L2_PIX_FMT_NV24:
812 format |= LDBBSIFR_SWPL | LDBBSIFR_SWPW | LDBBSIFR_SWPB;
813 break;
814 case V4L2_PIX_FMT_BGR32:
815 default:
816 format |= LDBBSIFR_SWPL;
817 break;
818 }
819
820 switch (ovl->format->fourcc) {
821 case V4L2_PIX_FMT_RGB565:
822 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB16;
823 break;
824 case V4L2_PIX_FMT_BGR24:
825 format |= LDBBSIFR_AL_1 | LDBBSIFR_RY | LDBBSIFR_RPKF_RGB24;
826 break;
827 case V4L2_PIX_FMT_BGR32:
828 format |= LDBBSIFR_AL_PK | LDBBSIFR_RY | LDDFR_PKF_ARGB32;
829 break;
830 case V4L2_PIX_FMT_NV12:
831 case V4L2_PIX_FMT_NV21:
832 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_420;
833 break;
834 case V4L2_PIX_FMT_NV16:
835 case V4L2_PIX_FMT_NV61:
836 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_422;
837 break;
838 case V4L2_PIX_FMT_NV24:
839 case V4L2_PIX_FMT_NV42:
840 format |= LDBBSIFR_AL_1 | LDBBSIFR_CHRR_444;
841 break;
842 }
843
844 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
845
846 lcdc_write_overlay(ovl, LDBnBSIFR(ovl->index), format);
847
848 lcdc_write_overlay(ovl, LDBnBSSZR(ovl->index),
849 (ovl->yres << LDBBSSZR_BVSS_SHIFT) |
850 (ovl->xres << LDBBSSZR_BHSS_SHIFT));
851 lcdc_write_overlay(ovl, LDBnBLOCR(ovl->index),
852 (ovl->pos_y << LDBBLOCR_CVLC_SHIFT) |
853 (ovl->pos_x << LDBBLOCR_CHLC_SHIFT));
854 lcdc_write_overlay(ovl, LDBnBSMWR(ovl->index),
855 ovl->pitch << LDBBSMWR_BSMW_SHIFT);
856
857 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
858 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
859
860 lcdc_write(ovl->channel->lcdc, LDBCR,
861 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
862}
863
9a217e34 864/*
d7ad3342 865 * __sh_mobile_lcdc_start - Configure and start the LCDC
9a217e34
LP		 866 * @priv: LCDC device
867 *
868 * Configure all enabled channels and start the LCDC device. All external
869 * devices (clocks, MERAM, panels, ...) are not touched by this function.
870 */
871static void __sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
cfb4f5d1
MD		 872{
873 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1 874 unsigned long tmp;
9a217e34 875 int k, m;
8564557a 876
9a217e34
LP		 877 /* Enable LCDC channels. Read data from external memory, avoid using the
878 * BEU for now.
879 */
880 lcdc_write(priv, _LDCNT2R, priv->ch[0].enabled | priv->ch[1].enabled);
cfb4f5d1 881
9a217e34 882 /* Stop the LCDC first and disable all interrupts. */
cfb4f5d1 883 sh_mobile_lcdc_start_stop(priv, 0);
9a217e34 884 lcdc_write(priv, _LDINTR, 0);
cfb4f5d1 885
9a217e34 886 /* Configure power supply, dot clocks and start them. */
cfb4f5d1
MD		 887 tmp = priv->lddckr;
888 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
889 ch = &priv->ch[k];
9a217e34 890 if (!ch->enabled)
cfb4f5d1
MD		 891 continue;
892
9a217e34
LP		 893 /* Power supply */
894 lcdc_write_chan(ch, LDPMR, 0);
895
b5ef967d 896 m = ch->cfg->clock_divider;
cfb4f5d1
MD		 897 if (!m)
898 continue;
899
505c7de5
LP		 900 /* FIXME: sh7724 can only use 42, 48, 54 and 60 for the divider
901 * denominator.
902 */
903 lcdc_write_chan(ch, LDDCKPAT1R, 0);
904 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
905
cfb4f5d1 906 if (m == 1)
ce1c0b08 907 m = LDDCKR_MOSEL;
cfb4f5d1 908 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
cfb4f5d1
MD		 909 }
910
911 lcdc_write(priv, _LDDCKR, tmp);
cfb4f5d1
MD		 912 lcdc_write(priv, _LDDCKSTPR, 0);
913 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
914
9a217e34 915 /* Setup geometry, format, frame buffer memory and operation mode. */
cfb4f5d1
MD		 916 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
917 ch = &priv->ch[k];
cfb4f5d1
MD		 918 if (!ch->enabled)
919 continue;
920
6011bdea 921 sh_mobile_lcdc_geometry(ch);
cfb4f5d1 922
fc9e78e6 923 tmp = ch->format->lddfr;
edd153a3 924
fc9e78e6 925 if (ch->format->yuv) {
58f03d99 926 switch (ch->colorspace) {
edd153a3
LP		 927 case V4L2_COLORSPACE_REC709:
928 tmp |= LDDFR_CF1;
53b50314 929 break;
edd153a3
LP		 930 case V4L2_COLORSPACE_JPEG:
931 tmp |= LDDFR_CF0;
53b50314
DHG		 932 break;
933 }
417d4827 934 }
7caa4342 935
9a217e34 936 lcdc_write_chan(ch, LDDFR, tmp);
72c04af9 937 lcdc_write_chan(ch, LDMLSR, ch->line_size);
9a217e34 938 lcdc_write_chan(ch, LDSA1R, ch->base_addr_y);
fc9e78e6 939 if (ch->format->yuv)
9a217e34 940 lcdc_write_chan(ch, LDSA2R, ch->base_addr_c);
7caa4342 941
9a217e34
LP		 942 /* When using deferred I/O mode, configure the LCDC for one-shot
943 * operation and enable the frame end interrupt. Otherwise use
944 * continuous read mode.
945 */
946 if (ch->ldmt1r_value & LDMT1R_IFM &&
b5ef967d 947 ch->cfg->sys_bus_cfg.deferred_io_msec) {
9a217e34
LP		 948 lcdc_write_chan(ch, LDSM1R, LDSM1R_OS);
949 lcdc_write(priv, _LDINTR, LDINTR_FE);
950 } else {
951 lcdc_write_chan(ch, LDSM1R, 0);
952 }
953 }
7caa4342 954
9a217e34 955 /* Word and long word swap. */
fc9e78e6 956 switch (priv->ch[0].format->fourcc) {
edd153a3
LP		 957 case V4L2_PIX_FMT_RGB565:
958 case V4L2_PIX_FMT_NV21:
959 case V4L2_PIX_FMT_NV61:
960 case V4L2_PIX_FMT_NV42:
961 tmp = LDDDSR_LS | LDDDSR_WS;
962 break;
963 case V4L2_PIX_FMT_BGR24:
964 case V4L2_PIX_FMT_NV12:
965 case V4L2_PIX_FMT_NV16:
966 case V4L2_PIX_FMT_NV24:
9a217e34 967 tmp = LDDDSR_LS | LDDDSR_WS | LDDDSR_BS;
edd153a3
LP		 968 break;
969 case V4L2_PIX_FMT_BGR32:
970 default:
971 tmp = LDDDSR_LS;
972 break;
9a217e34
LP		 973 }
974 lcdc_write(priv, _LDDDSR, tmp);
7caa4342 975
9a217e34
LP		 976 /* Enable the display output. */
977 lcdc_write(priv, _LDCNT1R, LDCNT1R_DE);
978 sh_mobile_lcdc_start_stop(priv, 1);
979 priv->started = 1;
980}
cfb4f5d1 981
9a217e34
LP		 982static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
983{
9a217e34
LP		 984 struct sh_mobile_lcdc_chan *ch;
985 unsigned long tmp;
986 int ret;
987 int k;
cfb4f5d1 988
9a217e34
LP		 989 /* enable clocks before accessing the hardware */
990 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
991 if (priv->ch[k].enabled)
992 sh_mobile_lcdc_clk_on(priv);
993 }
8564557a 994
9a217e34
LP		 995 /* reset */
996 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LDCNT2R_BR);
997 lcdc_wait_bit(priv, _LDCNT2R, LDCNT2R_BR, 0);
8564557a 998
9a217e34 999 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
b5ef967d 1000 const struct sh_mobile_lcdc_panel_cfg *panel;
8564557a 1001
37c5dcc2 1002 ch = &priv->ch[k];
9a217e34
LP		 1003 if (!ch->enabled)
1004 continue;
1005
b5ef967d 1006 panel = &ch->cfg->panel_cfg;
afaad83b
LP		 1007 if (panel->setup_sys) {
1008 ret = panel->setup_sys(ch, &sh_mobile_lcdc_sys_bus_ops);
9a217e34
LP		 1009 if (ret)
1010 return ret;
8564557a 1011 }
cfb4f5d1
MD		 1012 }
1013
9a217e34
LP		 1014 /* Compute frame buffer base address and pitch for each channel. */
1015 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
9a217e34
LP		 1016 ch = &priv->ch[k];
1017 if (!ch->enabled)
1018 continue;
cfb4f5d1 1019
58f03d99 1020 ch->base_addr_y = ch->dma_handle;
a4aa25f6
LP		 1021 ch->base_addr_c = ch->dma_handle
1022 + ch->xres_virtual * ch->yres_virtual;
72c04af9 1023 ch->line_size = ch->pitch;
9a217e34
LP		 1024 }
1025
c5deac3c
LP		 1026 for (k = 0; k < ARRAY_SIZE(priv->overlays); ++k) {
1027 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[k];
1028 sh_mobile_lcdc_overlay_setup(ovl);
1029 }
1030
9a217e34
LP		 1031 /* Start the LCDC. */
1032 __sh_mobile_lcdc_start(priv);
1033
1034 /* Setup deferred I/O, tell the board code to enable the panels, and
1035 * turn backlight on.
1036 */
cfb4f5d1
MD		 1037 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1038 ch = &priv->ch[k];
21bc1f02
MD		 1039 if (!ch->enabled)
1040 continue;
1041
b5ef967d 1042 tmp = ch->cfg->sys_bus_cfg.deferred_io_msec;
9a217e34
LP		 1043 if (ch->ldmt1r_value & LDMT1R_IFM && tmp) {
1044 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
1045 ch->defio.delay = msecs_to_jiffies(tmp);
1046 ch->info->fbdefio = &ch->defio;
1047 fb_deferred_io_init(ch->info);
1048 }
1049
37c5dcc2 1050 sh_mobile_lcdc_display_on(ch);
3b0fd9d7
AC		 1051
1052 if (ch->bl) {
1053 ch->bl->props.power = FB_BLANK_UNBLANK;
1054 backlight_update_status(ch->bl);
1055 }
cfb4f5d1
MD		 1056 }
1057
1058 return 0;
1059}
1060
1061static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
1062{
1063 struct sh_mobile_lcdc_chan *ch;
cfb4f5d1
MD		 1064 int k;
1065
2feb075a 1066 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 1067 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
1068 ch = &priv->ch[k];
21bc1f02
MD		 1069 if (!ch->enabled)
1070 continue;
8564557a 1071
2feb075a
MD		 1072 /* deferred io mode:
1073 * flush frame, and wait for frame end interrupt
1074 * clean up deferred io and enable clock
1075 */
5ef6b505 1076 if (ch->info && ch->info->fbdefio) {
2feb075a 1077 ch->frame_end = 0;
e33afddc 1078 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 1079 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 1080 fb_deferred_io_cleanup(ch->info);
1081 ch->info->fbdefio = NULL;
2feb075a 1082 sh_mobile_lcdc_clk_on(priv);
8564557a 1083 }
2feb075a 1084
3b0fd9d7
AC		 1085 if (ch->bl) {
1086 ch->bl->props.power = FB_BLANK_POWERDOWN;
1087 backlight_update_status(ch->bl);
1088 }
1089
37c5dcc2 1090 sh_mobile_lcdc_display_off(ch);
cfb4f5d1
MD		 1091 }
1092
1093 /* stop the lcdc */
8e9bb19e
MD		 1094 if (priv->started) {
1095 sh_mobile_lcdc_start_stop(priv, 0);
1096 priv->started = 0;
1097 }
b51339ff 1098
8564557a
MD		 1099 /* stop clocks */
1100 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
1101 if (priv->ch[k].enabled)
1102 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1103}
1104
c5deac3c
LP		 1105static int __sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1106 struct fb_info *info)
1107{
1108 if (var->xres > MAX_XRES || var->yres > MAX_YRES)
1109 return -EINVAL;
1110
1111 /* Make sure the virtual resolution is at least as big as the visible
1112 * resolution.
1113 */
1114 if (var->xres_virtual < var->xres)
1115 var->xres_virtual = var->xres;
1116 if (var->yres_virtual < var->yres)
1117 var->yres_virtual = var->yres;
1118
1119 if (sh_mobile_format_is_fourcc(var)) {
1120 const struct sh_mobile_lcdc_format_info *format;
1121
1122 format = sh_mobile_format_info(var->grayscale);
1123 if (format == NULL)
1124 return -EINVAL;
1125 var->bits_per_pixel = format->bpp;
1126
1127 /* Default to RGB and JPEG color-spaces for RGB and YUV formats
1128 * respectively.
1129 */
1130 if (!format->yuv)
1131 var->colorspace = V4L2_COLORSPACE_SRGB;
1132 else if (var->colorspace != V4L2_COLORSPACE_REC709)
1133 var->colorspace = V4L2_COLORSPACE_JPEG;
1134 } else {
1135 if (var->bits_per_pixel <= 16) { /* RGB 565 */
1136 var->bits_per_pixel = 16;
1137 var->red.offset = 11;
1138 var->red.length = 5;
1139 var->green.offset = 5;
1140 var->green.length = 6;
1141 var->blue.offset = 0;
1142 var->blue.length = 5;
1143 var->transp.offset = 0;
1144 var->transp.length = 0;
1145 } else if (var->bits_per_pixel <= 24) { /* RGB 888 */
1146 var->bits_per_pixel = 24;
1147 var->red.offset = 16;
1148 var->red.length = 8;
1149 var->green.offset = 8;
1150 var->green.length = 8;
1151 var->blue.offset = 0;
1152 var->blue.length = 8;
1153 var->transp.offset = 0;
1154 var->transp.length = 0;
1155 } else if (var->bits_per_pixel <= 32) { /* RGBA 888 */
1156 var->bits_per_pixel = 32;
1157 var->red.offset = 16;
1158 var->red.length = 8;
1159 var->green.offset = 8;
1160 var->green.length = 8;
1161 var->blue.offset = 0;
1162 var->blue.length = 8;
1163 var->transp.offset = 24;
1164 var->transp.length = 8;
1165 } else
1166 return -EINVAL;
1167
1168 var->red.msb_right = 0;
1169 var->green.msb_right = 0;
1170 var->blue.msb_right = 0;
1171 var->transp.msb_right = 0;
1172 }
1173
1174 /* Make sure we don't exceed our allocated memory. */
1175 if (var->xres_virtual * var->yres_virtual * var->bits_per_pixel / 8 >
1176 info->fix.smem_len)
1177 return -EINVAL;
1178
1179 return 0;
1180}
1181
1182/* -----------------------------------------------------------------------------
1183 * Frame buffer operations - Overlays
1184 */
1185
1186static ssize_t
1187overlay_alpha_show(struct device *dev, struct device_attribute *attr, char *buf)
1188{
1189 struct fb_info *info = dev_get_drvdata(dev);
1190 struct sh_mobile_lcdc_overlay *ovl = info->par;
1191
1192 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->alpha);
1193}
1194
1195static ssize_t
1196overlay_alpha_store(struct device *dev, struct device_attribute *attr,
1197 const char *buf, size_t count)
1198{
1199 struct fb_info *info = dev_get_drvdata(dev);
1200 struct sh_mobile_lcdc_overlay *ovl = info->par;
1201 unsigned int alpha;
1202 char *endp;
1203
1204 alpha = simple_strtoul(buf, &endp, 10);
1205 if (isspace(*endp))
1206 endp++;
1207
1208 if (endp - buf != count)
1209 return -EINVAL;
1210
1211 if (alpha > 255)
1212 return -EINVAL;
1213
1214 if (ovl->alpha != alpha) {
1215 ovl->alpha = alpha;
1216
1217 if (ovl->mode == LCDC_OVERLAY_BLEND && ovl->enabled)
1218 sh_mobile_lcdc_overlay_setup(ovl);
1219 }
1220
1221 return count;
1222}
1223
1224static ssize_t
1225overlay_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1226{
1227 struct fb_info *info = dev_get_drvdata(dev);
1228 struct sh_mobile_lcdc_overlay *ovl = info->par;
1229
1230 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->mode);
1231}
1232
1233static ssize_t
1234overlay_mode_store(struct device *dev, struct device_attribute *attr,
1235 const char *buf, size_t count)
1236{
1237 struct fb_info *info = dev_get_drvdata(dev);
1238 struct sh_mobile_lcdc_overlay *ovl = info->par;
1239 unsigned int mode;
1240 char *endp;
1241
1242 mode = simple_strtoul(buf, &endp, 10);
1243 if (isspace(*endp))
1244 endp++;
1245
1246 if (endp - buf != count)
1247 return -EINVAL;
1248
1249 if (mode != LCDC_OVERLAY_BLEND && mode != LCDC_OVERLAY_ROP3)
1250 return -EINVAL;
1251
1252 if (ovl->mode != mode) {
1253 ovl->mode = mode;
1254
1255 if (ovl->enabled)
1256 sh_mobile_lcdc_overlay_setup(ovl);
1257 }
1258
1259 return count;
1260}
1261
1262static ssize_t
1263overlay_position_show(struct device *dev, struct device_attribute *attr,
1264 char *buf)
1265{
1266 struct fb_info *info = dev_get_drvdata(dev);
1267 struct sh_mobile_lcdc_overlay *ovl = info->par;
1268
1269 return scnprintf(buf, PAGE_SIZE, "%d,%d\n", ovl->pos_x, ovl->pos_y);
1270}
1271
1272static ssize_t
1273overlay_position_store(struct device *dev, struct device_attribute *attr,
1274 const char *buf, size_t count)
1275{
1276 struct fb_info *info = dev_get_drvdata(dev);
1277 struct sh_mobile_lcdc_overlay *ovl = info->par;
1278 char *endp;
1279 int pos_x;
1280 int pos_y;
1281
1282 pos_x = simple_strtol(buf, &endp, 10);
1283 if (*endp != ',')
1284 return -EINVAL;
1285
1286 pos_y = simple_strtol(endp + 1, &endp, 10);
1287 if (isspace(*endp))
1288 endp++;
1289
1290 if (endp - buf != count)
1291 return -EINVAL;
1292
1293 if (ovl->pos_x != pos_x || ovl->pos_y != pos_y) {
1294 ovl->pos_x = pos_x;
1295 ovl->pos_y = pos_y;
1296
1297 if (ovl->enabled)
1298 sh_mobile_lcdc_overlay_setup(ovl);
1299 }
1300
1301 return count;
1302}
1303
1304static ssize_t
1305overlay_rop3_show(struct device *dev, struct device_attribute *attr, char *buf)
1306{
1307 struct fb_info *info = dev_get_drvdata(dev);
1308 struct sh_mobile_lcdc_overlay *ovl = info->par;
1309
1310 return scnprintf(buf, PAGE_SIZE, "%u\n", ovl->rop3);
1311}
1312
1313static ssize_t
1314overlay_rop3_store(struct device *dev, struct device_attribute *attr,
1315 const char *buf, size_t count)
1316{
1317 struct fb_info *info = dev_get_drvdata(dev);
1318 struct sh_mobile_lcdc_overlay *ovl = info->par;
1319 unsigned int rop3;
1320 char *endp;
1321
14048ffe 1322 rop3 = simple_strtoul(buf, &endp, 10);
c5deac3c
LP		 1323 if (isspace(*endp))
1324 endp++;
1325
1326 if (endp - buf != count)
1327 return -EINVAL;
1328
1329 if (rop3 > 255)
1330 return -EINVAL;
1331
1332 if (ovl->rop3 != rop3) {
1333 ovl->rop3 = rop3;
1334
1335 if (ovl->mode == LCDC_OVERLAY_ROP3 && ovl->enabled)
1336 sh_mobile_lcdc_overlay_setup(ovl);
1337 }
1338
1339 return count;
1340}
1341
1342static const struct device_attribute overlay_sysfs_attrs[] = {
1343 __ATTR(ovl_alpha, S_IRUGO|S_IWUSR,
1344 overlay_alpha_show, overlay_alpha_store),
1345 __ATTR(ovl_mode, S_IRUGO|S_IWUSR,
1346 overlay_mode_show, overlay_mode_store),
1347 __ATTR(ovl_position, S_IRUGO|S_IWUSR,
1348 overlay_position_show, overlay_position_store),
1349 __ATTR(ovl_rop3, S_IRUGO|S_IWUSR,
1350 overlay_rop3_show, overlay_rop3_store),
1351};
1352
1353static const struct fb_fix_screeninfo sh_mobile_lcdc_overlay_fix = {
1354 .id = "SH Mobile LCDC",
1355 .type = FB_TYPE_PACKED_PIXELS,
1356 .visual = FB_VISUAL_TRUECOLOR,
1357 .accel = FB_ACCEL_NONE,
15dede88 1358 .xpanstep = 1,
c5deac3c
LP		 1359 .ypanstep = 1,
1360 .ywrapstep = 0,
1361 .capabilities = FB_CAP_FOURCC,
1362};
1363
1364static int sh_mobile_lcdc_overlay_pan(struct fb_var_screeninfo *var,
1365 struct fb_info *info)
1366{
1367 struct sh_mobile_lcdc_overlay *ovl = info->par;
1368 unsigned long base_addr_y;
1369 unsigned long base_addr_c;
a4aa25f6 1370 unsigned long y_offset;
c5deac3c
LP		 1371 unsigned long c_offset;
1372
a4aa25f6
LP		 1373 if (!ovl->format->yuv) {
1374 y_offset = (var->yoffset * ovl->xres_virtual + var->xoffset)
1375 * ovl->format->bpp / 8;
1376 c_offset = 0;
1377 } else {
1378 unsigned int xsub = ovl->format->bpp < 24 ? 2 : 1;
1379 unsigned int ysub = ovl->format->bpp < 16 ? 2 : 1;
1380
1381 y_offset = var->yoffset * ovl->xres_virtual + var->xoffset;
1382 c_offset = var->yoffset / ysub * ovl->xres_virtual * 2 / xsub
1383 + var->xoffset * 2 / xsub;
1384 }
c5deac3c 1385
a4aa25f6
LP		 1386 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1387 * nothing to do in that case.
1388 */
1389 if (y_offset == ovl->pan_y_offset)
1390 return 0;
c5deac3c
LP		 1391
1392 /* Set the source address for the next refresh */
a4aa25f6
LP		 1393 base_addr_y = ovl->dma_handle + y_offset;
1394 base_addr_c = ovl->dma_handle + ovl->xres_virtual * ovl->yres_virtual
1395 + c_offset;
c5deac3c
LP		 1396
1397 ovl->base_addr_y = base_addr_y;
a4aa25f6
LP		 1398 ovl->base_addr_c = base_addr_c;
1399 ovl->pan_y_offset = y_offset;
c5deac3c 1400
8be7c669
LP		 1401 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index));
1402
c5deac3c
LP		 1403 lcdc_write_overlay(ovl, LDBnBSAYR(ovl->index), ovl->base_addr_y);
1404 lcdc_write_overlay(ovl, LDBnBSACR(ovl->index), ovl->base_addr_c);
1405
8be7c669
LP		 1406 lcdc_write(ovl->channel->lcdc, LDBCR,
1407 LDBCR_UPF(ovl->index) | LDBCR_UPD(ovl->index));
1408
c5deac3c
LP		 1409 return 0;
1410}
1411
1412static int sh_mobile_lcdc_overlay_ioctl(struct fb_info *info, unsigned int cmd,
1413 unsigned long arg)
1414{
1415 struct sh_mobile_lcdc_overlay *ovl = info->par;
1416
1417 switch (cmd) {
1418 case FBIO_WAITFORVSYNC:
1419 return sh_mobile_lcdc_wait_for_vsync(ovl->channel);
1420
1421 default:
1422 return -ENOIOCTLCMD;
1423 }
1424}
1425
1426static int sh_mobile_lcdc_overlay_check_var(struct fb_var_screeninfo *var,
1427 struct fb_info *info)
1428{
1429 return __sh_mobile_lcdc_check_var(var, info);
1430}
1431
1432static int sh_mobile_lcdc_overlay_set_par(struct fb_info *info)
1433{
1434 struct sh_mobile_lcdc_overlay *ovl = info->par;
1435
1436 ovl->format =
1437 sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
1438
1439 ovl->xres = info->var.xres;
1440 ovl->xres_virtual = info->var.xres_virtual;
1441 ovl->yres = info->var.yres;
1442 ovl->yres_virtual = info->var.yres_virtual;
1443
1444 if (ovl->format->yuv)
16ca21c9 1445 ovl->pitch = info->var.xres_virtual;
c5deac3c 1446 else
16ca21c9 1447 ovl->pitch = info->var.xres_virtual * ovl->format->bpp / 8;
c5deac3c
LP		 1448
1449 sh_mobile_lcdc_overlay_setup(ovl);
1450
1451 info->fix.line_length = ovl->pitch;
1452
1453 if (sh_mobile_format_is_fourcc(&info->var)) {
1454 info->fix.type = FB_TYPE_FOURCC;
1455 info->fix.visual = FB_VISUAL_FOURCC;
1456 } else {
1457 info->fix.type = FB_TYPE_PACKED_PIXELS;
1458 info->fix.visual = FB_VISUAL_TRUECOLOR;
1459 }
1460
1461 return 0;
1462}
1463
1464/* Overlay blanking. Disable the overlay when blanked. */
1465static int sh_mobile_lcdc_overlay_blank(int blank, struct fb_info *info)
1466{
1467 struct sh_mobile_lcdc_overlay *ovl = info->par;
1468
1469 ovl->enabled = !blank;
1470 sh_mobile_lcdc_overlay_setup(ovl);
1471
1472 /* Prevent the backlight from receiving a blanking event by returning
1473 * a non-zero value.
1474 */
1475 return 1;
1476}
1477
bf10a537
HE		 1478static int
1479sh_mobile_lcdc_overlay_mmap(struct fb_info *info, struct vm_area_struct *vma)
1480{
1481 struct sh_mobile_lcdc_overlay *ovl = info->par;
1482
1483 return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem,
1484 ovl->dma_handle, ovl->fb_size);
1485}
1486
8a48ac33 1487static const struct fb_ops sh_mobile_lcdc_overlay_ops = {
c5deac3c
LP		 1488 .owner = THIS_MODULE,
1489 .fb_read = fb_sys_read,
1490 .fb_write = fb_sys_write,
1491 .fb_fillrect = sys_fillrect,
1492 .fb_copyarea = sys_copyarea,
1493 .fb_imageblit = sys_imageblit,
1494 .fb_blank = sh_mobile_lcdc_overlay_blank,
1495 .fb_pan_display = sh_mobile_lcdc_overlay_pan,
1496 .fb_ioctl = sh_mobile_lcdc_overlay_ioctl,
1497 .fb_check_var = sh_mobile_lcdc_overlay_check_var,
1498 .fb_set_par = sh_mobile_lcdc_overlay_set_par,
bf10a537 1499 .fb_mmap = sh_mobile_lcdc_overlay_mmap,
c5deac3c
LP		 1500};
1501
1502static void
1503sh_mobile_lcdc_overlay_fb_unregister(struct sh_mobile_lcdc_overlay *ovl)
1504{
1505 struct fb_info *info = ovl->info;
1506
1507 if (info == NULL || info->dev == NULL)
1508 return;
1509
1510 unregister_framebuffer(ovl->info);
1511}
1512
48c68c4f 1513static int
c5deac3c
LP		 1514sh_mobile_lcdc_overlay_fb_register(struct sh_mobile_lcdc_overlay *ovl)
1515{
1516 struct sh_mobile_lcdc_priv *lcdc = ovl->channel->lcdc;
1517 struct fb_info *info = ovl->info;
1518 unsigned int i;
1519 int ret;
1520
1521 if (info == NULL)
1522 return 0;
1523
1524 ret = register_framebuffer(info);
1525 if (ret < 0)
1526 return ret;
1527
1528 dev_info(lcdc->dev, "registered %s/overlay %u as %dx%d %dbpp.\n",
1529 dev_name(lcdc->dev), ovl->index, info->var.xres,
1530 info->var.yres, info->var.bits_per_pixel);
1531
1532 for (i = 0; i < ARRAY_SIZE(overlay_sysfs_attrs); ++i) {
1533 ret = device_create_file(info->dev, &overlay_sysfs_attrs[i]);
1534 if (ret < 0)
1535 return ret;
1536 }
1537
1538 return 0;
1539}
1540
1541static void
1542sh_mobile_lcdc_overlay_fb_cleanup(struct sh_mobile_lcdc_overlay *ovl)
1543{
1544 struct fb_info *info = ovl->info;
1545
1546 if (info == NULL || info->device == NULL)
1547 return;
1548
1549 framebuffer_release(info);
1550}
1551
48c68c4f 1552static int
c5deac3c
LP		 1553sh_mobile_lcdc_overlay_fb_init(struct sh_mobile_lcdc_overlay *ovl)
1554{
1555 struct sh_mobile_lcdc_priv *priv = ovl->channel->lcdc;
1556 struct fb_var_screeninfo *var;
1557 struct fb_info *info;
1558
1559 /* Allocate and initialize the frame buffer device. */
1560 info = framebuffer_alloc(0, priv->dev);
0adcdbcb 1561 if (!info)
c5deac3c 1562 return -ENOMEM;
c5deac3c
LP		 1563
1564 ovl->info = info;
1565
1566 info->flags = FBINFO_FLAG_DEFAULT;
1567 info->fbops = &sh_mobile_lcdc_overlay_ops;
1568 info->device = priv->dev;
5d30146f 1569 info->screen_buffer = ovl->fb_mem;
c5deac3c
LP		 1570 info->par = ovl;
1571
1572 /* Initialize fixed screen information. Restrict pan to 2 lines steps
1573 * for NV12 and NV21.
1574 */
1575 info->fix = sh_mobile_lcdc_overlay_fix;
1576 snprintf(info->fix.id, sizeof(info->fix.id),
1577 "SH Mobile LCDC Overlay %u", ovl->index);
1578 info->fix.smem_start = ovl->dma_handle;
1579 info->fix.smem_len = ovl->fb_size;
1580 info->fix.line_length = ovl->pitch;
1581
1582 if (ovl->format->yuv)
1583 info->fix.visual = FB_VISUAL_FOURCC;
1584 else
1585 info->fix.visual = FB_VISUAL_TRUECOLOR;
1586
15dede88 1587 switch (ovl->format->fourcc) {
15dede88
LP		 1588 case V4L2_PIX_FMT_NV12:
1589 case V4L2_PIX_FMT_NV21:
ac33a207 1590 info->fix.ypanstep = 2;
ad04fae0 1591 fallthrough;
ac33a207
LP		 1592 case V4L2_PIX_FMT_NV16:
1593 case V4L2_PIX_FMT_NV61:
15dede88
LP		 1594 info->fix.xpanstep = 2;
1595 }
c5deac3c
LP		 1596
1597 /* Initialize variable screen information. */
1598 var = &info->var;
1599 memset(var, 0, sizeof(*var));
1600 var->xres = ovl->xres;
1601 var->yres = ovl->yres;
1602 var->xres_virtual = ovl->xres_virtual;
1603 var->yres_virtual = ovl->yres_virtual;
1604 var->activate = FB_ACTIVATE_NOW;
1605
1606 /* Use the legacy API by default for RGB formats, and the FOURCC API
1607 * for YUV formats.
1608 */
1609 if (!ovl->format->yuv)
1610 var->bits_per_pixel = ovl->format->bpp;
1611 else
1612 var->grayscale = ovl->format->fourcc;
1613
1614 return sh_mobile_lcdc_overlay_check_var(var, info);
1615}
1616
f1f60b5f 1617/* -----------------------------------------------------------------------------
c5deac3c 1618 * Frame buffer operations - main frame buffer
f1f60b5f 1619 */
cfb4f5d1
MD		 1620
1621static int sh_mobile_lcdc_setcolreg(u_int regno,
1622 u_int red, u_int green, u_int blue,
1623 u_int transp, struct fb_info *info)
1624{
1625 u32 *palette = info->pseudo_palette;
1626
1627 if (regno >= PALETTE_NR)
1628 return -EINVAL;
1629
1630 /* only FB_VISUAL_TRUECOLOR supported */
1631
1632 red >>= 16 - info->var.red.length;
1633 green >>= 16 - info->var.green.length;
1634 blue >>= 16 - info->var.blue.length;
1635 transp >>= 16 - info->var.transp.length;
1636
1637 palette[regno] = (red << info->var.red.offset) |
1638 (green << info->var.green.offset) |
1639 (blue << info->var.blue.offset) |
1640 (transp << info->var.transp.offset);
1641
1642 return 0;
1643}
1644
3281e54c 1645static const struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
cfb4f5d1
MD		 1646 .id = "SH Mobile LCDC",
1647 .type = FB_TYPE_PACKED_PIXELS,
1648 .visual = FB_VISUAL_TRUECOLOR,
1649 .accel = FB_ACCEL_NONE,
15dede88 1650 .xpanstep = 1,
9dd38819
PE		 1651 .ypanstep = 1,
1652 .ywrapstep = 0,
edd153a3 1653 .capabilities = FB_CAP_FOURCC,
cfb4f5d1
MD		 1654};
1655
8564557a
MD		 1656static void sh_mobile_lcdc_fillrect(struct fb_info *info,
1657 const struct fb_fillrect *rect)
1658{
1659 sys_fillrect(info, rect);
1660 sh_mobile_lcdc_deferred_io_touch(info);
1661}
1662
1663static void sh_mobile_lcdc_copyarea(struct fb_info *info,
1664 const struct fb_copyarea *area)
1665{
1666 sys_copyarea(info, area);
1667 sh_mobile_lcdc_deferred_io_touch(info);
1668}
1669
1670static void sh_mobile_lcdc_imageblit(struct fb_info *info,
1671 const struct fb_image *image)
1672{
1673 sys_imageblit(info, image);
1674 sh_mobile_lcdc_deferred_io_touch(info);
1675}
1676
d7ad3342
LP		 1677static int sh_mobile_lcdc_pan(struct fb_var_screeninfo *var,
1678 struct fb_info *info)
9dd38819
PE		 1679{
1680 struct sh_mobile_lcdc_chan *ch = info->par;
92e1f9a7
PE		 1681 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
1682 unsigned long ldrcntr;
a4aa25f6
LP		 1683 unsigned long base_addr_y, base_addr_c;
1684 unsigned long y_offset;
53b50314 1685 unsigned long c_offset;
92e1f9a7 1686
a4aa25f6
LP		 1687 if (!ch->format->yuv) {
1688 y_offset = (var->yoffset * ch->xres_virtual + var->xoffset)
1689 * ch->format->bpp / 8;
1690 c_offset = 0;
1691 } else {
1692 unsigned int xsub = ch->format->bpp < 24 ? 2 : 1;
1693 unsigned int ysub = ch->format->bpp < 16 ? 2 : 1;
9dd38819 1694
a4aa25f6
LP		 1695 y_offset = var->yoffset * ch->xres_virtual + var->xoffset;
1696 c_offset = var->yoffset / ysub * ch->xres_virtual * 2 / xsub
1697 + var->xoffset * 2 / xsub;
1698 }
9dd38819 1699
a4aa25f6
LP		 1700 /* If the Y offset hasn't changed, the C offset hasn't either. There's
1701 * nothing to do in that case.
1702 */
1703 if (y_offset == ch->pan_y_offset)
1704 return 0;
9dd38819 1705
92e1f9a7 1706 /* Set the source address for the next refresh */
a4aa25f6
LP		 1707 base_addr_y = ch->dma_handle + y_offset;
1708 base_addr_c = ch->dma_handle + ch->xres_virtual * ch->yres_virtual
1709 + c_offset;
53b50314 1710
49d79ba2
LP		 1711 ch->base_addr_y = base_addr_y;
1712 ch->base_addr_c = base_addr_c;
a4aa25f6 1713 ch->pan_y_offset = y_offset;
7caa4342 1714
49d79ba2 1715 lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
58f03d99 1716 if (ch->format->yuv)
49d79ba2 1717 lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
53b50314 1718
a4aa25f6 1719 ldrcntr = lcdc_read(priv, _LDRCNTR);
92e1f9a7
PE		 1720 if (lcdc_chan_is_sublcd(ch))
1721 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
1722 else
1723 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS);
1724
92e1f9a7
PE		 1725
1726 sh_mobile_lcdc_deferred_io_touch(info);
9dd38819
PE		 1727
1728 return 0;
1729}
1730
d7ad3342
LP		 1731static int sh_mobile_lcdc_ioctl(struct fb_info *info, unsigned int cmd,
1732 unsigned long arg)
40331b21 1733{
d7ad3342 1734 struct sh_mobile_lcdc_chan *ch = info->par;
40331b21
PE		 1735 int retval;
1736
1737 switch (cmd) {
1738 case FBIO_WAITFORVSYNC:
d7ad3342 1739 retval = sh_mobile_lcdc_wait_for_vsync(ch);
40331b21
PE		 1740 break;
1741
1742 default:
1743 retval = -ENOIOCTLCMD;
1744 break;
1745 }
1746 return retval;
1747}
1748
dd210503
GL		 1749static void sh_mobile_fb_reconfig(struct fb_info *info)
1750{
1751 struct sh_mobile_lcdc_chan *ch = info->par;
2d04559d
LP		 1752 struct fb_var_screeninfo var;
1753 struct fb_videomode mode;
dd210503
GL		 1754
1755 if (ch->use_count > 1 || (ch->use_count == 1 && !info->fbcon_par))
1756 /* More framebuffer users are active */
1757 return;
1758
2d04559d 1759 fb_var_to_videomode(&mode, &info->var);
dd210503 1760
2d04559d 1761 if (fb_mode_is_equal(&ch->display.mode, &mode))
dd210503
GL		 1762 return;
1763
1764 /* Display has been re-plugged, framebuffer is free now, reconfigure */
2d04559d
LP		 1765 var = info->var;
1766 fb_videomode_to_var(&var, &ch->display.mode);
1767 var.width = ch->display.width;
1768 var.height = ch->display.height;
1769 var.activate = FB_ACTIVATE_NOW;
1770
1771 if (fb_set_var(info, &var) < 0)
dd210503
GL		 1772 /* Couldn't reconfigure, hopefully, can continue as before */
1773 return;
1774
9e146700 1775 fbcon_update_vcs(info, true);
dd210503
GL		 1776}
1777
1778/*
1779 * Locking: both .fb_release() and .fb_open() are called with info->lock held if
1780 * user == 1, or with console sem held, if user == 0.
1781 */
d7ad3342 1782static int sh_mobile_lcdc_release(struct fb_info *info, int user)
dd210503
GL		 1783{
1784 struct sh_mobile_lcdc_chan *ch = info->par;
1785
1786 mutex_lock(&ch->open_lock);
1787 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1788
1789 ch->use_count--;
1790
1791 /* Nothing to reconfigure, when called from fbcon */
1792 if (user) {
ac751efa 1793 console_lock();
dd210503 1794 sh_mobile_fb_reconfig(info);
ac751efa 1795 console_unlock();
dd210503
GL		 1796 }
1797
1798 mutex_unlock(&ch->open_lock);
1799
1800 return 0;
1801}
1802
d7ad3342 1803static int sh_mobile_lcdc_open(struct fb_info *info, int user)
dd210503
GL		 1804{
1805 struct sh_mobile_lcdc_chan *ch = info->par;
1806
1807 mutex_lock(&ch->open_lock);
1808 ch->use_count++;
1809
1810 dev_dbg(info->dev, "%s(): %d users\n", __func__, ch->use_count);
1811 mutex_unlock(&ch->open_lock);
1812
1813 return 0;
1814}
1815
d7ad3342
LP		 1816static int sh_mobile_lcdc_check_var(struct fb_var_screeninfo *var,
1817 struct fb_info *info)
dd210503
GL		 1818{
1819 struct sh_mobile_lcdc_chan *ch = info->par;
417d4827 1820 struct sh_mobile_lcdc_priv *p = ch->lcdc;
03862194
LP		 1821 unsigned int best_dist = (unsigned int)-1;
1822 unsigned int best_xres = 0;
1823 unsigned int best_yres = 0;
1824 unsigned int i;
c5deac3c 1825 int ret;
03862194
LP		 1826
1827 /* If board code provides us with a list of available modes, make sure
1828 * we use one of them. Find the mode closest to the requested one. The
1829 * distance between two modes is defined as the size of the
1830 * non-overlapping parts of the two rectangles.
1831 */
b5ef967d
LP		 1832 for (i = 0; i < ch->cfg->num_modes; ++i) {
1833 const struct fb_videomode *mode = &ch->cfg->lcd_modes[i];
03862194
LP		 1834 unsigned int dist;
1835
1836 /* We can only round up. */
1837 if (var->xres > mode->xres || var->yres > mode->yres)
1838 continue;
1839
1840 dist = var->xres * var->yres + mode->xres * mode->yres
1841 - 2 * min(var->xres, mode->xres)
1842 * min(var->yres, mode->yres);
1843
1844 if (dist < best_dist) {
1845 best_xres = mode->xres;
1846 best_yres = mode->yres;
1847 best_dist = dist;
1848 }
dd210503 1849 }
417d4827 1850
03862194 1851 /* If no available mode can be used, return an error. */
b5ef967d 1852 if (ch->cfg->num_modes != 0) {
03862194
LP		 1853 if (best_dist == (unsigned int)-1)
1854 return -EINVAL;
1855
1856 var->xres = best_xres;
1857 var->yres = best_yres;
1858 }
1859
c5deac3c
LP		 1860 ret = __sh_mobile_lcdc_check_var(var, info);
1861 if (ret < 0)
1862 return ret;
03862194 1863
edd153a3
LP		 1864 /* only accept the forced_fourcc for dual channel configurations */
1865 if (p->forced_fourcc &&
1866 p->forced_fourcc != sh_mobile_format_fourcc(var))
417d4827 1867 return -EINVAL;
417d4827 1868
dd210503
GL		 1869 return 0;
1870}
40331b21 1871
d7ad3342 1872static int sh_mobile_lcdc_set_par(struct fb_info *info)
ed5bebf2
LP		 1873{
1874 struct sh_mobile_lcdc_chan *ch = info->par;
1875 int ret;
1876
1877 sh_mobile_lcdc_stop(ch->lcdc);
91fba48d 1878
fc9e78e6 1879 ch->format = sh_mobile_format_info(sh_mobile_format_fourcc(&info->var));
58f03d99
LP		 1880 ch->colorspace = info->var.colorspace;
1881
1882 ch->xres = info->var.xres;
1883 ch->xres_virtual = info->var.xres_virtual;
1884 ch->yres = info->var.yres;
1885 ch->yres_virtual = info->var.yres_virtual;
1886
1887 if (ch->format->yuv)
16ca21c9 1888 ch->pitch = info->var.xres_virtual;
58f03d99 1889 else
16ca21c9 1890 ch->pitch = info->var.xres_virtual * ch->format->bpp / 8;
fc9e78e6 1891
ed5bebf2 1892 ret = sh_mobile_lcdc_start(ch->lcdc);
58f03d99 1893 if (ret < 0)
ed5bebf2 1894 dev_err(info->dev, "%s: unable to restart LCDC\n", __func__);
58f03d99
LP		 1895
1896 info->fix.line_length = ch->pitch;
ed5bebf2 1897
edd153a3
LP		 1898 if (sh_mobile_format_is_fourcc(&info->var)) {
1899 info->fix.type = FB_TYPE_FOURCC;
1900 info->fix.visual = FB_VISUAL_FOURCC;
1901 } else {
1902 info->fix.type = FB_TYPE_PACKED_PIXELS;
1903 info->fix.visual = FB_VISUAL_TRUECOLOR;
1904 }
1905
ed5bebf2
LP		 1906 return ret;
1907}
1908
8857b9aa
AC		 1909/*
1910 * Screen blanking. Behavior is as follows:
1911 * FB_BLANK_UNBLANK: screen unblanked, clocks enabled
1912 * FB_BLANK_NORMAL: screen blanked, clocks enabled
1913 * FB_BLANK_VSYNC,
1914 * FB_BLANK_HSYNC,
1915 * FB_BLANK_POWEROFF: screen blanked, clocks disabled
1916 */
1917static int sh_mobile_lcdc_blank(int blank, struct fb_info *info)
1918{
1919 struct sh_mobile_lcdc_chan *ch = info->par;
1920 struct sh_mobile_lcdc_priv *p = ch->lcdc;
1921
1922 /* blank the screen? */
1923 if (blank > FB_BLANK_UNBLANK && ch->blank_status == FB_BLANK_UNBLANK) {
1924 struct fb_fillrect rect = {
58f03d99
LP		 1925 .width = ch->xres,
1926 .height = ch->yres,
8857b9aa
AC		 1927 };
1928 sh_mobile_lcdc_fillrect(info, &rect);
1929 }
1930 /* turn clocks on? */
1931 if (blank <= FB_BLANK_NORMAL && ch->blank_status > FB_BLANK_NORMAL) {
1932 sh_mobile_lcdc_clk_on(p);
1933 }
1934 /* turn clocks off? */
1935 if (blank > FB_BLANK_NORMAL && ch->blank_status <= FB_BLANK_NORMAL) {
1936 /* make sure the screen is updated with the black fill before
1937 * switching the clocks off. one vsync is not enough since
1938 * blanking may occur in the middle of a refresh. deferred io
1939 * mode will reenable the clocks and update the screen in time,
1940 * so it does not need this. */
1941 if (!info->fbdefio) {
d7ad3342
LP		 1942 sh_mobile_lcdc_wait_for_vsync(ch);
1943 sh_mobile_lcdc_wait_for_vsync(ch);
8857b9aa
AC		 1944 }
1945 sh_mobile_lcdc_clk_off(p);
1946 }
1947
1948 ch->blank_status = blank;
1949 return 0;
1950}
1951
bf10a537
HE		 1952static int
1953sh_mobile_lcdc_mmap(struct fb_info *info, struct vm_area_struct *vma)
1954{
1955 struct sh_mobile_lcdc_chan *ch = info->par;
1956
1957 return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem,
1958 ch->dma_handle, ch->fb_size);
1959}
1960
8a48ac33 1961static const struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 1962 .owner = THIS_MODULE,
cfb4f5d1 1963 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 1964 .fb_read = fb_sys_read,
1965 .fb_write = fb_sys_write,
8564557a
MD		 1966 .fb_fillrect = sh_mobile_lcdc_fillrect,
1967 .fb_copyarea = sh_mobile_lcdc_copyarea,
1968 .fb_imageblit = sh_mobile_lcdc_imageblit,
8857b9aa 1969 .fb_blank = sh_mobile_lcdc_blank,
d7ad3342
LP		 1970 .fb_pan_display = sh_mobile_lcdc_pan,
1971 .fb_ioctl = sh_mobile_lcdc_ioctl,
1972 .fb_open = sh_mobile_lcdc_open,
1973 .fb_release = sh_mobile_lcdc_release,
1974 .fb_check_var = sh_mobile_lcdc_check_var,
1975 .fb_set_par = sh_mobile_lcdc_set_par,
bf10a537 1976 .fb_mmap = sh_mobile_lcdc_mmap,
cfb4f5d1
MD		 1977};
1978
a67f379d
LP		 1979static void
1980sh_mobile_lcdc_channel_fb_unregister(struct sh_mobile_lcdc_chan *ch)
1981{
1982 if (ch->info && ch->info->dev)
1983 unregister_framebuffer(ch->info);
1984}
1985
48c68c4f 1986static int
a67f379d
LP		 1987sh_mobile_lcdc_channel_fb_register(struct sh_mobile_lcdc_chan *ch)
1988{
1989 struct fb_info *info = ch->info;
1990 int ret;
1991
1992 if (info->fbdefio) {
1993 ch->sglist = vmalloc(sizeof(struct scatterlist) *
1994 ch->fb_size >> PAGE_SHIFT);
e281018b 1995 if (!ch->sglist)
a67f379d 1996 return -ENOMEM;
a67f379d
LP		 1997 }
1998
1999 info->bl_dev = ch->bl;
2000
2001 ret = register_framebuffer(info);
2002 if (ret < 0)
2003 return ret;
2004
2005 dev_info(ch->lcdc->dev, "registered %s/%s as %dx%d %dbpp.\n",
b5ef967d 2006 dev_name(ch->lcdc->dev), (ch->cfg->chan == LCDC_CHAN_MAINLCD) ?
a67f379d
LP		 2007 "mainlcd" : "sublcd", info->var.xres, info->var.yres,
2008 info->var.bits_per_pixel);
2009
2010 /* deferred io mode: disable clock to save power */
2011 if (info->fbdefio || info->state == FBINFO_STATE_SUSPENDED)
2012 sh_mobile_lcdc_clk_off(ch->lcdc);
2013
2014 return ret;
2015}
2016
2017static void
2018sh_mobile_lcdc_channel_fb_cleanup(struct sh_mobile_lcdc_chan *ch)
2019{
2020 struct fb_info *info = ch->info;
2021
2022 if (!info || !info->device)
2023 return;
2024
f8582758 2025 vfree(ch->sglist);
a67f379d
LP		 2026
2027 fb_dealloc_cmap(&info->cmap);
2028 framebuffer_release(info);
2029}
2030
48c68c4f 2031static int
a67f379d 2032sh_mobile_lcdc_channel_fb_init(struct sh_mobile_lcdc_chan *ch,
352d6138 2033 const struct fb_videomode *modes,
a67f379d
LP		 2034 unsigned int num_modes)
2035{
2036 struct sh_mobile_lcdc_priv *priv = ch->lcdc;
2037 struct fb_var_screeninfo *var;
2038 struct fb_info *info;
2039 int ret;
2040
2041 /* Allocate and initialize the frame buffer device. Create the modes
2042 * list and allocate the color map.
2043 */
2044 info = framebuffer_alloc(0, priv->dev);
0adcdbcb 2045 if (!info)
a67f379d 2046 return -ENOMEM;
a67f379d
LP		 2047
2048 ch->info = info;
2049
2050 info->flags = FBINFO_FLAG_DEFAULT;
2051 info->fbops = &sh_mobile_lcdc_ops;
2052 info->device = priv->dev;
5d30146f 2053 info->screen_buffer = ch->fb_mem;
a67f379d
LP		 2054 info->pseudo_palette = &ch->pseudo_palette;
2055 info->par = ch;
2056
352d6138 2057 fb_videomode_to_modelist(modes, num_modes, &info->modelist);
a67f379d
LP		 2058
2059 ret = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
2060 if (ret < 0) {
2061 dev_err(priv->dev, "unable to allocate cmap\n");
2062 return ret;
2063 }
2064
2065 /* Initialize fixed screen information. Restrict pan to 2 lines steps
2066 * for NV12 and NV21.
2067 */
2068 info->fix = sh_mobile_lcdc_fix;
2069 info->fix.smem_start = ch->dma_handle;
2070 info->fix.smem_len = ch->fb_size;
58f03d99
LP		 2071 info->fix.line_length = ch->pitch;
2072
2073 if (ch->format->yuv)
2074 info->fix.visual = FB_VISUAL_FOURCC;
2075 else
2076 info->fix.visual = FB_VISUAL_TRUECOLOR;
2077
15dede88 2078 switch (ch->format->fourcc) {
15dede88
LP		 2079 case V4L2_PIX_FMT_NV12:
2080 case V4L2_PIX_FMT_NV21:
ac33a207 2081 info->fix.ypanstep = 2;
ad04fae0 2082 fallthrough;
ac33a207
LP		 2083 case V4L2_PIX_FMT_NV16:
2084 case V4L2_PIX_FMT_NV61:
15dede88
LP		 2085 info->fix.xpanstep = 2;
2086 }
a67f379d
LP		 2087
2088 /* Initialize variable screen information using the first mode as
bd5f2c69 2089 * default.
a67f379d
LP		 2090 */
2091 var = &info->var;
352d6138 2092 fb_videomode_to_var(var, modes);
856e8dfe
LP		 2093 var->width = ch->display.width;
2094 var->height = ch->display.height;
bd5f2c69
LP		 2095 var->xres_virtual = ch->xres_virtual;
2096 var->yres_virtual = ch->yres_virtual;
a67f379d
LP		 2097 var->activate = FB_ACTIVATE_NOW;
2098
2099 /* Use the legacy API by default for RGB formats, and the FOURCC API
2100 * for YUV formats.
2101 */
2102 if (!ch->format->yuv)
2103 var->bits_per_pixel = ch->format->bpp;
2104 else
2105 var->grayscale = ch->format->fourcc;
2106
d7ad3342 2107 ret = sh_mobile_lcdc_check_var(var, info);
a67f379d
LP		 2108 if (ret)
2109 return ret;
2110
a67f379d
LP		 2111 return 0;
2112}
2113
f1f60b5f
LP		 2114/* -----------------------------------------------------------------------------
2115 * Backlight
2116 */
2117
3b0fd9d7
AC		 2118static int sh_mobile_lcdc_update_bl(struct backlight_device *bdev)
2119{
2120 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7
AC		 2121 int brightness = bdev->props.brightness;
2122
2123 if (bdev->props.power != FB_BLANK_UNBLANK ||
2124 bdev->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
2125 brightness = 0;
2126
656d4f33 2127 ch->bl_brightness = brightness;
b5ef967d 2128 return ch->cfg->bl_info.set_brightness(brightness);
3b0fd9d7
AC		 2129}
2130
2131static int sh_mobile_lcdc_get_brightness(struct backlight_device *bdev)
2132{
2133 struct sh_mobile_lcdc_chan *ch = bl_get_data(bdev);
3b0fd9d7 2134
656d4f33 2135 return ch->bl_brightness;
3b0fd9d7
AC		 2136}
2137
2138static int sh_mobile_lcdc_check_fb(struct backlight_device *bdev,
2139 struct fb_info *info)
2140{
2141 return (info->bl_dev == bdev);
2142}
2143
0e25884b 2144static const struct backlight_ops sh_mobile_lcdc_bl_ops = {
3b0fd9d7
AC		 2145 .options = BL_CORE_SUSPENDRESUME,
2146 .update_status = sh_mobile_lcdc_update_bl,
2147 .get_brightness = sh_mobile_lcdc_get_brightness,
2148 .check_fb = sh_mobile_lcdc_check_fb,
2149};
2150
2151static struct backlight_device *sh_mobile_lcdc_bl_probe(struct device *parent,
2152 struct sh_mobile_lcdc_chan *ch)
2153{
2154 struct backlight_device *bl;
2155
b5ef967d 2156 bl = backlight_device_register(ch->cfg->bl_info.name, parent, ch,
3b0fd9d7 2157 &sh_mobile_lcdc_bl_ops, NULL);
beee1f20
DC		 2158 if (IS_ERR(bl)) {
2159 dev_err(parent, "unable to register backlight device: %ld\n",
2160 PTR_ERR(bl));
3b0fd9d7
AC		 2161 return NULL;
2162 }
2163
b5ef967d 2164 bl->props.max_brightness = ch->cfg->bl_info.max_brightness;
3b0fd9d7
AC		 2165 bl->props.brightness = bl->props.max_brightness;
2166 backlight_update_status(bl);
2167
2168 return bl;
2169}
2170
2171static void sh_mobile_lcdc_bl_remove(struct backlight_device *bdev)
2172{
2173 backlight_device_unregister(bdev);
2174}
2175
f1f60b5f
LP		 2176/* -----------------------------------------------------------------------------
2177 * Power management
2178 */
2179
2feb075a
MD		 2180static int sh_mobile_lcdc_suspend(struct device *dev)
2181{
2182 struct platform_device *pdev = to_platform_device(dev);
2183
2184 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
2185 return 0;
2186}
2187
2188static int sh_mobile_lcdc_resume(struct device *dev)
2189{
2190 struct platform_device *pdev = to_platform_device(dev);
2191
2192 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
2193}
2194
0246c471
MD		 2195static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
2196{
b2faabc8 2197 struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
0246c471
MD		 2198
2199 /* turn off LCDC hardware */
2427bb24
LP		 2200 lcdc_write(priv, _LDCNT1R, 0);
2201
0246c471
MD		 2202 return 0;
2203}
2204
2205static int sh_mobile_lcdc_runtime_resume(struct device *dev)
2206{
b2faabc8 2207 struct sh_mobile_lcdc_priv *priv = dev_get_drvdata(dev);
0246c471 2208
2427bb24 2209 __sh_mobile_lcdc_start(priv);
0246c471
MD		 2210
2211 return 0;
2212}
2213
47145210 2214static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 2215 .suspend = sh_mobile_lcdc_suspend,
2216 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 2217 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
2218 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 2219};
2220
f1f60b5f
LP		 2221/* -----------------------------------------------------------------------------
2222 * Framebuffer notifier
2223 */
2224
f1f60b5f
LP		 2225/* -----------------------------------------------------------------------------
2226 * Probe/remove and driver init/exit
2227 */
2228
48c68c4f 2229static const struct fb_videomode default_720p = {
f1f60b5f
LP		 2230 .name = "HDMI 720p",
2231 .xres = 1280,
2232 .yres = 720,
2233
2234 .left_margin = 220,
2235 .right_margin = 110,
2236 .hsync_len = 40,
2237
2238 .upper_margin = 20,
2239 .lower_margin = 5,
2240 .vsync_len = 5,
2241
2242 .pixclock = 13468,
2243 .refresh = 60,
2244 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
2245};
2246
b4bee692
LP		 2247static int sh_mobile_lcdc_remove(struct platform_device *pdev)
2248{
2249 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
c5deac3c 2250 unsigned int i;
b4bee692 2251
c5deac3c
LP		 2252 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++)
2253 sh_mobile_lcdc_overlay_fb_unregister(&priv->overlays[i]);
b4bee692 2254 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
a67f379d 2255 sh_mobile_lcdc_channel_fb_unregister(&priv->ch[i]);
b4bee692
LP		 2256
2257 sh_mobile_lcdc_stop(priv);
2258
c5deac3c
LP		 2259 for (i = 0; i < ARRAY_SIZE(priv->overlays); i++) {
2260 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2261
2262 sh_mobile_lcdc_overlay_fb_cleanup(ovl);
2263
2264 if (ovl->fb_mem)
2265 dma_free_coherent(&pdev->dev, ovl->fb_size,
2266 ovl->fb_mem, ovl->dma_handle);
2267 }
2268
b4bee692 2269 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
9a2985e7 2270 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
b4bee692 2271
e34d0bbb
LP		 2272 if (ch->tx_dev) {
2273 ch->tx_dev->lcdc = NULL;
b5ef967d 2274 module_put(ch->cfg->tx_dev->dev.driver->owner);
e34d0bbb 2275 }
9a2985e7 2276
a67f379d 2277 sh_mobile_lcdc_channel_fb_cleanup(ch);
b4bee692 2278
a67f379d
LP		 2279 if (ch->fb_mem)
2280 dma_free_coherent(&pdev->dev, ch->fb_size,
2281 ch->fb_mem, ch->dma_handle);
b4bee692
LP		 2282 }
2283
2284 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
0c75c4e0
LP		 2285 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
2286
2287 if (ch->bl)
2288 sh_mobile_lcdc_bl_remove(ch->bl);
2289 mutex_destroy(&ch->open_lock);
b4bee692
LP		 2290 }
2291
4774c12a
LP		 2292 if (priv->dot_clk) {
2293 pm_runtime_disable(&pdev->dev);
b4bee692 2294 clk_put(priv->dot_clk);
4774c12a 2295 }
b4bee692
LP		 2296
2297 if (priv->base)
2298 iounmap(priv->base);
2299
2300 if (priv->irq)
2301 free_irq(priv->irq, priv);
2302 kfree(priv);
2303 return 0;
2304}
cfb4f5d1 2305
48c68c4f 2306static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
f1f60b5f 2307{
b5ef967d 2308 int interface_type = ch->cfg->interface_type;
f1f60b5f
LP		 2309
2310 switch (interface_type) {
2311 case RGB8:
2312 case RGB9:
2313 case RGB12A:
2314 case RGB12B:
2315 case RGB16:
2316 case RGB18:
2317 case RGB24:
2318 case SYS8A:
2319 case SYS8B:
2320 case SYS8C:
2321 case SYS8D:
2322 case SYS9:
2323 case SYS12:
2324 case SYS16A:
2325 case SYS16B:
2326 case SYS16C:
2327 case SYS18:
2328 case SYS24:
2329 break;
2330 default:
2331 return -EINVAL;
2332 }
2333
2334 /* SUBLCD only supports SYS interface */
2335 if (lcdc_chan_is_sublcd(ch)) {
2336 if (!(interface_type & LDMT1R_IFM))
2337 return -EINVAL;
2338
2339 interface_type &= ~LDMT1R_IFM;
2340 }
2341
2342 ch->ldmt1r_value = interface_type;
2343 return 0;
2344}
2345
48c68c4f 2346static int
0707330b 2347sh_mobile_lcdc_overlay_init(struct sh_mobile_lcdc_overlay *ovl)
c5deac3c
LP		 2348{
2349 const struct sh_mobile_lcdc_format_info *format;
0707330b 2350 struct device *dev = ovl->channel->lcdc->dev;
c5deac3c
LP		 2351 int ret;
2352
2353 if (ovl->cfg->fourcc == 0)
2354 return 0;
2355
2356 /* Validate the format. */
2357 format = sh_mobile_format_info(ovl->cfg->fourcc);
2358 if (format == NULL) {
0707330b 2359 dev_err(dev, "Invalid FOURCC %08x\n", ovl->cfg->fourcc);
c5deac3c
LP		 2360 return -EINVAL;
2361 }
2362
2363 ovl->enabled = false;
2364 ovl->mode = LCDC_OVERLAY_BLEND;
2365 ovl->alpha = 255;
2366 ovl->rop3 = 0;
2367 ovl->pos_x = 0;
2368 ovl->pos_y = 0;
2369
2370 /* The default Y virtual resolution is twice the panel size to allow for
2371 * double-buffering.
2372 */
2373 ovl->format = format;
2374 ovl->xres = ovl->cfg->max_xres;
2375 ovl->xres_virtual = ovl->xres;
2376 ovl->yres = ovl->cfg->max_yres;
2377 ovl->yres_virtual = ovl->yres * 2;
2378
2379 if (!format->yuv)
16ca21c9 2380 ovl->pitch = ovl->xres_virtual * format->bpp / 8;
c5deac3c 2381 else
16ca21c9 2382 ovl->pitch = ovl->xres_virtual;
c5deac3c
LP		 2383
2384 /* Allocate frame buffer memory. */
2385 ovl->fb_size = ovl->cfg->max_xres * ovl->cfg->max_yres
2386 * format->bpp / 8 * 2;
0707330b
LP		 2387 ovl->fb_mem = dma_alloc_coherent(dev, ovl->fb_size, &ovl->dma_handle,
2388 GFP_KERNEL);
c5deac3c 2389 if (!ovl->fb_mem) {
0707330b 2390 dev_err(dev, "unable to allocate buffer\n");
c5deac3c
LP		 2391 return -ENOMEM;
2392 }
2393
2394 ret = sh_mobile_lcdc_overlay_fb_init(ovl);
2395 if (ret < 0)
2396 return ret;
2397
2398 return 0;
2399}
2400
48c68c4f 2401static int
0707330b 2402sh_mobile_lcdc_channel_init(struct sh_mobile_lcdc_chan *ch)
cfb4f5d1 2403{
105784bb 2404 const struct sh_mobile_lcdc_format_info *format;
b5ef967d 2405 const struct sh_mobile_lcdc_chan_cfg *cfg = ch->cfg;
0707330b 2406 struct device *dev = ch->lcdc->dev;
3ce05599
LP		 2407 const struct fb_videomode *max_mode;
2408 const struct fb_videomode *mode;
a67f379d 2409 unsigned int num_modes;
3ce05599 2410 unsigned int max_size;
a67f379d 2411 unsigned int i;
3ce05599 2412
105784bb
LP		 2413 /* Validate the format. */
2414 format = sh_mobile_format_info(cfg->fourcc);
2415 if (format == NULL) {
0707330b 2416 dev_err(dev, "Invalid FOURCC %08x.\n", cfg->fourcc);
105784bb
LP		 2417 return -EINVAL;
2418 }
2419
3ce05599
LP		 2420 /* Iterate through the modes to validate them and find the highest
2421 * resolution.
2422 */
2423 max_mode = NULL;
2424 max_size = 0;
2425
93ff2598 2426 for (i = 0, mode = cfg->lcd_modes; i < cfg->num_modes; i++, mode++) {
3ce05599
LP		 2427 unsigned int size = mode->yres * mode->xres;
2428
edd153a3
LP		 2429 /* NV12/NV21 buffers must have even number of lines */
2430 if ((cfg->fourcc == V4L2_PIX_FMT_NV12 ||
2431 cfg->fourcc == V4L2_PIX_FMT_NV21) && (mode->yres & 0x1)) {
0707330b 2432 dev_err(dev, "yres must be multiple of 2 for "
0a7f17aa 2433 "YCbCr420 mode.\n");
3ce05599
LP		 2434 return -EINVAL;
2435 }
2436
2437 if (size > max_size) {
2438 max_mode = mode;
2439 max_size = size;
2440 }
2441 }
2442
2443 if (!max_size)
2444 max_size = MAX_XRES * MAX_YRES;
2445 else
0707330b 2446 dev_dbg(dev, "Found largest videomode %ux%u\n",
3ce05599
LP		 2447 max_mode->xres, max_mode->yres);
2448
93ff2598 2449 if (cfg->lcd_modes == NULL) {
3ce05599 2450 mode = &default_720p;
93ff2598 2451 num_modes = 1;
3ce05599 2452 } else {
93ff2598
LP		 2453 mode = cfg->lcd_modes;
2454 num_modes = cfg->num_modes;
3ce05599
LP		 2455 }
2456
bd5f2c69
LP		 2457 /* Use the first mode as default. The default Y virtual resolution is
2458 * twice the panel size to allow for double-buffering.
2459 */
58f03d99
LP		 2460 ch->format = format;
2461 ch->xres = mode->xres;
2462 ch->xres_virtual = mode->xres;
2463 ch->yres = mode->yres;
2464 ch->yres_virtual = mode->yres * 2;
2465
2466 if (!format->yuv) {
2467 ch->colorspace = V4L2_COLORSPACE_SRGB;
16ca21c9 2468 ch->pitch = ch->xres_virtual * format->bpp / 8;
58f03d99
LP		 2469 } else {
2470 ch->colorspace = V4L2_COLORSPACE_REC709;
16ca21c9 2471 ch->pitch = ch->xres_virtual;
58f03d99
LP		 2472 }
2473
a67f379d
LP		 2474 ch->display.width = cfg->panel_cfg.width;
2475 ch->display.height = cfg->panel_cfg.height;
2476 ch->display.mode = *mode;
2477
2478 /* Allocate frame buffer memory. */
2479 ch->fb_size = max_size * format->bpp / 8 * 2;
0707330b 2480 ch->fb_mem = dma_alloc_coherent(dev, ch->fb_size, &ch->dma_handle,
a67f379d
LP		 2481 GFP_KERNEL);
2482 if (ch->fb_mem == NULL) {
0707330b 2483 dev_err(dev, "unable to allocate buffer\n");
a67f379d
LP		 2484 return -ENOMEM;
2485 }
3ce05599 2486
13f80eea
LP		 2487 /* Initialize the transmitter device if present. */
2488 if (cfg->tx_dev) {
2489 if (!cfg->tx_dev->dev.driver ||
2490 !try_module_get(cfg->tx_dev->dev.driver->owner)) {
0707330b 2491 dev_warn(dev, "unable to get transmitter device\n");
13f80eea
LP		 2492 return -EINVAL;
2493 }
2494 ch->tx_dev = platform_get_drvdata(cfg->tx_dev);
2495 ch->tx_dev->lcdc = ch;
2496 ch->tx_dev->def_mode = *mode;
2497 }
2498
a67f379d 2499 return sh_mobile_lcdc_channel_fb_init(ch, mode, num_modes);
3ce05599
LP		 2500}
2501
48c68c4f 2502static int sh_mobile_lcdc_probe(struct platform_device *pdev)
3ce05599 2503{
01ac25b5 2504 struct sh_mobile_lcdc_info *pdata = pdev->dev.platform_data;
3ce05599 2505 struct sh_mobile_lcdc_priv *priv;
cfb4f5d1 2506 struct resource *res;
3ce05599 2507 int num_channels;
cfb4f5d1 2508 int error;
7374ccc0 2509 int irq, i;
cfb4f5d1 2510
01ac25b5 2511 if (!pdata) {
cfb4f5d1 2512 dev_err(&pdev->dev, "no platform data defined\n");
8bed9055 2513 return -EINVAL;
cfb4f5d1
MD		 2514 }
2515
2516 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7374ccc0
GU		 2517 irq = platform_get_irq(pdev, 0);
2518 if (!res || irq < 0) {
8564557a 2519 dev_err(&pdev->dev, "cannot get platform resources\n");
8bed9055 2520 return -ENOENT;
cfb4f5d1
MD		 2521 }
2522
2523 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
e281018b 2524 if (!priv)
8bed9055 2525 return -ENOMEM;
cfb4f5d1 2526
4774c12a 2527 priv->dev = &pdev->dev;
9076aa99 2528
7374ccc0
GU		 2529 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
2530 mutex_init(&priv->ch[i].open_lock);
8bed9055
GL		 2531 platform_set_drvdata(pdev, priv);
2532
7374ccc0 2533 error = request_irq(irq, sh_mobile_lcdc_irq, 0,
7ad33e74 2534 dev_name(&pdev->dev), priv);
8564557a
MD		 2535 if (error) {
2536 dev_err(&pdev->dev, "unable to request irq\n");
2537 goto err1;
2538 }
2539
7374ccc0 2540 priv->irq = irq;
5ef6b505 2541 atomic_set(&priv->hw_usecnt, -1);
cfb4f5d1 2542
3ce05599
LP		 2543 for (i = 0, num_channels = 0; i < ARRAY_SIZE(pdata->ch); i++) {
2544 struct sh_mobile_lcdc_chan *ch = priv->ch + num_channels;
cfb4f5d1 2545
01ac25b5 2546 ch->lcdc = priv;
b5ef967d 2547 ch->cfg = &pdata->ch[i];
cfb4f5d1 2548
01ac25b5 2549 error = sh_mobile_lcdc_check_interface(ch);
cfb4f5d1
MD		 2550 if (error) {
2551 dev_err(&pdev->dev, "unsupported interface type\n");
2552 goto err1;
2553 }
01ac25b5
GL		 2554 init_waitqueue_head(&ch->frame_end_wait);
2555 init_completion(&ch->vsync_completion);
cfb4f5d1 2556
3b0fd9d7 2557 /* probe the backlight is there is one defined */
b5ef967d 2558 if (ch->cfg->bl_info.max_brightness)
3b0fd9d7
AC		 2559 ch->bl = sh_mobile_lcdc_bl_probe(&pdev->dev, ch);
2560
cfb4f5d1
MD		 2561 switch (pdata->ch[i].chan) {
2562 case LCDC_CHAN_MAINLCD:
ce1c0b08 2563 ch->enabled = LDCNT2R_ME;
01ac25b5 2564 ch->reg_offs = lcdc_offs_mainlcd;
3ce05599 2565 num_channels++;
cfb4f5d1
MD		 2566 break;
2567 case LCDC_CHAN_SUBLCD:
ce1c0b08 2568 ch->enabled = LDCNT2R_SE;
01ac25b5 2569 ch->reg_offs = lcdc_offs_sublcd;
3ce05599 2570 num_channels++;
cfb4f5d1
MD		 2571 break;
2572 }
2573 }
2574
3ce05599 2575 if (!num_channels) {
cfb4f5d1
MD		 2576 dev_err(&pdev->dev, "no channels defined\n");
2577 error = -EINVAL;
2578 goto err1;
2579 }
2580
edd153a3 2581 /* for dual channel LCDC (MAIN + SUB) force shared format setting */
3ce05599 2582 if (num_channels == 2)
edd153a3 2583 priv->forced_fourcc = pdata->ch[0].fourcc;
417d4827 2584
4bdc0d67 2585 priv->base = ioremap(res->start, resource_size(res));
b49898ce
WY		 2586 if (!priv->base) {
2587 error = -ENOMEM;
dba6f385 2588 goto err1;
b49898ce 2589 }
dba6f385 2590
0a7f17aa 2591 error = sh_mobile_lcdc_setup_clocks(priv, pdata->clock_source);
cfb4f5d1
MD		 2592 if (error) {
2593 dev_err(&pdev->dev, "unable to setup clocks\n");
2594 goto err1;
2595 }
2596
4774c12a
LP		 2597 /* Enable runtime PM. */
2598 pm_runtime_enable(&pdev->dev);
7caa4342 2599
3ce05599 2600 for (i = 0; i < num_channels; i++) {
0707330b 2601 struct sh_mobile_lcdc_chan *ch = &priv->ch[i];
c44f9f76 2602
0707330b 2603 error = sh_mobile_lcdc_channel_init(ch);
cfb4f5d1 2604 if (error)
3ce05599 2605 goto err1;
cfb4f5d1
MD		 2606 }
2607
c5deac3c
LP		 2608 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2609 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2610
2611 ovl->cfg = &pdata->overlays[i];
2612 ovl->channel = &priv->ch[0];
2613
0707330b 2614 error = sh_mobile_lcdc_overlay_init(ovl);
c5deac3c
LP		 2615 if (error)
2616 goto err1;
2617 }
2618
cfb4f5d1
MD		 2619 error = sh_mobile_lcdc_start(priv);
2620 if (error) {
2621 dev_err(&pdev->dev, "unable to start hardware\n");
2622 goto err1;
2623 }
2624
3ce05599 2625 for (i = 0; i < num_channels; i++) {
1c6a307a 2626 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1c6a307a 2627
a67f379d
LP		 2628 error = sh_mobile_lcdc_channel_fb_register(ch);
2629 if (error)
cfb4f5d1 2630 goto err1;
cfb4f5d1
MD		 2631 }
2632
c5deac3c
LP		 2633 for (i = 0; i < ARRAY_SIZE(pdata->overlays); i++) {
2634 struct sh_mobile_lcdc_overlay *ovl = &priv->overlays[i];
2635
2636 error = sh_mobile_lcdc_overlay_fb_register(ovl);
2637 if (error)
2638 goto err1;
2639 }
2640
cfb4f5d1 2641 return 0;
8bed9055 2642err1:
cfb4f5d1 2643 sh_mobile_lcdc_remove(pdev);
8bed9055 2644
cfb4f5d1
MD		 2645 return error;
2646}
2647
cfb4f5d1
MD		 2648static struct platform_driver sh_mobile_lcdc_driver = {
2649 .driver = {
2650 .name = "sh_mobile_lcdc_fb",
2feb075a 2651 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 2652 },
2653 .probe = sh_mobile_lcdc_probe,
2654 .remove = sh_mobile_lcdc_remove,
2655};
2656
4277f2c4 2657module_platform_driver(sh_mobile_lcdc_driver);
cfb4f5d1
MD		 2658
2659MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
2660MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
2661MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)