Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Permedia2 framebuffer driver. | |
3 | * | |
4 | * 2.5/2.6 driver: | |
5 | * Copyright (c) 2003 Jim Hague (jim.hague@acm.org) | |
6 | * | |
7 | * based on 2.4 driver: | |
8 | * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT) | |
9 | * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com) | |
10 | * | |
11 | * and additional input from James Simmon's port of Hannu Mallat's tdfx | |
12 | * driver. | |
13 | * | |
45f169ec | 14 | * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I |
1da177e4 LT |
15 | * have no access to other pm2fb implementations. Sparc (and thus |
16 | * hopefully other big-endian) devices now work, thanks to a lot of | |
17 | * testing work by Ron Murray. I have no access to CVision hardware, | |
18 | * and therefore for now I am omitting the CVision code. | |
19 | * | |
20 | * Multiple boards support has been on the TODO list for ages. | |
21 | * Don't expect this to change. | |
22 | * | |
23 | * This file is subject to the terms and conditions of the GNU General Public | |
24 | * License. See the file COPYING in the main directory of this archive for | |
25 | * more details. | |
26 | * | |
2f7bb99f | 27 | * |
1da177e4 LT |
28 | */ |
29 | ||
1da177e4 LT |
30 | #include <linux/module.h> |
31 | #include <linux/moduleparam.h> | |
32 | #include <linux/kernel.h> | |
33 | #include <linux/errno.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/mm.h> | |
1da177e4 LT |
36 | #include <linux/slab.h> |
37 | #include <linux/delay.h> | |
38 | #include <linux/fb.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/pci.h> | |
1da177e4 LT |
41 | #include <video/permedia2.h> |
42 | #include <video/cvisionppc.h> | |
43 | ||
44 | #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) | |
45 | #error "The endianness of the target host has not been defined." | |
46 | #endif | |
47 | ||
48 | #if !defined(CONFIG_PCI) | |
49 | #error "Only generic PCI cards supported." | |
50 | #endif | |
51 | ||
52 | #undef PM2FB_MASTER_DEBUG | |
53 | #ifdef PM2FB_MASTER_DEBUG | |
3843faa2 | 54 | #define DPRINTK(a, b...) \ |
5ae12170 | 55 | printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b) |
1da177e4 | 56 | #else |
3843faa2 | 57 | #define DPRINTK(a, b...) |
1da177e4 LT |
58 | #endif |
59 | ||
91b3a6f4 KH |
60 | #define PM2_PIXMAP_SIZE (1600 * 4) |
61 | ||
1da177e4 | 62 | /* |
2f7bb99f | 63 | * Driver data |
1da177e4 | 64 | */ |
1ddc28d7 | 65 | static int hwcursor = 1; |
48c68c4f | 66 | static char *mode_option; |
1da177e4 LT |
67 | |
68 | /* | |
69 | * The XFree GLINT driver will (I think to implement hardware cursor | |
70 | * support on TVP4010 and similar where there is no RAMDAC - see | |
71 | * comment in set_video) always request +ve sync regardless of what | |
72 | * the mode requires. This screws me because I have a Sun | |
73 | * fixed-frequency monitor which absolutely has to have -ve sync. So | |
74 | * these flags allow the user to specify that requests for +ve sync | |
75 | * should be silently turned in -ve sync. | |
76 | */ | |
90ab5ee9 RR |
77 | static bool lowhsync; |
78 | static bool lowvsync; | |
48c68c4f | 79 | static bool noaccel; |
48c68c4f | 80 | static bool nomtrr; |
1da177e4 LT |
81 | |
82 | /* | |
83 | * The hardware state of the graphics card that isn't part of the | |
84 | * screeninfo. | |
85 | */ | |
86 | struct pm2fb_par | |
87 | { | |
88 | pm2type_t type; /* Board type */ | |
1da177e4 | 89 | unsigned char __iomem *v_regs;/* virtual address of p_regs */ |
2f7bb99f | 90 | u32 memclock; /* memclock */ |
1da177e4 LT |
91 | u32 video; /* video flags before blanking */ |
92 | u32 mem_config; /* MemConfig reg at probe */ | |
93 | u32 mem_control; /* MemControl reg at probe */ | |
94 | u32 boot_address; /* BootAddress reg at probe */ | |
2f7bb99f | 95 | u32 palette[16]; |
f8f05cdc | 96 | int wc_cookie; |
1da177e4 LT |
97 | }; |
98 | ||
99 | /* | |
100 | * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo | |
101 | * if we don't use modedb. | |
102 | */ | |
48c68c4f | 103 | static struct fb_fix_screeninfo pm2fb_fix = { |
2f7bb99f | 104 | .id = "", |
1da177e4 LT |
105 | .type = FB_TYPE_PACKED_PIXELS, |
106 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
107 | .xpanstep = 1, | |
108 | .ypanstep = 1, | |
2f7bb99f | 109 | .ywrapstep = 0, |
87a7cc68 | 110 | .accel = FB_ACCEL_3DLABS_PERMEDIA2, |
1da177e4 LT |
111 | }; |
112 | ||
113 | /* | |
114 | * Default video mode. In case the modedb doesn't work. | |
115 | */ | |
ca9384c5 | 116 | static const struct fb_var_screeninfo pm2fb_var = { |
1da177e4 | 117 | /* "640x480, 8 bpp @ 60 Hz */ |
2f7bb99f KH |
118 | .xres = 640, |
119 | .yres = 480, | |
120 | .xres_virtual = 640, | |
121 | .yres_virtual = 480, | |
122 | .bits_per_pixel = 8, | |
123 | .red = {0, 8, 0}, | |
124 | .blue = {0, 8, 0}, | |
125 | .green = {0, 8, 0}, | |
126 | .activate = FB_ACTIVATE_NOW, | |
127 | .height = -1, | |
128 | .width = -1, | |
129 | .accel_flags = 0, | |
130 | .pixclock = 39721, | |
131 | .left_margin = 40, | |
132 | .right_margin = 24, | |
133 | .upper_margin = 32, | |
134 | .lower_margin = 11, | |
135 | .hsync_len = 96, | |
136 | .vsync_len = 2, | |
137 | .vmode = FB_VMODE_NONINTERLACED | |
1da177e4 LT |
138 | }; |
139 | ||
140 | /* | |
141 | * Utility functions | |
142 | */ | |
143 | ||
3843faa2 | 144 | static inline u32 pm2_RD(struct pm2fb_par *p, s32 off) |
1da177e4 | 145 | { |
45f169ec | 146 | return fb_readl(p->v_regs + off); |
1da177e4 LT |
147 | } |
148 | ||
3843faa2 | 149 | static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v) |
1da177e4 | 150 | { |
45f169ec | 151 | fb_writel(v, p->v_regs + off); |
1da177e4 LT |
152 | } |
153 | ||
3843faa2 | 154 | static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx) |
1da177e4 | 155 | { |
45f169ec | 156 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); |
1da177e4 | 157 | mb(); |
45f169ec KH |
158 | return pm2_RD(p, PM2R_RD_INDEXED_DATA); |
159 | } | |
160 | ||
3843faa2 | 161 | static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx) |
45f169ec KH |
162 | { |
163 | pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); | |
164 | mb(); | |
165 | return pm2_RD(p, PM2VR_RD_INDEXED_DATA); | |
1da177e4 LT |
166 | } |
167 | ||
3843faa2 | 168 | static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) |
1da177e4 | 169 | { |
45f169ec | 170 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx); |
11d1a62c | 171 | wmb(); |
45f169ec | 172 | pm2_WR(p, PM2R_RD_INDEXED_DATA, v); |
11d1a62c | 173 | wmb(); |
1da177e4 LT |
174 | } |
175 | ||
3843faa2 | 176 | static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v) |
1da177e4 LT |
177 | { |
178 | pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff); | |
11d1a62c | 179 | wmb(); |
1da177e4 | 180 | pm2_WR(p, PM2VR_RD_INDEXED_DATA, v); |
11d1a62c | 181 | wmb(); |
1da177e4 LT |
182 | } |
183 | ||
184 | #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT | |
2f7bb99f | 185 | #define WAIT_FIFO(p, a) |
1da177e4 | 186 | #else |
3843faa2 | 187 | static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a) |
1da177e4 | 188 | { |
6416ad73 KH |
189 | while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a) |
190 | cpu_relax(); | |
1da177e4 LT |
191 | } |
192 | #endif | |
193 | ||
194 | /* | |
195 | * partial products for the supported horizontal resolutions. | |
196 | */ | |
2f7bb99f | 197 | #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0)) |
1da177e4 LT |
198 | static const struct { |
199 | u16 width; | |
200 | u16 pp; | |
201 | } pp_table[] = { | |
202 | { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) }, | |
203 | { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) }, | |
204 | { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) }, | |
205 | { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) }, | |
206 | { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) }, | |
207 | { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) }, | |
208 | { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) }, | |
209 | { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) }, | |
210 | { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) }, | |
211 | { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) }, | |
212 | { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) }, | |
213 | { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) }, | |
214 | { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) }, | |
215 | { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) }, | |
216 | { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) }, | |
217 | { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) }, | |
218 | { 0, 0 } }; | |
219 | ||
220 | static u32 partprod(u32 xres) | |
221 | { | |
222 | int i; | |
223 | ||
224 | for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++) | |
225 | ; | |
45f169ec | 226 | if (pp_table[i].width == 0) |
1da177e4 LT |
227 | DPRINTK("invalid width %u\n", xres); |
228 | return pp_table[i].pp; | |
229 | } | |
230 | ||
231 | static u32 to3264(u32 timing, int bpp, int is64) | |
232 | { | |
233 | switch (bpp) { | |
45f169ec KH |
234 | case 24: |
235 | timing *= 3; | |
1da177e4 | 236 | case 8: |
45f169ec | 237 | timing >>= 1; |
1da177e4 | 238 | case 16: |
45f169ec | 239 | timing >>= 1; |
1da177e4 | 240 | case 32: |
1da177e4 LT |
241 | break; |
242 | } | |
45f169ec KH |
243 | if (is64) |
244 | timing >>= 1; | |
1da177e4 LT |
245 | return timing; |
246 | } | |
247 | ||
3843faa2 KH |
248 | static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn, |
249 | unsigned char *pp) | |
1da177e4 LT |
250 | { |
251 | unsigned char m; | |
252 | unsigned char n; | |
253 | unsigned char p; | |
254 | u32 f; | |
255 | s32 curr; | |
256 | s32 delta = 100000; | |
257 | ||
258 | *mm = *nn = *pp = 0; | |
259 | for (n = 2; n < 15; n++) { | |
260 | for (m = 2; m; m++) { | |
261 | f = PM2_REFERENCE_CLOCK * m / n; | |
262 | if (f >= 150000 && f <= 300000) { | |
45f169ec KH |
263 | for (p = 0; p < 5; p++, f >>= 1) { |
264 | curr = (clk > f) ? clk - f : f - clk; | |
265 | if (curr < delta) { | |
266 | delta = curr; | |
267 | *mm = m; | |
268 | *nn = n; | |
269 | *pp = p; | |
1da177e4 LT |
270 | } |
271 | } | |
272 | } | |
273 | } | |
274 | } | |
275 | } | |
276 | ||
3843faa2 KH |
277 | static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn, |
278 | unsigned char *pp) | |
1da177e4 LT |
279 | { |
280 | unsigned char m; | |
281 | unsigned char n; | |
282 | unsigned char p; | |
283 | u32 f; | |
284 | s32 delta = 1000; | |
285 | ||
286 | *mm = *nn = *pp = 0; | |
45f169ec | 287 | for (m = 1; m < 128; m++) { |
d4a96b53 | 288 | for (n = 2 * m + 1; n; n++) { |
45f169ec KH |
289 | for (p = 0; p < 2; p++) { |
290 | f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m; | |
291 | if (clk > f - delta && clk < f + delta) { | |
292 | delta = (clk > f) ? clk - f : f - clk; | |
293 | *mm = m; | |
294 | *nn = n; | |
295 | *pp = p; | |
1da177e4 LT |
296 | } |
297 | } | |
298 | } | |
299 | } | |
300 | } | |
301 | ||
3843faa2 KH |
302 | static void clear_palette(struct pm2fb_par *p) |
303 | { | |
45f169ec | 304 | int i = 256; |
1da177e4 LT |
305 | |
306 | WAIT_FIFO(p, 1); | |
307 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0); | |
308 | wmb(); | |
309 | while (i--) { | |
310 | WAIT_FIFO(p, 3); | |
311 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
312 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
313 | pm2_WR(p, PM2R_RD_PALETTE_DATA, 0); | |
314 | } | |
315 | } | |
316 | ||
3843faa2 | 317 | static void reset_card(struct pm2fb_par *p) |
1da177e4 LT |
318 | { |
319 | if (p->type == PM2_TYPE_PERMEDIA2V) | |
320 | pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0); | |
321 | pm2_WR(p, PM2R_RESET_STATUS, 0); | |
322 | mb(); | |
323 | while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET) | |
6416ad73 | 324 | cpu_relax(); |
1da177e4 LT |
325 | mb(); |
326 | #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT | |
327 | DPRINTK("FIFO disconnect enabled\n"); | |
328 | pm2_WR(p, PM2R_FIFO_DISCON, 1); | |
329 | mb(); | |
330 | #endif | |
331 | ||
332 | /* Restore stashed memory config information from probe */ | |
333 | WAIT_FIFO(p, 3); | |
334 | pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control); | |
335 | pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address); | |
336 | wmb(); | |
337 | pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config); | |
338 | } | |
339 | ||
3843faa2 | 340 | static void reset_config(struct pm2fb_par *p) |
1da177e4 | 341 | { |
138a451c | 342 | WAIT_FIFO(p, 53); |
2f7bb99f | 343 | pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) & |
45f169ec | 344 | ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED)); |
1da177e4 LT |
345 | pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L)); |
346 | pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L)); | |
347 | pm2_WR(p, PM2R_FIFO_CONTROL, 0); | |
348 | pm2_WR(p, PM2R_APERTURE_ONE, 0); | |
349 | pm2_WR(p, PM2R_APERTURE_TWO, 0); | |
350 | pm2_WR(p, PM2R_RASTERIZER_MODE, 0); | |
351 | pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB); | |
352 | pm2_WR(p, PM2R_LB_READ_FORMAT, 0); | |
2f7bb99f | 353 | pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0); |
1da177e4 LT |
354 | pm2_WR(p, PM2R_LB_READ_MODE, 0); |
355 | pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0); | |
356 | pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0); | |
357 | pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0); | |
358 | pm2_WR(p, PM2R_FB_WINDOW_BASE, 0); | |
359 | pm2_WR(p, PM2R_LB_WINDOW_BASE, 0); | |
360 | pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L)); | |
361 | pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L)); | |
362 | pm2_WR(p, PM2R_FB_READ_PIXEL, 0); | |
363 | pm2_WR(p, PM2R_DITHER_MODE, 0); | |
364 | pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0); | |
365 | pm2_WR(p, PM2R_DEPTH_MODE, 0); | |
366 | pm2_WR(p, PM2R_STENCIL_MODE, 0); | |
367 | pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0); | |
368 | pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0); | |
369 | pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0); | |
370 | pm2_WR(p, PM2R_YUV_MODE, 0); | |
371 | pm2_WR(p, PM2R_COLOR_DDA_MODE, 0); | |
372 | pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0); | |
373 | pm2_WR(p, PM2R_FOG_MODE, 0); | |
374 | pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0); | |
375 | pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0); | |
376 | pm2_WR(p, PM2R_STATISTICS_MODE, 0); | |
377 | pm2_WR(p, PM2R_SCISSOR_MODE, 0); | |
378 | pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION); | |
138a451c | 379 | pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff); |
1da177e4 LT |
380 | switch (p->type) { |
381 | case PM2_TYPE_PERMEDIA2: | |
382 | pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */ | |
383 | pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0); | |
384 | pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8); | |
45f169ec KH |
385 | pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0); |
386 | pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0); | |
387 | pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0); | |
388 | pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0); | |
389 | pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0); | |
1da177e4 LT |
390 | break; |
391 | case PM2_TYPE_PERMEDIA2V: | |
392 | pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */ | |
393 | break; | |
394 | } | |
1da177e4 LT |
395 | } |
396 | ||
3843faa2 | 397 | static void set_aperture(struct pm2fb_par *p, u32 depth) |
1da177e4 LT |
398 | { |
399 | /* | |
400 | * The hardware is little-endian. When used in big-endian | |
401 | * hosts, the on-chip aperture settings are used where | |
402 | * possible to translate from host to card byte order. | |
403 | */ | |
45f169ec | 404 | WAIT_FIFO(p, 2); |
1da177e4 LT |
405 | #ifdef __LITTLE_ENDIAN |
406 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); | |
407 | #else | |
408 | switch (depth) { | |
409 | case 24: /* RGB->BGR */ | |
410 | /* | |
411 | * We can't use the aperture to translate host to | |
412 | * card byte order here, so we switch to BGR mode | |
413 | * in pm2fb_set_par(). | |
414 | */ | |
415 | case 8: /* B->B */ | |
416 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD); | |
417 | break; | |
418 | case 16: /* HL->LH */ | |
419 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP); | |
420 | break; | |
421 | case 32: /* RGBA->ABGR */ | |
422 | pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP); | |
423 | break; | |
424 | } | |
425 | #endif | |
426 | ||
3843faa2 | 427 | /* We don't use aperture two, so this may be superflous */ |
1da177e4 LT |
428 | pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD); |
429 | } | |
430 | ||
3843faa2 | 431 | static void set_color(struct pm2fb_par *p, unsigned char regno, |
1da177e4 LT |
432 | unsigned char r, unsigned char g, unsigned char b) |
433 | { | |
434 | WAIT_FIFO(p, 4); | |
435 | pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno); | |
436 | wmb(); | |
437 | pm2_WR(p, PM2R_RD_PALETTE_DATA, r); | |
438 | wmb(); | |
439 | pm2_WR(p, PM2R_RD_PALETTE_DATA, g); | |
440 | wmb(); | |
441 | pm2_WR(p, PM2R_RD_PALETTE_DATA, b); | |
442 | } | |
443 | ||
3843faa2 | 444 | static void set_memclock(struct pm2fb_par *par, u32 clk) |
1da177e4 LT |
445 | { |
446 | int i; | |
447 | unsigned char m, n, p; | |
448 | ||
e5d809d7 KH |
449 | switch (par->type) { |
450 | case PM2_TYPE_PERMEDIA2V: | |
451 | pm2v_mnp(clk/2, &m, &n, &p); | |
45f169ec | 452 | WAIT_FIFO(par, 12); |
e5d809d7 KH |
453 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8); |
454 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0); | |
e5d809d7 KH |
455 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m); |
456 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n); | |
457 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p); | |
e5d809d7 KH |
458 | pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1); |
459 | rmb(); | |
45f169ec KH |
460 | for (i = 256; i; i--) |
461 | if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2) | |
462 | break; | |
e5d809d7 KH |
463 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); |
464 | break; | |
465 | case PM2_TYPE_PERMEDIA2: | |
466 | pm2_mnp(clk, &m, &n, &p); | |
467 | WAIT_FIFO(par, 10); | |
468 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6); | |
e5d809d7 KH |
469 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m); |
470 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n); | |
e5d809d7 | 471 | pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p); |
e5d809d7 KH |
472 | pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS); |
473 | rmb(); | |
45f169ec KH |
474 | for (i = 256; i; i--) |
475 | if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) | |
476 | break; | |
e5d809d7 KH |
477 | break; |
478 | } | |
1da177e4 LT |
479 | } |
480 | ||
3843faa2 | 481 | static void set_pixclock(struct pm2fb_par *par, u32 clk) |
1da177e4 LT |
482 | { |
483 | int i; | |
484 | unsigned char m, n, p; | |
485 | ||
486 | switch (par->type) { | |
487 | case PM2_TYPE_PERMEDIA2: | |
488 | pm2_mnp(clk, &m, &n, &p); | |
45f169ec | 489 | WAIT_FIFO(par, 10); |
1da177e4 | 490 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0); |
1da177e4 LT |
491 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m); |
492 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n); | |
1da177e4 | 493 | pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p); |
1da177e4 LT |
494 | pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS); |
495 | rmb(); | |
45f169ec KH |
496 | for (i = 256; i; i--) |
497 | if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED) | |
498 | break; | |
1da177e4 LT |
499 | break; |
500 | case PM2_TYPE_PERMEDIA2V: | |
501 | pm2v_mnp(clk/2, &m, &n, &p); | |
502 | WAIT_FIFO(par, 8); | |
503 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8); | |
504 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m); | |
505 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n); | |
506 | pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p); | |
507 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
508 | break; | |
509 | } | |
510 | } | |
511 | ||
3843faa2 KH |
512 | static void set_video(struct pm2fb_par *p, u32 video) |
513 | { | |
1da177e4 | 514 | u32 tmp; |
45f169ec | 515 | u32 vsync = video; |
1da177e4 LT |
516 | |
517 | DPRINTK("video = 0x%x\n", video); | |
2f7bb99f | 518 | |
1da177e4 LT |
519 | /* |
520 | * The hardware cursor needs +vsync to recognise vert retrace. | |
521 | * We may not be using the hardware cursor, but the X Glint | |
522 | * driver may well. So always set +hsync/+vsync and then set | |
523 | * the RAMDAC to invert the sync if necessary. | |
524 | */ | |
45f169ec KH |
525 | vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK); |
526 | vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH; | |
1da177e4 | 527 | |
138a451c | 528 | WAIT_FIFO(p, 3); |
1da177e4 LT |
529 | pm2_WR(p, PM2R_VIDEO_CONTROL, vsync); |
530 | ||
531 | switch (p->type) { | |
532 | case PM2_TYPE_PERMEDIA2: | |
533 | tmp = PM2F_RD_PALETTE_WIDTH_8; | |
534 | if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) | |
535 | tmp |= 4; /* invert hsync */ | |
536 | if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) | |
537 | tmp |= 8; /* invert vsync */ | |
538 | pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp); | |
539 | break; | |
540 | case PM2_TYPE_PERMEDIA2V: | |
541 | tmp = 0; | |
542 | if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW) | |
543 | tmp |= 1; /* invert hsync */ | |
544 | if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW) | |
545 | tmp |= 4; /* invert vsync */ | |
546 | pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp); | |
1da177e4 LT |
547 | break; |
548 | } | |
549 | } | |
550 | ||
551 | /* | |
2f7bb99f KH |
552 | * pm2fb_check_var - Optional function. Validates a var passed in. |
553 | * @var: frame buffer variable screen structure | |
554 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
555 | * |
556 | * Checks to see if the hardware supports the state requested by | |
557 | * var passed in. | |
558 | * | |
559 | * Returns negative errno on error, or zero on success. | |
560 | */ | |
561 | static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
562 | { | |
563 | u32 lpitch; | |
564 | ||
565 | if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 && | |
566 | var->bits_per_pixel != 24 && var->bits_per_pixel != 32) { | |
567 | DPRINTK("depth not supported: %u\n", var->bits_per_pixel); | |
568 | return -EINVAL; | |
569 | } | |
570 | ||
571 | if (var->xres != var->xres_virtual) { | |
3843faa2 KH |
572 | DPRINTK("virtual x resolution != " |
573 | "physical x resolution not supported\n"); | |
1da177e4 LT |
574 | return -EINVAL; |
575 | } | |
576 | ||
577 | if (var->yres > var->yres_virtual) { | |
3843faa2 KH |
578 | DPRINTK("virtual y resolution < " |
579 | "physical y resolution not possible\n"); | |
1da177e4 LT |
580 | return -EINVAL; |
581 | } | |
582 | ||
1ddc28d7 KH |
583 | /* permedia cannot blit over 2048 */ |
584 | if (var->yres_virtual > 2047) { | |
585 | var->yres_virtual = 2047; | |
586 | } | |
587 | ||
1da177e4 LT |
588 | if (var->xoffset) { |
589 | DPRINTK("xoffset not supported\n"); | |
590 | return -EINVAL; | |
591 | } | |
592 | ||
593 | if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { | |
594 | DPRINTK("interlace not supported\n"); | |
595 | return -EINVAL; | |
596 | } | |
597 | ||
598 | var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */ | |
45f169ec | 599 | lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3); |
2f7bb99f | 600 | |
1da177e4 LT |
601 | if (var->xres < 320 || var->xres > 1600) { |
602 | DPRINTK("width not supported: %u\n", var->xres); | |
603 | return -EINVAL; | |
604 | } | |
2f7bb99f | 605 | |
1da177e4 LT |
606 | if (var->yres < 200 || var->yres > 1200) { |
607 | DPRINTK("height not supported: %u\n", var->yres); | |
608 | return -EINVAL; | |
609 | } | |
2f7bb99f | 610 | |
1da177e4 LT |
611 | if (lpitch * var->yres_virtual > info->fix.smem_len) { |
612 | DPRINTK("no memory for screen (%ux%ux%u)\n", | |
613 | var->xres, var->yres_virtual, var->bits_per_pixel); | |
614 | return -EINVAL; | |
615 | } | |
2f7bb99f | 616 | |
1da177e4 | 617 | if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) { |
3843faa2 KH |
618 | DPRINTK("pixclock too high (%ldKHz)\n", |
619 | PICOS2KHZ(var->pixclock)); | |
1da177e4 LT |
620 | return -EINVAL; |
621 | } | |
622 | ||
76c7d3ff | 623 | var->transp.offset = 0; |
624 | var->transp.length = 0; | |
3843faa2 | 625 | switch (var->bits_per_pixel) { |
1da177e4 | 626 | case 8: |
3843faa2 KH |
627 | var->red.length = 8; |
628 | var->green.length = 8; | |
629 | var->blue.length = 8; | |
1da177e4 LT |
630 | break; |
631 | case 16: | |
632 | var->red.offset = 11; | |
633 | var->red.length = 5; | |
634 | var->green.offset = 5; | |
635 | var->green.length = 6; | |
636 | var->blue.offset = 0; | |
637 | var->blue.length = 5; | |
638 | break; | |
639 | case 32: | |
640 | var->transp.offset = 24; | |
641 | var->transp.length = 8; | |
642 | var->red.offset = 16; | |
643 | var->green.offset = 8; | |
644 | var->blue.offset = 0; | |
3843faa2 KH |
645 | var->red.length = 8; |
646 | var->green.length = 8; | |
647 | var->blue.length = 8; | |
1da177e4 LT |
648 | break; |
649 | case 24: | |
650 | #ifdef __BIG_ENDIAN | |
651 | var->red.offset = 0; | |
652 | var->blue.offset = 16; | |
653 | #else | |
654 | var->red.offset = 16; | |
655 | var->blue.offset = 0; | |
656 | #endif | |
657 | var->green.offset = 8; | |
3843faa2 KH |
658 | var->red.length = 8; |
659 | var->green.length = 8; | |
660 | var->blue.length = 8; | |
1da177e4 LT |
661 | break; |
662 | } | |
3843faa2 KH |
663 | var->height = -1; |
664 | var->width = -1; | |
2f7bb99f | 665 | |
1da177e4 | 666 | var->accel_flags = 0; /* Can't mmap if this is on */ |
2f7bb99f | 667 | |
1da177e4 LT |
668 | DPRINTK("Checking graphics mode at %dx%d depth %d\n", |
669 | var->xres, var->yres, var->bits_per_pixel); | |
670 | return 0; | |
671 | } | |
672 | ||
673 | /** | |
2f7bb99f KH |
674 | * pm2fb_set_par - Alters the hardware state. |
675 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
676 | * |
677 | * Using the fb_var_screeninfo in fb_info we set the resolution of the | |
678 | * this particular framebuffer. | |
679 | */ | |
680 | static int pm2fb_set_par(struct fb_info *info) | |
681 | { | |
6772a2ee | 682 | struct pm2fb_par *par = info->par; |
1da177e4 | 683 | u32 pixclock; |
45f169ec KH |
684 | u32 width = (info->var.xres_virtual + 7) & ~7; |
685 | u32 height = info->var.yres_virtual; | |
686 | u32 depth = (info->var.bits_per_pixel + 7) & ~7; | |
1da177e4 LT |
687 | u32 hsstart, hsend, hbend, htotal; |
688 | u32 vsstart, vsend, vbend, vtotal; | |
689 | u32 stride; | |
690 | u32 base; | |
691 | u32 video = 0; | |
692 | u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE; | |
693 | u32 txtmap = 0; | |
694 | u32 pixsize = 0; | |
695 | u32 clrformat = 0; | |
138a451c | 696 | u32 misc = 1; /* 8-bit DAC */ |
45f169ec | 697 | u32 xres = (info->var.xres + 31) & ~31; |
1da177e4 LT |
698 | int data64; |
699 | ||
700 | reset_card(par); | |
701 | reset_config(par); | |
702 | clear_palette(par); | |
45f169ec | 703 | if (par->memclock) |
1da177e4 | 704 | set_memclock(par, par->memclock); |
2f7bb99f | 705 | |
1da177e4 LT |
706 | depth = (depth > 32) ? 32 : depth; |
707 | data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V; | |
708 | ||
1da177e4 LT |
709 | pixclock = PICOS2KHZ(info->var.pixclock); |
710 | if (pixclock > PM2_MAX_PIXCLOCK) { | |
711 | DPRINTK("pixclock too high (%uKHz)\n", pixclock); | |
712 | return -EINVAL; | |
713 | } | |
2f7bb99f | 714 | |
1da177e4 LT |
715 | hsstart = to3264(info->var.right_margin, depth, data64); |
716 | hsend = hsstart + to3264(info->var.hsync_len, depth, data64); | |
717 | hbend = hsend + to3264(info->var.left_margin, depth, data64); | |
718 | htotal = to3264(xres, depth, data64) + hbend - 1; | |
719 | vsstart = (info->var.lower_margin) | |
720 | ? info->var.lower_margin - 1 | |
721 | : 0; /* FIXME! */ | |
722 | vsend = info->var.lower_margin + info->var.vsync_len - 1; | |
3843faa2 KH |
723 | vbend = info->var.lower_margin + info->var.vsync_len + |
724 | info->var.upper_margin; | |
1da177e4 LT |
725 | vtotal = info->var.yres + vbend - 1; |
726 | stride = to3264(width, depth, 1); | |
727 | base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1); | |
728 | if (data64) | |
729 | video |= PM2F_DATA_64_ENABLE; | |
2f7bb99f | 730 | |
1da177e4 LT |
731 | if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) { |
732 | if (lowhsync) { | |
733 | DPRINTK("ignoring +hsync, using -hsync.\n"); | |
734 | video |= PM2F_HSYNC_ACT_LOW; | |
735 | } else | |
736 | video |= PM2F_HSYNC_ACT_HIGH; | |
3843faa2 | 737 | } else |
1da177e4 | 738 | video |= PM2F_HSYNC_ACT_LOW; |
3843faa2 | 739 | |
1da177e4 LT |
740 | if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) { |
741 | if (lowvsync) { | |
742 | DPRINTK("ignoring +vsync, using -vsync.\n"); | |
743 | video |= PM2F_VSYNC_ACT_LOW; | |
744 | } else | |
745 | video |= PM2F_VSYNC_ACT_HIGH; | |
3843faa2 | 746 | } else |
1da177e4 | 747 | video |= PM2F_VSYNC_ACT_LOW; |
3843faa2 | 748 | |
45f169ec | 749 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) { |
1da177e4 LT |
750 | DPRINTK("interlaced not supported\n"); |
751 | return -EINVAL; | |
752 | } | |
45f169ec | 753 | if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) |
1da177e4 | 754 | video |= PM2F_LINE_DOUBLE; |
45f169ec | 755 | if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) |
1da177e4 LT |
756 | video |= PM2F_VIDEO_ENABLE; |
757 | par->video = video; | |
758 | ||
759 | info->fix.visual = | |
760 | (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
761 | info->fix.line_length = info->var.xres * depth / 8; | |
762 | info->cmap.len = 256; | |
763 | ||
764 | /* | |
765 | * Settings calculated. Now write them out. | |
766 | */ | |
767 | if (par->type == PM2_TYPE_PERMEDIA2V) { | |
768 | WAIT_FIFO(par, 1); | |
769 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
770 | } | |
2f7bb99f | 771 | |
1da177e4 | 772 | set_aperture(par, depth); |
2f7bb99f | 773 | |
1da177e4 LT |
774 | mb(); |
775 | WAIT_FIFO(par, 19); | |
1da177e4 LT |
776 | switch (depth) { |
777 | case 8: | |
778 | pm2_WR(par, PM2R_FB_READ_PIXEL, 0); | |
138a451c | 779 | clrformat = 0x2e; |
1da177e4 LT |
780 | break; |
781 | case 16: | |
782 | pm2_WR(par, PM2R_FB_READ_PIXEL, 1); | |
783 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565; | |
784 | txtmap = PM2F_TEXTEL_SIZE_16; | |
785 | pixsize = 1; | |
786 | clrformat = 0x70; | |
138a451c | 787 | misc |= 8; |
1da177e4 LT |
788 | break; |
789 | case 32: | |
790 | pm2_WR(par, PM2R_FB_READ_PIXEL, 2); | |
791 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888; | |
792 | txtmap = PM2F_TEXTEL_SIZE_32; | |
793 | pixsize = 2; | |
794 | clrformat = 0x20; | |
138a451c | 795 | misc |= 8; |
1da177e4 LT |
796 | break; |
797 | case 24: | |
798 | pm2_WR(par, PM2R_FB_READ_PIXEL, 4); | |
799 | clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888; | |
800 | txtmap = PM2F_TEXTEL_SIZE_24; | |
801 | pixsize = 4; | |
802 | clrformat = 0x20; | |
138a451c | 803 | misc |= 8; |
1da177e4 LT |
804 | break; |
805 | } | |
806 | pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE); | |
807 | pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); | |
808 | pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres)); | |
809 | pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres)); | |
810 | pm2_WR(par, PM2R_H_TOTAL, htotal); | |
811 | pm2_WR(par, PM2R_HS_START, hsstart); | |
812 | pm2_WR(par, PM2R_HS_END, hsend); | |
813 | pm2_WR(par, PM2R_HG_END, hbend); | |
814 | pm2_WR(par, PM2R_HB_END, hbend); | |
815 | pm2_WR(par, PM2R_V_TOTAL, vtotal); | |
816 | pm2_WR(par, PM2R_VS_START, vsstart); | |
817 | pm2_WR(par, PM2R_VS_END, vsend); | |
818 | pm2_WR(par, PM2R_VB_END, vbend); | |
819 | pm2_WR(par, PM2R_SCREEN_STRIDE, stride); | |
820 | wmb(); | |
821 | pm2_WR(par, PM2R_WINDOW_ORIGIN, 0); | |
822 | pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width); | |
823 | pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE); | |
824 | wmb(); | |
825 | pm2_WR(par, PM2R_SCREEN_BASE, base); | |
826 | wmb(); | |
827 | set_video(par, video); | |
138a451c | 828 | WAIT_FIFO(par, 10); |
1da177e4 LT |
829 | switch (par->type) { |
830 | case PM2_TYPE_PERMEDIA2: | |
831 | pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode); | |
45f169ec | 832 | pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL, |
3843faa2 | 833 | (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF); |
1da177e4 LT |
834 | break; |
835 | case PM2_TYPE_PERMEDIA2V: | |
138a451c | 836 | pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0); |
1da177e4 LT |
837 | pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize); |
838 | pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat); | |
138a451c KH |
839 | pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc); |
840 | pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0); | |
1da177e4 LT |
841 | break; |
842 | } | |
843 | set_pixclock(par, pixclock); | |
844 | DPRINTK("Setting graphics mode at %dx%d depth %d\n", | |
845 | info->var.xres, info->var.yres, info->var.bits_per_pixel); | |
2f7bb99f | 846 | return 0; |
1da177e4 LT |
847 | } |
848 | ||
849 | /** | |
2f7bb99f KH |
850 | * pm2fb_setcolreg - Sets a color register. |
851 | * @regno: boolean, 0 copy local, 1 get_user() function | |
852 | * @red: frame buffer colormap structure | |
853 | * @green: The green value which can be up to 16 bits wide | |
1da177e4 | 854 | * @blue: The blue value which can be up to 16 bits wide. |
2f7bb99f KH |
855 | * @transp: If supported the alpha value which can be up to 16 bits wide. |
856 | * @info: frame buffer info structure | |
857 | * | |
858 | * Set a single color register. The values supplied have a 16 bit | |
859 | * magnitude which needs to be scaled in this function for the hardware. | |
1da177e4 | 860 | * Pretty much a direct lift from tdfxfb.c. |
2f7bb99f | 861 | * |
1da177e4 LT |
862 | * Returns negative errno on error, or zero on success. |
863 | */ | |
864 | static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green, | |
865 | unsigned blue, unsigned transp, | |
866 | struct fb_info *info) | |
867 | { | |
6772a2ee | 868 | struct pm2fb_par *par = info->par; |
1da177e4 LT |
869 | |
870 | if (regno >= info->cmap.len) /* no. of hw registers */ | |
138a451c | 871 | return -EINVAL; |
1da177e4 LT |
872 | /* |
873 | * Program hardware... do anything you want with transp | |
874 | */ | |
875 | ||
876 | /* grayscale works only partially under directcolor */ | |
3843faa2 KH |
877 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ |
878 | if (info->var.grayscale) | |
1da177e4 | 879 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; |
1da177e4 LT |
880 | |
881 | /* Directcolor: | |
882 | * var->{color}.offset contains start of bitfield | |
883 | * var->{color}.length contains length of bitfield | |
884 | * {hardwarespecific} contains width of DAC | |
885 | * cmap[X] is programmed to | |
886 | * (X << red.offset) | (X << green.offset) | (X << blue.offset) | |
887 | * RAMDAC[X] is programmed to (red, green, blue) | |
888 | * | |
889 | * Pseudocolor: | |
890 | * uses offset = 0 && length = DAC register width. | |
891 | * var->{color}.offset is 0 | |
551e378c | 892 | * var->{color}.length contains width of DAC |
1da177e4 LT |
893 | * cmap is not used |
894 | * DAC[X] is programmed to (red, green, blue) | |
895 | * Truecolor: | |
896 | * does not use RAMDAC (usually has 3 of them). | |
897 | * var->{color}.offset contains start of bitfield | |
898 | * var->{color}.length contains length of bitfield | |
899 | * cmap is programmed to | |
900 | * (red << red.offset) | (green << green.offset) | | |
901 | * (blue << blue.offset) | (transp << transp.offset) | |
902 | * RAMDAC does not exist | |
903 | */ | |
2f7bb99f | 904 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16) |
1da177e4 LT |
905 | switch (info->fix.visual) { |
906 | case FB_VISUAL_TRUECOLOR: | |
907 | case FB_VISUAL_PSEUDOCOLOR: | |
908 | red = CNVT_TOHW(red, info->var.red.length); | |
909 | green = CNVT_TOHW(green, info->var.green.length); | |
910 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
911 | transp = CNVT_TOHW(transp, info->var.transp.length); | |
912 | break; | |
913 | case FB_VISUAL_DIRECTCOLOR: | |
2f7bb99f KH |
914 | /* example here assumes 8 bit DAC. Might be different |
915 | * for your hardware */ | |
916 | red = CNVT_TOHW(red, 8); | |
1da177e4 LT |
917 | green = CNVT_TOHW(green, 8); |
918 | blue = CNVT_TOHW(blue, 8); | |
919 | /* hey, there is bug in transp handling... */ | |
920 | transp = CNVT_TOHW(transp, 8); | |
921 | break; | |
922 | } | |
923 | #undef CNVT_TOHW | |
924 | /* Truecolor has hardware independent palette */ | |
925 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
926 | u32 v; | |
927 | ||
928 | if (regno >= 16) | |
138a451c | 929 | return -EINVAL; |
1da177e4 LT |
930 | |
931 | v = (red << info->var.red.offset) | | |
932 | (green << info->var.green.offset) | | |
933 | (blue << info->var.blue.offset) | | |
934 | (transp << info->var.transp.offset); | |
935 | ||
936 | switch (info->var.bits_per_pixel) { | |
937 | case 8: | |
2f7bb99f KH |
938 | break; |
939 | case 16: | |
1da177e4 | 940 | case 24: |
2f7bb99f KH |
941 | case 32: |
942 | par->palette[regno] = v; | |
1da177e4 LT |
943 | break; |
944 | } | |
945 | return 0; | |
3843faa2 | 946 | } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) |
1da177e4 LT |
947 | set_color(par, regno, red, green, blue); |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
952 | /** | |
2f7bb99f KH |
953 | * pm2fb_pan_display - Pans the display. |
954 | * @var: frame buffer variable screen structure | |
955 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 LT |
956 | * |
957 | * Pan (or wrap, depending on the `vmode' field) the display using the | |
2f7bb99f KH |
958 | * `xoffset' and `yoffset' fields of the `var' structure. |
959 | * If the values don't fit, return -EINVAL. | |
1da177e4 | 960 | * |
2f7bb99f | 961 | * Returns negative errno on error, or zero on success. |
1da177e4 LT |
962 | * |
963 | */ | |
964 | static int pm2fb_pan_display(struct fb_var_screeninfo *var, | |
965 | struct fb_info *info) | |
966 | { | |
6772a2ee | 967 | struct pm2fb_par *p = info->par; |
1da177e4 | 968 | u32 base; |
df9306de LP |
969 | u32 depth = (info->var.bits_per_pixel + 7) & ~7; |
970 | u32 xres = (info->var.xres + 31) & ~31; | |
1da177e4 | 971 | |
1da177e4 LT |
972 | depth = (depth > 32) ? 32 : depth; |
973 | base = to3264(var->yoffset * xres + var->xoffset, depth, 1); | |
974 | WAIT_FIFO(p, 1); | |
2f7bb99f | 975 | pm2_WR(p, PM2R_SCREEN_BASE, base); |
1da177e4 LT |
976 | return 0; |
977 | } | |
978 | ||
979 | /** | |
2f7bb99f KH |
980 | * pm2fb_blank - Blanks the display. |
981 | * @blank_mode: the blank mode we want. | |
982 | * @info: frame buffer structure that represents a single frame buffer | |
1da177e4 | 983 | * |
2f7bb99f KH |
984 | * Blank the screen if blank_mode != 0, else unblank. Return 0 if |
985 | * blanking succeeded, != 0 if un-/blanking failed due to e.g. a | |
986 | * video mode which doesn't support it. Implements VESA suspend | |
987 | * and powerdown modes on hardware that supports disabling hsync/vsync: | |
988 | * blank_mode == 2: suspend vsync | |
989 | * blank_mode == 3: suspend hsync | |
990 | * blank_mode == 4: powerdown | |
1da177e4 | 991 | * |
2f7bb99f | 992 | * Returns negative errno on error, or zero on success. |
1da177e4 LT |
993 | * |
994 | */ | |
995 | static int pm2fb_blank(int blank_mode, struct fb_info *info) | |
996 | { | |
6772a2ee | 997 | struct pm2fb_par *par = info->par; |
1da177e4 LT |
998 | u32 video = par->video; |
999 | ||
1000 | DPRINTK("blank_mode %d\n", blank_mode); | |
1001 | ||
1002 | switch (blank_mode) { | |
1003 | case FB_BLANK_UNBLANK: | |
1004 | /* Screen: On */ | |
1005 | video |= PM2F_VIDEO_ENABLE; | |
1006 | break; | |
1007 | case FB_BLANK_NORMAL: | |
1008 | /* Screen: Off */ | |
1009 | video &= ~PM2F_VIDEO_ENABLE; | |
1010 | break; | |
1011 | case FB_BLANK_VSYNC_SUSPEND: | |
1012 | /* VSync: Off */ | |
45f169ec | 1013 | video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1014 | break; |
1015 | case FB_BLANK_HSYNC_SUSPEND: | |
1016 | /* HSync: Off */ | |
45f169ec | 1017 | video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1018 | break; |
1019 | case FB_BLANK_POWERDOWN: | |
1020 | /* HSync: Off, VSync: Off */ | |
3843faa2 | 1021 | video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW); |
1da177e4 LT |
1022 | break; |
1023 | } | |
1024 | set_video(par, video); | |
1025 | return 0; | |
1026 | } | |
1027 | ||
03b9ae4b AD |
1028 | static int pm2fb_sync(struct fb_info *info) |
1029 | { | |
1030 | struct pm2fb_par *par = info->par; | |
1031 | ||
1032 | WAIT_FIFO(par, 1); | |
1033 | pm2_WR(par, PM2R_SYNC, 0); | |
1034 | mb(); | |
1035 | do { | |
1036 | while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0) | |
6416ad73 | 1037 | cpu_relax(); |
03b9ae4b AD |
1038 | } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC)); |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
3843faa2 | 1043 | static void pm2fb_fillrect(struct fb_info *info, |
87a7cc68 KH |
1044 | const struct fb_fillrect *region) |
1045 | { | |
3843faa2 | 1046 | struct pm2fb_par *par = info->par; |
87a7cc68 KH |
1047 | struct fb_fillrect modded; |
1048 | int vxres, vyres; | |
1049 | u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? | |
3843faa2 | 1050 | ((u32 *)info->pseudo_palette)[region->color] : region->color; |
87a7cc68 KH |
1051 | |
1052 | if (info->state != FBINFO_STATE_RUNNING) | |
1053 | return; | |
1054 | if ((info->flags & FBINFO_HWACCEL_DISABLED) || | |
1055 | region->rop != ROP_COPY ) { | |
1056 | cfb_fillrect(info, region); | |
1057 | return; | |
1058 | } | |
1059 | ||
1060 | vxres = info->var.xres_virtual; | |
1061 | vyres = info->var.yres_virtual; | |
1062 | ||
1063 | memcpy(&modded, region, sizeof(struct fb_fillrect)); | |
1064 | ||
45f169ec KH |
1065 | if (!modded.width || !modded.height || |
1066 | modded.dx >= vxres || modded.dy >= vyres) | |
87a7cc68 KH |
1067 | return; |
1068 | ||
45f169ec | 1069 | if (modded.dx + modded.width > vxres) |
87a7cc68 | 1070 | modded.width = vxres - modded.dx; |
45f169ec | 1071 | if (modded.dy + modded.height > vyres) |
87a7cc68 KH |
1072 | modded.height = vyres - modded.dy; |
1073 | ||
45f169ec | 1074 | if (info->var.bits_per_pixel == 8) |
87a7cc68 | 1075 | color |= color << 8; |
45f169ec | 1076 | if (info->var.bits_per_pixel <= 16) |
87a7cc68 KH |
1077 | color |= color << 16; |
1078 | ||
45f169ec KH |
1079 | WAIT_FIFO(par, 3); |
1080 | pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE); | |
1081 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); | |
1082 | pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); | |
1083 | if (info->var.bits_per_pixel != 24) { | |
1084 | WAIT_FIFO(par, 2); | |
1085 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, color); | |
1086 | wmb(); | |
1087 | pm2_WR(par, PM2R_RENDER, | |
1088 | PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL); | |
1089 | } else { | |
30dcc909 KH |
1090 | WAIT_FIFO(par, 4); |
1091 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); | |
1092 | pm2_WR(par, PM2R_CONSTANT_COLOR, color); | |
1093 | wmb(); | |
1094 | pm2_WR(par, PM2R_RENDER, | |
3843faa2 KH |
1095 | PM2F_RENDER_RECTANGLE | |
1096 | PM2F_INCREASE_X | PM2F_INCREASE_Y ); | |
30dcc909 | 1097 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); |
45f169ec | 1098 | } |
87a7cc68 KH |
1099 | } |
1100 | ||
1101 | static void pm2fb_copyarea(struct fb_info *info, | |
1102 | const struct fb_copyarea *area) | |
1103 | { | |
45f169ec | 1104 | struct pm2fb_par *par = info->par; |
87a7cc68 KH |
1105 | struct fb_copyarea modded; |
1106 | u32 vxres, vyres; | |
1107 | ||
1108 | if (info->state != FBINFO_STATE_RUNNING) | |
1109 | return; | |
1110 | if (info->flags & FBINFO_HWACCEL_DISABLED) { | |
1111 | cfb_copyarea(info, area); | |
1112 | return; | |
1113 | } | |
1114 | ||
1115 | memcpy(&modded, area, sizeof(struct fb_copyarea)); | |
1116 | ||
1117 | vxres = info->var.xres_virtual; | |
1118 | vyres = info->var.yres_virtual; | |
1119 | ||
45f169ec KH |
1120 | if (!modded.width || !modded.height || |
1121 | modded.sx >= vxres || modded.sy >= vyres || | |
1122 | modded.dx >= vxres || modded.dy >= vyres) | |
87a7cc68 KH |
1123 | return; |
1124 | ||
45f169ec | 1125 | if (modded.sx + modded.width > vxres) |
87a7cc68 | 1126 | modded.width = vxres - modded.sx; |
45f169ec | 1127 | if (modded.dx + modded.width > vxres) |
87a7cc68 | 1128 | modded.width = vxres - modded.dx; |
45f169ec | 1129 | if (modded.sy + modded.height > vyres) |
87a7cc68 | 1130 | modded.height = vyres - modded.sy; |
45f169ec | 1131 | if (modded.dy + modded.height > vyres) |
87a7cc68 KH |
1132 | modded.height = vyres - modded.dy; |
1133 | ||
45f169ec KH |
1134 | WAIT_FIFO(par, 5); |
1135 | pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE | | |
1136 | PM2F_CONFIG_FB_READ_SOURCE_ENABLE); | |
1137 | pm2_WR(par, PM2R_FB_SOURCE_DELTA, | |
3843faa2 KH |
1138 | ((modded.sy - modded.dy) & 0xfff) << 16 | |
1139 | ((modded.sx - modded.dx) & 0xfff)); | |
45f169ec KH |
1140 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx); |
1141 | pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width); | |
1142 | wmb(); | |
1143 | pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE | | |
3843faa2 KH |
1144 | (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) | |
1145 | (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0)); | |
87a7cc68 KH |
1146 | } |
1147 | ||
91b3a6f4 KH |
1148 | static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image) |
1149 | { | |
1150 | struct pm2fb_par *par = info->par; | |
1151 | u32 height = image->height; | |
1152 | u32 fgx, bgx; | |
3843faa2 | 1153 | const u32 *src = (const u32 *)image->data; |
91b3a6f4 | 1154 | u32 xres = (info->var.xres + 31) & ~31; |
bc9c6a17 KH |
1155 | int raster_mode = 1; /* invert bits */ |
1156 | ||
1157 | #ifdef __LITTLE_ENDIAN | |
1158 | raster_mode |= 3 << 7; /* reverse byte order */ | |
1159 | #endif | |
91b3a6f4 KH |
1160 | |
1161 | if (info->state != FBINFO_STATE_RUNNING) | |
1162 | return; | |
1163 | if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) { | |
1164 | cfb_imageblit(info, image); | |
1165 | return; | |
1166 | } | |
1167 | switch (info->fix.visual) { | |
45f169ec KH |
1168 | case FB_VISUAL_PSEUDOCOLOR: |
1169 | fgx = image->fg_color; | |
1170 | bgx = image->bg_color; | |
1171 | break; | |
1172 | case FB_VISUAL_TRUECOLOR: | |
1173 | default: | |
1174 | fgx = par->palette[image->fg_color]; | |
1175 | bgx = par->palette[image->bg_color]; | |
1176 | break; | |
91b3a6f4 KH |
1177 | } |
1178 | if (info->var.bits_per_pixel == 8) { | |
1179 | fgx |= fgx << 8; | |
1180 | bgx |= bgx << 8; | |
1181 | } | |
1182 | if (info->var.bits_per_pixel <= 16) { | |
1183 | fgx |= fgx << 16; | |
1184 | bgx |= bgx << 16; | |
1185 | } | |
1186 | ||
1187 | WAIT_FIFO(par, 13); | |
1188 | pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres)); | |
1189 | pm2_WR(par, PM2R_SCISSOR_MIN_XY, | |
1190 | ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); | |
1191 | pm2_WR(par, PM2R_SCISSOR_MAX_XY, | |
1192 | (((image->dy + image->height) & 0x0fff) << 16) | | |
1193 | ((image->dx + image->width) & 0x0fff)); | |
1194 | pm2_WR(par, PM2R_SCISSOR_MODE, 1); | |
1195 | /* GXcopy & UNIT_ENABLE */ | |
45f169ec | 1196 | pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1); |
91b3a6f4 KH |
1197 | pm2_WR(par, PM2R_RECTANGLE_ORIGIN, |
1198 | ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff)); | |
1199 | pm2_WR(par, PM2R_RECTANGLE_SIZE, | |
1200 | ((image->height & 0x0fff) << 16) | | |
1201 | ((image->width) & 0x0fff)); | |
1202 | if (info->var.bits_per_pixel == 24) { | |
1203 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 1); | |
1204 | /* clear area */ | |
1205 | pm2_WR(par, PM2R_CONSTANT_COLOR, bgx); | |
1206 | pm2_WR(par, PM2R_RENDER, | |
1207 | PM2F_RENDER_RECTANGLE | | |
45f169ec | 1208 | PM2F_INCREASE_X | PM2F_INCREASE_Y); |
bc9c6a17 KH |
1209 | /* BitMapPackEachScanline */ |
1210 | pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9)); | |
91b3a6f4 KH |
1211 | pm2_WR(par, PM2R_CONSTANT_COLOR, fgx); |
1212 | pm2_WR(par, PM2R_RENDER, | |
1213 | PM2F_RENDER_RECTANGLE | | |
1214 | PM2F_INCREASE_X | PM2F_INCREASE_Y | | |
1215 | PM2F_RENDER_SYNC_ON_BIT_MASK); | |
1216 | } else { | |
1217 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); | |
1218 | /* clear area */ | |
1219 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx); | |
1220 | pm2_WR(par, PM2R_RENDER, | |
1221 | PM2F_RENDER_RECTANGLE | | |
1222 | PM2F_RENDER_FASTFILL | | |
45f169ec | 1223 | PM2F_INCREASE_X | PM2F_INCREASE_Y); |
bc9c6a17 | 1224 | pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode); |
91b3a6f4 KH |
1225 | pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx); |
1226 | pm2_WR(par, PM2R_RENDER, | |
1227 | PM2F_RENDER_RECTANGLE | | |
1228 | PM2F_INCREASE_X | PM2F_INCREASE_Y | | |
1229 | PM2F_RENDER_FASTFILL | | |
1230 | PM2F_RENDER_SYNC_ON_BIT_MASK); | |
1231 | } | |
1232 | ||
1233 | while (height--) { | |
1234 | int width = ((image->width + 7) >> 3) | |
1235 | + info->pixmap.scan_align - 1; | |
1236 | width >>= 2; | |
1237 | WAIT_FIFO(par, width); | |
1238 | while (width--) { | |
1239 | pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src); | |
1240 | src++; | |
1241 | } | |
1242 | } | |
1243 | WAIT_FIFO(par, 3); | |
1244 | pm2_WR(par, PM2R_RASTERIZER_MODE, 0); | |
1245 | pm2_WR(par, PM2R_COLOR_DDA_MODE, 0); | |
1246 | pm2_WR(par, PM2R_SCISSOR_MODE, 0); | |
1247 | } | |
1248 | ||
8f5d050a KH |
1249 | /* |
1250 | * Hardware cursor support. | |
1251 | */ | |
1252 | static const u8 cursor_bits_lookup[16] = { | |
1253 | 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54, | |
1254 | 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55 | |
1255 | }; | |
1256 | ||
1257 | static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
1258 | { | |
1259 | struct pm2fb_par *par = info->par; | |
2a36f9c4 | 1260 | u8 mode = PM2F_CURSORMODE_TYPE_X; |
1ddc28d7 KH |
1261 | int x = cursor->image.dx - info->var.xoffset; |
1262 | int y = cursor->image.dy - info->var.yoffset; | |
8f5d050a | 1263 | |
8f5d050a KH |
1264 | if (cursor->enable) |
1265 | mode |= PM2F_CURSORMODE_CURSOR_ENABLE; | |
1266 | ||
1267 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode); | |
1268 | ||
1ddc28d7 KH |
1269 | if (!cursor->enable) |
1270 | x = 2047; /* push it outside display */ | |
1271 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff); | |
1272 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf); | |
1273 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff); | |
1274 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf); | |
1275 | ||
8f5d050a KH |
1276 | /* |
1277 | * If the cursor is not be changed this means either we want the | |
1278 | * current cursor state (if enable is set) or we want to query what | |
1279 | * we can do with the cursor (if enable is not set) | |
1280 | */ | |
1281 | if (!cursor->set) | |
1282 | return 0; | |
1283 | ||
8f5d050a KH |
1284 | if (cursor->set & FB_CUR_SETHOT) { |
1285 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT, | |
1286 | cursor->hot.x & 0x3f); | |
1287 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT, | |
1288 | cursor->hot.y & 0x3f); | |
1289 | } | |
1290 | ||
1291 | if (cursor->set & FB_CUR_SETCMAP) { | |
1292 | u32 fg_idx = cursor->image.fg_color; | |
1293 | u32 bg_idx = cursor->image.bg_color; | |
1294 | struct fb_cmap cmap = info->cmap; | |
1295 | ||
1296 | /* the X11 driver says one should use these color registers */ | |
1297 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8); | |
1298 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0, | |
1299 | cmap.red[bg_idx] >> 8 ); | |
1300 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1, | |
1301 | cmap.green[bg_idx] >> 8 ); | |
1302 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2, | |
1303 | cmap.blue[bg_idx] >> 8 ); | |
1304 | ||
1305 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3, | |
1306 | cmap.red[fg_idx] >> 8 ); | |
1307 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4, | |
1308 | cmap.green[fg_idx] >> 8 ); | |
1309 | pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5, | |
1310 | cmap.blue[fg_idx] >> 8 ); | |
1311 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
1312 | } | |
1313 | ||
1314 | if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { | |
1315 | u8 *bitmap = (u8 *)cursor->image.data; | |
1316 | u8 *mask = (u8 *)cursor->mask; | |
1317 | int i; | |
1318 | int pos = PM2VI_RD_CURSOR_PATTERN; | |
1319 | ||
1320 | for (i = 0; i < cursor->image.height; i++) { | |
1321 | int j = (cursor->image.width + 7) >> 3; | |
1322 | int k = 8 - j; | |
1323 | ||
1324 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8); | |
1325 | ||
1326 | for (; j > 0; j--) { | |
1327 | u8 data = *bitmap ^ *mask; | |
1328 | ||
1329 | if (cursor->rop == ROP_COPY) | |
1330 | data = *mask & *bitmap; | |
1331 | /* Upper 4 bits of bitmap data */ | |
1332 | pm2v_RDAC_WR(par, pos++, | |
1333 | cursor_bits_lookup[data >> 4] | | |
1334 | (cursor_bits_lookup[*mask >> 4] << 1)); | |
1335 | /* Lower 4 bits of bitmap */ | |
1336 | pm2v_RDAC_WR(par, pos++, | |
1337 | cursor_bits_lookup[data & 0xf] | | |
1338 | (cursor_bits_lookup[*mask & 0xf] << 1)); | |
1339 | bitmap++; | |
1340 | mask++; | |
1341 | } | |
1342 | for (; k > 0; k--) { | |
1343 | pm2v_RDAC_WR(par, pos++, 0); | |
1344 | pm2v_RDAC_WR(par, pos++, 0); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) { | |
1349 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8); | |
1350 | pm2v_RDAC_WR(par, pos++, 0); | |
1351 | } | |
1352 | ||
1353 | pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0); | |
1354 | } | |
1355 | return 0; | |
1356 | } | |
1357 | ||
1358 | static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
1359 | { | |
1360 | struct pm2fb_par *par = info->par; | |
2a36f9c4 KH |
1361 | u8 mode; |
1362 | ||
1363 | if (!hwcursor) | |
1364 | return -EINVAL; /* just to force soft_cursor() call */ | |
1365 | ||
1366 | /* Too large of a cursor or wrong bpp :-( */ | |
1367 | if (cursor->image.width > 64 || | |
1368 | cursor->image.height > 64 || | |
1369 | cursor->image.depth > 1) | |
1370 | return -EINVAL; | |
8f5d050a KH |
1371 | |
1372 | if (par->type == PM2_TYPE_PERMEDIA2V) | |
1373 | return pm2vfb_cursor(info, cursor); | |
1374 | ||
1ddc28d7 | 1375 | mode = 0x40; |
2a36f9c4 KH |
1376 | if (cursor->enable) |
1377 | mode = 0x43; | |
1378 | ||
1379 | pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode); | |
1380 | ||
1381 | /* | |
1382 | * If the cursor is not be changed this means either we want the | |
1383 | * current cursor state (if enable is set) or we want to query what | |
1384 | * we can do with the cursor (if enable is not set) | |
1385 | */ | |
1386 | if (!cursor->set) | |
1387 | return 0; | |
1388 | ||
1389 | if (cursor->set & FB_CUR_SETPOS) { | |
1ddc28d7 KH |
1390 | int x = cursor->image.dx - info->var.xoffset + 63; |
1391 | int y = cursor->image.dy - info->var.yoffset + 63; | |
2a36f9c4 | 1392 | |
2a36f9c4 KH |
1393 | WAIT_FIFO(par, 4); |
1394 | pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff); | |
1395 | pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7); | |
1396 | pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff); | |
1397 | pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7); | |
1398 | } | |
1399 | ||
1400 | if (cursor->set & FB_CUR_SETCMAP) { | |
1401 | u32 fg_idx = cursor->image.fg_color; | |
1402 | u32 bg_idx = cursor->image.bg_color; | |
1403 | ||
1404 | WAIT_FIFO(par, 7); | |
1405 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1); | |
1406 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1407 | info->cmap.red[bg_idx] >> 8); | |
1408 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1409 | info->cmap.green[bg_idx] >> 8); | |
1410 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1411 | info->cmap.blue[bg_idx] >> 8); | |
1412 | ||
1413 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1414 | info->cmap.red[fg_idx] >> 8); | |
1415 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1416 | info->cmap.green[fg_idx] >> 8); | |
1417 | pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA, | |
1418 | info->cmap.blue[fg_idx] >> 8); | |
1419 | } | |
1420 | ||
1421 | if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { | |
1422 | u8 *bitmap = (u8 *)cursor->image.data; | |
1423 | u8 *mask = (u8 *)cursor->mask; | |
1424 | int i; | |
1425 | ||
1426 | WAIT_FIFO(par, 1); | |
1427 | pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0); | |
1428 | ||
1429 | for (i = 0; i < cursor->image.height; i++) { | |
1430 | int j = (cursor->image.width + 7) >> 3; | |
1431 | int k = 8 - j; | |
1432 | ||
1433 | WAIT_FIFO(par, 8); | |
1434 | for (; j > 0; j--) { | |
1435 | u8 data = *bitmap ^ *mask; | |
1436 | ||
1437 | if (cursor->rop == ROP_COPY) | |
1438 | data = *mask & *bitmap; | |
1439 | /* bitmap data */ | |
1440 | pm2_WR(par, PM2R_RD_CURSOR_DATA, data); | |
1441 | bitmap++; | |
1442 | mask++; | |
1443 | } | |
1444 | for (; k > 0; k--) | |
1445 | pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); | |
1446 | } | |
1447 | for (; i < 64; i++) { | |
1448 | int j = 8; | |
1449 | WAIT_FIFO(par, 8); | |
1450 | while (j-- > 0) | |
1451 | pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); | |
1452 | } | |
1453 | ||
1454 | mask = (u8 *)cursor->mask; | |
1455 | for (i = 0; i < cursor->image.height; i++) { | |
1456 | int j = (cursor->image.width + 7) >> 3; | |
1457 | int k = 8 - j; | |
1458 | ||
1459 | WAIT_FIFO(par, 8); | |
1460 | for (; j > 0; j--) { | |
1461 | /* mask */ | |
1462 | pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask); | |
1463 | mask++; | |
1464 | } | |
1465 | for (; k > 0; k--) | |
1466 | pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); | |
1467 | } | |
1468 | for (; i < 64; i++) { | |
1469 | int j = 8; | |
1470 | WAIT_FIFO(par, 8); | |
1471 | while (j-- > 0) | |
1472 | pm2_WR(par, PM2R_RD_CURSOR_DATA, 0); | |
1473 | } | |
1474 | } | |
1475 | return 0; | |
8f5d050a KH |
1476 | } |
1477 | ||
1da177e4 LT |
1478 | /* ------------ Hardware Independent Functions ------------ */ |
1479 | ||
1480 | /* | |
1481 | * Frame buffer operations | |
1482 | */ | |
1483 | ||
1484 | static struct fb_ops pm2fb_ops = { | |
1485 | .owner = THIS_MODULE, | |
1486 | .fb_check_var = pm2fb_check_var, | |
1487 | .fb_set_par = pm2fb_set_par, | |
1488 | .fb_setcolreg = pm2fb_setcolreg, | |
1489 | .fb_blank = pm2fb_blank, | |
1490 | .fb_pan_display = pm2fb_pan_display, | |
87a7cc68 KH |
1491 | .fb_fillrect = pm2fb_fillrect, |
1492 | .fb_copyarea = pm2fb_copyarea, | |
91b3a6f4 | 1493 | .fb_imageblit = pm2fb_imageblit, |
03b9ae4b | 1494 | .fb_sync = pm2fb_sync, |
8f5d050a | 1495 | .fb_cursor = pm2fb_cursor, |
1da177e4 LT |
1496 | }; |
1497 | ||
1498 | /* | |
1499 | * PCI stuff | |
1500 | */ | |
1501 | ||
1502 | ||
1503 | /** | |
1504 | * Device initialisation | |
1505 | * | |
1506 | * Initialise and allocate resource for PCI device. | |
1507 | * | |
1508 | * @param pdev PCI device. | |
1509 | * @param id PCI device ID. | |
1510 | */ | |
48c68c4f | 1511 | static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1da177e4 LT |
1512 | { |
1513 | struct pm2fb_par *default_par; | |
1514 | struct fb_info *info; | |
3843faa2 KH |
1515 | int err; |
1516 | int retval = -ENXIO; | |
1da177e4 LT |
1517 | |
1518 | err = pci_enable_device(pdev); | |
45f169ec | 1519 | if (err) { |
1da177e4 LT |
1520 | printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err); |
1521 | return err; | |
1522 | } | |
1523 | ||
6772a2ee | 1524 | info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev); |
45f169ec | 1525 | if (!info) |
1da177e4 | 1526 | return -ENOMEM; |
6772a2ee | 1527 | default_par = info->par; |
1da177e4 LT |
1528 | |
1529 | switch (pdev->device) { | |
1530 | case PCI_DEVICE_ID_TI_TVP4020: | |
1531 | strcpy(pm2fb_fix.id, "TVP4020"); | |
1532 | default_par->type = PM2_TYPE_PERMEDIA2; | |
1533 | break; | |
1534 | case PCI_DEVICE_ID_3DLABS_PERMEDIA2: | |
1535 | strcpy(pm2fb_fix.id, "Permedia2"); | |
1536 | default_par->type = PM2_TYPE_PERMEDIA2; | |
1537 | break; | |
1538 | case PCI_DEVICE_ID_3DLABS_PERMEDIA2V: | |
1539 | strcpy(pm2fb_fix.id, "Permedia2v"); | |
1540 | default_par->type = PM2_TYPE_PERMEDIA2V; | |
1541 | break; | |
1542 | } | |
1543 | ||
1544 | pm2fb_fix.mmio_start = pci_resource_start(pdev, 0); | |
1545 | pm2fb_fix.mmio_len = PM2_REGS_SIZE; | |
1546 | ||
1547 | #if defined(__BIG_ENDIAN) | |
1548 | /* | |
1549 | * PM2 has a 64k register file, mapped twice in 128k. Lower | |
1550 | * map is little-endian, upper map is big-endian. | |
1551 | */ | |
1552 | pm2fb_fix.mmio_start += PM2_REGS_SIZE; | |
1553 | DPRINTK("Adjusting register base for big-endian.\n"); | |
1554 | #endif | |
1555 | DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start); | |
2f7bb99f | 1556 | |
1da177e4 | 1557 | /* Registers - request region and map it. */ |
45f169ec KH |
1558 | if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len, |
1559 | "pm2fb regbase")) { | |
1da177e4 LT |
1560 | printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n"); |
1561 | goto err_exit_neither; | |
1562 | } | |
1563 | default_par->v_regs = | |
1564 | ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
45f169ec | 1565 | if (!default_par->v_regs) { |
1da177e4 LT |
1566 | printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n", |
1567 | pm2fb_fix.id); | |
1568 | release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
1569 | goto err_exit_neither; | |
1570 | } | |
1571 | ||
1572 | /* Stash away memory register info for use when we reset the board */ | |
1573 | default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL); | |
1574 | default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS); | |
1575 | default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG); | |
1576 | DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n", | |
1577 | default_par->mem_control, default_par->boot_address, | |
1578 | default_par->mem_config); | |
1579 | ||
45f169ec | 1580 | if (default_par->mem_control == 0 && |
9127fa28 | 1581 | default_par->boot_address == 0x31 && |
f1c15f93 | 1582 | default_par->mem_config == 0x259fffff) { |
9a31f0f7 | 1583 | default_par->memclock = CVPPC_MEMCLOCK; |
45f169ec KH |
1584 | default_par->mem_control = 0; |
1585 | default_par->boot_address = 0x20; | |
1586 | default_par->mem_config = 0xe6002021; | |
f1c15f93 KH |
1587 | if (pdev->subsystem_vendor == 0x1048 && |
1588 | pdev->subsystem_device == 0x0a31) { | |
3843faa2 KH |
1589 | DPRINTK("subsystem_vendor: %04x, " |
1590 | "subsystem_device: %04x\n", | |
f1c15f93 | 1591 | pdev->subsystem_vendor, pdev->subsystem_device); |
3843faa2 KH |
1592 | DPRINTK("We have not been initialized by VGA BIOS and " |
1593 | "are running on an Elsa Winner 2000 Office\n"); | |
f1c15f93 | 1594 | DPRINTK("Initializing card timings manually...\n"); |
138a451c | 1595 | default_par->memclock = 100000; |
f1c15f93 KH |
1596 | } |
1597 | if (pdev->subsystem_vendor == 0x3d3d && | |
1598 | pdev->subsystem_device == 0x0100) { | |
3843faa2 KH |
1599 | DPRINTK("subsystem_vendor: %04x, " |
1600 | "subsystem_device: %04x\n", | |
f1c15f93 | 1601 | pdev->subsystem_vendor, pdev->subsystem_device); |
3843faa2 KH |
1602 | DPRINTK("We have not been initialized by VGA BIOS and " |
1603 | "are running on an 3dlabs reference board\n"); | |
f1c15f93 | 1604 | DPRINTK("Initializing card timings manually...\n"); |
45f169ec | 1605 | default_par->memclock = 74894; |
f1c15f93 | 1606 | } |
9127fa28 PDS |
1607 | } |
1608 | ||
1da177e4 | 1609 | /* Now work out how big lfb is going to be. */ |
3843faa2 | 1610 | switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) { |
1da177e4 | 1611 | case PM2F_MEM_BANKS_1: |
45f169ec | 1612 | pm2fb_fix.smem_len = 0x200000; |
1da177e4 LT |
1613 | break; |
1614 | case PM2F_MEM_BANKS_2: | |
45f169ec | 1615 | pm2fb_fix.smem_len = 0x400000; |
1da177e4 LT |
1616 | break; |
1617 | case PM2F_MEM_BANKS_3: | |
45f169ec | 1618 | pm2fb_fix.smem_len = 0x600000; |
1da177e4 LT |
1619 | break; |
1620 | case PM2F_MEM_BANKS_4: | |
45f169ec | 1621 | pm2fb_fix.smem_len = 0x800000; |
1da177e4 LT |
1622 | break; |
1623 | } | |
1da177e4 | 1624 | pm2fb_fix.smem_start = pci_resource_start(pdev, 1); |
1da177e4 LT |
1625 | |
1626 | /* Linear frame buffer - request region and map it. */ | |
45f169ec KH |
1627 | if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len, |
1628 | "pm2fb smem")) { | |
1da177e4 LT |
1629 | printk(KERN_WARNING "pm2fb: Can't reserve smem.\n"); |
1630 | goto err_exit_mmio; | |
1631 | } | |
4560daaf | 1632 | info->screen_base = |
f8f05cdc | 1633 | ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len); |
45f169ec | 1634 | if (!info->screen_base) { |
1da177e4 LT |
1635 | printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n"); |
1636 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | |
1637 | goto err_exit_mmio; | |
1638 | } | |
1639 | ||
d5383fcc | 1640 | if (!nomtrr) |
f8f05cdc LR |
1641 | default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start, |
1642 | pm2fb_fix.smem_len); | |
d5383fcc | 1643 | |
1da177e4 | 1644 | info->fbops = &pm2fb_ops; |
2f7bb99f | 1645 | info->fix = pm2fb_fix; |
6772a2ee | 1646 | info->pseudo_palette = default_par->palette; |
1da177e4 | 1647 | info->flags = FBINFO_DEFAULT | |
2f7bb99f KH |
1648 | FBINFO_HWACCEL_YPAN | |
1649 | FBINFO_HWACCEL_COPYAREA | | |
91b3a6f4 | 1650 | FBINFO_HWACCEL_IMAGEBLIT | |
2f7bb99f | 1651 | FBINFO_HWACCEL_FILLRECT; |
1da177e4 | 1652 | |
91b3a6f4 KH |
1653 | info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL); |
1654 | if (!info->pixmap.addr) { | |
3843faa2 | 1655 | retval = -ENOMEM; |
91b3a6f4 KH |
1656 | goto err_exit_pixmap; |
1657 | } | |
1658 | info->pixmap.size = PM2_PIXMAP_SIZE; | |
1659 | info->pixmap.buf_align = 4; | |
1660 | info->pixmap.scan_align = 4; | |
1661 | info->pixmap.access_align = 32; | |
1662 | info->pixmap.flags = FB_PIXMAP_SYSTEM; | |
1663 | ||
d5383fcc | 1664 | if (noaccel) { |
91b3a6f4 KH |
1665 | printk(KERN_DEBUG "disabling acceleration\n"); |
1666 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
1667 | info->pixmap.scan_align = 1; | |
d5383fcc KH |
1668 | } |
1669 | ||
5eb81e80 KH |
1670 | if (!mode_option) |
1671 | mode_option = "640x480@60"; | |
2f7bb99f | 1672 | |
5eb81e80 | 1673 | err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); |
1da177e4 LT |
1674 | if (!err || err == 4) |
1675 | info->var = pm2fb_var; | |
1676 | ||
2ae09f0d KH |
1677 | retval = fb_alloc_cmap(&info->cmap, 256, 0); |
1678 | if (retval < 0) | |
435d56fc | 1679 | goto err_exit_both; |
1da177e4 | 1680 | |
2ae09f0d KH |
1681 | retval = register_framebuffer(info); |
1682 | if (retval < 0) | |
435d56fc | 1683 | goto err_exit_all; |
1da177e4 | 1684 | |
31b6780c JP |
1685 | fb_info(info, "%s frame buffer device, memory = %dK\n", |
1686 | info->fix.id, pm2fb_fix.smem_len / 1024); | |
1da177e4 LT |
1687 | |
1688 | /* | |
1689 | * Our driver data | |
1690 | */ | |
1691 | pci_set_drvdata(pdev, info); | |
1692 | ||
1693 | return 0; | |
1694 | ||
1695 | err_exit_all: | |
2f7bb99f KH |
1696 | fb_dealloc_cmap(&info->cmap); |
1697 | err_exit_both: | |
91b3a6f4 KH |
1698 | kfree(info->pixmap.addr); |
1699 | err_exit_pixmap: | |
1da177e4 LT |
1700 | iounmap(info->screen_base); |
1701 | release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len); | |
1702 | err_exit_mmio: | |
1703 | iounmap(default_par->v_regs); | |
1704 | release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len); | |
1705 | err_exit_neither: | |
1706 | framebuffer_release(info); | |
3843faa2 | 1707 | return retval; |
1da177e4 LT |
1708 | } |
1709 | ||
1710 | /** | |
1711 | * Device removal. | |
1712 | * | |
1713 | * Release all device resources. | |
1714 | * | |
1715 | * @param pdev PCI device to clean up. | |
1716 | */ | |
48c68c4f | 1717 | static void pm2fb_remove(struct pci_dev *pdev) |
1da177e4 | 1718 | { |
3843faa2 KH |
1719 | struct fb_info *info = pci_get_drvdata(pdev); |
1720 | struct fb_fix_screeninfo *fix = &info->fix; | |
1da177e4 LT |
1721 | struct pm2fb_par *par = info->par; |
1722 | ||
1723 | unregister_framebuffer(info); | |
f8f05cdc | 1724 | arch_phys_wc_del(par->wc_cookie); |
1da177e4 LT |
1725 | iounmap(info->screen_base); |
1726 | release_mem_region(fix->smem_start, fix->smem_len); | |
1727 | iounmap(par->v_regs); | |
1728 | release_mem_region(fix->mmio_start, fix->mmio_len); | |
1729 | ||
27aa069a | 1730 | fb_dealloc_cmap(&info->cmap); |
3843faa2 | 1731 | kfree(info->pixmap.addr); |
491bcc9b | 1732 | framebuffer_release(info); |
1da177e4 LT |
1733 | } |
1734 | ||
8bceaa32 | 1735 | static const struct pci_device_id pm2fb_id_table[] = { |
1da177e4 | 1736 | { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020, |
138a451c | 1737 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
1da177e4 | 1738 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2, |
138a451c | 1739 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
f1c15f93 | 1740 | { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V, |
138a451c | 1741 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
1da177e4 LT |
1742 | { 0, } |
1743 | }; | |
1744 | ||
1745 | static struct pci_driver pm2fb_driver = { | |
1746 | .name = "pm2fb", | |
2f7bb99f KH |
1747 | .id_table = pm2fb_id_table, |
1748 | .probe = pm2fb_probe, | |
48c68c4f | 1749 | .remove = pm2fb_remove, |
1da177e4 LT |
1750 | }; |
1751 | ||
1752 | MODULE_DEVICE_TABLE(pci, pm2fb_id_table); | |
1753 | ||
1754 | ||
1755 | #ifndef MODULE | |
1756 | /** | |
75e1b6a8 | 1757 | * Parse user specified options. |
1da177e4 LT |
1758 | * |
1759 | * This is, comma-separated options following `video=pm2fb:'. | |
1760 | */ | |
1761 | static int __init pm2fb_setup(char *options) | |
1762 | { | |
3843faa2 | 1763 | char *this_opt; |
1da177e4 LT |
1764 | |
1765 | if (!options || !*options) | |
1766 | return 0; | |
1767 | ||
2f7bb99f | 1768 | while ((this_opt = strsep(&options, ",")) != NULL) { |
1da177e4 LT |
1769 | if (!*this_opt) |
1770 | continue; | |
3843faa2 | 1771 | if (!strcmp(this_opt, "lowhsync")) |
1da177e4 | 1772 | lowhsync = 1; |
3843faa2 | 1773 | else if (!strcmp(this_opt, "lowvsync")) |
1da177e4 | 1774 | lowvsync = 1; |
8f5d050a KH |
1775 | else if (!strncmp(this_opt, "hwcursor=", 9)) |
1776 | hwcursor = simple_strtoul(this_opt + 9, NULL, 0); | |
3843faa2 | 1777 | else if (!strncmp(this_opt, "nomtrr", 6)) |
d5383fcc | 1778 | nomtrr = 1; |
3843faa2 | 1779 | else if (!strncmp(this_opt, "noaccel", 7)) |
d5383fcc | 1780 | noaccel = 1; |
3843faa2 | 1781 | else |
5eb81e80 | 1782 | mode_option = this_opt; |
1da177e4 LT |
1783 | } |
1784 | return 0; | |
1785 | } | |
1786 | #endif | |
1787 | ||
1788 | ||
1789 | static int __init pm2fb_init(void) | |
1790 | { | |
1791 | #ifndef MODULE | |
1792 | char *option = NULL; | |
1793 | ||
1794 | if (fb_get_options("pm2fb", &option)) | |
1795 | return -ENODEV; | |
1796 | pm2fb_setup(option); | |
1797 | #endif | |
1798 | ||
1799 | return pci_register_driver(&pm2fb_driver); | |
1800 | } | |
1801 | ||
1802 | module_init(pm2fb_init); | |
1803 | ||
1804 | #ifdef MODULE | |
1805 | /* | |
1806 | * Cleanup | |
1807 | */ | |
1808 | ||
1809 | static void __exit pm2fb_exit(void) | |
1810 | { | |
1811 | pci_unregister_driver(&pm2fb_driver); | |
1812 | } | |
1813 | #endif | |
1814 | ||
1815 | #ifdef MODULE | |
1816 | module_exit(pm2fb_exit); | |
1817 | ||
5eb81e80 KH |
1818 | module_param(mode_option, charp, 0); |
1819 | MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); | |
9e3f0ca8 KH |
1820 | module_param_named(mode, mode_option, charp, 0); |
1821 | MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)"); | |
1da177e4 LT |
1822 | module_param(lowhsync, bool, 0); |
1823 | MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode"); | |
1824 | module_param(lowvsync, bool, 0); | |
1825 | MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode"); | |
d5383fcc KH |
1826 | module_param(noaccel, bool, 0); |
1827 | MODULE_PARM_DESC(noaccel, "Disable acceleration"); | |
8f5d050a KH |
1828 | module_param(hwcursor, int, 0644); |
1829 | MODULE_PARM_DESC(hwcursor, "Enable hardware cursor " | |
1ddc28d7 | 1830 | "(1=enable, 0=disable, default=1)"); |
d5383fcc KH |
1831 | module_param(nomtrr, bool, 0); |
1832 | MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); | |
1da177e4 LT |
1833 | |
1834 | MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>"); | |
1835 | MODULE_DESCRIPTION("Permedia2 framebuffer device driver"); | |
1836 | MODULE_LICENSE("GPL"); | |
1837 | #endif |