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caab277b | 1 | // SPDX-License-Identifier: GPL-2.0-only |
f76ee892 TV |
2 | /* |
3 | * linux/drivers/video/omap2/dss/dsi.c | |
4 | * | |
5 | * Copyright (C) 2009 Nokia Corporation | |
6 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
f76ee892 TV |
7 | */ |
8 | ||
9 | #define DSS_SUBSYS_NAME "DSI" | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/clk.h> | |
14 | #include <linux/device.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/mutex.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/semaphore.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/regulator/consumer.h> | |
24 | #include <linux/wait.h> | |
25 | #include <linux/workqueue.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/debugfs.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/of.h> | |
ada5caa4 | 31 | #include <linux/of_graph.h> |
f76ee892 TV |
32 | #include <linux/of_platform.h> |
33 | #include <linux/component.h> | |
34 | ||
62d9e44e | 35 | #include <video/omapfb_dss.h> |
f76ee892 TV |
36 | #include <video/mipi_display.h> |
37 | ||
38 | #include "dss.h" | |
39 | #include "dss_features.h" | |
40 | ||
41 | #define DSI_CATCH_MISSING_TE | |
42 | ||
43 | struct dsi_reg { u16 module; u16 idx; }; | |
44 | ||
45 | #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) | |
46 | ||
47 | /* DSI Protocol Engine */ | |
48 | ||
49 | #define DSI_PROTO 0 | |
50 | #define DSI_PROTO_SZ 0x200 | |
51 | ||
52 | #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) | |
53 | #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) | |
54 | #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) | |
55 | #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) | |
56 | #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) | |
57 | #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) | |
58 | #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) | |
59 | #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) | |
60 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) | |
61 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) | |
62 | #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) | |
63 | #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) | |
64 | #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) | |
65 | #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) | |
66 | #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) | |
67 | #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) | |
68 | #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) | |
69 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) | |
70 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) | |
71 | #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) | |
72 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) | |
73 | #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) | |
74 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) | |
75 | #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) | |
76 | #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) | |
77 | #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) | |
78 | #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) | |
79 | #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) | |
80 | #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) | |
81 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) | |
82 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) | |
83 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) | |
84 | #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) | |
85 | #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) | |
86 | ||
87 | /* DSIPHY_SCP */ | |
88 | ||
89 | #define DSI_PHY 1 | |
90 | #define DSI_PHY_OFFSET 0x200 | |
91 | #define DSI_PHY_SZ 0x40 | |
92 | ||
93 | #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) | |
94 | #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) | |
95 | #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) | |
96 | #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) | |
97 | #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) | |
98 | ||
99 | /* DSI_PLL_CTRL_SCP */ | |
100 | ||
101 | #define DSI_PLL 2 | |
102 | #define DSI_PLL_OFFSET 0x300 | |
103 | #define DSI_PLL_SZ 0x20 | |
104 | ||
105 | #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) | |
106 | #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) | |
107 | #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) | |
108 | #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) | |
109 | #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) | |
110 | ||
111 | #define REG_GET(dsidev, idx, start, end) \ | |
112 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | |
113 | ||
114 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ | |
115 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) | |
116 | ||
117 | /* Global interrupts */ | |
118 | #define DSI_IRQ_VC0 (1 << 0) | |
119 | #define DSI_IRQ_VC1 (1 << 1) | |
120 | #define DSI_IRQ_VC2 (1 << 2) | |
121 | #define DSI_IRQ_VC3 (1 << 3) | |
122 | #define DSI_IRQ_WAKEUP (1 << 4) | |
123 | #define DSI_IRQ_RESYNC (1 << 5) | |
124 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
125 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
126 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
127 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
128 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
129 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
130 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
131 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
132 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
133 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
134 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
135 | #define DSI_IRQ_ERROR_MASK \ | |
136 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
137 | DSI_IRQ_TA_TIMEOUT) | |
138 | #define DSI_IRQ_CHANNEL_MASK 0xf | |
139 | ||
140 | /* Virtual channel interrupts */ | |
141 | #define DSI_VC_IRQ_CS (1 << 0) | |
142 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
143 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
144 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
145 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
146 | #define DSI_VC_IRQ_BTA (1 << 5) | |
147 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
148 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
149 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
150 | #define DSI_VC_IRQ_ERROR_MASK \ | |
151 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
152 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
153 | DSI_VC_IRQ_FIFO_TX_UDF) | |
154 | ||
155 | /* ComplexIO interrupts */ | |
156 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
157 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
158 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
159 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) | |
160 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
161 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) | |
162 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
163 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
164 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) | |
165 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
166 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) | |
167 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
168 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
169 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) | |
170 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
171 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) | |
172 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
173 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
174 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) | |
175 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) | |
177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
180 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
181 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
182 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) | |
183 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
184 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
185 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
186 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) | |
187 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
188 | #define DSI_CIO_IRQ_ERROR_MASK \ | |
189 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
190 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ | |
191 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
192 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
193 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
194 | DSI_CIO_IRQ_ERRESC5 | \ | |
195 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
196 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
197 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
198 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ | |
199 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
200 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ | |
201 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
202 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
203 | ||
204 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); | |
205 | ||
206 | static int dsi_display_init_dispc(struct platform_device *dsidev, | |
207 | struct omap_overlay_manager *mgr); | |
208 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, | |
209 | struct omap_overlay_manager *mgr); | |
210 | ||
211 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); | |
212 | ||
213 | /* DSI PLL HSDIV indices */ | |
214 | #define HSDIV_DISPC 0 | |
215 | #define HSDIV_DSI 1 | |
216 | ||
217 | #define DSI_MAX_NR_ISRS 2 | |
218 | #define DSI_MAX_NR_LANES 5 | |
219 | ||
220 | enum dsi_lane_function { | |
221 | DSI_LANE_UNUSED = 0, | |
222 | DSI_LANE_CLK, | |
223 | DSI_LANE_DATA1, | |
224 | DSI_LANE_DATA2, | |
225 | DSI_LANE_DATA3, | |
226 | DSI_LANE_DATA4, | |
227 | }; | |
228 | ||
229 | struct dsi_lane_config { | |
230 | enum dsi_lane_function function; | |
231 | u8 polarity; | |
232 | }; | |
233 | ||
234 | struct dsi_isr_data { | |
235 | omap_dsi_isr_t isr; | |
236 | void *arg; | |
237 | u32 mask; | |
238 | }; | |
239 | ||
240 | enum fifo_size { | |
241 | DSI_FIFO_SIZE_0 = 0, | |
242 | DSI_FIFO_SIZE_32 = 1, | |
243 | DSI_FIFO_SIZE_64 = 2, | |
244 | DSI_FIFO_SIZE_96 = 3, | |
245 | DSI_FIFO_SIZE_128 = 4, | |
246 | }; | |
247 | ||
248 | enum dsi_vc_source { | |
249 | DSI_VC_SOURCE_L4 = 0, | |
250 | DSI_VC_SOURCE_VP, | |
251 | }; | |
252 | ||
253 | struct dsi_irq_stats { | |
254 | unsigned long last_reset; | |
255 | unsigned irq_count; | |
256 | unsigned dsi_irqs[32]; | |
257 | unsigned vc_irqs[4][32]; | |
258 | unsigned cio_irqs[32]; | |
259 | }; | |
260 | ||
261 | struct dsi_isr_tables { | |
262 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
263 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
264 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
265 | }; | |
266 | ||
267 | struct dsi_clk_calc_ctx { | |
268 | struct platform_device *dsidev; | |
269 | struct dss_pll *pll; | |
270 | ||
271 | /* inputs */ | |
272 | ||
273 | const struct omap_dss_dsi_config *config; | |
274 | ||
275 | unsigned long req_pck_min, req_pck_nom, req_pck_max; | |
276 | ||
277 | /* outputs */ | |
278 | ||
279 | struct dss_pll_clock_info dsi_cinfo; | |
280 | struct dispc_clock_info dispc_cinfo; | |
281 | ||
282 | struct omap_video_timings dispc_vm; | |
283 | struct omap_dss_dsi_videomode_timings dsi_vm; | |
284 | }; | |
285 | ||
286 | struct dsi_lp_clock_info { | |
287 | unsigned long lp_clk; | |
288 | u16 lp_clk_div; | |
289 | }; | |
290 | ||
291 | struct dsi_data { | |
292 | struct platform_device *pdev; | |
293 | void __iomem *proto_base; | |
294 | void __iomem *phy_base; | |
295 | void __iomem *pll_base; | |
296 | ||
297 | int module_id; | |
298 | ||
299 | int irq; | |
300 | ||
301 | bool is_enabled; | |
302 | ||
303 | struct clk *dss_clk; | |
304 | ||
305 | struct dispc_clock_info user_dispc_cinfo; | |
306 | struct dss_pll_clock_info user_dsi_cinfo; | |
307 | ||
308 | struct dsi_lp_clock_info user_lp_cinfo; | |
309 | struct dsi_lp_clock_info current_lp_cinfo; | |
310 | ||
311 | struct dss_pll pll; | |
312 | ||
313 | bool vdds_dsi_enabled; | |
314 | struct regulator *vdds_dsi_reg; | |
315 | ||
316 | struct { | |
317 | enum dsi_vc_source source; | |
318 | struct omap_dss_device *dssdev; | |
319 | enum fifo_size tx_fifo_size; | |
320 | enum fifo_size rx_fifo_size; | |
321 | int vc_id; | |
322 | } vc[4]; | |
323 | ||
324 | struct mutex lock; | |
325 | struct semaphore bus_lock; | |
326 | ||
327 | spinlock_t irq_lock; | |
328 | struct dsi_isr_tables isr_tables; | |
329 | /* space for a copy used by the interrupt handler */ | |
330 | struct dsi_isr_tables isr_tables_copy; | |
331 | ||
332 | int update_channel; | |
333 | #ifdef DSI_PERF_MEASURE | |
334 | unsigned update_bytes; | |
335 | #endif | |
336 | ||
337 | bool te_enabled; | |
338 | bool ulps_enabled; | |
339 | ||
340 | void (*framedone_callback)(int, void *); | |
341 | void *framedone_data; | |
342 | ||
343 | struct delayed_work framedone_timeout_work; | |
344 | ||
345 | #ifdef DSI_CATCH_MISSING_TE | |
346 | struct timer_list te_timer; | |
347 | #endif | |
348 | ||
349 | unsigned long cache_req_pck; | |
350 | unsigned long cache_clk_freq; | |
351 | struct dss_pll_clock_info cache_cinfo; | |
352 | ||
353 | u32 errors; | |
354 | spinlock_t errors_lock; | |
355 | #ifdef DSI_PERF_MEASURE | |
356 | ktime_t perf_setup_time; | |
357 | ktime_t perf_start_time; | |
358 | #endif | |
359 | int debug_read; | |
360 | int debug_write; | |
361 | ||
35b522cf | 362 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
f76ee892 TV |
363 | spinlock_t irq_stats_lock; |
364 | struct dsi_irq_stats irq_stats; | |
365 | #endif | |
366 | ||
367 | unsigned num_lanes_supported; | |
368 | unsigned line_buffer_size; | |
369 | ||
370 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; | |
371 | unsigned num_lanes_used; | |
372 | ||
373 | unsigned scp_clk_refcount; | |
374 | ||
375 | struct dss_lcd_mgr_config mgr_config; | |
376 | struct omap_video_timings timings; | |
377 | enum omap_dss_dsi_pixel_format pix_fmt; | |
378 | enum omap_dss_dsi_mode mode; | |
379 | struct omap_dss_dsi_videomode_timings vm_timings; | |
380 | ||
381 | struct omap_dss_device output; | |
382 | }; | |
383 | ||
384 | struct dsi_packet_sent_handler_data { | |
385 | struct platform_device *dsidev; | |
386 | struct completion *completion; | |
387 | }; | |
388 | ||
389 | struct dsi_module_id_data { | |
390 | u32 address; | |
391 | int id; | |
392 | }; | |
393 | ||
394 | static const struct of_device_id dsi_of_match[]; | |
395 | ||
396 | #ifdef DSI_PERF_MEASURE | |
397 | static bool dsi_perf; | |
398 | module_param(dsi_perf, bool, 0644); | |
399 | #endif | |
400 | ||
401 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) | |
402 | { | |
0b5e0f45 | 403 | return platform_get_drvdata(dsidev); |
f76ee892 TV |
404 | } |
405 | ||
406 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) | |
407 | { | |
408 | return to_platform_device(dssdev->dev); | |
409 | } | |
410 | ||
411 | static struct platform_device *dsi_get_dsidev_from_id(int module) | |
412 | { | |
413 | struct omap_dss_device *out; | |
414 | enum omap_dss_output_id id; | |
415 | ||
416 | switch (module) { | |
417 | case 0: | |
418 | id = OMAP_DSS_OUTPUT_DSI1; | |
419 | break; | |
420 | case 1: | |
421 | id = OMAP_DSS_OUTPUT_DSI2; | |
422 | break; | |
423 | default: | |
424 | return NULL; | |
425 | } | |
426 | ||
427 | out = omap_dss_get_output(id); | |
428 | ||
429 | return out ? to_platform_device(out->dev) : NULL; | |
430 | } | |
431 | ||
432 | static inline void dsi_write_reg(struct platform_device *dsidev, | |
433 | const struct dsi_reg idx, u32 val) | |
434 | { | |
435 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
436 | void __iomem *base; | |
437 | ||
438 | switch(idx.module) { | |
439 | case DSI_PROTO: base = dsi->proto_base; break; | |
440 | case DSI_PHY: base = dsi->phy_base; break; | |
441 | case DSI_PLL: base = dsi->pll_base; break; | |
442 | default: return; | |
443 | } | |
444 | ||
445 | __raw_writel(val, base + idx.idx); | |
446 | } | |
447 | ||
448 | static inline u32 dsi_read_reg(struct platform_device *dsidev, | |
449 | const struct dsi_reg idx) | |
450 | { | |
451 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
452 | void __iomem *base; | |
453 | ||
454 | switch(idx.module) { | |
455 | case DSI_PROTO: base = dsi->proto_base; break; | |
456 | case DSI_PHY: base = dsi->phy_base; break; | |
457 | case DSI_PLL: base = dsi->pll_base; break; | |
458 | default: return 0; | |
459 | } | |
460 | ||
461 | return __raw_readl(base + idx.idx); | |
462 | } | |
463 | ||
464 | static void dsi_bus_lock(struct omap_dss_device *dssdev) | |
465 | { | |
466 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
467 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
468 | ||
469 | down(&dsi->bus_lock); | |
470 | } | |
471 | ||
472 | static void dsi_bus_unlock(struct omap_dss_device *dssdev) | |
473 | { | |
474 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
475 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
476 | ||
477 | up(&dsi->bus_lock); | |
478 | } | |
479 | ||
480 | static bool dsi_bus_is_locked(struct platform_device *dsidev) | |
481 | { | |
482 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
483 | ||
484 | return dsi->bus_lock.count == 0; | |
485 | } | |
486 | ||
487 | static void dsi_completion_handler(void *data, u32 mask) | |
488 | { | |
489 | complete((struct completion *)data); | |
490 | } | |
491 | ||
492 | static inline int wait_for_bit_change(struct platform_device *dsidev, | |
493 | const struct dsi_reg idx, int bitnum, int value) | |
494 | { | |
495 | unsigned long timeout; | |
496 | ktime_t wait; | |
497 | int t; | |
498 | ||
499 | /* first busyloop to see if the bit changes right away */ | |
500 | t = 100; | |
501 | while (t-- > 0) { | |
502 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
503 | return value; | |
504 | } | |
505 | ||
506 | /* then loop for 500ms, sleeping for 1ms in between */ | |
507 | timeout = jiffies + msecs_to_jiffies(500); | |
508 | while (time_before(jiffies, timeout)) { | |
509 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
510 | return value; | |
511 | ||
512 | wait = ns_to_ktime(1000 * 1000); | |
513 | set_current_state(TASK_UNINTERRUPTIBLE); | |
514 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
515 | } | |
516 | ||
517 | return !value; | |
518 | } | |
519 | ||
520 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) | |
521 | { | |
522 | switch (fmt) { | |
523 | case OMAP_DSS_DSI_FMT_RGB888: | |
524 | case OMAP_DSS_DSI_FMT_RGB666: | |
525 | return 24; | |
526 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
527 | return 18; | |
528 | case OMAP_DSS_DSI_FMT_RGB565: | |
529 | return 16; | |
530 | default: | |
531 | BUG(); | |
532 | return 0; | |
533 | } | |
534 | } | |
535 | ||
536 | #ifdef DSI_PERF_MEASURE | |
537 | static void dsi_perf_mark_setup(struct platform_device *dsidev) | |
538 | { | |
539 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
540 | dsi->perf_setup_time = ktime_get(); | |
541 | } | |
542 | ||
543 | static void dsi_perf_mark_start(struct platform_device *dsidev) | |
544 | { | |
545 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
546 | dsi->perf_start_time = ktime_get(); | |
547 | } | |
548 | ||
549 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) | |
550 | { | |
551 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
552 | ktime_t t, setup_time, trans_time; | |
553 | u32 total_bytes; | |
554 | u32 setup_us, trans_us, total_us; | |
555 | ||
556 | if (!dsi_perf) | |
557 | return; | |
558 | ||
559 | t = ktime_get(); | |
560 | ||
561 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); | |
562 | setup_us = (u32)ktime_to_us(setup_time); | |
563 | if (setup_us == 0) | |
564 | setup_us = 1; | |
565 | ||
566 | trans_time = ktime_sub(t, dsi->perf_start_time); | |
567 | trans_us = (u32)ktime_to_us(trans_time); | |
568 | if (trans_us == 0) | |
569 | trans_us = 1; | |
570 | ||
571 | total_us = setup_us + trans_us; | |
572 | ||
573 | total_bytes = dsi->update_bytes; | |
574 | ||
575 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " | |
576 | "%u bytes, %u kbytes/sec\n", | |
577 | name, | |
578 | setup_us, | |
579 | trans_us, | |
580 | total_us, | |
581 | 1000*1000 / total_us, | |
582 | total_bytes, | |
583 | total_bytes * 1000 / total_us); | |
584 | } | |
585 | #else | |
586 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) | |
587 | { | |
588 | } | |
589 | ||
590 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) | |
591 | { | |
592 | } | |
593 | ||
594 | static inline void dsi_perf_show(struct platform_device *dsidev, | |
595 | const char *name) | |
596 | { | |
597 | } | |
598 | #endif | |
599 | ||
600 | static int verbose_irq; | |
601 | ||
602 | static void print_irq_status(u32 status) | |
603 | { | |
604 | if (status == 0) | |
605 | return; | |
606 | ||
607 | if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) | |
608 | return; | |
609 | ||
610 | #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" | |
611 | ||
612 | pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
613 | status, | |
614 | verbose_irq ? PIS(VC0) : "", | |
615 | verbose_irq ? PIS(VC1) : "", | |
616 | verbose_irq ? PIS(VC2) : "", | |
617 | verbose_irq ? PIS(VC3) : "", | |
618 | PIS(WAKEUP), | |
619 | PIS(RESYNC), | |
620 | PIS(PLL_LOCK), | |
621 | PIS(PLL_UNLOCK), | |
622 | PIS(PLL_RECALL), | |
623 | PIS(COMPLEXIO_ERR), | |
624 | PIS(HS_TX_TIMEOUT), | |
625 | PIS(LP_RX_TIMEOUT), | |
626 | PIS(TE_TRIGGER), | |
627 | PIS(ACK_TRIGGER), | |
628 | PIS(SYNC_LOST), | |
629 | PIS(LDO_POWER_GOOD), | |
630 | PIS(TA_TIMEOUT)); | |
631 | #undef PIS | |
632 | } | |
633 | ||
634 | static void print_irq_status_vc(int channel, u32 status) | |
635 | { | |
636 | if (status == 0) | |
637 | return; | |
638 | ||
639 | if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) | |
640 | return; | |
641 | ||
642 | #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" | |
643 | ||
644 | pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", | |
645 | channel, | |
646 | status, | |
647 | PIS(CS), | |
648 | PIS(ECC_CORR), | |
649 | PIS(ECC_NO_CORR), | |
650 | verbose_irq ? PIS(PACKET_SENT) : "", | |
651 | PIS(BTA), | |
652 | PIS(FIFO_TX_OVF), | |
653 | PIS(FIFO_RX_OVF), | |
654 | PIS(FIFO_TX_UDF), | |
655 | PIS(PP_BUSY_CHANGE)); | |
656 | #undef PIS | |
657 | } | |
658 | ||
659 | static void print_irq_status_cio(u32 status) | |
660 | { | |
661 | if (status == 0) | |
662 | return; | |
663 | ||
664 | #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" | |
665 | ||
666 | pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", | |
667 | status, | |
668 | PIS(ERRSYNCESC1), | |
669 | PIS(ERRSYNCESC2), | |
670 | PIS(ERRSYNCESC3), | |
671 | PIS(ERRESC1), | |
672 | PIS(ERRESC2), | |
673 | PIS(ERRESC3), | |
674 | PIS(ERRCONTROL1), | |
675 | PIS(ERRCONTROL2), | |
676 | PIS(ERRCONTROL3), | |
677 | PIS(STATEULPS1), | |
678 | PIS(STATEULPS2), | |
679 | PIS(STATEULPS3), | |
680 | PIS(ERRCONTENTIONLP0_1), | |
681 | PIS(ERRCONTENTIONLP1_1), | |
682 | PIS(ERRCONTENTIONLP0_2), | |
683 | PIS(ERRCONTENTIONLP1_2), | |
684 | PIS(ERRCONTENTIONLP0_3), | |
685 | PIS(ERRCONTENTIONLP1_3), | |
686 | PIS(ULPSACTIVENOT_ALL0), | |
687 | PIS(ULPSACTIVENOT_ALL1)); | |
688 | #undef PIS | |
689 | } | |
690 | ||
35b522cf | 691 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
f76ee892 TV |
692 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
693 | u32 *vcstatus, u32 ciostatus) | |
694 | { | |
695 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
696 | int i; | |
697 | ||
698 | spin_lock(&dsi->irq_stats_lock); | |
699 | ||
700 | dsi->irq_stats.irq_count++; | |
701 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
702 | ||
703 | for (i = 0; i < 4; ++i) | |
704 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); | |
705 | ||
706 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); | |
707 | ||
708 | spin_unlock(&dsi->irq_stats_lock); | |
709 | } | |
710 | #else | |
711 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) | |
712 | #endif | |
713 | ||
714 | static int debug_irq; | |
715 | ||
716 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, | |
717 | u32 *vcstatus, u32 ciostatus) | |
718 | { | |
719 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
720 | int i; | |
721 | ||
722 | if (irqstatus & DSI_IRQ_ERROR_MASK) { | |
723 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
724 | print_irq_status(irqstatus); | |
725 | spin_lock(&dsi->errors_lock); | |
726 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
727 | spin_unlock(&dsi->errors_lock); | |
728 | } else if (debug_irq) { | |
729 | print_irq_status(irqstatus); | |
730 | } | |
731 | ||
732 | for (i = 0; i < 4; ++i) { | |
733 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { | |
734 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
735 | i, vcstatus[i]); | |
736 | print_irq_status_vc(i, vcstatus[i]); | |
737 | } else if (debug_irq) { | |
738 | print_irq_status_vc(i, vcstatus[i]); | |
739 | } | |
740 | } | |
741 | ||
742 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { | |
743 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
744 | print_irq_status_cio(ciostatus); | |
745 | } else if (debug_irq) { | |
746 | print_irq_status_cio(ciostatus); | |
747 | } | |
748 | } | |
749 | ||
750 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, | |
751 | unsigned isr_array_size, u32 irqstatus) | |
752 | { | |
753 | struct dsi_isr_data *isr_data; | |
754 | int i; | |
755 | ||
756 | for (i = 0; i < isr_array_size; i++) { | |
757 | isr_data = &isr_array[i]; | |
758 | if (isr_data->isr && isr_data->mask & irqstatus) | |
759 | isr_data->isr(isr_data->arg, irqstatus); | |
760 | } | |
761 | } | |
762 | ||
763 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
764 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
765 | { | |
766 | int i; | |
767 | ||
768 | dsi_call_isrs(isr_tables->isr_table, | |
769 | ARRAY_SIZE(isr_tables->isr_table), | |
770 | irqstatus); | |
771 | ||
772 | for (i = 0; i < 4; ++i) { | |
773 | if (vcstatus[i] == 0) | |
774 | continue; | |
775 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
776 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
777 | vcstatus[i]); | |
778 | } | |
779 | ||
780 | if (ciostatus != 0) | |
781 | dsi_call_isrs(isr_tables->isr_table_cio, | |
782 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
783 | ciostatus); | |
784 | } | |
785 | ||
786 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) | |
787 | { | |
788 | struct platform_device *dsidev; | |
789 | struct dsi_data *dsi; | |
790 | u32 irqstatus, vcstatus[4], ciostatus; | |
791 | int i; | |
792 | ||
793 | dsidev = (struct platform_device *) arg; | |
794 | dsi = dsi_get_dsidrv_data(dsidev); | |
795 | ||
796 | if (!dsi->is_enabled) | |
797 | return IRQ_NONE; | |
798 | ||
799 | spin_lock(&dsi->irq_lock); | |
800 | ||
801 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); | |
802 | ||
803 | /* IRQ is not for us */ | |
804 | if (!irqstatus) { | |
805 | spin_unlock(&dsi->irq_lock); | |
806 | return IRQ_NONE; | |
807 | } | |
808 | ||
809 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); | |
810 | /* flush posted write */ | |
811 | dsi_read_reg(dsidev, DSI_IRQSTATUS); | |
812 | ||
813 | for (i = 0; i < 4; ++i) { | |
814 | if ((irqstatus & (1 << i)) == 0) { | |
815 | vcstatus[i] = 0; | |
816 | continue; | |
817 | } | |
818 | ||
819 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); | |
820 | ||
821 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); | |
822 | /* flush posted write */ | |
823 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); | |
824 | } | |
825 | ||
826 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
827 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); | |
828 | ||
829 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); | |
830 | /* flush posted write */ | |
831 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); | |
832 | } else { | |
833 | ciostatus = 0; | |
834 | } | |
835 | ||
836 | #ifdef DSI_CATCH_MISSING_TE | |
837 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
838 | del_timer(&dsi->te_timer); | |
839 | #endif | |
840 | ||
841 | /* make a copy and unlock, so that isrs can unregister | |
842 | * themselves */ | |
843 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, | |
844 | sizeof(dsi->isr_tables)); | |
845 | ||
846 | spin_unlock(&dsi->irq_lock); | |
847 | ||
848 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); | |
849 | ||
850 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); | |
851 | ||
852 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); | |
853 | ||
854 | return IRQ_HANDLED; | |
855 | } | |
856 | ||
857 | /* dsi->irq_lock has to be locked by the caller */ | |
858 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, | |
859 | struct dsi_isr_data *isr_array, | |
860 | unsigned isr_array_size, u32 default_mask, | |
861 | const struct dsi_reg enable_reg, | |
862 | const struct dsi_reg status_reg) | |
863 | { | |
864 | struct dsi_isr_data *isr_data; | |
865 | u32 mask; | |
866 | u32 old_mask; | |
867 | int i; | |
868 | ||
869 | mask = default_mask; | |
870 | ||
871 | for (i = 0; i < isr_array_size; i++) { | |
872 | isr_data = &isr_array[i]; | |
873 | ||
874 | if (isr_data->isr == NULL) | |
875 | continue; | |
876 | ||
877 | mask |= isr_data->mask; | |
878 | } | |
879 | ||
880 | old_mask = dsi_read_reg(dsidev, enable_reg); | |
881 | /* clear the irqstatus for newly enabled irqs */ | |
882 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); | |
883 | dsi_write_reg(dsidev, enable_reg, mask); | |
884 | ||
885 | /* flush posted writes */ | |
886 | dsi_read_reg(dsidev, enable_reg); | |
887 | dsi_read_reg(dsidev, status_reg); | |
888 | } | |
889 | ||
890 | /* dsi->irq_lock has to be locked by the caller */ | |
891 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) | |
892 | { | |
893 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
894 | u32 mask = DSI_IRQ_ERROR_MASK; | |
895 | #ifdef DSI_CATCH_MISSING_TE | |
896 | mask |= DSI_IRQ_TE_TRIGGER; | |
897 | #endif | |
898 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, | |
899 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, | |
900 | DSI_IRQENABLE, DSI_IRQSTATUS); | |
901 | } | |
902 | ||
903 | /* dsi->irq_lock has to be locked by the caller */ | |
904 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) | |
905 | { | |
906 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
907 | ||
908 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], | |
909 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), | |
910 | DSI_VC_IRQ_ERROR_MASK, | |
911 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
912 | } | |
913 | ||
914 | /* dsi->irq_lock has to be locked by the caller */ | |
915 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) | |
916 | { | |
917 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
918 | ||
919 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, | |
920 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), | |
921 | DSI_CIO_IRQ_ERROR_MASK, | |
922 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
923 | } | |
924 | ||
925 | static void _dsi_initialize_irq(struct platform_device *dsidev) | |
926 | { | |
927 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
928 | unsigned long flags; | |
929 | int vc; | |
930 | ||
931 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
932 | ||
933 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); | |
934 | ||
935 | _omap_dsi_set_irqs(dsidev); | |
936 | for (vc = 0; vc < 4; ++vc) | |
937 | _omap_dsi_set_irqs_vc(dsidev, vc); | |
938 | _omap_dsi_set_irqs_cio(dsidev); | |
939 | ||
940 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
941 | } | |
942 | ||
943 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
944 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
945 | { | |
946 | struct dsi_isr_data *isr_data; | |
947 | int free_idx; | |
948 | int i; | |
949 | ||
950 | BUG_ON(isr == NULL); | |
951 | ||
952 | /* check for duplicate entry and find a free slot */ | |
953 | free_idx = -1; | |
954 | for (i = 0; i < isr_array_size; i++) { | |
955 | isr_data = &isr_array[i]; | |
956 | ||
957 | if (isr_data->isr == isr && isr_data->arg == arg && | |
958 | isr_data->mask == mask) { | |
959 | return -EINVAL; | |
960 | } | |
961 | ||
962 | if (isr_data->isr == NULL && free_idx == -1) | |
963 | free_idx = i; | |
964 | } | |
965 | ||
966 | if (free_idx == -1) | |
967 | return -EBUSY; | |
968 | ||
969 | isr_data = &isr_array[free_idx]; | |
970 | isr_data->isr = isr; | |
971 | isr_data->arg = arg; | |
972 | isr_data->mask = mask; | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
978 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
979 | { | |
980 | struct dsi_isr_data *isr_data; | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < isr_array_size; i++) { | |
984 | isr_data = &isr_array[i]; | |
985 | if (isr_data->isr != isr || isr_data->arg != arg || | |
986 | isr_data->mask != mask) | |
987 | continue; | |
988 | ||
989 | isr_data->isr = NULL; | |
990 | isr_data->arg = NULL; | |
991 | isr_data->mask = 0; | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
996 | return -EINVAL; | |
997 | } | |
998 | ||
999 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, | |
1000 | void *arg, u32 mask) | |
1001 | { | |
1002 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1003 | unsigned long flags; | |
1004 | int r; | |
1005 | ||
1006 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1007 | ||
1008 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, | |
1009 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
1010 | ||
1011 | if (r == 0) | |
1012 | _omap_dsi_set_irqs(dsidev); | |
1013 | ||
1014 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1015 | ||
1016 | return r; | |
1017 | } | |
1018 | ||
1019 | static int dsi_unregister_isr(struct platform_device *dsidev, | |
1020 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
1021 | { | |
1022 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1023 | unsigned long flags; | |
1024 | int r; | |
1025 | ||
1026 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1027 | ||
1028 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, | |
1029 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
1030 | ||
1031 | if (r == 0) | |
1032 | _omap_dsi_set_irqs(dsidev); | |
1033 | ||
1034 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1035 | ||
1036 | return r; | |
1037 | } | |
1038 | ||
1039 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, | |
1040 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
1041 | { | |
1042 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1043 | unsigned long flags; | |
1044 | int r; | |
1045 | ||
1046 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1047 | ||
1048 | r = _dsi_register_isr(isr, arg, mask, | |
1049 | dsi->isr_tables.isr_table_vc[channel], | |
1050 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
1051 | ||
1052 | if (r == 0) | |
1053 | _omap_dsi_set_irqs_vc(dsidev, channel); | |
1054 | ||
1055 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1056 | ||
1057 | return r; | |
1058 | } | |
1059 | ||
1060 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, | |
1061 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
1062 | { | |
1063 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1064 | unsigned long flags; | |
1065 | int r; | |
1066 | ||
1067 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1068 | ||
1069 | r = _dsi_unregister_isr(isr, arg, mask, | |
1070 | dsi->isr_tables.isr_table_vc[channel], | |
1071 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
1072 | ||
1073 | if (r == 0) | |
1074 | _omap_dsi_set_irqs_vc(dsidev, channel); | |
1075 | ||
1076 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1077 | ||
1078 | return r; | |
1079 | } | |
1080 | ||
1081 | static int dsi_register_isr_cio(struct platform_device *dsidev, | |
1082 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
1083 | { | |
1084 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1085 | unsigned long flags; | |
1086 | int r; | |
1087 | ||
1088 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1089 | ||
1090 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, | |
1091 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
1092 | ||
1093 | if (r == 0) | |
1094 | _omap_dsi_set_irqs_cio(dsidev); | |
1095 | ||
1096 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1097 | ||
1098 | return r; | |
1099 | } | |
1100 | ||
1101 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, | |
1102 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
1103 | { | |
1104 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1105 | unsigned long flags; | |
1106 | int r; | |
1107 | ||
1108 | spin_lock_irqsave(&dsi->irq_lock, flags); | |
1109 | ||
1110 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, | |
1111 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
1112 | ||
1113 | if (r == 0) | |
1114 | _omap_dsi_set_irqs_cio(dsidev); | |
1115 | ||
1116 | spin_unlock_irqrestore(&dsi->irq_lock, flags); | |
1117 | ||
1118 | return r; | |
1119 | } | |
1120 | ||
1121 | static u32 dsi_get_errors(struct platform_device *dsidev) | |
1122 | { | |
1123 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1124 | unsigned long flags; | |
1125 | u32 e; | |
1126 | spin_lock_irqsave(&dsi->errors_lock, flags); | |
1127 | e = dsi->errors; | |
1128 | dsi->errors = 0; | |
1129 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
1130 | return e; | |
1131 | } | |
1132 | ||
1133 | static int dsi_runtime_get(struct platform_device *dsidev) | |
1134 | { | |
1135 | int r; | |
1136 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1137 | ||
1138 | DSSDBG("dsi_runtime_get\n"); | |
1139 | ||
b0e07060 ZQ |
1140 | r = pm_runtime_resume_and_get(&dsi->pdev->dev); |
1141 | if (WARN_ON(r < 0)) | |
78c2ce9b | 1142 | return r; |
78c2ce9b | 1143 | return 0; |
f76ee892 TV |
1144 | } |
1145 | ||
1146 | static void dsi_runtime_put(struct platform_device *dsidev) | |
1147 | { | |
1148 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1149 | int r; | |
1150 | ||
1151 | DSSDBG("dsi_runtime_put\n"); | |
1152 | ||
1153 | r = pm_runtime_put_sync(&dsi->pdev->dev); | |
1154 | WARN_ON(r < 0 && r != -ENOSYS); | |
1155 | } | |
1156 | ||
1157 | static int dsi_regulator_init(struct platform_device *dsidev) | |
1158 | { | |
1159 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1160 | struct regulator *vdds_dsi; | |
f76ee892 TV |
1161 | |
1162 | if (dsi->vdds_dsi_reg != NULL) | |
1163 | return 0; | |
1164 | ||
1165 | vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); | |
1166 | ||
1167 | if (IS_ERR(vdds_dsi)) { | |
1168 | if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) | |
1169 | DSSERR("can't get DSI VDD regulator\n"); | |
1170 | return PTR_ERR(vdds_dsi); | |
1171 | } | |
1172 | ||
f76ee892 TV |
1173 | dsi->vdds_dsi_reg = vdds_dsi; |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | static void _dsi_print_reset_status(struct platform_device *dsidev) | |
1179 | { | |
f76ee892 TV |
1180 | int b0, b1, b2; |
1181 | ||
1182 | /* A dummy read using the SCP interface to any DSIPHY register is | |
1183 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1184 | * I/O. */ | |
c96da175 | 1185 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
f76ee892 TV |
1186 | |
1187 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { | |
1188 | b0 = 28; | |
1189 | b1 = 27; | |
1190 | b2 = 26; | |
1191 | } else { | |
1192 | b0 = 24; | |
1193 | b1 = 25; | |
1194 | b2 = 26; | |
1195 | } | |
1196 | ||
1197 | #define DSI_FLD_GET(fld, start, end)\ | |
1198 | FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) | |
1199 | ||
1200 | pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", | |
1201 | DSI_FLD_GET(PLL_STATUS, 0, 0), | |
1202 | DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), | |
1203 | DSI_FLD_GET(DSIPHY_CFG5, b0, b0), | |
1204 | DSI_FLD_GET(DSIPHY_CFG5, b1, b1), | |
1205 | DSI_FLD_GET(DSIPHY_CFG5, b2, b2), | |
1206 | DSI_FLD_GET(DSIPHY_CFG5, 29, 29), | |
1207 | DSI_FLD_GET(DSIPHY_CFG5, 30, 30), | |
1208 | DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); | |
1209 | ||
1210 | #undef DSI_FLD_GET | |
1211 | } | |
1212 | ||
1213 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) | |
1214 | { | |
1215 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1216 | ||
1217 | enable = enable ? 1 : 0; | |
1218 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ | |
1219 | ||
1220 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { | |
1221 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); | |
1222 | return -EIO; | |
1223 | } | |
1224 | ||
1225 | return 0; | |
1226 | } | |
1227 | ||
1228 | static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) | |
1229 | { | |
1230 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1231 | ||
1232 | return dsi->pll.cinfo.clkout[HSDIV_DISPC]; | |
1233 | } | |
1234 | ||
1235 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) | |
1236 | { | |
1237 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1238 | ||
1239 | return dsi->pll.cinfo.clkout[HSDIV_DSI]; | |
1240 | } | |
1241 | ||
1242 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) | |
1243 | { | |
1244 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1245 | ||
1246 | return dsi->pll.cinfo.clkdco / 16; | |
1247 | } | |
1248 | ||
1249 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) | |
1250 | { | |
1251 | unsigned long r; | |
1252 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1253 | ||
1254 | if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { | |
1255 | /* DSI FCLK source is DSS_CLK_FCK */ | |
1256 | r = clk_get_rate(dsi->dss_clk); | |
1257 | } else { | |
1258 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ | |
1259 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); | |
1260 | } | |
1261 | ||
1262 | return r; | |
1263 | } | |
1264 | ||
1265 | static int dsi_lp_clock_calc(unsigned long dsi_fclk, | |
1266 | unsigned long lp_clk_min, unsigned long lp_clk_max, | |
1267 | struct dsi_lp_clock_info *lp_cinfo) | |
1268 | { | |
1269 | unsigned lp_clk_div; | |
1270 | unsigned long lp_clk; | |
1271 | ||
1272 | lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); | |
1273 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1274 | ||
1275 | if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) | |
1276 | return -EINVAL; | |
1277 | ||
1278 | lp_cinfo->lp_clk_div = lp_clk_div; | |
1279 | lp_cinfo->lp_clk = lp_clk; | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) | |
1285 | { | |
1286 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1287 | unsigned long dsi_fclk; | |
1288 | unsigned lp_clk_div; | |
1289 | unsigned long lp_clk; | |
1290 | unsigned lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
1291 | ||
1292 | ||
1293 | lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; | |
1294 | ||
1295 | if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) | |
1296 | return -EINVAL; | |
1297 | ||
1298 | dsi_fclk = dsi_fclk_rate(dsidev); | |
1299 | ||
1300 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1301 | ||
1302 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
1303 | dsi->current_lp_cinfo.lp_clk = lp_clk; | |
1304 | dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; | |
1305 | ||
1306 | /* LP_CLK_DIVISOR */ | |
1307 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); | |
1308 | ||
1309 | /* LP_RX_SYNCHRO_ENABLE */ | |
1310 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); | |
1311 | ||
1312 | return 0; | |
1313 | } | |
1314 | ||
1315 | static void dsi_enable_scp_clk(struct platform_device *dsidev) | |
1316 | { | |
1317 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1318 | ||
1319 | if (dsi->scp_clk_refcount++ == 0) | |
1320 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ | |
1321 | } | |
1322 | ||
1323 | static void dsi_disable_scp_clk(struct platform_device *dsidev) | |
1324 | { | |
1325 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1326 | ||
1327 | WARN_ON(dsi->scp_clk_refcount == 0); | |
1328 | if (--dsi->scp_clk_refcount == 0) | |
1329 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ | |
1330 | } | |
1331 | ||
1332 | enum dsi_pll_power_state { | |
1333 | DSI_PLL_POWER_OFF = 0x0, | |
1334 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1335 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1336 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1337 | }; | |
1338 | ||
1339 | static int dsi_pll_power(struct platform_device *dsidev, | |
1340 | enum dsi_pll_power_state state) | |
1341 | { | |
1342 | int t = 0; | |
1343 | ||
1344 | /* DSI-PLL power command 0x3 is not working */ | |
1345 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1346 | state == DSI_PLL_POWER_ON_DIV) | |
1347 | state = DSI_PLL_POWER_ON_ALL; | |
1348 | ||
1349 | /* PLL_PWR_CMD */ | |
1350 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); | |
1351 | ||
1352 | /* PLL_PWR_STATUS */ | |
1353 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { | |
1354 | if (++t > 1000) { | |
1355 | DSSERR("Failed to set DSI PLL power mode to %d\n", | |
1356 | state); | |
1357 | return -ENODEV; | |
1358 | } | |
1359 | udelay(1); | |
1360 | } | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | ||
1366 | static void dsi_pll_calc_dsi_fck(struct dss_pll_clock_info *cinfo) | |
1367 | { | |
1368 | unsigned long max_dsi_fck; | |
1369 | ||
1370 | max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK); | |
1371 | ||
1372 | cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); | |
1373 | cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; | |
1374 | } | |
1375 | ||
1376 | static int dsi_pll_enable(struct dss_pll *pll) | |
1377 | { | |
1378 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); | |
1379 | struct platform_device *dsidev = dsi->pdev; | |
1380 | int r = 0; | |
1381 | ||
1382 | DSSDBG("PLL init\n"); | |
1383 | ||
1384 | r = dsi_regulator_init(dsidev); | |
1385 | if (r) | |
1386 | return r; | |
1387 | ||
1388 | r = dsi_runtime_get(dsidev); | |
1389 | if (r) | |
1390 | return r; | |
1391 | ||
1392 | /* | |
1393 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1394 | */ | |
1395 | dsi_enable_scp_clk(dsidev); | |
1396 | ||
1397 | if (!dsi->vdds_dsi_enabled) { | |
1398 | r = regulator_enable(dsi->vdds_dsi_reg); | |
1399 | if (r) | |
1400 | goto err0; | |
1401 | dsi->vdds_dsi_enabled = true; | |
1402 | } | |
1403 | ||
1404 | /* XXX PLL does not come out of reset without this... */ | |
1405 | dispc_pck_free_enable(1); | |
1406 | ||
1407 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { | |
1408 | DSSERR("PLL not coming out of reset.\n"); | |
1409 | r = -ENODEV; | |
1410 | dispc_pck_free_enable(0); | |
1411 | goto err1; | |
1412 | } | |
1413 | ||
1414 | /* XXX ... but if left on, we get problems when planes do not | |
1415 | * fill the whole display. No idea about this */ | |
1416 | dispc_pck_free_enable(0); | |
1417 | ||
1418 | r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); | |
1419 | ||
1420 | if (r) | |
1421 | goto err1; | |
1422 | ||
1423 | DSSDBG("PLL init done\n"); | |
1424 | ||
1425 | return 0; | |
1426 | err1: | |
1427 | if (dsi->vdds_dsi_enabled) { | |
1428 | regulator_disable(dsi->vdds_dsi_reg); | |
1429 | dsi->vdds_dsi_enabled = false; | |
1430 | } | |
1431 | err0: | |
1432 | dsi_disable_scp_clk(dsidev); | |
1433 | dsi_runtime_put(dsidev); | |
1434 | return r; | |
1435 | } | |
1436 | ||
1437 | static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) | |
1438 | { | |
1439 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1440 | ||
1441 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); | |
1442 | if (disconnect_lanes) { | |
1443 | WARN_ON(!dsi->vdds_dsi_enabled); | |
1444 | regulator_disable(dsi->vdds_dsi_reg); | |
1445 | dsi->vdds_dsi_enabled = false; | |
1446 | } | |
1447 | ||
1448 | dsi_disable_scp_clk(dsidev); | |
1449 | dsi_runtime_put(dsidev); | |
1450 | ||
1451 | DSSDBG("PLL uninit done\n"); | |
1452 | } | |
1453 | ||
1454 | static void dsi_pll_disable(struct dss_pll *pll) | |
1455 | { | |
1456 | struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); | |
1457 | struct platform_device *dsidev = dsi->pdev; | |
1458 | ||
1459 | dsi_pll_uninit(dsidev, true); | |
1460 | } | |
1461 | ||
1462 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, | |
1463 | struct seq_file *s) | |
1464 | { | |
1465 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1466 | struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; | |
1467 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; | |
1468 | int dsi_module = dsi->module_id; | |
1469 | struct dss_pll *pll = &dsi->pll; | |
1470 | ||
1471 | dispc_clk_src = dss_get_dispc_clk_source(); | |
1472 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); | |
1473 | ||
1474 | if (dsi_runtime_get(dsidev)) | |
1475 | return; | |
1476 | ||
1477 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); | |
1478 | ||
1479 | seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); | |
1480 | ||
1481 | seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); | |
1482 | ||
1483 | seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", | |
1484 | cinfo->clkdco, cinfo->m); | |
1485 | ||
1486 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", | |
1487 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1488 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | |
1489 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), | |
1490 | cinfo->clkout[HSDIV_DISPC], | |
1491 | cinfo->mX[HSDIV_DISPC], | |
1492 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? | |
1493 | "off" : "on"); | |
1494 | ||
1495 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", | |
1496 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1497 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | |
1498 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), | |
1499 | cinfo->clkout[HSDIV_DSI], | |
1500 | cinfo->mX[HSDIV_DSI], | |
1501 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? | |
1502 | "off" : "on"); | |
1503 | ||
1504 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); | |
1505 | ||
1506 | seq_printf(s, "dsi fclk source = %s (%s)\n", | |
1507 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1508 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
1509 | ||
1510 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); | |
1511 | ||
1512 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1513 | cinfo->clkdco / 4); | |
1514 | ||
1515 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); | |
1516 | ||
1517 | seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); | |
1518 | ||
1519 | dsi_runtime_put(dsidev); | |
1520 | } | |
1521 | ||
1522 | void dsi_dump_clocks(struct seq_file *s) | |
1523 | { | |
1524 | struct platform_device *dsidev; | |
1525 | int i; | |
1526 | ||
1527 | for (i = 0; i < MAX_NUM_DSI; i++) { | |
1528 | dsidev = dsi_get_dsidev_from_id(i); | |
1529 | if (dsidev) | |
1530 | dsi_dump_dsidev_clocks(dsidev, s); | |
1531 | } | |
1532 | } | |
1533 | ||
35b522cf | 1534 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
f76ee892 TV |
1535 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
1536 | struct seq_file *s) | |
1537 | { | |
1538 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1539 | unsigned long flags; | |
634cf6ea AB |
1540 | struct dsi_irq_stats *stats; |
1541 | ||
1542 | stats = kzalloc(sizeof(*stats), GFP_KERNEL); | |
1543 | if (!stats) { | |
1544 | seq_printf(s, "out of memory\n"); | |
1545 | return; | |
1546 | } | |
f76ee892 TV |
1547 | |
1548 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); | |
1549 | ||
634cf6ea | 1550 | *stats = dsi->irq_stats; |
f76ee892 TV |
1551 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); |
1552 | dsi->irq_stats.last_reset = jiffies; | |
1553 | ||
1554 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); | |
1555 | ||
1556 | seq_printf(s, "period %u ms\n", | |
634cf6ea | 1557 | jiffies_to_msecs(jiffies - stats->last_reset)); |
f76ee892 | 1558 | |
634cf6ea | 1559 | seq_printf(s, "irqs %d\n", stats->irq_count); |
f76ee892 | 1560 | #define PIS(x) \ |
634cf6ea | 1561 | seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1]) |
f76ee892 TV |
1562 | |
1563 | seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); | |
1564 | PIS(VC0); | |
1565 | PIS(VC1); | |
1566 | PIS(VC2); | |
1567 | PIS(VC3); | |
1568 | PIS(WAKEUP); | |
1569 | PIS(RESYNC); | |
1570 | PIS(PLL_LOCK); | |
1571 | PIS(PLL_UNLOCK); | |
1572 | PIS(PLL_RECALL); | |
1573 | PIS(COMPLEXIO_ERR); | |
1574 | PIS(HS_TX_TIMEOUT); | |
1575 | PIS(LP_RX_TIMEOUT); | |
1576 | PIS(TE_TRIGGER); | |
1577 | PIS(ACK_TRIGGER); | |
1578 | PIS(SYNC_LOST); | |
1579 | PIS(LDO_POWER_GOOD); | |
1580 | PIS(TA_TIMEOUT); | |
1581 | #undef PIS | |
1582 | ||
1583 | #define PIS(x) \ | |
1584 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
634cf6ea AB |
1585 | stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ |
1586 | stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1587 | stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1588 | stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
f76ee892 TV |
1589 | |
1590 | seq_printf(s, "-- VC interrupts --\n"); | |
1591 | PIS(CS); | |
1592 | PIS(ECC_CORR); | |
1593 | PIS(PACKET_SENT); | |
1594 | PIS(FIFO_TX_OVF); | |
1595 | PIS(FIFO_RX_OVF); | |
1596 | PIS(BTA); | |
1597 | PIS(ECC_NO_CORR); | |
1598 | PIS(FIFO_TX_UDF); | |
1599 | PIS(PP_BUSY_CHANGE); | |
1600 | #undef PIS | |
1601 | ||
1602 | #define PIS(x) \ | |
1603 | seq_printf(s, "%-20s %10d\n", #x, \ | |
634cf6ea | 1604 | stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); |
f76ee892 TV |
1605 | |
1606 | seq_printf(s, "-- CIO interrupts --\n"); | |
1607 | PIS(ERRSYNCESC1); | |
1608 | PIS(ERRSYNCESC2); | |
1609 | PIS(ERRSYNCESC3); | |
1610 | PIS(ERRESC1); | |
1611 | PIS(ERRESC2); | |
1612 | PIS(ERRESC3); | |
1613 | PIS(ERRCONTROL1); | |
1614 | PIS(ERRCONTROL2); | |
1615 | PIS(ERRCONTROL3); | |
1616 | PIS(STATEULPS1); | |
1617 | PIS(STATEULPS2); | |
1618 | PIS(STATEULPS3); | |
1619 | PIS(ERRCONTENTIONLP0_1); | |
1620 | PIS(ERRCONTENTIONLP1_1); | |
1621 | PIS(ERRCONTENTIONLP0_2); | |
1622 | PIS(ERRCONTENTIONLP1_2); | |
1623 | PIS(ERRCONTENTIONLP0_3); | |
1624 | PIS(ERRCONTENTIONLP1_3); | |
1625 | PIS(ULPSACTIVENOT_ALL0); | |
1626 | PIS(ULPSACTIVENOT_ALL1); | |
1627 | #undef PIS | |
634cf6ea AB |
1628 | |
1629 | kfree(stats); | |
f76ee892 TV |
1630 | } |
1631 | ||
1632 | static void dsi1_dump_irqs(struct seq_file *s) | |
1633 | { | |
1634 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
1635 | ||
1636 | dsi_dump_dsidev_irqs(dsidev, s); | |
1637 | } | |
1638 | ||
1639 | static void dsi2_dump_irqs(struct seq_file *s) | |
1640 | { | |
1641 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1642 | ||
1643 | dsi_dump_dsidev_irqs(dsidev, s); | |
1644 | } | |
1645 | #endif | |
1646 | ||
1647 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, | |
1648 | struct seq_file *s) | |
1649 | { | |
1650 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) | |
1651 | ||
1652 | if (dsi_runtime_get(dsidev)) | |
1653 | return; | |
1654 | dsi_enable_scp_clk(dsidev); | |
1655 | ||
1656 | DUMPREG(DSI_REVISION); | |
1657 | DUMPREG(DSI_SYSCONFIG); | |
1658 | DUMPREG(DSI_SYSSTATUS); | |
1659 | DUMPREG(DSI_IRQSTATUS); | |
1660 | DUMPREG(DSI_IRQENABLE); | |
1661 | DUMPREG(DSI_CTRL); | |
1662 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1663 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1664 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1665 | DUMPREG(DSI_CLK_CTRL); | |
1666 | DUMPREG(DSI_TIMING1); | |
1667 | DUMPREG(DSI_TIMING2); | |
1668 | DUMPREG(DSI_VM_TIMING1); | |
1669 | DUMPREG(DSI_VM_TIMING2); | |
1670 | DUMPREG(DSI_VM_TIMING3); | |
1671 | DUMPREG(DSI_CLK_TIMING); | |
1672 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1673 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1674 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1675 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1676 | DUMPREG(DSI_VM_TIMING4); | |
1677 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1678 | DUMPREG(DSI_VM_TIMING5); | |
1679 | DUMPREG(DSI_VM_TIMING6); | |
1680 | DUMPREG(DSI_VM_TIMING7); | |
1681 | DUMPREG(DSI_STOPCLK_TIMING); | |
1682 | ||
1683 | DUMPREG(DSI_VC_CTRL(0)); | |
1684 | DUMPREG(DSI_VC_TE(0)); | |
1685 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1686 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1687 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1688 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1689 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1690 | ||
1691 | DUMPREG(DSI_VC_CTRL(1)); | |
1692 | DUMPREG(DSI_VC_TE(1)); | |
1693 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1694 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1695 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1696 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1697 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1698 | ||
1699 | DUMPREG(DSI_VC_CTRL(2)); | |
1700 | DUMPREG(DSI_VC_TE(2)); | |
1701 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1702 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1703 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1704 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1705 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1706 | ||
1707 | DUMPREG(DSI_VC_CTRL(3)); | |
1708 | DUMPREG(DSI_VC_TE(3)); | |
1709 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1710 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1711 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1712 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1713 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1714 | ||
1715 | DUMPREG(DSI_DSIPHY_CFG0); | |
1716 | DUMPREG(DSI_DSIPHY_CFG1); | |
1717 | DUMPREG(DSI_DSIPHY_CFG2); | |
1718 | DUMPREG(DSI_DSIPHY_CFG5); | |
1719 | ||
1720 | DUMPREG(DSI_PLL_CONTROL); | |
1721 | DUMPREG(DSI_PLL_STATUS); | |
1722 | DUMPREG(DSI_PLL_GO); | |
1723 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1724 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
1725 | ||
1726 | dsi_disable_scp_clk(dsidev); | |
1727 | dsi_runtime_put(dsidev); | |
1728 | #undef DUMPREG | |
1729 | } | |
1730 | ||
1731 | static void dsi1_dump_regs(struct seq_file *s) | |
1732 | { | |
1733 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
1734 | ||
1735 | dsi_dump_dsidev_regs(dsidev, s); | |
1736 | } | |
1737 | ||
1738 | static void dsi2_dump_regs(struct seq_file *s) | |
1739 | { | |
1740 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1741 | ||
1742 | dsi_dump_dsidev_regs(dsidev, s); | |
1743 | } | |
1744 | ||
1745 | enum dsi_cio_power_state { | |
1746 | DSI_COMPLEXIO_POWER_OFF = 0x0, | |
1747 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
1748 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
1749 | }; | |
1750 | ||
1751 | static int dsi_cio_power(struct platform_device *dsidev, | |
1752 | enum dsi_cio_power_state state) | |
1753 | { | |
1754 | int t = 0; | |
1755 | ||
1756 | /* PWR_CMD */ | |
1757 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); | |
1758 | ||
1759 | /* PWR_STATUS */ | |
1760 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), | |
1761 | 26, 25) != state) { | |
1762 | if (++t > 1000) { | |
1763 | DSSERR("failed to set complexio power state to " | |
1764 | "%d\n", state); | |
1765 | return -ENODEV; | |
1766 | } | |
1767 | udelay(1); | |
1768 | } | |
1769 | ||
1770 | return 0; | |
1771 | } | |
1772 | ||
1773 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) | |
1774 | { | |
1775 | int val; | |
1776 | ||
1777 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
1778 | /* XXX: for some reason using full buffer size causes | |
1779 | * considerable TX slowdown with update sizes that fill the | |
1780 | * whole buffer */ | |
1781 | if (!dss_has_feature(FEAT_DSI_GNQ)) | |
1782 | return 1023 * 3; | |
1783 | ||
1784 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ | |
1785 | ||
1786 | switch (val) { | |
1787 | case 1: | |
1788 | return 512 * 3; /* 512x24 bits */ | |
1789 | case 2: | |
1790 | return 682 * 3; /* 682x24 bits */ | |
1791 | case 3: | |
1792 | return 853 * 3; /* 853x24 bits */ | |
1793 | case 4: | |
1794 | return 1024 * 3; /* 1024x24 bits */ | |
1795 | case 5: | |
1796 | return 1194 * 3; /* 1194x24 bits */ | |
1797 | case 6: | |
1798 | return 1365 * 3; /* 1365x24 bits */ | |
1799 | case 7: | |
1800 | return 1920 * 3; /* 1920x24 bits */ | |
1801 | default: | |
1802 | BUG(); | |
1803 | return 0; | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | static int dsi_set_lane_config(struct platform_device *dsidev) | |
1808 | { | |
1809 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1810 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; | |
1811 | static const enum dsi_lane_function functions[] = { | |
1812 | DSI_LANE_CLK, | |
1813 | DSI_LANE_DATA1, | |
1814 | DSI_LANE_DATA2, | |
1815 | DSI_LANE_DATA3, | |
1816 | DSI_LANE_DATA4, | |
1817 | }; | |
1818 | u32 r; | |
1819 | int i; | |
1820 | ||
1821 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); | |
1822 | ||
1823 | for (i = 0; i < dsi->num_lanes_used; ++i) { | |
1824 | unsigned offset = offsets[i]; | |
1825 | unsigned polarity, lane_number; | |
1826 | unsigned t; | |
1827 | ||
1828 | for (t = 0; t < dsi->num_lanes_supported; ++t) | |
1829 | if (dsi->lanes[t].function == functions[i]) | |
1830 | break; | |
1831 | ||
1832 | if (t == dsi->num_lanes_supported) | |
1833 | return -EINVAL; | |
1834 | ||
1835 | lane_number = t; | |
1836 | polarity = dsi->lanes[t].polarity; | |
1837 | ||
1838 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); | |
1839 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); | |
1840 | } | |
1841 | ||
1842 | /* clear the unused lanes */ | |
1843 | for (; i < dsi->num_lanes_supported; ++i) { | |
1844 | unsigned offset = offsets[i]; | |
1845 | ||
1846 | r = FLD_MOD(r, 0, offset + 2, offset); | |
1847 | r = FLD_MOD(r, 0, offset + 3, offset + 3); | |
1848 | } | |
1849 | ||
1850 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); | |
1851 | ||
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) | |
1856 | { | |
1857 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1858 | ||
1859 | /* convert time in ns to ddr ticks, rounding up */ | |
1860 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; | |
1861 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; | |
1862 | } | |
1863 | ||
1864 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) | |
1865 | { | |
1866 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1867 | ||
1868 | unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; | |
1869 | return ddr * 1000 * 1000 / (ddr_clk / 1000); | |
1870 | } | |
1871 | ||
1872 | static void dsi_cio_timings(struct platform_device *dsidev) | |
1873 | { | |
1874 | u32 r; | |
1875 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
1876 | u32 tlpx_half, tclk_trail, tclk_zero; | |
1877 | u32 tclk_prepare; | |
1878 | ||
1879 | /* calculate timings */ | |
1880 | ||
1881 | /* 1 * DDR_CLK = 2 * UI */ | |
1882 | ||
1883 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
1884 | ths_prepare = ns2ddr(dsidev, 70) + 2; | |
1885 | ||
1886 | /* min 145ns + 10*UI */ | |
1887 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; | |
1888 | ||
1889 | /* min max(8*UI, 60ns+4*UI) */ | |
1890 | ths_trail = ns2ddr(dsidev, 60) + 5; | |
1891 | ||
1892 | /* min 100ns */ | |
1893 | ths_exit = ns2ddr(dsidev, 145); | |
1894 | ||
1895 | /* tlpx min 50n */ | |
1896 | tlpx_half = ns2ddr(dsidev, 25); | |
1897 | ||
1898 | /* min 60ns */ | |
1899 | tclk_trail = ns2ddr(dsidev, 60) + 2; | |
1900 | ||
1901 | /* min 38ns, max 95ns */ | |
1902 | tclk_prepare = ns2ddr(dsidev, 65); | |
1903 | ||
1904 | /* min tclk-prepare + tclk-zero = 300ns */ | |
1905 | tclk_zero = ns2ddr(dsidev, 260); | |
1906 | ||
1907 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
1908 | ths_prepare, ddr2ns(dsidev, ths_prepare), | |
1909 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); | |
1910 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", | |
1911 | ths_trail, ddr2ns(dsidev, ths_trail), | |
1912 | ths_exit, ddr2ns(dsidev, ths_exit)); | |
1913 | ||
1914 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
1915 | "tclk_zero %u (%uns)\n", | |
1916 | tlpx_half, ddr2ns(dsidev, tlpx_half), | |
1917 | tclk_trail, ddr2ns(dsidev, tclk_trail), | |
1918 | tclk_zero, ddr2ns(dsidev, tclk_zero)); | |
1919 | DSSDBG("tclk_prepare %u (%uns)\n", | |
1920 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); | |
1921 | ||
1922 | /* program timings */ | |
1923 | ||
1924 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); | |
1925 | r = FLD_MOD(r, ths_prepare, 31, 24); | |
1926 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
1927 | r = FLD_MOD(r, ths_trail, 15, 8); | |
1928 | r = FLD_MOD(r, ths_exit, 7, 0); | |
1929 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); | |
1930 | ||
1931 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); | |
1932 | r = FLD_MOD(r, tlpx_half, 20, 16); | |
1933 | r = FLD_MOD(r, tclk_trail, 15, 8); | |
1934 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
1935 | ||
1936 | if (dss_has_feature(FEAT_DSI_PHY_DCC)) { | |
1937 | r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ | |
1938 | r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ | |
1939 | r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ | |
1940 | } | |
1941 | ||
1942 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); | |
1943 | ||
1944 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); | |
1945 | r = FLD_MOD(r, tclk_prepare, 7, 0); | |
1946 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); | |
1947 | } | |
1948 | ||
1949 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ | |
1950 | static void dsi_cio_enable_lane_override(struct platform_device *dsidev, | |
1951 | unsigned mask_p, unsigned mask_n) | |
1952 | { | |
1953 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1954 | int i; | |
1955 | u32 l; | |
1956 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; | |
1957 | ||
1958 | l = 0; | |
1959 | ||
1960 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
1961 | unsigned p = dsi->lanes[i].polarity; | |
1962 | ||
1963 | if (mask_p & (1 << i)) | |
1964 | l |= 1 << (i * 2 + (p ? 0 : 1)); | |
1965 | ||
1966 | if (mask_n & (1 << i)) | |
1967 | l |= 1 << (i * 2 + (p ? 1 : 0)); | |
1968 | } | |
1969 | ||
1970 | /* | |
1971 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
1972 | * 17: DY0 18: DX0 | |
1973 | * 19: DY1 20: DX1 | |
1974 | * 21: DY2 22: DX2 | |
1975 | * 23: DY3 24: DX3 | |
1976 | * 25: DY4 26: DX4 | |
1977 | */ | |
1978 | ||
1979 | /* Set the lane override configuration */ | |
1980 | ||
1981 | /* REGLPTXSCPDAT4TO0DXDY */ | |
1982 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); | |
1983 | ||
1984 | /* Enable lane override */ | |
1985 | ||
1986 | /* ENLPTXSCPDAT */ | |
1987 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); | |
1988 | } | |
1989 | ||
1990 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) | |
1991 | { | |
1992 | /* Disable lane override */ | |
1993 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ | |
1994 | /* Reset the lane override configuration */ | |
1995 | /* REGLPTXSCPDAT4TO0DXDY */ | |
1996 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); | |
1997 | } | |
1998 | ||
1999 | static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) | |
2000 | { | |
2001 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2002 | int t, i; | |
2003 | bool in_use[DSI_MAX_NR_LANES]; | |
2004 | static const u8 offsets_old[] = { 28, 27, 26 }; | |
2005 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; | |
2006 | const u8 *offsets; | |
2007 | ||
2008 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) | |
2009 | offsets = offsets_old; | |
2010 | else | |
2011 | offsets = offsets_new; | |
2012 | ||
2013 | for (i = 0; i < dsi->num_lanes_supported; ++i) | |
2014 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; | |
2015 | ||
2016 | t = 100000; | |
2017 | while (true) { | |
2018 | u32 l; | |
2019 | int ok; | |
2020 | ||
2021 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); | |
2022 | ||
2023 | ok = 0; | |
2024 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2025 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
2026 | ok++; | |
2027 | } | |
2028 | ||
2029 | if (ok == dsi->num_lanes_supported) | |
2030 | break; | |
2031 | ||
2032 | if (--t == 0) { | |
2033 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2034 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
2035 | continue; | |
2036 | ||
2037 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
2038 | "out of reset\n", i); | |
2039 | } | |
2040 | return -EIO; | |
2041 | } | |
2042 | } | |
2043 | ||
2044 | return 0; | |
2045 | } | |
2046 | ||
2047 | /* return bitmask of enabled lanes, lane0 being the lsb */ | |
2048 | static unsigned dsi_get_lane_mask(struct platform_device *dsidev) | |
2049 | { | |
2050 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2051 | unsigned mask = 0; | |
2052 | int i; | |
2053 | ||
2054 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2055 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) | |
2056 | mask |= 1 << i; | |
2057 | } | |
2058 | ||
2059 | return mask; | |
2060 | } | |
2061 | ||
2062 | static int dsi_cio_init(struct platform_device *dsidev) | |
2063 | { | |
2064 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2065 | int r; | |
2066 | u32 l; | |
2067 | ||
2068 | DSSDBG("DSI CIO init starts"); | |
2069 | ||
2070 | r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); | |
2071 | if (r) | |
2072 | return r; | |
2073 | ||
2074 | dsi_enable_scp_clk(dsidev); | |
2075 | ||
2076 | /* A dummy read using the SCP interface to any DSIPHY register is | |
2077 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2078 | * I/O. */ | |
2079 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); | |
2080 | ||
2081 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { | |
2082 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); | |
2083 | r = -EIO; | |
2084 | goto err_scp_clk_dom; | |
2085 | } | |
2086 | ||
2087 | r = dsi_set_lane_config(dsidev); | |
2088 | if (r) | |
2089 | goto err_scp_clk_dom; | |
2090 | ||
2091 | /* set TX STOP MODE timer to maximum for this operation */ | |
2092 | l = dsi_read_reg(dsidev, DSI_TIMING1); | |
2093 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ | |
2094 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2095 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2096 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
2097 | dsi_write_reg(dsidev, DSI_TIMING1, l); | |
2098 | ||
2099 | if (dsi->ulps_enabled) { | |
2100 | unsigned mask_p; | |
2101 | int i; | |
2102 | ||
2103 | DSSDBG("manual ulps exit\n"); | |
2104 | ||
2105 | /* ULPS is exited by Mark-1 state for 1ms, followed by | |
2106 | * stop state. DSS HW cannot do this via the normal | |
2107 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2108 | * that we are not in ULPS mode, and refuses to send the | |
2109 | * sequence. So we need to send the ULPS exit sequence | |
2110 | * manually by setting positive lines high and negative lines | |
2111 | * low for 1ms. | |
2112 | */ | |
2113 | ||
2114 | mask_p = 0; | |
2115 | ||
2116 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2117 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
2118 | continue; | |
2119 | mask_p |= 1 << i; | |
2120 | } | |
2121 | ||
2122 | dsi_cio_enable_lane_override(dsidev, mask_p, 0); | |
2123 | } | |
2124 | ||
2125 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); | |
2126 | if (r) | |
2127 | goto err_cio_pwr; | |
2128 | ||
2129 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { | |
2130 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); | |
2131 | r = -ENODEV; | |
2132 | goto err_cio_pwr_dom; | |
2133 | } | |
2134 | ||
2135 | dsi_if_enable(dsidev, true); | |
2136 | dsi_if_enable(dsidev, false); | |
2137 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
2138 | ||
2139 | r = dsi_cio_wait_tx_clk_esc_reset(dsidev); | |
2140 | if (r) | |
2141 | goto err_tx_clk_esc_rst; | |
2142 | ||
2143 | if (dsi->ulps_enabled) { | |
2144 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ | |
2145 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2146 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2147 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2148 | ||
2149 | /* Disable the override. The lanes should be set to Mark-11 | |
2150 | * state by the HW */ | |
2151 | dsi_cio_disable_lane_override(dsidev); | |
2152 | } | |
2153 | ||
2154 | /* FORCE_TX_STOP_MODE_IO */ | |
2155 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); | |
2156 | ||
2157 | dsi_cio_timings(dsidev); | |
2158 | ||
2159 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
2160 | /* DDR_CLK_ALWAYS_ON */ | |
2161 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, | |
2162 | dsi->vm_timings.ddr_clk_always_on, 13, 13); | |
2163 | } | |
2164 | ||
2165 | dsi->ulps_enabled = false; | |
2166 | ||
2167 | DSSDBG("CIO init done\n"); | |
2168 | ||
2169 | return 0; | |
2170 | ||
2171 | err_tx_clk_esc_rst: | |
2172 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ | |
2173 | err_cio_pwr_dom: | |
2174 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); | |
2175 | err_cio_pwr: | |
2176 | if (dsi->ulps_enabled) | |
2177 | dsi_cio_disable_lane_override(dsidev); | |
2178 | err_scp_clk_dom: | |
2179 | dsi_disable_scp_clk(dsidev); | |
2180 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); | |
2181 | return r; | |
2182 | } | |
2183 | ||
2184 | static void dsi_cio_uninit(struct platform_device *dsidev) | |
2185 | { | |
2186 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2187 | ||
2188 | /* DDR_CLK_ALWAYS_ON */ | |
2189 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
2190 | ||
2191 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); | |
2192 | dsi_disable_scp_clk(dsidev); | |
2193 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev)); | |
2194 | } | |
2195 | ||
2196 | static void dsi_config_tx_fifo(struct platform_device *dsidev, | |
2197 | enum fifo_size size1, enum fifo_size size2, | |
2198 | enum fifo_size size3, enum fifo_size size4) | |
2199 | { | |
2200 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2201 | u32 r = 0; | |
2202 | int add = 0; | |
2203 | int i; | |
2204 | ||
2205 | dsi->vc[0].tx_fifo_size = size1; | |
2206 | dsi->vc[1].tx_fifo_size = size2; | |
2207 | dsi->vc[2].tx_fifo_size = size3; | |
2208 | dsi->vc[3].tx_fifo_size = size4; | |
2209 | ||
2210 | for (i = 0; i < 4; i++) { | |
2211 | u8 v; | |
2212 | int size = dsi->vc[i].tx_fifo_size; | |
2213 | ||
2214 | if (add + size > 4) { | |
2215 | DSSERR("Illegal FIFO configuration\n"); | |
2216 | BUG(); | |
2217 | return; | |
2218 | } | |
2219 | ||
2220 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2221 | r |= v << (8 * i); | |
2222 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2223 | add += size; | |
2224 | } | |
2225 | ||
2226 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); | |
2227 | } | |
2228 | ||
2229 | static void dsi_config_rx_fifo(struct platform_device *dsidev, | |
2230 | enum fifo_size size1, enum fifo_size size2, | |
2231 | enum fifo_size size3, enum fifo_size size4) | |
2232 | { | |
2233 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2234 | u32 r = 0; | |
2235 | int add = 0; | |
2236 | int i; | |
2237 | ||
2238 | dsi->vc[0].rx_fifo_size = size1; | |
2239 | dsi->vc[1].rx_fifo_size = size2; | |
2240 | dsi->vc[2].rx_fifo_size = size3; | |
2241 | dsi->vc[3].rx_fifo_size = size4; | |
2242 | ||
2243 | for (i = 0; i < 4; i++) { | |
2244 | u8 v; | |
2245 | int size = dsi->vc[i].rx_fifo_size; | |
2246 | ||
2247 | if (add + size > 4) { | |
2248 | DSSERR("Illegal FIFO configuration\n"); | |
2249 | BUG(); | |
2250 | return; | |
2251 | } | |
2252 | ||
2253 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2254 | r |= v << (8 * i); | |
2255 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2256 | add += size; | |
2257 | } | |
2258 | ||
2259 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); | |
2260 | } | |
2261 | ||
2262 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) | |
2263 | { | |
2264 | u32 r; | |
2265 | ||
2266 | r = dsi_read_reg(dsidev, DSI_TIMING1); | |
2267 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ | |
2268 | dsi_write_reg(dsidev, DSI_TIMING1, r); | |
2269 | ||
2270 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { | |
2271 | DSSERR("TX_STOP bit not going down\n"); | |
2272 | return -EIO; | |
2273 | } | |
2274 | ||
2275 | return 0; | |
2276 | } | |
2277 | ||
2278 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) | |
2279 | { | |
2280 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); | |
2281 | } | |
2282 | ||
2283 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2284 | { | |
2285 | struct dsi_packet_sent_handler_data *vp_data = | |
2286 | (struct dsi_packet_sent_handler_data *) data; | |
2287 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); | |
2288 | const int channel = dsi->update_channel; | |
2289 | u8 bit = dsi->te_enabled ? 30 : 31; | |
2290 | ||
2291 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) | |
2292 | complete(vp_data->completion); | |
2293 | } | |
2294 | ||
2295 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) | |
2296 | { | |
2297 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2298 | DECLARE_COMPLETION_ONSTACK(completion); | |
2299 | struct dsi_packet_sent_handler_data vp_data = { | |
2300 | .dsidev = dsidev, | |
2301 | .completion = &completion | |
2302 | }; | |
2303 | int r = 0; | |
2304 | u8 bit; | |
2305 | ||
2306 | bit = dsi->te_enabled ? 30 : 31; | |
2307 | ||
2308 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, | |
2309 | &vp_data, DSI_VC_IRQ_PACKET_SENT); | |
2310 | if (r) | |
2311 | goto err0; | |
2312 | ||
2313 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
2314 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { | |
2315 | if (wait_for_completion_timeout(&completion, | |
2316 | msecs_to_jiffies(10)) == 0) { | |
2317 | DSSERR("Failed to complete previous frame transfer\n"); | |
2318 | r = -EIO; | |
2319 | goto err1; | |
2320 | } | |
2321 | } | |
2322 | ||
2323 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, | |
2324 | &vp_data, DSI_VC_IRQ_PACKET_SENT); | |
2325 | ||
2326 | return 0; | |
2327 | err1: | |
2328 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, | |
2329 | &vp_data, DSI_VC_IRQ_PACKET_SENT); | |
2330 | err0: | |
2331 | return r; | |
2332 | } | |
2333 | ||
2334 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2335 | { | |
2336 | struct dsi_packet_sent_handler_data *l4_data = | |
2337 | (struct dsi_packet_sent_handler_data *) data; | |
2338 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); | |
2339 | const int channel = dsi->update_channel; | |
2340 | ||
2341 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) | |
2342 | complete(l4_data->completion); | |
2343 | } | |
2344 | ||
2345 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) | |
2346 | { | |
2347 | DECLARE_COMPLETION_ONSTACK(completion); | |
2348 | struct dsi_packet_sent_handler_data l4_data = { | |
2349 | .dsidev = dsidev, | |
2350 | .completion = &completion | |
2351 | }; | |
2352 | int r = 0; | |
2353 | ||
2354 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, | |
2355 | &l4_data, DSI_VC_IRQ_PACKET_SENT); | |
2356 | if (r) | |
2357 | goto err0; | |
2358 | ||
2359 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
2360 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { | |
2361 | if (wait_for_completion_timeout(&completion, | |
2362 | msecs_to_jiffies(10)) == 0) { | |
2363 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2364 | r = -EIO; | |
2365 | goto err1; | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, | |
2370 | &l4_data, DSI_VC_IRQ_PACKET_SENT); | |
2371 | ||
2372 | return 0; | |
2373 | err1: | |
2374 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, | |
2375 | &l4_data, DSI_VC_IRQ_PACKET_SENT); | |
2376 | err0: | |
2377 | return r; | |
2378 | } | |
2379 | ||
2380 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) | |
2381 | { | |
2382 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2383 | ||
2384 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
2385 | ||
f76ee892 TV |
2386 | if (!dsi_vc_is_enabled(dsidev, channel)) |
2387 | return 0; | |
2388 | ||
2389 | switch (dsi->vc[channel].source) { | |
2390 | case DSI_VC_SOURCE_VP: | |
2391 | return dsi_sync_vc_vp(dsidev, channel); | |
2392 | case DSI_VC_SOURCE_L4: | |
2393 | return dsi_sync_vc_l4(dsidev, channel); | |
2394 | default: | |
2395 | BUG(); | |
2396 | return -EINVAL; | |
2397 | } | |
2398 | } | |
2399 | ||
2400 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, | |
2401 | bool enable) | |
2402 | { | |
2403 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", | |
2404 | channel, enable); | |
2405 | ||
2406 | enable = enable ? 1 : 0; | |
2407 | ||
2408 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); | |
2409 | ||
2410 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), | |
2411 | 0, enable) != enable) { | |
2412 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); | |
2413 | return -EIO; | |
2414 | } | |
2415 | ||
2416 | return 0; | |
2417 | } | |
2418 | ||
2419 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) | |
2420 | { | |
2421 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2422 | u32 r; | |
2423 | ||
2424 | DSSDBG("Initial config of virtual channel %d", channel); | |
2425 | ||
2426 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); | |
2427 | ||
2428 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2429 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2430 | channel); | |
2431 | ||
2432 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2433 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2434 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2435 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2436 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2437 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2438 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
2439 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) | |
2440 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
2441 | ||
2442 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2443 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2444 | ||
2445 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); | |
2446 | ||
2447 | dsi->vc[channel].source = DSI_VC_SOURCE_L4; | |
2448 | } | |
2449 | ||
2450 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, | |
2451 | enum dsi_vc_source source) | |
2452 | { | |
2453 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2454 | ||
2455 | if (dsi->vc[channel].source == source) | |
2456 | return 0; | |
2457 | ||
2458 | DSSDBG("Source config of virtual channel %d", channel); | |
2459 | ||
2460 | dsi_sync_vc(dsidev, channel); | |
2461 | ||
2462 | dsi_vc_enable(dsidev, channel, 0); | |
2463 | ||
2464 | /* VC_BUSY */ | |
2465 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { | |
2466 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); | |
2467 | return -EIO; | |
2468 | } | |
2469 | ||
2470 | /* SOURCE, 0 = L4, 1 = video port */ | |
2471 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); | |
2472 | ||
2473 | /* DCS_CMD_ENABLE */ | |
2474 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { | |
2475 | bool enable = source == DSI_VC_SOURCE_VP; | |
2476 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); | |
2477 | } | |
2478 | ||
2479 | dsi_vc_enable(dsidev, channel, 1); | |
2480 | ||
2481 | dsi->vc[channel].source = source; | |
2482 | ||
2483 | return 0; | |
2484 | } | |
2485 | ||
2486 | static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, | |
2487 | bool enable) | |
2488 | { | |
2489 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2490 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2491 | ||
2492 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); | |
2493 | ||
2494 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
2495 | ||
2496 | dsi_vc_enable(dsidev, channel, 0); | |
2497 | dsi_if_enable(dsidev, 0); | |
2498 | ||
2499 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); | |
2500 | ||
2501 | dsi_vc_enable(dsidev, channel, 1); | |
2502 | dsi_if_enable(dsidev, 1); | |
2503 | ||
2504 | dsi_force_tx_stop_mode_io(dsidev); | |
2505 | ||
2506 | /* start the DDR clock by sending a NULL packet */ | |
2507 | if (dsi->vm_timings.ddr_clk_always_on && enable) | |
2508 | dsi_vc_send_null(dssdev, channel); | |
2509 | } | |
2510 | ||
2511 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) | |
2512 | { | |
2513 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
2514 | u32 val; | |
2515 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2516 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", | |
2517 | (val >> 0) & 0xff, | |
2518 | (val >> 8) & 0xff, | |
2519 | (val >> 16) & 0xff, | |
2520 | (val >> 24) & 0xff); | |
2521 | } | |
2522 | } | |
2523 | ||
2524 | static void dsi_show_rx_ack_with_err(u16 err) | |
2525 | { | |
2526 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2527 | if (err & (1 << 0)) | |
2528 | DSSERR("\t\tSoT Error\n"); | |
2529 | if (err & (1 << 1)) | |
2530 | DSSERR("\t\tSoT Sync Error\n"); | |
2531 | if (err & (1 << 2)) | |
2532 | DSSERR("\t\tEoT Sync Error\n"); | |
2533 | if (err & (1 << 3)) | |
2534 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2535 | if (err & (1 << 4)) | |
2536 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2537 | if (err & (1 << 5)) | |
2538 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2539 | if (err & (1 << 6)) | |
2540 | DSSERR("\t\tFalse Control Error\n"); | |
2541 | if (err & (1 << 7)) | |
2542 | DSSERR("\t\t(reserved7)\n"); | |
2543 | if (err & (1 << 8)) | |
2544 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2545 | if (err & (1 << 9)) | |
2546 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2547 | if (err & (1 << 10)) | |
2548 | DSSERR("\t\tChecksum Error\n"); | |
2549 | if (err & (1 << 11)) | |
2550 | DSSERR("\t\tData type not recognized\n"); | |
2551 | if (err & (1 << 12)) | |
2552 | DSSERR("\t\tInvalid VC ID\n"); | |
2553 | if (err & (1 << 13)) | |
2554 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2555 | if (err & (1 << 14)) | |
2556 | DSSERR("\t\t(reserved14)\n"); | |
2557 | if (err & (1 << 15)) | |
2558 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2559 | } | |
2560 | ||
2561 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, | |
2562 | int channel) | |
2563 | { | |
2564 | /* RX_FIFO_NOT_EMPTY */ | |
2565 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
2566 | u32 val; | |
2567 | u8 dt; | |
2568 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2569 | DSSERR("\trawval %#08x\n", val); | |
2570 | dt = FLD_GET(val, 5, 0); | |
2571 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { | |
2572 | u16 err = FLD_GET(val, 23, 8); | |
2573 | dsi_show_rx_ack_with_err(err); | |
2574 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { | |
2575 | DSSERR("\tDCS short response, 1 byte: %#x\n", | |
2576 | FLD_GET(val, 23, 8)); | |
2577 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { | |
2578 | DSSERR("\tDCS short response, 2 byte: %#x\n", | |
2579 | FLD_GET(val, 23, 8)); | |
2580 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { | |
2581 | DSSERR("\tDCS long response, len %d\n", | |
2582 | FLD_GET(val, 23, 8)); | |
2583 | dsi_vc_flush_long_data(dsidev, channel); | |
2584 | } else { | |
2585 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2586 | } | |
2587 | } | |
2588 | return 0; | |
2589 | } | |
2590 | ||
2591 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) | |
2592 | { | |
2593 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2594 | ||
2595 | if (dsi->debug_write || dsi->debug_read) | |
2596 | DSSDBG("dsi_vc_send_bta %d\n", channel); | |
2597 | ||
2598 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
2599 | ||
2600 | /* RX_FIFO_NOT_EMPTY */ | |
2601 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
2602 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); | |
2603 | dsi_vc_flush_receive_data(dsidev, channel); | |
2604 | } | |
2605 | ||
2606 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ | |
2607 | ||
2608 | /* flush posted write */ | |
2609 | dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); | |
2610 | ||
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) | |
2615 | { | |
2616 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2617 | DECLARE_COMPLETION_ONSTACK(completion); | |
2618 | int r = 0; | |
2619 | u32 err; | |
2620 | ||
2621 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, | |
2622 | &completion, DSI_VC_IRQ_BTA); | |
2623 | if (r) | |
2624 | goto err0; | |
2625 | ||
2626 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, | |
2627 | DSI_IRQ_ERROR_MASK); | |
2628 | if (r) | |
2629 | goto err1; | |
2630 | ||
2631 | r = dsi_vc_send_bta(dsidev, channel); | |
2632 | if (r) | |
2633 | goto err2; | |
2634 | ||
2635 | if (wait_for_completion_timeout(&completion, | |
2636 | msecs_to_jiffies(500)) == 0) { | |
2637 | DSSERR("Failed to receive BTA\n"); | |
2638 | r = -EIO; | |
2639 | goto err2; | |
2640 | } | |
2641 | ||
2642 | err = dsi_get_errors(dsidev); | |
2643 | if (err) { | |
2644 | DSSERR("Error while sending BTA: %x\n", err); | |
2645 | r = -EIO; | |
2646 | goto err2; | |
2647 | } | |
2648 | err2: | |
2649 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, | |
2650 | DSI_IRQ_ERROR_MASK); | |
2651 | err1: | |
2652 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, | |
2653 | &completion, DSI_VC_IRQ_BTA); | |
2654 | err0: | |
2655 | return r; | |
2656 | } | |
2657 | ||
2658 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, | |
2659 | int channel, u8 data_type, u16 len, u8 ecc) | |
2660 | { | |
2661 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2662 | u32 val; | |
2663 | u8 data_id; | |
2664 | ||
2665 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
2666 | ||
2667 | data_id = data_type | dsi->vc[channel].vc_id << 6; | |
2668 | ||
2669 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2670 | FLD_VAL(ecc, 31, 24); | |
2671 | ||
2672 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); | |
2673 | } | |
2674 | ||
2675 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, | |
2676 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) | |
2677 | { | |
2678 | u32 val; | |
2679 | ||
2680 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2681 | ||
2682 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2683 | b1, b2, b3, b4, val); */ | |
2684 | ||
2685 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); | |
2686 | } | |
2687 | ||
2688 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, | |
2689 | u8 data_type, u8 *data, u16 len, u8 ecc) | |
2690 | { | |
2691 | /*u32 val; */ | |
2692 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2693 | int i; | |
2694 | u8 *p; | |
2695 | int r = 0; | |
2696 | u8 b1, b2, b3, b4; | |
2697 | ||
2698 | if (dsi->debug_write) | |
2699 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); | |
2700 | ||
2701 | /* len + header */ | |
2702 | if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { | |
2703 | DSSERR("unable to send long packet: packet too long.\n"); | |
2704 | return -EINVAL; | |
2705 | } | |
2706 | ||
2707 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); | |
2708 | ||
2709 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); | |
2710 | ||
2711 | p = data; | |
2712 | for (i = 0; i < len >> 2; i++) { | |
2713 | if (dsi->debug_write) | |
2714 | DSSDBG("\tsending full packet %d\n", i); | |
2715 | ||
2716 | b1 = *p++; | |
2717 | b2 = *p++; | |
2718 | b3 = *p++; | |
2719 | b4 = *p++; | |
2720 | ||
2721 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); | |
2722 | } | |
2723 | ||
2724 | i = len % 4; | |
2725 | if (i) { | |
2726 | b1 = 0; b2 = 0; b3 = 0; | |
2727 | ||
2728 | if (dsi->debug_write) | |
2729 | DSSDBG("\tsending remainder bytes %d\n", i); | |
2730 | ||
2731 | switch (i) { | |
2732 | case 3: | |
2733 | b1 = *p++; | |
2734 | b2 = *p++; | |
2735 | b3 = *p++; | |
2736 | break; | |
2737 | case 2: | |
2738 | b1 = *p++; | |
2739 | b2 = *p++; | |
2740 | break; | |
2741 | case 1: | |
2742 | b1 = *p++; | |
2743 | break; | |
2744 | } | |
2745 | ||
2746 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); | |
2747 | } | |
2748 | ||
2749 | return r; | |
2750 | } | |
2751 | ||
2752 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, | |
2753 | u8 data_type, u16 data, u8 ecc) | |
2754 | { | |
2755 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2756 | u32 r; | |
2757 | u8 data_id; | |
2758 | ||
2759 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
2760 | ||
2761 | if (dsi->debug_write) | |
2762 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", | |
2763 | channel, | |
2764 | data_type, data & 0xff, (data >> 8) & 0xff); | |
2765 | ||
2766 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); | |
2767 | ||
2768 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { | |
2769 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); | |
2770 | return -EINVAL; | |
2771 | } | |
2772 | ||
2773 | data_id = data_type | dsi->vc[channel].vc_id << 6; | |
2774 | ||
2775 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
2776 | ||
2777 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); | |
2778 | ||
2779 | return 0; | |
2780 | } | |
2781 | ||
2782 | static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) | |
2783 | { | |
2784 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2785 | ||
2786 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, | |
2787 | 0, 0); | |
2788 | } | |
2789 | ||
2790 | static int dsi_vc_write_nosync_common(struct platform_device *dsidev, | |
2791 | int channel, u8 *data, int len, enum dss_dsi_content_type type) | |
2792 | { | |
2793 | int r; | |
2794 | ||
2795 | if (len == 0) { | |
2796 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
2797 | r = dsi_vc_send_short(dsidev, channel, | |
2798 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); | |
2799 | } else if (len == 1) { | |
2800 | r = dsi_vc_send_short(dsidev, channel, | |
2801 | type == DSS_DSI_CONTENT_GENERIC ? | |
2802 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
2803 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); | |
2804 | } else if (len == 2) { | |
2805 | r = dsi_vc_send_short(dsidev, channel, | |
2806 | type == DSS_DSI_CONTENT_GENERIC ? | |
2807 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
2808 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, | |
2809 | data[0] | (data[1] << 8), 0); | |
2810 | } else { | |
2811 | r = dsi_vc_send_long(dsidev, channel, | |
2812 | type == DSS_DSI_CONTENT_GENERIC ? | |
2813 | MIPI_DSI_GENERIC_LONG_WRITE : | |
2814 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
2815 | } | |
2816 | ||
2817 | return r; | |
2818 | } | |
2819 | ||
2820 | static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, | |
2821 | u8 *data, int len) | |
2822 | { | |
2823 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2824 | ||
2825 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, | |
2826 | DSS_DSI_CONTENT_DCS); | |
2827 | } | |
2828 | ||
2829 | static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, | |
2830 | u8 *data, int len) | |
2831 | { | |
2832 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2833 | ||
2834 | return dsi_vc_write_nosync_common(dsidev, channel, data, len, | |
2835 | DSS_DSI_CONTENT_GENERIC); | |
2836 | } | |
2837 | ||
2838 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, | |
2839 | u8 *data, int len, enum dss_dsi_content_type type) | |
2840 | { | |
2841 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
2842 | int r; | |
2843 | ||
2844 | r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); | |
2845 | if (r) | |
2846 | goto err; | |
2847 | ||
2848 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
2849 | if (r) | |
2850 | goto err; | |
2851 | ||
2852 | /* RX_FIFO_NOT_EMPTY */ | |
2853 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
2854 | DSSERR("rx fifo not empty after write, dumping data:\n"); | |
2855 | dsi_vc_flush_receive_data(dsidev, channel); | |
2856 | r = -EIO; | |
2857 | goto err; | |
2858 | } | |
2859 | ||
2860 | return 0; | |
2861 | err: | |
2862 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", | |
2863 | channel, data[0], len); | |
2864 | return r; | |
2865 | } | |
2866 | ||
2867 | static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
2868 | int len) | |
2869 | { | |
2870 | return dsi_vc_write_common(dssdev, channel, data, len, | |
2871 | DSS_DSI_CONTENT_DCS); | |
2872 | } | |
2873 | ||
2874 | static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
2875 | int len) | |
2876 | { | |
2877 | return dsi_vc_write_common(dssdev, channel, data, len, | |
2878 | DSS_DSI_CONTENT_GENERIC); | |
2879 | } | |
2880 | ||
2881 | static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, | |
2882 | int channel, u8 dcs_cmd) | |
2883 | { | |
2884 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2885 | int r; | |
2886 | ||
2887 | if (dsi->debug_read) | |
2888 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", | |
2889 | channel, dcs_cmd); | |
2890 | ||
2891 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); | |
2892 | if (r) { | |
2893 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
2894 | " failed\n", channel, dcs_cmd); | |
2895 | return r; | |
2896 | } | |
2897 | ||
2898 | return 0; | |
2899 | } | |
2900 | ||
2901 | static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, | |
2902 | int channel, u8 *reqdata, int reqlen) | |
2903 | { | |
2904 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2905 | u16 data; | |
2906 | u8 data_type; | |
2907 | int r; | |
2908 | ||
2909 | if (dsi->debug_read) | |
2910 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
2911 | channel, reqlen); | |
2912 | ||
2913 | if (reqlen == 0) { | |
2914 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
2915 | data = 0; | |
2916 | } else if (reqlen == 1) { | |
2917 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
2918 | data = reqdata[0]; | |
2919 | } else if (reqlen == 2) { | |
2920 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
2921 | data = reqdata[0] | (reqdata[1] << 8); | |
2922 | } else { | |
2923 | BUG(); | |
2924 | return -EINVAL; | |
2925 | } | |
2926 | ||
2927 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); | |
2928 | if (r) { | |
2929 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
2930 | " failed\n", channel, reqlen); | |
2931 | return r; | |
2932 | } | |
2933 | ||
2934 | return 0; | |
2935 | } | |
2936 | ||
2937 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, | |
2938 | u8 *buf, int buflen, enum dss_dsi_content_type type) | |
2939 | { | |
2940 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2941 | u32 val; | |
2942 | u8 dt; | |
2943 | int r; | |
2944 | ||
2945 | /* RX_FIFO_NOT_EMPTY */ | |
2946 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { | |
2947 | DSSERR("RX fifo empty when trying to read.\n"); | |
2948 | r = -EIO; | |
2949 | goto err; | |
2950 | } | |
2951 | ||
2952 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2953 | if (dsi->debug_read) | |
2954 | DSSDBG("\theader: %08x\n", val); | |
2955 | dt = FLD_GET(val, 5, 0); | |
2956 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { | |
2957 | u16 err = FLD_GET(val, 23, 8); | |
2958 | dsi_show_rx_ack_with_err(err); | |
2959 | r = -EIO; | |
2960 | goto err; | |
2961 | ||
2962 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? | |
2963 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
2964 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
2965 | u8 data = FLD_GET(val, 15, 8); | |
2966 | if (dsi->debug_read) | |
2967 | DSSDBG("\t%s short response, 1 byte: %02x\n", | |
2968 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
2969 | "DCS", data); | |
2970 | ||
2971 | if (buflen < 1) { | |
2972 | r = -EIO; | |
2973 | goto err; | |
2974 | } | |
2975 | ||
2976 | buf[0] = data; | |
2977 | ||
2978 | return 1; | |
2979 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? | |
2980 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
2981 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
2982 | u16 data = FLD_GET(val, 23, 8); | |
2983 | if (dsi->debug_read) | |
2984 | DSSDBG("\t%s short response, 2 byte: %04x\n", | |
2985 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
2986 | "DCS", data); | |
2987 | ||
2988 | if (buflen < 2) { | |
2989 | r = -EIO; | |
2990 | goto err; | |
2991 | } | |
2992 | ||
2993 | buf[0] = data & 0xff; | |
2994 | buf[1] = (data >> 8) & 0xff; | |
2995 | ||
2996 | return 2; | |
2997 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? | |
2998 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
2999 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3000 | int w; | |
3001 | int len = FLD_GET(val, 23, 8); | |
3002 | if (dsi->debug_read) | |
3003 | DSSDBG("\t%s long response, len %d\n", | |
3004 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3005 | "DCS", len); | |
3006 | ||
3007 | if (len > buflen) { | |
3008 | r = -EIO; | |
3009 | goto err; | |
3010 | } | |
3011 | ||
3012 | /* two byte checksum ends the packet, not included in len */ | |
3013 | for (w = 0; w < len + 2;) { | |
3014 | int b; | |
3015 | val = dsi_read_reg(dsidev, | |
3016 | DSI_VC_SHORT_PACKET_HEADER(channel)); | |
3017 | if (dsi->debug_read) | |
3018 | DSSDBG("\t\t%02x %02x %02x %02x\n", | |
3019 | (val >> 0) & 0xff, | |
3020 | (val >> 8) & 0xff, | |
3021 | (val >> 16) & 0xff, | |
3022 | (val >> 24) & 0xff); | |
3023 | ||
3024 | for (b = 0; b < 4; ++b) { | |
3025 | if (w < len) | |
3026 | buf[w] = (val >> (b * 8)) & 0xff; | |
3027 | /* we discard the 2 byte checksum */ | |
3028 | ++w; | |
3029 | } | |
3030 | } | |
3031 | ||
3032 | return len; | |
3033 | } else { | |
3034 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
3035 | r = -EIO; | |
3036 | goto err; | |
3037 | } | |
3038 | ||
3039 | err: | |
3040 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, | |
3041 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
3042 | ||
3043 | return r; | |
3044 | } | |
3045 | ||
3046 | static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | |
3047 | u8 *buf, int buflen) | |
3048 | { | |
3049 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3050 | int r; | |
3051 | ||
3052 | r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); | |
3053 | if (r) | |
3054 | goto err; | |
3055 | ||
3056 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3057 | if (r) | |
3058 | goto err; | |
3059 | ||
3060 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3061 | DSS_DSI_CONTENT_DCS); | |
3062 | if (r < 0) | |
3063 | goto err; | |
3064 | ||
3065 | if (r != buflen) { | |
3066 | r = -EIO; | |
3067 | goto err; | |
3068 | } | |
3069 | ||
3070 | return 0; | |
3071 | err: | |
3072 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3073 | return r; | |
3074 | } | |
3075 | ||
3076 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, | |
3077 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3078 | { | |
3079 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3080 | int r; | |
3081 | ||
3082 | r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); | |
3083 | if (r) | |
3084 | return r; | |
3085 | ||
3086 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3087 | if (r) | |
3088 | return r; | |
3089 | ||
3090 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3091 | DSS_DSI_CONTENT_GENERIC); | |
3092 | if (r < 0) | |
3093 | return r; | |
3094 | ||
3095 | if (r != buflen) { | |
3096 | r = -EIO; | |
3097 | return r; | |
3098 | } | |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | ||
3103 | static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, | |
3104 | u16 len) | |
3105 | { | |
3106 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3107 | ||
3108 | return dsi_vc_send_short(dsidev, channel, | |
3109 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); | |
3110 | } | |
3111 | ||
3112 | static int dsi_enter_ulps(struct platform_device *dsidev) | |
3113 | { | |
3114 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3115 | DECLARE_COMPLETION_ONSTACK(completion); | |
3116 | int r, i; | |
3117 | unsigned mask; | |
3118 | ||
3119 | DSSDBG("Entering ULPS"); | |
3120 | ||
3121 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
3122 | ||
3123 | WARN_ON(dsi->ulps_enabled); | |
3124 | ||
3125 | if (dsi->ulps_enabled) | |
3126 | return 0; | |
3127 | ||
3128 | /* DDR_CLK_ALWAYS_ON */ | |
3129 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { | |
3130 | dsi_if_enable(dsidev, 0); | |
3131 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
3132 | dsi_if_enable(dsidev, 1); | |
3133 | } | |
3134 | ||
3135 | dsi_sync_vc(dsidev, 0); | |
3136 | dsi_sync_vc(dsidev, 1); | |
3137 | dsi_sync_vc(dsidev, 2); | |
3138 | dsi_sync_vc(dsidev, 3); | |
3139 | ||
3140 | dsi_force_tx_stop_mode_io(dsidev); | |
3141 | ||
3142 | dsi_vc_enable(dsidev, 0, false); | |
3143 | dsi_vc_enable(dsidev, 1, false); | |
3144 | dsi_vc_enable(dsidev, 2, false); | |
3145 | dsi_vc_enable(dsidev, 3, false); | |
3146 | ||
3147 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ | |
3148 | DSSERR("HS busy when enabling ULPS\n"); | |
3149 | return -EIO; | |
3150 | } | |
3151 | ||
3152 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ | |
3153 | DSSERR("LP busy when enabling ULPS\n"); | |
3154 | return -EIO; | |
3155 | } | |
3156 | ||
3157 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, | |
3158 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); | |
3159 | if (r) | |
3160 | return r; | |
3161 | ||
3162 | mask = 0; | |
3163 | ||
3164 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
3165 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
3166 | continue; | |
3167 | mask |= 1 << i; | |
3168 | } | |
3169 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ | |
3170 | /* LANEx_ULPS_SIG2 */ | |
3171 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); | |
3172 | ||
3173 | /* flush posted write and wait for SCP interface to finish the write */ | |
3174 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
3175 | ||
3176 | if (wait_for_completion_timeout(&completion, | |
3177 | msecs_to_jiffies(1000)) == 0) { | |
3178 | DSSERR("ULPS enable timeout\n"); | |
3179 | r = -EIO; | |
3180 | goto err; | |
3181 | } | |
3182 | ||
3183 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, | |
3184 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); | |
3185 | ||
3186 | /* Reset LANEx_ULPS_SIG2 */ | |
3187 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); | |
3188 | ||
3189 | /* flush posted write and wait for SCP interface to finish the write */ | |
3190 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
3191 | ||
3192 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); | |
3193 | ||
3194 | dsi_if_enable(dsidev, false); | |
3195 | ||
3196 | dsi->ulps_enabled = true; | |
3197 | ||
3198 | return 0; | |
3199 | ||
3200 | err: | |
3201 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, | |
3202 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); | |
3203 | return r; | |
3204 | } | |
3205 | ||
3206 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, | |
3207 | unsigned ticks, bool x4, bool x16) | |
3208 | { | |
3209 | unsigned long fck; | |
3210 | unsigned long total_ticks; | |
3211 | u32 r; | |
3212 | ||
3213 | BUG_ON(ticks > 0x1fff); | |
3214 | ||
3215 | /* ticks in DSI_FCK */ | |
3216 | fck = dsi_fclk_rate(dsidev); | |
3217 | ||
3218 | r = dsi_read_reg(dsidev, DSI_TIMING2); | |
3219 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ | |
3220 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ | |
3221 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3222 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ | |
3223 | dsi_write_reg(dsidev, DSI_TIMING2, r); | |
3224 | ||
3225 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); | |
3226 | ||
3227 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3228 | total_ticks, | |
3229 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3230 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3231 | } | |
3232 | ||
3233 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, | |
3234 | bool x8, bool x16) | |
3235 | { | |
3236 | unsigned long fck; | |
3237 | unsigned long total_ticks; | |
3238 | u32 r; | |
3239 | ||
3240 | BUG_ON(ticks > 0x1fff); | |
3241 | ||
3242 | /* ticks in DSI_FCK */ | |
3243 | fck = dsi_fclk_rate(dsidev); | |
3244 | ||
3245 | r = dsi_read_reg(dsidev, DSI_TIMING1); | |
3246 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ | |
3247 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ | |
3248 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3249 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ | |
3250 | dsi_write_reg(dsidev, DSI_TIMING1, r); | |
3251 | ||
3252 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); | |
3253 | ||
3254 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3255 | total_ticks, | |
3256 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3257 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3258 | } | |
3259 | ||
3260 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, | |
3261 | unsigned ticks, bool x4, bool x16) | |
3262 | { | |
3263 | unsigned long fck; | |
3264 | unsigned long total_ticks; | |
3265 | u32 r; | |
3266 | ||
3267 | BUG_ON(ticks > 0x1fff); | |
3268 | ||
3269 | /* ticks in DSI_FCK */ | |
3270 | fck = dsi_fclk_rate(dsidev); | |
3271 | ||
3272 | r = dsi_read_reg(dsidev, DSI_TIMING1); | |
3273 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ | |
3274 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ | |
3275 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3276 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
3277 | dsi_write_reg(dsidev, DSI_TIMING1, r); | |
3278 | ||
3279 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); | |
3280 | ||
3281 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3282 | total_ticks, | |
3283 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3284 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3285 | } | |
3286 | ||
3287 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, | |
3288 | unsigned ticks, bool x4, bool x16) | |
3289 | { | |
3290 | unsigned long fck; | |
3291 | unsigned long total_ticks; | |
3292 | u32 r; | |
3293 | ||
3294 | BUG_ON(ticks > 0x1fff); | |
3295 | ||
3296 | /* ticks in TxByteClkHS */ | |
3297 | fck = dsi_get_txbyteclkhs(dsidev); | |
3298 | ||
3299 | r = dsi_read_reg(dsidev, DSI_TIMING2); | |
3300 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ | |
3301 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ | |
3302 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3303 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ | |
3304 | dsi_write_reg(dsidev, DSI_TIMING2, r); | |
3305 | ||
3306 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); | |
3307 | ||
3308 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3309 | total_ticks, | |
3310 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3311 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3312 | } | |
3313 | ||
3314 | static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) | |
3315 | { | |
3316 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3317 | int num_line_buffers; | |
3318 | ||
3319 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3320 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); | |
3321 | struct omap_video_timings *timings = &dsi->timings; | |
3322 | /* | |
3323 | * Don't use line buffers if width is greater than the video | |
3324 | * port's line buffer size | |
3325 | */ | |
3326 | if (dsi->line_buffer_size <= timings->x_res * bpp / 8) | |
3327 | num_line_buffers = 0; | |
3328 | else | |
3329 | num_line_buffers = 2; | |
3330 | } else { | |
3331 | /* Use maximum number of line buffers in command mode */ | |
3332 | num_line_buffers = 2; | |
3333 | } | |
3334 | ||
3335 | /* LINE_BUFFER */ | |
3336 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); | |
3337 | } | |
3338 | ||
3339 | static void dsi_config_vp_sync_events(struct platform_device *dsidev) | |
3340 | { | |
3341 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3342 | bool sync_end; | |
3343 | u32 r; | |
3344 | ||
3345 | if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) | |
3346 | sync_end = true; | |
3347 | else | |
3348 | sync_end = false; | |
3349 | ||
3350 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3351 | r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ | |
3352 | r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ | |
3353 | r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ | |
3354 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ | |
3355 | r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ | |
3356 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ | |
3357 | r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ | |
3358 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3359 | } | |
3360 | ||
3361 | static void dsi_config_blanking_modes(struct platform_device *dsidev) | |
3362 | { | |
3363 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3364 | int blanking_mode = dsi->vm_timings.blanking_mode; | |
3365 | int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; | |
3366 | int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; | |
3367 | int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; | |
3368 | u32 r; | |
3369 | ||
3370 | /* | |
3371 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods | |
3372 | * 1 = Long blanking packets are sent in corresponding blanking periods | |
3373 | */ | |
3374 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3375 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ | |
3376 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ | |
3377 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ | |
3378 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ | |
3379 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3380 | } | |
3381 | ||
3382 | /* | |
3383 | * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 | |
3384 | * results in maximum transition time for data and clock lanes to enter and | |
3385 | * exit HS mode. Hence, this is the scenario where the least amount of command | |
3386 | * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS | |
3387 | * clock cycles that can be used to interleave command mode data in HS so that | |
3388 | * all scenarios are satisfied. | |
3389 | */ | |
3390 | static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, | |
3391 | int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) | |
3392 | { | |
3393 | int transition; | |
3394 | ||
3395 | /* | |
3396 | * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition | |
3397 | * time of data lanes only, if it isn't set, we need to consider HS | |
3398 | * transition time of both data and clock lanes. HS transition time | |
3399 | * of Scenario 3 is considered. | |
3400 | */ | |
3401 | if (ddr_alwon) { | |
3402 | transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3403 | } else { | |
3404 | int trans1, trans2; | |
3405 | trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3406 | trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + | |
3407 | enter_hs + 1; | |
3408 | transition = max(trans1, trans2); | |
3409 | } | |
3410 | ||
3411 | return blank > transition ? blank - transition : 0; | |
3412 | } | |
3413 | ||
3414 | /* | |
3415 | * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 | |
3416 | * results in maximum transition time for data lanes to enter and exit LP mode. | |
3417 | * Hence, this is the scenario where the least amount of command mode data can | |
3418 | * be interleaved. We program the minimum amount of bytes that can be | |
3419 | * interleaved in LP so that all scenarios are satisfied. | |
3420 | */ | |
3421 | static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, | |
3422 | int lp_clk_div, int tdsi_fclk) | |
3423 | { | |
3424 | int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ | |
3425 | int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ | |
3426 | int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ | |
3427 | int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ | |
3428 | int lp_inter; /* cmd mode data that can be interleaved, in bytes */ | |
3429 | ||
3430 | /* maximum LP transition time according to Scenario 1 */ | |
3431 | trans_lp = exit_hs + max(enter_hs, 2) + 1; | |
3432 | ||
3433 | /* CLKIN4DDR = 16 * TXBYTECLKHS */ | |
3434 | tlp_avail = thsbyte_clk * (blank - trans_lp); | |
3435 | ||
3436 | ttxclkesc = tdsi_fclk * lp_clk_div; | |
3437 | ||
3438 | lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - | |
3439 | 26) / 16; | |
3440 | ||
3441 | return max(lp_inter, 0); | |
3442 | } | |
3443 | ||
3444 | static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) | |
3445 | { | |
3446 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3447 | int blanking_mode; | |
3448 | int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; | |
3449 | int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; | |
3450 | int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; | |
3451 | int tclk_trail, ths_exit, exiths_clk; | |
3452 | bool ddr_alwon; | |
3453 | struct omap_video_timings *timings = &dsi->timings; | |
3454 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); | |
3455 | int ndl = dsi->num_lanes_used - 1; | |
3456 | int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; | |
3457 | int hsa_interleave_hs = 0, hsa_interleave_lp = 0; | |
3458 | int hfp_interleave_hs = 0, hfp_interleave_lp = 0; | |
3459 | int hbp_interleave_hs = 0, hbp_interleave_lp = 0; | |
3460 | int bl_interleave_hs = 0, bl_interleave_lp = 0; | |
3461 | u32 r; | |
3462 | ||
3463 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3464 | blanking_mode = FLD_GET(r, 20, 20); | |
3465 | hfp_blanking_mode = FLD_GET(r, 21, 21); | |
3466 | hbp_blanking_mode = FLD_GET(r, 22, 22); | |
3467 | hsa_blanking_mode = FLD_GET(r, 23, 23); | |
3468 | ||
3469 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
3470 | hbp = FLD_GET(r, 11, 0); | |
3471 | hfp = FLD_GET(r, 23, 12); | |
3472 | hsa = FLD_GET(r, 31, 24); | |
3473 | ||
3474 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); | |
3475 | ddr_clk_post = FLD_GET(r, 7, 0); | |
3476 | ddr_clk_pre = FLD_GET(r, 15, 8); | |
3477 | ||
3478 | r = dsi_read_reg(dsidev, DSI_VM_TIMING7); | |
3479 | exit_hs_mode_lat = FLD_GET(r, 15, 0); | |
3480 | enter_hs_mode_lat = FLD_GET(r, 31, 16); | |
3481 | ||
3482 | r = dsi_read_reg(dsidev, DSI_CLK_CTRL); | |
3483 | lp_clk_div = FLD_GET(r, 12, 0); | |
3484 | ddr_alwon = FLD_GET(r, 13, 13); | |
3485 | ||
3486 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); | |
3487 | ths_exit = FLD_GET(r, 7, 0); | |
3488 | ||
3489 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); | |
3490 | tclk_trail = FLD_GET(r, 15, 8); | |
3491 | ||
3492 | exiths_clk = ths_exit + tclk_trail; | |
3493 | ||
3494 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
3495 | bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); | |
3496 | ||
3497 | if (!hsa_blanking_mode) { | |
3498 | hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, | |
3499 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3500 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3501 | hsa_interleave_lp = dsi_compute_interleave_lp(hsa, | |
3502 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3503 | lp_clk_div, dsi_fclk_hsdiv); | |
3504 | } | |
3505 | ||
3506 | if (!hfp_blanking_mode) { | |
3507 | hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, | |
3508 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3509 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3510 | hfp_interleave_lp = dsi_compute_interleave_lp(hfp, | |
3511 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3512 | lp_clk_div, dsi_fclk_hsdiv); | |
3513 | } | |
3514 | ||
3515 | if (!hbp_blanking_mode) { | |
3516 | hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, | |
3517 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3518 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3519 | ||
3520 | hbp_interleave_lp = dsi_compute_interleave_lp(hbp, | |
3521 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3522 | lp_clk_div, dsi_fclk_hsdiv); | |
3523 | } | |
3524 | ||
3525 | if (!blanking_mode) { | |
3526 | bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, | |
3527 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3528 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3529 | ||
3530 | bl_interleave_lp = dsi_compute_interleave_lp(bllp, | |
3531 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3532 | lp_clk_div, dsi_fclk_hsdiv); | |
3533 | } | |
3534 | ||
3535 | DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3536 | hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, | |
3537 | bl_interleave_hs); | |
3538 | ||
3539 | DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3540 | hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, | |
3541 | bl_interleave_lp); | |
3542 | ||
3543 | r = dsi_read_reg(dsidev, DSI_VM_TIMING4); | |
3544 | r = FLD_MOD(r, hsa_interleave_hs, 23, 16); | |
3545 | r = FLD_MOD(r, hfp_interleave_hs, 15, 8); | |
3546 | r = FLD_MOD(r, hbp_interleave_hs, 7, 0); | |
3547 | dsi_write_reg(dsidev, DSI_VM_TIMING4, r); | |
3548 | ||
3549 | r = dsi_read_reg(dsidev, DSI_VM_TIMING5); | |
3550 | r = FLD_MOD(r, hsa_interleave_lp, 23, 16); | |
3551 | r = FLD_MOD(r, hfp_interleave_lp, 15, 8); | |
3552 | r = FLD_MOD(r, hbp_interleave_lp, 7, 0); | |
3553 | dsi_write_reg(dsidev, DSI_VM_TIMING5, r); | |
3554 | ||
3555 | r = dsi_read_reg(dsidev, DSI_VM_TIMING6); | |
3556 | r = FLD_MOD(r, bl_interleave_hs, 31, 15); | |
3557 | r = FLD_MOD(r, bl_interleave_lp, 16, 0); | |
3558 | dsi_write_reg(dsidev, DSI_VM_TIMING6, r); | |
3559 | } | |
3560 | ||
3561 | static int dsi_proto_config(struct platform_device *dsidev) | |
3562 | { | |
3563 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3564 | u32 r; | |
3565 | int buswidth = 0; | |
3566 | ||
3567 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, | |
3568 | DSI_FIFO_SIZE_32, | |
3569 | DSI_FIFO_SIZE_32, | |
3570 | DSI_FIFO_SIZE_32); | |
3571 | ||
3572 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, | |
3573 | DSI_FIFO_SIZE_32, | |
3574 | DSI_FIFO_SIZE_32, | |
3575 | DSI_FIFO_SIZE_32); | |
3576 | ||
3577 | /* XXX what values for the timeouts? */ | |
3578 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); | |
3579 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); | |
3580 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); | |
3581 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); | |
3582 | ||
3583 | switch (dsi_get_pixel_size(dsi->pix_fmt)) { | |
3584 | case 16: | |
3585 | buswidth = 0; | |
3586 | break; | |
3587 | case 18: | |
3588 | buswidth = 1; | |
3589 | break; | |
3590 | case 24: | |
3591 | buswidth = 2; | |
3592 | break; | |
3593 | default: | |
3594 | BUG(); | |
3595 | return -EINVAL; | |
3596 | } | |
3597 | ||
3598 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3599 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ | |
3600 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3601 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3602 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3603 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3604 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3605 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ | |
3606 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
3607 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { | |
3608 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
3609 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3610 | r = FLD_MOD(r, 0, 25, 25); | |
3611 | } | |
3612 | ||
3613 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3614 | ||
3615 | dsi_config_vp_num_line_buffers(dsidev); | |
3616 | ||
3617 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3618 | dsi_config_vp_sync_events(dsidev); | |
3619 | dsi_config_blanking_modes(dsidev); | |
3620 | dsi_config_cmd_mode_interleaving(dsidev); | |
3621 | } | |
3622 | ||
3623 | dsi_vc_initial_config(dsidev, 0); | |
3624 | dsi_vc_initial_config(dsidev, 1); | |
3625 | dsi_vc_initial_config(dsidev, 2); | |
3626 | dsi_vc_initial_config(dsidev, 3); | |
3627 | ||
3628 | return 0; | |
3629 | } | |
3630 | ||
3631 | static void dsi_proto_timings(struct platform_device *dsidev) | |
3632 | { | |
3633 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
c96da175 | 3634 | unsigned tlpx, tclk_zero, tclk_prepare; |
f76ee892 TV |
3635 | unsigned tclk_pre, tclk_post; |
3636 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3637 | unsigned ths_trail, ths_exit; | |
3638 | unsigned ddr_clk_pre, ddr_clk_post; | |
3639 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
3640 | unsigned ths_eot; | |
3641 | int ndl = dsi->num_lanes_used - 1; | |
3642 | u32 r; | |
3643 | ||
3644 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); | |
3645 | ths_prepare = FLD_GET(r, 31, 24); | |
3646 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3647 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3648 | ths_trail = FLD_GET(r, 15, 8); | |
3649 | ths_exit = FLD_GET(r, 7, 0); | |
3650 | ||
3651 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); | |
3652 | tlpx = FLD_GET(r, 20, 16) * 2; | |
f76ee892 TV |
3653 | tclk_zero = FLD_GET(r, 7, 0); |
3654 | ||
3655 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); | |
3656 | tclk_prepare = FLD_GET(r, 7, 0); | |
3657 | ||
3658 | /* min 8*UI */ | |
3659 | tclk_pre = 20; | |
3660 | /* min 60ns + 52*UI */ | |
3661 | tclk_post = ns2ddr(dsidev, 60) + 26; | |
3662 | ||
3663 | ths_eot = DIV_ROUND_UP(4, ndl); | |
3664 | ||
3665 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3666 | 4); | |
3667 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3668 | ||
3669 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3670 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3671 | ||
3672 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); | |
3673 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); | |
3674 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
3675 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); | |
3676 | ||
3677 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3678 | ddr_clk_pre, | |
3679 | ddr_clk_post); | |
3680 | ||
3681 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3682 | DIV_ROUND_UP(ths_prepare, 4) + | |
3683 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3684 | ||
3685 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3686 | ||
3687 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3688 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
3689 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); | |
3690 | ||
3691 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3692 | enter_hs_mode_lat, exit_hs_mode_lat); | |
3693 | ||
3694 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3695 | /* TODO: Implement a video mode check_timings function */ | |
3696 | int hsa = dsi->vm_timings.hsa; | |
3697 | int hfp = dsi->vm_timings.hfp; | |
3698 | int hbp = dsi->vm_timings.hbp; | |
3699 | int vsa = dsi->vm_timings.vsa; | |
3700 | int vfp = dsi->vm_timings.vfp; | |
3701 | int vbp = dsi->vm_timings.vbp; | |
3702 | int window_sync = dsi->vm_timings.window_sync; | |
3703 | bool hsync_end; | |
3704 | struct omap_video_timings *timings = &dsi->timings; | |
3705 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); | |
3706 | int tl, t_he, width_bytes; | |
3707 | ||
3708 | hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; | |
3709 | t_he = hsync_end ? | |
3710 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; | |
3711 | ||
3712 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
3713 | ||
3714 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ | |
3715 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + | |
3716 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; | |
3717 | ||
3718 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, | |
3719 | hfp, hsync_end ? hsa : 0, tl); | |
3720 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, | |
3721 | vsa, timings->y_res); | |
3722 | ||
3723 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
3724 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ | |
3725 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ | |
3726 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ | |
3727 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); | |
3728 | ||
3729 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); | |
3730 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ | |
3731 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ | |
3732 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ | |
3733 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ | |
3734 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); | |
3735 | ||
3736 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); | |
3737 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ | |
3738 | r = FLD_MOD(r, tl, 31, 16); /* TL */ | |
3739 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); | |
3740 | } | |
3741 | } | |
3742 | ||
3743 | static int dsi_configure_pins(struct omap_dss_device *dssdev, | |
3744 | const struct omap_dsi_pin_config *pin_cfg) | |
3745 | { | |
3746 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3747 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3748 | int num_pins; | |
3749 | const int *pins; | |
3750 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; | |
3751 | int num_lanes; | |
3752 | int i; | |
3753 | ||
3754 | static const enum dsi_lane_function functions[] = { | |
3755 | DSI_LANE_CLK, | |
3756 | DSI_LANE_DATA1, | |
3757 | DSI_LANE_DATA2, | |
3758 | DSI_LANE_DATA3, | |
3759 | DSI_LANE_DATA4, | |
3760 | }; | |
3761 | ||
3762 | num_pins = pin_cfg->num_pins; | |
3763 | pins = pin_cfg->pins; | |
3764 | ||
3765 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 | |
3766 | || num_pins % 2 != 0) | |
3767 | return -EINVAL; | |
3768 | ||
3769 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) | |
3770 | lanes[i].function = DSI_LANE_UNUSED; | |
3771 | ||
3772 | num_lanes = 0; | |
3773 | ||
3774 | for (i = 0; i < num_pins; i += 2) { | |
3775 | u8 lane, pol; | |
3776 | int dx, dy; | |
3777 | ||
3778 | dx = pins[i]; | |
3779 | dy = pins[i + 1]; | |
3780 | ||
3781 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) | |
3782 | return -EINVAL; | |
3783 | ||
3784 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) | |
3785 | return -EINVAL; | |
3786 | ||
3787 | if (dx & 1) { | |
3788 | if (dy != dx - 1) | |
3789 | return -EINVAL; | |
3790 | pol = 1; | |
3791 | } else { | |
3792 | if (dy != dx + 1) | |
3793 | return -EINVAL; | |
3794 | pol = 0; | |
3795 | } | |
3796 | ||
3797 | lane = dx / 2; | |
3798 | ||
3799 | lanes[lane].function = functions[i / 2]; | |
3800 | lanes[lane].polarity = pol; | |
3801 | num_lanes++; | |
3802 | } | |
3803 | ||
3804 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); | |
3805 | dsi->num_lanes_used = num_lanes; | |
3806 | ||
3807 | return 0; | |
3808 | } | |
3809 | ||
3810 | static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) | |
3811 | { | |
3812 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3813 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3814 | struct omap_overlay_manager *mgr = dsi->output.manager; | |
3815 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); | |
3816 | struct omap_dss_device *out = &dsi->output; | |
3817 | u8 data_type; | |
3818 | u16 word_count; | |
3819 | int r; | |
3820 | ||
3821 | if (out->manager == NULL) { | |
3822 | DSSERR("failed to enable display: no output/manager\n"); | |
3823 | return -ENODEV; | |
3824 | } | |
3825 | ||
3826 | r = dsi_display_init_dispc(dsidev, mgr); | |
3827 | if (r) | |
3828 | goto err_init_dispc; | |
3829 | ||
3830 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3831 | switch (dsi->pix_fmt) { | |
3832 | case OMAP_DSS_DSI_FMT_RGB888: | |
3833 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
3834 | break; | |
3835 | case OMAP_DSS_DSI_FMT_RGB666: | |
3836 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
3837 | break; | |
3838 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
3839 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
3840 | break; | |
3841 | case OMAP_DSS_DSI_FMT_RGB565: | |
3842 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
3843 | break; | |
3844 | default: | |
3845 | r = -EINVAL; | |
3846 | goto err_pix_fmt; | |
3847 | } | |
3848 | ||
3849 | dsi_if_enable(dsidev, false); | |
3850 | dsi_vc_enable(dsidev, channel, false); | |
3851 | ||
3852 | /* MODE, 1 = video mode */ | |
3853 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); | |
3854 | ||
3855 | word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); | |
3856 | ||
3857 | dsi_vc_write_long_header(dsidev, channel, data_type, | |
3858 | word_count, 0); | |
3859 | ||
3860 | dsi_vc_enable(dsidev, channel, true); | |
3861 | dsi_if_enable(dsidev, true); | |
3862 | } | |
3863 | ||
3864 | r = dss_mgr_enable(mgr); | |
3865 | if (r) | |
3866 | goto err_mgr_enable; | |
3867 | ||
3868 | return 0; | |
3869 | ||
3870 | err_mgr_enable: | |
3871 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3872 | dsi_if_enable(dsidev, false); | |
3873 | dsi_vc_enable(dsidev, channel, false); | |
3874 | } | |
3875 | err_pix_fmt: | |
3876 | dsi_display_uninit_dispc(dsidev, mgr); | |
3877 | err_init_dispc: | |
3878 | return r; | |
3879 | } | |
3880 | ||
3881 | static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) | |
3882 | { | |
3883 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3884 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3885 | struct omap_overlay_manager *mgr = dsi->output.manager; | |
3886 | ||
3887 | if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3888 | dsi_if_enable(dsidev, false); | |
3889 | dsi_vc_enable(dsidev, channel, false); | |
3890 | ||
3891 | /* MODE, 0 = command mode */ | |
3892 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); | |
3893 | ||
3894 | dsi_vc_enable(dsidev, channel, true); | |
3895 | dsi_if_enable(dsidev, true); | |
3896 | } | |
3897 | ||
3898 | dss_mgr_disable(mgr); | |
3899 | ||
3900 | dsi_display_uninit_dispc(dsidev, mgr); | |
3901 | } | |
3902 | ||
3903 | static void dsi_update_screen_dispc(struct platform_device *dsidev) | |
3904 | { | |
3905 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3906 | struct omap_overlay_manager *mgr = dsi->output.manager; | |
3907 | unsigned bytespp; | |
3908 | unsigned bytespl; | |
3909 | unsigned bytespf; | |
3910 | unsigned total_len; | |
3911 | unsigned packet_payload; | |
3912 | unsigned packet_len; | |
3913 | u32 l; | |
3914 | int r; | |
3915 | const unsigned channel = dsi->update_channel; | |
3916 | const unsigned line_buf_size = dsi->line_buffer_size; | |
3917 | u16 w = dsi->timings.x_res; | |
3918 | u16 h = dsi->timings.y_res; | |
3919 | ||
3920 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); | |
3921 | ||
3922 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); | |
3923 | ||
3924 | bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; | |
3925 | bytespl = w * bytespp; | |
3926 | bytespf = bytespl * h; | |
3927 | ||
3928 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
3929 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
3930 | ||
3931 | if (bytespf < line_buf_size) | |
3932 | packet_payload = bytespf; | |
3933 | else | |
3934 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
3935 | ||
3936 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
3937 | total_len = (bytespf / packet_payload) * packet_len; | |
3938 | ||
3939 | if (bytespf % packet_payload) | |
3940 | total_len += (bytespf % packet_payload) + 1; | |
3941 | ||
3942 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ | |
3943 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); | |
3944 | ||
3945 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, | |
3946 | packet_len, 0); | |
3947 | ||
3948 | if (dsi->te_enabled) | |
3949 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ | |
3950 | else | |
3951 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
3952 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); | |
3953 | ||
3954 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
3955 | * because DSS interrupts are not capable of waking up the CPU and the | |
3956 | * framedone interrupt could be delayed for quite a long time. I think | |
3957 | * the same goes for any DSS interrupts, but for some reason I have not | |
3958 | * seen the problem anywhere else than here. | |
3959 | */ | |
3960 | dispc_disable_sidle(); | |
3961 | ||
3962 | dsi_perf_mark_start(dsidev); | |
3963 | ||
3964 | r = schedule_delayed_work(&dsi->framedone_timeout_work, | |
3965 | msecs_to_jiffies(250)); | |
3966 | BUG_ON(r == 0); | |
3967 | ||
3968 | dss_mgr_set_timings(mgr, &dsi->timings); | |
3969 | ||
3970 | dss_mgr_start_update(mgr); | |
3971 | ||
3972 | if (dsi->te_enabled) { | |
3973 | /* disable LP_RX_TO, so that we can receive TE. Time to wait | |
3974 | * for TE is longer than the timer allows */ | |
3975 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ | |
3976 | ||
3977 | dsi_vc_send_bta(dsidev, channel); | |
3978 | ||
3979 | #ifdef DSI_CATCH_MISSING_TE | |
3980 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); | |
3981 | #endif | |
3982 | } | |
3983 | } | |
3984 | ||
3985 | #ifdef DSI_CATCH_MISSING_TE | |
6c789357 | 3986 | static void dsi_te_timeout(struct timer_list *unused) |
f76ee892 TV |
3987 | { |
3988 | DSSERR("TE not received for 250ms!\n"); | |
3989 | } | |
3990 | #endif | |
3991 | ||
3992 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) | |
3993 | { | |
3994 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3995 | ||
3996 | /* SIDLEMODE back to smart-idle */ | |
3997 | dispc_enable_sidle(); | |
3998 | ||
3999 | if (dsi->te_enabled) { | |
4000 | /* enable LP_RX_TO again after the TE */ | |
4001 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ | |
4002 | } | |
4003 | ||
4004 | dsi->framedone_callback(error, dsi->framedone_data); | |
4005 | ||
4006 | if (!error) | |
4007 | dsi_perf_show(dsidev, "DISPC"); | |
4008 | } | |
4009 | ||
4010 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) | |
4011 | { | |
4012 | struct dsi_data *dsi = container_of(work, struct dsi_data, | |
4013 | framedone_timeout_work.work); | |
4014 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after | |
4015 | * 250ms which would conflict with this timeout work. What should be | |
4016 | * done is first cancel the transfer on the HW, and then cancel the | |
4017 | * possibly scheduled framedone work. However, cancelling the transfer | |
4018 | * on the HW is buggy, and would probably require resetting the whole | |
4019 | * DSI */ | |
4020 | ||
4021 | DSSERR("Framedone not received for 250ms!\n"); | |
4022 | ||
4023 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); | |
4024 | } | |
4025 | ||
4026 | static void dsi_framedone_irq_callback(void *data) | |
4027 | { | |
4028 | struct platform_device *dsidev = (struct platform_device *) data; | |
4029 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4030 | ||
4031 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and | |
4032 | * turns itself off. However, DSI still has the pixels in its buffers, | |
4033 | * and is sending the data. | |
4034 | */ | |
4035 | ||
4036 | cancel_delayed_work(&dsi->framedone_timeout_work); | |
4037 | ||
4038 | dsi_handle_framedone(dsidev, 0); | |
4039 | } | |
4040 | ||
4041 | static int dsi_update(struct omap_dss_device *dssdev, int channel, | |
4042 | void (*callback)(int, void *), void *data) | |
4043 | { | |
4044 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4045 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
f76ee892 TV |
4046 | |
4047 | dsi_perf_mark_setup(dsidev); | |
4048 | ||
4049 | dsi->update_channel = channel; | |
4050 | ||
4051 | dsi->framedone_callback = callback; | |
4052 | dsi->framedone_data = data; | |
4053 | ||
f76ee892 | 4054 | #ifdef DSI_PERF_MEASURE |
c96da175 | 4055 | dsi->update_bytes = dsi->timings.x_res * dsi->timings.y_res * |
f76ee892 TV |
4056 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
4057 | #endif | |
4058 | dsi_update_screen_dispc(dsidev); | |
4059 | ||
4060 | return 0; | |
4061 | } | |
4062 | ||
4063 | /* Display funcs */ | |
4064 | ||
4065 | static int dsi_configure_dispc_clocks(struct platform_device *dsidev) | |
4066 | { | |
4067 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4068 | struct dispc_clock_info dispc_cinfo; | |
4069 | int r; | |
4070 | unsigned long fck; | |
4071 | ||
4072 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
4073 | ||
4074 | dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; | |
4075 | dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; | |
4076 | ||
4077 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
4078 | if (r) { | |
4079 | DSSERR("Failed to calc dispc clocks\n"); | |
4080 | return r; | |
4081 | } | |
4082 | ||
4083 | dsi->mgr_config.clock_info = dispc_cinfo; | |
4084 | ||
4085 | return 0; | |
4086 | } | |
4087 | ||
4088 | static int dsi_display_init_dispc(struct platform_device *dsidev, | |
4089 | struct omap_overlay_manager *mgr) | |
4090 | { | |
4091 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4092 | int r; | |
4093 | ||
4094 | dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ? | |
4095 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | |
4096 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); | |
4097 | ||
4098 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { | |
4099 | r = dss_mgr_register_framedone_handler(mgr, | |
4100 | dsi_framedone_irq_callback, dsidev); | |
4101 | if (r) { | |
4102 | DSSERR("can't register FRAMEDONE handler\n"); | |
4103 | goto err; | |
4104 | } | |
4105 | ||
4106 | dsi->mgr_config.stallmode = true; | |
4107 | dsi->mgr_config.fifohandcheck = true; | |
4108 | } else { | |
4109 | dsi->mgr_config.stallmode = false; | |
4110 | dsi->mgr_config.fifohandcheck = false; | |
4111 | } | |
4112 | ||
4113 | /* | |
4114 | * override interlace, logic level and edge related parameters in | |
4115 | * omap_video_timings with default values | |
4116 | */ | |
4117 | dsi->timings.interlace = false; | |
4118 | dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4119 | dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4120 | dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | |
4121 | dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4122 | dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_FALLING_EDGE; | |
4123 | ||
4124 | dss_mgr_set_timings(mgr, &dsi->timings); | |
4125 | ||
4126 | r = dsi_configure_dispc_clocks(dsidev); | |
4127 | if (r) | |
4128 | goto err1; | |
4129 | ||
4130 | dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; | |
4131 | dsi->mgr_config.video_port_width = | |
4132 | dsi_get_pixel_size(dsi->pix_fmt); | |
4133 | dsi->mgr_config.lcden_sig_polarity = 0; | |
4134 | ||
4135 | dss_mgr_set_lcd_config(mgr, &dsi->mgr_config); | |
4136 | ||
4137 | return 0; | |
4138 | err1: | |
4139 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) | |
4140 | dss_mgr_unregister_framedone_handler(mgr, | |
4141 | dsi_framedone_irq_callback, dsidev); | |
4142 | err: | |
4143 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); | |
4144 | return r; | |
4145 | } | |
4146 | ||
4147 | static void dsi_display_uninit_dispc(struct platform_device *dsidev, | |
4148 | struct omap_overlay_manager *mgr) | |
4149 | { | |
4150 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4151 | ||
4152 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) | |
4153 | dss_mgr_unregister_framedone_handler(mgr, | |
4154 | dsi_framedone_irq_callback, dsidev); | |
4155 | ||
4156 | dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK); | |
4157 | } | |
4158 | ||
4159 | static int dsi_configure_dsi_clocks(struct platform_device *dsidev) | |
4160 | { | |
4161 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4162 | struct dss_pll_clock_info cinfo; | |
4163 | int r; | |
4164 | ||
4165 | cinfo = dsi->user_dsi_cinfo; | |
4166 | ||
4167 | r = dss_pll_set_config(&dsi->pll, &cinfo); | |
4168 | if (r) { | |
4169 | DSSERR("Failed to set dsi clocks\n"); | |
4170 | return r; | |
4171 | } | |
4172 | ||
4173 | return 0; | |
4174 | } | |
4175 | ||
4176 | static int dsi_display_init_dsi(struct platform_device *dsidev) | |
4177 | { | |
4178 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4179 | int r; | |
4180 | ||
4181 | r = dss_pll_enable(&dsi->pll); | |
4182 | if (r) | |
4183 | goto err0; | |
4184 | ||
4185 | r = dsi_configure_dsi_clocks(dsidev); | |
4186 | if (r) | |
4187 | goto err1; | |
4188 | ||
4189 | dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? | |
4190 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | |
4191 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); | |
4192 | ||
4193 | DSSDBG("PLL OK\n"); | |
4194 | ||
4195 | r = dsi_cio_init(dsidev); | |
4196 | if (r) | |
4197 | goto err2; | |
4198 | ||
4199 | _dsi_print_reset_status(dsidev); | |
4200 | ||
4201 | dsi_proto_timings(dsidev); | |
4202 | dsi_set_lp_clk_divisor(dsidev); | |
4203 | ||
4204 | if (1) | |
4205 | _dsi_print_reset_status(dsidev); | |
4206 | ||
4207 | r = dsi_proto_config(dsidev); | |
4208 | if (r) | |
4209 | goto err3; | |
4210 | ||
4211 | /* enable interface */ | |
4212 | dsi_vc_enable(dsidev, 0, 1); | |
4213 | dsi_vc_enable(dsidev, 1, 1); | |
4214 | dsi_vc_enable(dsidev, 2, 1); | |
4215 | dsi_vc_enable(dsidev, 3, 1); | |
4216 | dsi_if_enable(dsidev, 1); | |
4217 | dsi_force_tx_stop_mode_io(dsidev); | |
4218 | ||
4219 | return 0; | |
4220 | err3: | |
4221 | dsi_cio_uninit(dsidev); | |
4222 | err2: | |
4223 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); | |
4224 | err1: | |
4225 | dss_pll_disable(&dsi->pll); | |
4226 | err0: | |
4227 | return r; | |
4228 | } | |
4229 | ||
4230 | static void dsi_display_uninit_dsi(struct platform_device *dsidev, | |
4231 | bool disconnect_lanes, bool enter_ulps) | |
4232 | { | |
4233 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4234 | ||
4235 | if (enter_ulps && !dsi->ulps_enabled) | |
4236 | dsi_enter_ulps(dsidev); | |
4237 | ||
4238 | /* disable interface */ | |
4239 | dsi_if_enable(dsidev, 0); | |
4240 | dsi_vc_enable(dsidev, 0, 0); | |
4241 | dsi_vc_enable(dsidev, 1, 0); | |
4242 | dsi_vc_enable(dsidev, 2, 0); | |
4243 | dsi_vc_enable(dsidev, 3, 0); | |
4244 | ||
4245 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); | |
4246 | dsi_cio_uninit(dsidev); | |
4247 | dsi_pll_uninit(dsidev, disconnect_lanes); | |
4248 | } | |
4249 | ||
4250 | static int dsi_display_enable(struct omap_dss_device *dssdev) | |
4251 | { | |
4252 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4253 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4254 | int r = 0; | |
4255 | ||
4256 | DSSDBG("dsi_display_enable\n"); | |
4257 | ||
4258 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
4259 | ||
4260 | mutex_lock(&dsi->lock); | |
4261 | ||
4262 | r = dsi_runtime_get(dsidev); | |
4263 | if (r) | |
4264 | goto err_get_dsi; | |
4265 | ||
4266 | _dsi_initialize_irq(dsidev); | |
4267 | ||
4268 | r = dsi_display_init_dsi(dsidev); | |
4269 | if (r) | |
4270 | goto err_init_dsi; | |
4271 | ||
4272 | mutex_unlock(&dsi->lock); | |
4273 | ||
4274 | return 0; | |
4275 | ||
4276 | err_init_dsi: | |
4277 | dsi_runtime_put(dsidev); | |
4278 | err_get_dsi: | |
4279 | mutex_unlock(&dsi->lock); | |
4280 | DSSDBG("dsi_display_enable FAILED\n"); | |
4281 | return r; | |
4282 | } | |
4283 | ||
4284 | static void dsi_display_disable(struct omap_dss_device *dssdev, | |
4285 | bool disconnect_lanes, bool enter_ulps) | |
4286 | { | |
4287 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4288 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4289 | ||
4290 | DSSDBG("dsi_display_disable\n"); | |
4291 | ||
4292 | WARN_ON(!dsi_bus_is_locked(dsidev)); | |
4293 | ||
4294 | mutex_lock(&dsi->lock); | |
4295 | ||
4296 | dsi_sync_vc(dsidev, 0); | |
4297 | dsi_sync_vc(dsidev, 1); | |
4298 | dsi_sync_vc(dsidev, 2); | |
4299 | dsi_sync_vc(dsidev, 3); | |
4300 | ||
4301 | dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); | |
4302 | ||
4303 | dsi_runtime_put(dsidev); | |
4304 | ||
4305 | mutex_unlock(&dsi->lock); | |
4306 | } | |
4307 | ||
4308 | static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) | |
4309 | { | |
4310 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4311 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4312 | ||
4313 | dsi->te_enabled = enable; | |
4314 | return 0; | |
4315 | } | |
4316 | ||
4317 | #ifdef PRINT_VERBOSE_VM_TIMINGS | |
4318 | static void print_dsi_vm(const char *str, | |
4319 | const struct omap_dss_dsi_videomode_timings *t) | |
4320 | { | |
4321 | unsigned long byteclk = t->hsclk / 4; | |
4322 | int bl, wc, pps, tot; | |
4323 | ||
4324 | wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); | |
4325 | pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ | |
4326 | bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; | |
4327 | tot = bl + pps; | |
4328 | ||
4329 | #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) | |
4330 | ||
4331 | pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " | |
4332 | "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", | |
4333 | str, | |
4334 | byteclk, | |
4335 | t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, | |
4336 | bl, pps, tot, | |
4337 | TO_DSI_T(t->hss), | |
4338 | TO_DSI_T(t->hsa), | |
4339 | TO_DSI_T(t->hse), | |
4340 | TO_DSI_T(t->hbp), | |
4341 | TO_DSI_T(pps), | |
4342 | TO_DSI_T(t->hfp), | |
4343 | ||
4344 | TO_DSI_T(bl), | |
4345 | TO_DSI_T(pps), | |
4346 | ||
4347 | TO_DSI_T(tot)); | |
4348 | #undef TO_DSI_T | |
4349 | } | |
4350 | ||
4351 | static void print_dispc_vm(const char *str, const struct omap_video_timings *t) | |
4352 | { | |
4353 | unsigned long pck = t->pixelclock; | |
4354 | int hact, bl, tot; | |
4355 | ||
4356 | hact = t->x_res; | |
4357 | bl = t->hsw + t->hbp + t->hfp; | |
4358 | tot = hact + bl; | |
4359 | ||
4360 | #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) | |
4361 | ||
4362 | pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " | |
4363 | "%u/%u/%u/%u = %u + %u = %u\n", | |
4364 | str, | |
4365 | pck, | |
4366 | t->hsw, t->hbp, hact, t->hfp, | |
4367 | bl, hact, tot, | |
4368 | TO_DISPC_T(t->hsw), | |
4369 | TO_DISPC_T(t->hbp), | |
4370 | TO_DISPC_T(hact), | |
4371 | TO_DISPC_T(t->hfp), | |
4372 | TO_DISPC_T(bl), | |
4373 | TO_DISPC_T(hact), | |
4374 | TO_DISPC_T(tot)); | |
4375 | #undef TO_DISPC_T | |
4376 | } | |
4377 | ||
4378 | /* note: this is not quite accurate */ | |
4379 | static void print_dsi_dispc_vm(const char *str, | |
4380 | const struct omap_dss_dsi_videomode_timings *t) | |
4381 | { | |
4382 | struct omap_video_timings vm = { 0 }; | |
4383 | unsigned long byteclk = t->hsclk / 4; | |
4384 | unsigned long pck; | |
4385 | u64 dsi_tput; | |
4386 | int dsi_hact, dsi_htot; | |
4387 | ||
4388 | dsi_tput = (u64)byteclk * t->ndl * 8; | |
4389 | pck = (u32)div64_u64(dsi_tput, t->bitspp); | |
4390 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); | |
4391 | dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; | |
4392 | ||
4393 | vm.pixelclock = pck; | |
4394 | vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); | |
4395 | vm.hbp = div64_u64((u64)t->hbp * pck, byteclk); | |
4396 | vm.hfp = div64_u64((u64)t->hfp * pck, byteclk); | |
4397 | vm.x_res = t->hact; | |
4398 | ||
4399 | print_dispc_vm(str, &vm); | |
4400 | } | |
4401 | #endif /* PRINT_VERBOSE_VM_TIMINGS */ | |
4402 | ||
4403 | static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
4404 | unsigned long pck, void *data) | |
4405 | { | |
4406 | struct dsi_clk_calc_ctx *ctx = data; | |
4407 | struct omap_video_timings *t = &ctx->dispc_vm; | |
4408 | ||
4409 | ctx->dispc_cinfo.lck_div = lckd; | |
4410 | ctx->dispc_cinfo.pck_div = pckd; | |
4411 | ctx->dispc_cinfo.lck = lck; | |
4412 | ctx->dispc_cinfo.pck = pck; | |
4413 | ||
4414 | *t = *ctx->config->timings; | |
4415 | t->pixelclock = pck; | |
4416 | t->x_res = ctx->config->timings->x_res; | |
4417 | t->y_res = ctx->config->timings->y_res; | |
4418 | t->hsw = t->hfp = t->hbp = t->vsw = 1; | |
4419 | t->vfp = t->vbp = 0; | |
4420 | ||
4421 | return true; | |
4422 | } | |
4423 | ||
4424 | static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, | |
4425 | void *data) | |
4426 | { | |
4427 | struct dsi_clk_calc_ctx *ctx = data; | |
4428 | ||
4429 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; | |
4430 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; | |
4431 | ||
4432 | return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, | |
4433 | dsi_cm_calc_dispc_cb, ctx); | |
4434 | } | |
4435 | ||
4436 | static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, | |
4437 | unsigned long clkdco, void *data) | |
4438 | { | |
4439 | struct dsi_clk_calc_ctx *ctx = data; | |
4440 | ||
4441 | ctx->dsi_cinfo.n = n; | |
4442 | ctx->dsi_cinfo.m = m; | |
4443 | ctx->dsi_cinfo.fint = fint; | |
4444 | ctx->dsi_cinfo.clkdco = clkdco; | |
4445 | ||
4446 | return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, | |
4447 | dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), | |
4448 | dsi_cm_calc_hsdiv_cb, ctx); | |
4449 | } | |
4450 | ||
4451 | static bool dsi_cm_calc(struct dsi_data *dsi, | |
4452 | const struct omap_dss_dsi_config *cfg, | |
4453 | struct dsi_clk_calc_ctx *ctx) | |
4454 | { | |
4455 | unsigned long clkin; | |
4456 | int bitspp, ndl; | |
4457 | unsigned long pll_min, pll_max; | |
4458 | unsigned long pck, txbyteclk; | |
4459 | ||
4460 | clkin = clk_get_rate(dsi->pll.clkin); | |
4461 | bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4462 | ndl = dsi->num_lanes_used - 1; | |
4463 | ||
4464 | /* | |
4465 | * Here we should calculate minimum txbyteclk to be able to send the | |
4466 | * frame in time, and also to handle TE. That's not very simple, though, | |
4467 | * especially as we go to LP between each pixel packet due to HW | |
4468 | * "feature". So let's just estimate very roughly and multiply by 1.5. | |
4469 | */ | |
4470 | pck = cfg->timings->pixelclock; | |
4471 | pck = pck * 3 / 2; | |
4472 | txbyteclk = pck * bitspp / 8 / ndl; | |
4473 | ||
4474 | memset(ctx, 0, sizeof(*ctx)); | |
4475 | ctx->dsidev = dsi->pdev; | |
4476 | ctx->pll = &dsi->pll; | |
4477 | ctx->config = cfg; | |
4478 | ctx->req_pck_min = pck; | |
4479 | ctx->req_pck_nom = pck; | |
4480 | ctx->req_pck_max = pck * 3 / 2; | |
4481 | ||
4482 | pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); | |
4483 | pll_max = cfg->hs_clk_max * 4; | |
4484 | ||
4485 | return dss_pll_calc(ctx->pll, clkin, | |
4486 | pll_min, pll_max, | |
4487 | dsi_cm_calc_pll_cb, ctx); | |
4488 | } | |
4489 | ||
4490 | static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) | |
4491 | { | |
4492 | struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); | |
4493 | const struct omap_dss_dsi_config *cfg = ctx->config; | |
4494 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4495 | int ndl = dsi->num_lanes_used - 1; | |
4496 | unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; | |
4497 | unsigned long byteclk = hsclk / 4; | |
4498 | ||
4499 | unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; | |
4500 | int xres; | |
4501 | int panel_htot, panel_hbl; /* pixels */ | |
4502 | int dispc_htot, dispc_hbl; /* pixels */ | |
4503 | int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ | |
4504 | int hfp, hsa, hbp; | |
4505 | const struct omap_video_timings *req_vm; | |
4506 | struct omap_video_timings *dispc_vm; | |
4507 | struct omap_dss_dsi_videomode_timings *dsi_vm; | |
4508 | u64 dsi_tput, dispc_tput; | |
4509 | ||
4510 | dsi_tput = (u64)byteclk * ndl * 8; | |
4511 | ||
4512 | req_vm = cfg->timings; | |
4513 | req_pck_min = ctx->req_pck_min; | |
4514 | req_pck_max = ctx->req_pck_max; | |
4515 | req_pck_nom = ctx->req_pck_nom; | |
4516 | ||
4517 | dispc_pck = ctx->dispc_cinfo.pck; | |
4518 | dispc_tput = (u64)dispc_pck * bitspp; | |
4519 | ||
4520 | xres = req_vm->x_res; | |
4521 | ||
4522 | panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw; | |
4523 | panel_htot = xres + panel_hbl; | |
4524 | ||
4525 | dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); | |
4526 | ||
4527 | /* | |
4528 | * When there are no line buffers, DISPC and DSI must have the | |
4529 | * same tput. Otherwise DISPC tput needs to be higher than DSI's. | |
4530 | */ | |
4531 | if (dsi->line_buffer_size < xres * bitspp / 8) { | |
4532 | if (dispc_tput != dsi_tput) | |
4533 | return false; | |
4534 | } else { | |
4535 | if (dispc_tput < dsi_tput) | |
4536 | return false; | |
4537 | } | |
4538 | ||
4539 | /* DSI tput must be over the min requirement */ | |
4540 | if (dsi_tput < (u64)bitspp * req_pck_min) | |
4541 | return false; | |
4542 | ||
4543 | /* When non-burst mode, DSI tput must be below max requirement. */ | |
4544 | if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { | |
4545 | if (dsi_tput > (u64)bitspp * req_pck_max) | |
4546 | return false; | |
4547 | } | |
4548 | ||
4549 | hss = DIV_ROUND_UP(4, ndl); | |
4550 | ||
4551 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4552 | if (ndl == 3 && req_vm->hsw == 0) | |
4553 | hse = 1; | |
4554 | else | |
4555 | hse = DIV_ROUND_UP(4, ndl); | |
4556 | } else { | |
4557 | hse = 0; | |
4558 | } | |
4559 | ||
4560 | /* DSI htot to match the panel's nominal pck */ | |
4561 | dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); | |
4562 | ||
4563 | /* fail if there would be no time for blanking */ | |
4564 | if (dsi_htot < hss + hse + dsi_hact) | |
4565 | return false; | |
4566 | ||
4567 | /* total DSI blanking needed to achieve panel's TL */ | |
4568 | dsi_hbl = dsi_htot - dsi_hact; | |
4569 | ||
4570 | /* DISPC htot to match the DSI TL */ | |
4571 | dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); | |
4572 | ||
4573 | /* verify that the DSI and DISPC TLs are the same */ | |
4574 | if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) | |
4575 | return false; | |
4576 | ||
4577 | dispc_hbl = dispc_htot - xres; | |
4578 | ||
4579 | /* setup DSI videomode */ | |
4580 | ||
4581 | dsi_vm = &ctx->dsi_vm; | |
4582 | memset(dsi_vm, 0, sizeof(*dsi_vm)); | |
4583 | ||
4584 | dsi_vm->hsclk = hsclk; | |
4585 | ||
4586 | dsi_vm->ndl = ndl; | |
4587 | dsi_vm->bitspp = bitspp; | |
4588 | ||
4589 | if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { | |
4590 | hsa = 0; | |
4591 | } else if (ndl == 3 && req_vm->hsw == 0) { | |
4592 | hsa = 0; | |
4593 | } else { | |
4594 | hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom); | |
4595 | hsa = max(hsa - hse, 1); | |
4596 | } | |
4597 | ||
4598 | hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom); | |
4599 | hbp = max(hbp, 1); | |
4600 | ||
4601 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4602 | if (hfp < 1) { | |
4603 | int t; | |
4604 | /* we need to take cycles from hbp */ | |
4605 | ||
4606 | t = 1 - hfp; | |
4607 | hbp = max(hbp - t, 1); | |
4608 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4609 | ||
4610 | if (hfp < 1 && hsa > 0) { | |
4611 | /* we need to take cycles from hsa */ | |
4612 | t = 1 - hfp; | |
4613 | hsa = max(hsa - t, 1); | |
4614 | hfp = dsi_hbl - (hss + hsa + hse + hbp); | |
4615 | } | |
4616 | } | |
4617 | ||
4618 | if (hfp < 1) | |
4619 | return false; | |
4620 | ||
4621 | dsi_vm->hss = hss; | |
4622 | dsi_vm->hsa = hsa; | |
4623 | dsi_vm->hse = hse; | |
4624 | dsi_vm->hbp = hbp; | |
4625 | dsi_vm->hact = xres; | |
4626 | dsi_vm->hfp = hfp; | |
4627 | ||
4628 | dsi_vm->vsa = req_vm->vsw; | |
4629 | dsi_vm->vbp = req_vm->vbp; | |
4630 | dsi_vm->vact = req_vm->y_res; | |
4631 | dsi_vm->vfp = req_vm->vfp; | |
4632 | ||
4633 | dsi_vm->trans_mode = cfg->trans_mode; | |
4634 | ||
4635 | dsi_vm->blanking_mode = 0; | |
4636 | dsi_vm->hsa_blanking_mode = 1; | |
4637 | dsi_vm->hfp_blanking_mode = 1; | |
4638 | dsi_vm->hbp_blanking_mode = 1; | |
4639 | ||
4640 | dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; | |
4641 | dsi_vm->window_sync = 4; | |
4642 | ||
4643 | /* setup DISPC videomode */ | |
4644 | ||
4645 | dispc_vm = &ctx->dispc_vm; | |
4646 | *dispc_vm = *req_vm; | |
4647 | dispc_vm->pixelclock = dispc_pck; | |
4648 | ||
4649 | if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { | |
4650 | hsa = div64_u64((u64)req_vm->hsw * dispc_pck, | |
4651 | req_pck_nom); | |
4652 | hsa = max(hsa, 1); | |
4653 | } else { | |
4654 | hsa = 1; | |
4655 | } | |
4656 | ||
4657 | hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom); | |
4658 | hbp = max(hbp, 1); | |
4659 | ||
4660 | hfp = dispc_hbl - hsa - hbp; | |
4661 | if (hfp < 1) { | |
4662 | int t; | |
4663 | /* we need to take cycles from hbp */ | |
4664 | ||
4665 | t = 1 - hfp; | |
4666 | hbp = max(hbp - t, 1); | |
4667 | hfp = dispc_hbl - hsa - hbp; | |
4668 | ||
4669 | if (hfp < 1) { | |
4670 | /* we need to take cycles from hsa */ | |
4671 | t = 1 - hfp; | |
4672 | hsa = max(hsa - t, 1); | |
4673 | hfp = dispc_hbl - hsa - hbp; | |
4674 | } | |
4675 | } | |
4676 | ||
4677 | if (hfp < 1) | |
4678 | return false; | |
4679 | ||
4680 | dispc_vm->hfp = hfp; | |
4681 | dispc_vm->hsw = hsa; | |
4682 | dispc_vm->hbp = hbp; | |
4683 | ||
4684 | return true; | |
4685 | } | |
4686 | ||
4687 | ||
4688 | static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, | |
4689 | unsigned long pck, void *data) | |
4690 | { | |
4691 | struct dsi_clk_calc_ctx *ctx = data; | |
4692 | ||
4693 | ctx->dispc_cinfo.lck_div = lckd; | |
4694 | ctx->dispc_cinfo.pck_div = pckd; | |
4695 | ctx->dispc_cinfo.lck = lck; | |
4696 | ctx->dispc_cinfo.pck = pck; | |
4697 | ||
4698 | if (dsi_vm_calc_blanking(ctx) == false) | |
4699 | return false; | |
4700 | ||
4701 | #ifdef PRINT_VERBOSE_VM_TIMINGS | |
4702 | print_dispc_vm("dispc", &ctx->dispc_vm); | |
4703 | print_dsi_vm("dsi ", &ctx->dsi_vm); | |
4704 | print_dispc_vm("req ", ctx->config->timings); | |
4705 | print_dsi_dispc_vm("act ", &ctx->dsi_vm); | |
4706 | #endif | |
4707 | ||
4708 | return true; | |
4709 | } | |
4710 | ||
4711 | static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, | |
4712 | void *data) | |
4713 | { | |
4714 | struct dsi_clk_calc_ctx *ctx = data; | |
4715 | unsigned long pck_max; | |
4716 | ||
4717 | ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; | |
4718 | ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; | |
4719 | ||
4720 | /* | |
4721 | * In burst mode we can let the dispc pck be arbitrarily high, but it | |
4722 | * limits our scaling abilities. So for now, don't aim too high. | |
4723 | */ | |
4724 | ||
4725 | if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) | |
4726 | pck_max = ctx->req_pck_max + 10000000; | |
4727 | else | |
4728 | pck_max = ctx->req_pck_max; | |
4729 | ||
4730 | return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, | |
4731 | dsi_vm_calc_dispc_cb, ctx); | |
4732 | } | |
4733 | ||
4734 | static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, | |
4735 | unsigned long clkdco, void *data) | |
4736 | { | |
4737 | struct dsi_clk_calc_ctx *ctx = data; | |
4738 | ||
4739 | ctx->dsi_cinfo.n = n; | |
4740 | ctx->dsi_cinfo.m = m; | |
4741 | ctx->dsi_cinfo.fint = fint; | |
4742 | ctx->dsi_cinfo.clkdco = clkdco; | |
4743 | ||
4744 | return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, | |
4745 | dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), | |
4746 | dsi_vm_calc_hsdiv_cb, ctx); | |
4747 | } | |
4748 | ||
4749 | static bool dsi_vm_calc(struct dsi_data *dsi, | |
4750 | const struct omap_dss_dsi_config *cfg, | |
4751 | struct dsi_clk_calc_ctx *ctx) | |
4752 | { | |
4753 | const struct omap_video_timings *t = cfg->timings; | |
4754 | unsigned long clkin; | |
4755 | unsigned long pll_min; | |
4756 | unsigned long pll_max; | |
4757 | int ndl = dsi->num_lanes_used - 1; | |
4758 | int bitspp = dsi_get_pixel_size(cfg->pixel_format); | |
4759 | unsigned long byteclk_min; | |
4760 | ||
4761 | clkin = clk_get_rate(dsi->pll.clkin); | |
4762 | ||
4763 | memset(ctx, 0, sizeof(*ctx)); | |
4764 | ctx->dsidev = dsi->pdev; | |
4765 | ctx->pll = &dsi->pll; | |
4766 | ctx->config = cfg; | |
4767 | ||
4768 | /* these limits should come from the panel driver */ | |
4769 | ctx->req_pck_min = t->pixelclock - 1000; | |
4770 | ctx->req_pck_nom = t->pixelclock; | |
4771 | ctx->req_pck_max = t->pixelclock + 1000; | |
4772 | ||
4773 | byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); | |
4774 | pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); | |
4775 | ||
4776 | if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { | |
4777 | pll_max = cfg->hs_clk_max * 4; | |
4778 | } else { | |
4779 | unsigned long byteclk_max; | |
4780 | byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, | |
4781 | ndl * 8); | |
4782 | ||
4783 | pll_max = byteclk_max * 4 * 4; | |
4784 | } | |
4785 | ||
4786 | return dss_pll_calc(ctx->pll, clkin, | |
4787 | pll_min, pll_max, | |
4788 | dsi_vm_calc_pll_cb, ctx); | |
4789 | } | |
4790 | ||
4791 | static int dsi_set_config(struct omap_dss_device *dssdev, | |
4792 | const struct omap_dss_dsi_config *config) | |
4793 | { | |
4794 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4795 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4796 | struct dsi_clk_calc_ctx ctx; | |
4797 | bool ok; | |
4798 | int r; | |
4799 | ||
4800 | mutex_lock(&dsi->lock); | |
4801 | ||
4802 | dsi->pix_fmt = config->pixel_format; | |
4803 | dsi->mode = config->mode; | |
4804 | ||
4805 | if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) | |
4806 | ok = dsi_vm_calc(dsi, config, &ctx); | |
4807 | else | |
4808 | ok = dsi_cm_calc(dsi, config, &ctx); | |
4809 | ||
4810 | if (!ok) { | |
4811 | DSSERR("failed to find suitable DSI clock settings\n"); | |
4812 | r = -EINVAL; | |
4813 | goto err; | |
4814 | } | |
4815 | ||
4816 | dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo); | |
4817 | ||
4818 | r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], | |
4819 | config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); | |
4820 | if (r) { | |
4821 | DSSERR("failed to find suitable DSI LP clock settings\n"); | |
4822 | goto err; | |
4823 | } | |
4824 | ||
4825 | dsi->user_dsi_cinfo = ctx.dsi_cinfo; | |
4826 | dsi->user_dispc_cinfo = ctx.dispc_cinfo; | |
4827 | ||
4828 | dsi->timings = ctx.dispc_vm; | |
4829 | dsi->vm_timings = ctx.dsi_vm; | |
4830 | ||
4831 | mutex_unlock(&dsi->lock); | |
4832 | ||
4833 | return 0; | |
4834 | err: | |
4835 | mutex_unlock(&dsi->lock); | |
4836 | ||
4837 | return r; | |
4838 | } | |
4839 | ||
4840 | /* | |
4841 | * Return a hardcoded channel for the DSI output. This should work for | |
4842 | * current use cases, but this can be later expanded to either resolve | |
4843 | * the channel in some more dynamic manner, or get the channel as a user | |
4844 | * parameter. | |
4845 | */ | |
4846 | static enum omap_channel dsi_get_channel(int module_id) | |
4847 | { | |
4848 | switch (omapdss_get_version()) { | |
4849 | case OMAPDSS_VER_OMAP24xx: | |
4850 | case OMAPDSS_VER_AM43xx: | |
4851 | DSSWARN("DSI not supported\n"); | |
4852 | return OMAP_DSS_CHANNEL_LCD; | |
4853 | ||
4854 | case OMAPDSS_VER_OMAP34xx_ES1: | |
4855 | case OMAPDSS_VER_OMAP34xx_ES3: | |
4856 | case OMAPDSS_VER_OMAP3630: | |
4857 | case OMAPDSS_VER_AM35xx: | |
4858 | return OMAP_DSS_CHANNEL_LCD; | |
4859 | ||
4860 | case OMAPDSS_VER_OMAP4430_ES1: | |
4861 | case OMAPDSS_VER_OMAP4430_ES2: | |
4862 | case OMAPDSS_VER_OMAP4: | |
4863 | switch (module_id) { | |
4864 | case 0: | |
4865 | return OMAP_DSS_CHANNEL_LCD; | |
4866 | case 1: | |
4867 | return OMAP_DSS_CHANNEL_LCD2; | |
4868 | default: | |
4869 | DSSWARN("unsupported module id\n"); | |
4870 | return OMAP_DSS_CHANNEL_LCD; | |
4871 | } | |
4872 | ||
4873 | case OMAPDSS_VER_OMAP5: | |
4874 | switch (module_id) { | |
4875 | case 0: | |
4876 | return OMAP_DSS_CHANNEL_LCD; | |
4877 | case 1: | |
4878 | return OMAP_DSS_CHANNEL_LCD3; | |
4879 | default: | |
4880 | DSSWARN("unsupported module id\n"); | |
4881 | return OMAP_DSS_CHANNEL_LCD; | |
4882 | } | |
4883 | ||
4884 | default: | |
4885 | DSSWARN("unsupported DSS version\n"); | |
4886 | return OMAP_DSS_CHANNEL_LCD; | |
4887 | } | |
4888 | } | |
4889 | ||
4890 | static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) | |
4891 | { | |
4892 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4893 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4894 | int i; | |
4895 | ||
4896 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { | |
4897 | if (!dsi->vc[i].dssdev) { | |
4898 | dsi->vc[i].dssdev = dssdev; | |
4899 | *channel = i; | |
4900 | return 0; | |
4901 | } | |
4902 | } | |
4903 | ||
4904 | DSSERR("cannot get VC for display %s", dssdev->name); | |
4905 | return -ENOSPC; | |
4906 | } | |
4907 | ||
4908 | static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) | |
4909 | { | |
4910 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4911 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4912 | ||
4913 | if (vc_id < 0 || vc_id > 3) { | |
4914 | DSSERR("VC ID out of range\n"); | |
4915 | return -EINVAL; | |
4916 | } | |
4917 | ||
4918 | if (channel < 0 || channel > 3) { | |
4919 | DSSERR("Virtual Channel out of range\n"); | |
4920 | return -EINVAL; | |
4921 | } | |
4922 | ||
4923 | if (dsi->vc[channel].dssdev != dssdev) { | |
4924 | DSSERR("Virtual Channel not allocated to display %s\n", | |
4925 | dssdev->name); | |
4926 | return -EINVAL; | |
4927 | } | |
4928 | ||
4929 | dsi->vc[channel].vc_id = vc_id; | |
4930 | ||
4931 | return 0; | |
4932 | } | |
4933 | ||
4934 | static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) | |
4935 | { | |
4936 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4937 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4938 | ||
4939 | if ((channel >= 0 && channel <= 3) && | |
4940 | dsi->vc[channel].dssdev == dssdev) { | |
4941 | dsi->vc[channel].dssdev = NULL; | |
4942 | dsi->vc[channel].vc_id = 0; | |
4943 | } | |
4944 | } | |
4945 | ||
4946 | ||
4947 | static int dsi_get_clocks(struct platform_device *dsidev) | |
4948 | { | |
4949 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4950 | struct clk *clk; | |
4951 | ||
4952 | clk = devm_clk_get(&dsidev->dev, "fck"); | |
4953 | if (IS_ERR(clk)) { | |
4954 | DSSERR("can't get fck\n"); | |
4955 | return PTR_ERR(clk); | |
4956 | } | |
4957 | ||
4958 | dsi->dss_clk = clk; | |
4959 | ||
4960 | return 0; | |
4961 | } | |
4962 | ||
4963 | static int dsi_connect(struct omap_dss_device *dssdev, | |
4964 | struct omap_dss_device *dst) | |
4965 | { | |
4966 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4967 | struct omap_overlay_manager *mgr; | |
4968 | int r; | |
4969 | ||
4970 | r = dsi_regulator_init(dsidev); | |
4971 | if (r) | |
4972 | return r; | |
4973 | ||
4974 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
4975 | if (!mgr) | |
4976 | return -ENODEV; | |
4977 | ||
4978 | r = dss_mgr_connect(mgr, dssdev); | |
4979 | if (r) | |
4980 | return r; | |
4981 | ||
4982 | r = omapdss_output_set_device(dssdev, dst); | |
4983 | if (r) { | |
4984 | DSSERR("failed to connect output to new device: %s\n", | |
4985 | dssdev->name); | |
4986 | dss_mgr_disconnect(mgr, dssdev); | |
4987 | return r; | |
4988 | } | |
4989 | ||
4990 | return 0; | |
4991 | } | |
4992 | ||
4993 | static void dsi_disconnect(struct omap_dss_device *dssdev, | |
4994 | struct omap_dss_device *dst) | |
4995 | { | |
4996 | WARN_ON(dst != dssdev->dst); | |
4997 | ||
4998 | if (dst != dssdev->dst) | |
4999 | return; | |
5000 | ||
5001 | omapdss_output_unset_device(dssdev); | |
5002 | ||
5003 | if (dssdev->manager) | |
5004 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
5005 | } | |
5006 | ||
5007 | static const struct omapdss_dsi_ops dsi_ops = { | |
5008 | .connect = dsi_connect, | |
5009 | .disconnect = dsi_disconnect, | |
5010 | ||
5011 | .bus_lock = dsi_bus_lock, | |
5012 | .bus_unlock = dsi_bus_unlock, | |
5013 | ||
5014 | .enable = dsi_display_enable, | |
5015 | .disable = dsi_display_disable, | |
5016 | ||
5017 | .enable_hs = dsi_vc_enable_hs, | |
5018 | ||
5019 | .configure_pins = dsi_configure_pins, | |
5020 | .set_config = dsi_set_config, | |
5021 | ||
5022 | .enable_video_output = dsi_enable_video_output, | |
5023 | .disable_video_output = dsi_disable_video_output, | |
5024 | ||
5025 | .update = dsi_update, | |
5026 | ||
5027 | .enable_te = dsi_enable_te, | |
5028 | ||
5029 | .request_vc = dsi_request_vc, | |
5030 | .set_vc_id = dsi_set_vc_id, | |
5031 | .release_vc = dsi_release_vc, | |
5032 | ||
5033 | .dcs_write = dsi_vc_dcs_write, | |
5034 | .dcs_write_nosync = dsi_vc_dcs_write_nosync, | |
5035 | .dcs_read = dsi_vc_dcs_read, | |
5036 | ||
5037 | .gen_write = dsi_vc_generic_write, | |
5038 | .gen_write_nosync = dsi_vc_generic_write_nosync, | |
5039 | .gen_read = dsi_vc_generic_read, | |
5040 | ||
5041 | .bta_sync = dsi_vc_send_bta_sync, | |
5042 | ||
5043 | .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, | |
5044 | }; | |
5045 | ||
5046 | static void dsi_init_output(struct platform_device *dsidev) | |
5047 | { | |
5048 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5049 | struct omap_dss_device *out = &dsi->output; | |
5050 | ||
5051 | out->dev = &dsidev->dev; | |
5052 | out->id = dsi->module_id == 0 ? | |
5053 | OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; | |
5054 | ||
5055 | out->output_type = OMAP_DISPLAY_TYPE_DSI; | |
5056 | out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; | |
5057 | out->dispc_channel = dsi_get_channel(dsi->module_id); | |
5058 | out->ops.dsi = &dsi_ops; | |
5059 | out->owner = THIS_MODULE; | |
5060 | ||
5061 | omapdss_register_output(out); | |
5062 | } | |
5063 | ||
5064 | static void dsi_uninit_output(struct platform_device *dsidev) | |
5065 | { | |
5066 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5067 | struct omap_dss_device *out = &dsi->output; | |
5068 | ||
5069 | omapdss_unregister_output(out); | |
5070 | } | |
5071 | ||
5072 | static int dsi_probe_of(struct platform_device *pdev) | |
5073 | { | |
5074 | struct device_node *node = pdev->dev.of_node; | |
5075 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
5076 | struct property *prop; | |
5077 | u32 lane_arr[10]; | |
5078 | int len, num_pins; | |
5079 | int r, i; | |
5080 | struct device_node *ep; | |
5081 | struct omap_dsi_pin_config pin_cfg; | |
5082 | ||
ada5caa4 | 5083 | ep = of_graph_get_endpoint_by_regs(node, 0, -1); |
f76ee892 TV |
5084 | if (!ep) |
5085 | return 0; | |
5086 | ||
5087 | prop = of_find_property(ep, "lanes", &len); | |
5088 | if (prop == NULL) { | |
5089 | dev_err(&pdev->dev, "failed to find lane data\n"); | |
5090 | r = -EINVAL; | |
5091 | goto err; | |
5092 | } | |
5093 | ||
5094 | num_pins = len / sizeof(u32); | |
5095 | ||
5096 | if (num_pins < 4 || num_pins % 2 != 0 || | |
5097 | num_pins > dsi->num_lanes_supported * 2) { | |
5098 | dev_err(&pdev->dev, "bad number of lanes\n"); | |
5099 | r = -EINVAL; | |
5100 | goto err; | |
5101 | } | |
5102 | ||
5103 | r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); | |
5104 | if (r) { | |
5105 | dev_err(&pdev->dev, "failed to read lane data\n"); | |
5106 | goto err; | |
5107 | } | |
5108 | ||
5109 | pin_cfg.num_pins = num_pins; | |
5110 | for (i = 0; i < num_pins; ++i) | |
5111 | pin_cfg.pins[i] = (int)lane_arr[i]; | |
5112 | ||
5113 | r = dsi_configure_pins(&dsi->output, &pin_cfg); | |
5114 | if (r) { | |
5115 | dev_err(&pdev->dev, "failed to configure pins"); | |
5116 | goto err; | |
5117 | } | |
5118 | ||
5119 | of_node_put(ep); | |
5120 | ||
5121 | return 0; | |
5122 | ||
5123 | err: | |
5124 | of_node_put(ep); | |
5125 | return r; | |
5126 | } | |
5127 | ||
5128 | static const struct dss_pll_ops dsi_pll_ops = { | |
5129 | .enable = dsi_pll_enable, | |
5130 | .disable = dsi_pll_disable, | |
5131 | .set_config = dss_pll_write_config_type_a, | |
5132 | }; | |
5133 | ||
5134 | static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { | |
5135 | .n_max = (1 << 7) - 1, | |
5136 | .m_max = (1 << 11) - 1, | |
5137 | .mX_max = (1 << 4) - 1, | |
5138 | .fint_min = 750000, | |
5139 | .fint_max = 2100000, | |
5140 | .clkdco_low = 1000000000, | |
5141 | .clkdco_max = 1800000000, | |
5142 | ||
5143 | .n_msb = 7, | |
5144 | .n_lsb = 1, | |
5145 | .m_msb = 18, | |
5146 | .m_lsb = 8, | |
5147 | ||
5148 | .mX_msb[0] = 22, | |
5149 | .mX_lsb[0] = 19, | |
5150 | .mX_msb[1] = 26, | |
5151 | .mX_lsb[1] = 23, | |
5152 | ||
5153 | .has_stopmode = true, | |
5154 | .has_freqsel = true, | |
5155 | .has_selfreqdco = false, | |
5156 | .has_refsel = false, | |
5157 | }; | |
5158 | ||
5159 | static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { | |
5160 | .n_max = (1 << 8) - 1, | |
5161 | .m_max = (1 << 12) - 1, | |
5162 | .mX_max = (1 << 5) - 1, | |
5163 | .fint_min = 500000, | |
5164 | .fint_max = 2500000, | |
5165 | .clkdco_low = 1000000000, | |
5166 | .clkdco_max = 1800000000, | |
5167 | ||
5168 | .n_msb = 8, | |
5169 | .n_lsb = 1, | |
5170 | .m_msb = 20, | |
5171 | .m_lsb = 9, | |
5172 | ||
5173 | .mX_msb[0] = 25, | |
5174 | .mX_lsb[0] = 21, | |
5175 | .mX_msb[1] = 30, | |
5176 | .mX_lsb[1] = 26, | |
5177 | ||
5178 | .has_stopmode = true, | |
5179 | .has_freqsel = false, | |
5180 | .has_selfreqdco = false, | |
5181 | .has_refsel = false, | |
5182 | }; | |
5183 | ||
5184 | static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { | |
5185 | .n_max = (1 << 8) - 1, | |
5186 | .m_max = (1 << 12) - 1, | |
5187 | .mX_max = (1 << 5) - 1, | |
5188 | .fint_min = 150000, | |
5189 | .fint_max = 52000000, | |
5190 | .clkdco_low = 1000000000, | |
5191 | .clkdco_max = 1800000000, | |
5192 | ||
5193 | .n_msb = 8, | |
5194 | .n_lsb = 1, | |
5195 | .m_msb = 20, | |
5196 | .m_lsb = 9, | |
5197 | ||
5198 | .mX_msb[0] = 25, | |
5199 | .mX_lsb[0] = 21, | |
5200 | .mX_msb[1] = 30, | |
5201 | .mX_lsb[1] = 26, | |
5202 | ||
5203 | .has_stopmode = true, | |
5204 | .has_freqsel = false, | |
5205 | .has_selfreqdco = true, | |
5206 | .has_refsel = true, | |
5207 | }; | |
5208 | ||
5209 | static int dsi_init_pll_data(struct platform_device *dsidev) | |
5210 | { | |
5211 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5212 | struct dss_pll *pll = &dsi->pll; | |
5213 | struct clk *clk; | |
5214 | int r; | |
5215 | ||
5216 | clk = devm_clk_get(&dsidev->dev, "sys_clk"); | |
5217 | if (IS_ERR(clk)) { | |
5218 | DSSERR("can't get sys_clk\n"); | |
5219 | return PTR_ERR(clk); | |
5220 | } | |
5221 | ||
5222 | pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; | |
5223 | pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; | |
5224 | pll->clkin = clk; | |
5225 | pll->base = dsi->pll_base; | |
5226 | ||
5227 | switch (omapdss_get_version()) { | |
5228 | case OMAPDSS_VER_OMAP34xx_ES1: | |
5229 | case OMAPDSS_VER_OMAP34xx_ES3: | |
5230 | case OMAPDSS_VER_OMAP3630: | |
5231 | case OMAPDSS_VER_AM35xx: | |
5232 | pll->hw = &dss_omap3_dsi_pll_hw; | |
5233 | break; | |
5234 | ||
5235 | case OMAPDSS_VER_OMAP4430_ES1: | |
5236 | case OMAPDSS_VER_OMAP4430_ES2: | |
5237 | case OMAPDSS_VER_OMAP4: | |
5238 | pll->hw = &dss_omap4_dsi_pll_hw; | |
5239 | break; | |
5240 | ||
5241 | case OMAPDSS_VER_OMAP5: | |
5242 | pll->hw = &dss_omap5_dsi_pll_hw; | |
5243 | break; | |
5244 | ||
5245 | default: | |
5246 | return -ENODEV; | |
5247 | } | |
5248 | ||
5249 | pll->ops = &dsi_pll_ops; | |
5250 | ||
5251 | r = dss_pll_register(pll); | |
5252 | if (r) | |
5253 | return r; | |
5254 | ||
5255 | return 0; | |
5256 | } | |
5257 | ||
5258 | /* DSI1 HW IP initialisation */ | |
5259 | static int dsi_bind(struct device *dev, struct device *master, void *data) | |
5260 | { | |
5261 | struct platform_device *dsidev = to_platform_device(dev); | |
5262 | u32 rev; | |
5263 | int r, i; | |
5264 | struct dsi_data *dsi; | |
5265 | struct resource *dsi_mem; | |
5266 | struct resource *res; | |
5267 | struct resource temp_res; | |
5268 | ||
5269 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); | |
5270 | if (!dsi) | |
5271 | return -ENOMEM; | |
5272 | ||
5273 | dsi->pdev = dsidev; | |
0b5e0f45 | 5274 | platform_set_drvdata(dsidev, dsi); |
f76ee892 TV |
5275 | |
5276 | spin_lock_init(&dsi->irq_lock); | |
5277 | spin_lock_init(&dsi->errors_lock); | |
5278 | dsi->errors = 0; | |
5279 | ||
35b522cf | 5280 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
f76ee892 TV |
5281 | spin_lock_init(&dsi->irq_stats_lock); |
5282 | dsi->irq_stats.last_reset = jiffies; | |
5283 | #endif | |
5284 | ||
5285 | mutex_init(&dsi->lock); | |
5286 | sema_init(&dsi->bus_lock, 1); | |
5287 | ||
5288 | INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, | |
5289 | dsi_framedone_timeout_work_callback); | |
5290 | ||
5291 | #ifdef DSI_CATCH_MISSING_TE | |
6c789357 | 5292 | timer_setup(&dsi->te_timer, dsi_te_timeout, 0); |
f76ee892 TV |
5293 | #endif |
5294 | ||
5295 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); | |
5296 | if (!res) { | |
5297 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5298 | if (!res) { | |
5299 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5300 | return -EINVAL; | |
5301 | } | |
5302 | ||
5303 | temp_res.start = res->start; | |
5304 | temp_res.end = temp_res.start + DSI_PROTO_SZ - 1; | |
5305 | res = &temp_res; | |
5306 | } | |
5307 | ||
5308 | dsi_mem = res; | |
5309 | ||
5310 | dsi->proto_base = devm_ioremap(&dsidev->dev, res->start, | |
5311 | resource_size(res)); | |
5312 | if (!dsi->proto_base) { | |
5313 | DSSERR("can't ioremap DSI protocol engine\n"); | |
5314 | return -ENOMEM; | |
5315 | } | |
5316 | ||
5317 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); | |
5318 | if (!res) { | |
5319 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5320 | if (!res) { | |
5321 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5322 | return -EINVAL; | |
5323 | } | |
5324 | ||
5325 | temp_res.start = res->start + DSI_PHY_OFFSET; | |
5326 | temp_res.end = temp_res.start + DSI_PHY_SZ - 1; | |
5327 | res = &temp_res; | |
5328 | } | |
5329 | ||
5330 | dsi->phy_base = devm_ioremap(&dsidev->dev, res->start, | |
5331 | resource_size(res)); | |
43da7575 | 5332 | if (!dsi->phy_base) { |
f76ee892 TV |
5333 | DSSERR("can't ioremap DSI PHY\n"); |
5334 | return -ENOMEM; | |
5335 | } | |
5336 | ||
5337 | res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); | |
5338 | if (!res) { | |
5339 | res = platform_get_resource(dsidev, IORESOURCE_MEM, 0); | |
5340 | if (!res) { | |
5341 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
5342 | return -EINVAL; | |
5343 | } | |
5344 | ||
5345 | temp_res.start = res->start + DSI_PLL_OFFSET; | |
5346 | temp_res.end = temp_res.start + DSI_PLL_SZ - 1; | |
5347 | res = &temp_res; | |
5348 | } | |
5349 | ||
5350 | dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, | |
5351 | resource_size(res)); | |
43da7575 | 5352 | if (!dsi->pll_base) { |
f76ee892 TV |
5353 | DSSERR("can't ioremap DSI PLL\n"); |
5354 | return -ENOMEM; | |
5355 | } | |
5356 | ||
5357 | dsi->irq = platform_get_irq(dsi->pdev, 0); | |
5358 | if (dsi->irq < 0) { | |
5359 | DSSERR("platform_get_irq failed\n"); | |
5360 | return -ENODEV; | |
5361 | } | |
5362 | ||
5363 | r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, | |
5364 | IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); | |
5365 | if (r < 0) { | |
5366 | DSSERR("request_irq failed\n"); | |
5367 | return r; | |
5368 | } | |
5369 | ||
5370 | if (dsidev->dev.of_node) { | |
5371 | const struct of_device_id *match; | |
5372 | const struct dsi_module_id_data *d; | |
5373 | ||
5374 | match = of_match_node(dsi_of_match, dsidev->dev.of_node); | |
5375 | if (!match) { | |
5376 | DSSERR("unsupported DSI module\n"); | |
5377 | return -ENODEV; | |
5378 | } | |
5379 | ||
5380 | d = match->data; | |
5381 | ||
5382 | while (d->address != 0 && d->address != dsi_mem->start) | |
5383 | d++; | |
5384 | ||
5385 | if (d->address == 0) { | |
5386 | DSSERR("unsupported DSI module\n"); | |
5387 | return -ENODEV; | |
5388 | } | |
5389 | ||
5390 | dsi->module_id = d->id; | |
5391 | } else { | |
5392 | dsi->module_id = dsidev->id; | |
5393 | } | |
5394 | ||
5395 | /* DSI VCs initialization */ | |
5396 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { | |
5397 | dsi->vc[i].source = DSI_VC_SOURCE_L4; | |
5398 | dsi->vc[i].dssdev = NULL; | |
5399 | dsi->vc[i].vc_id = 0; | |
5400 | } | |
5401 | ||
5402 | r = dsi_get_clocks(dsidev); | |
5403 | if (r) | |
5404 | return r; | |
5405 | ||
5406 | dsi_init_pll_data(dsidev); | |
5407 | ||
5408 | pm_runtime_enable(&dsidev->dev); | |
5409 | ||
5410 | r = dsi_runtime_get(dsidev); | |
5411 | if (r) | |
5412 | goto err_runtime_get; | |
5413 | ||
5414 | rev = dsi_read_reg(dsidev, DSI_REVISION); | |
5415 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", | |
5416 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); | |
5417 | ||
5418 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number | |
5419 | * of data to 3 by default */ | |
5420 | if (dss_has_feature(FEAT_DSI_GNQ)) | |
5421 | /* NB_DATA_LANES */ | |
5422 | dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); | |
5423 | else | |
5424 | dsi->num_lanes_supported = 3; | |
5425 | ||
5426 | dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); | |
5427 | ||
5428 | dsi_init_output(dsidev); | |
5429 | ||
5430 | if (dsidev->dev.of_node) { | |
5431 | r = dsi_probe_of(dsidev); | |
5432 | if (r) { | |
5433 | DSSERR("Invalid DSI DT data\n"); | |
5434 | goto err_probe_of; | |
5435 | } | |
5436 | ||
5437 | r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, | |
5438 | &dsidev->dev); | |
5439 | if (r) | |
5440 | DSSERR("Failed to populate DSI child devices: %d\n", r); | |
5441 | } | |
5442 | ||
5443 | dsi_runtime_put(dsidev); | |
5444 | ||
5445 | if (dsi->module_id == 0) | |
5446 | dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); | |
5447 | else if (dsi->module_id == 1) | |
5448 | dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); | |
5449 | ||
35b522cf | 5450 | #ifdef CONFIG_FB_OMAP2_DSS_COLLECT_IRQ_STATS |
f76ee892 TV |
5451 | if (dsi->module_id == 0) |
5452 | dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); | |
5453 | else if (dsi->module_id == 1) | |
5454 | dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); | |
5455 | #endif | |
5456 | ||
5457 | return 0; | |
5458 | ||
5459 | err_probe_of: | |
5460 | dsi_uninit_output(dsidev); | |
5461 | dsi_runtime_put(dsidev); | |
5462 | ||
5463 | err_runtime_get: | |
5464 | pm_runtime_disable(&dsidev->dev); | |
5465 | return r; | |
5466 | } | |
5467 | ||
5468 | static void dsi_unbind(struct device *dev, struct device *master, void *data) | |
5469 | { | |
5470 | struct platform_device *dsidev = to_platform_device(dev); | |
5471 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5472 | ||
5473 | of_platform_depopulate(&dsidev->dev); | |
5474 | ||
5475 | WARN_ON(dsi->scp_clk_refcount > 0); | |
5476 | ||
5477 | dss_pll_unregister(&dsi->pll); | |
5478 | ||
5479 | dsi_uninit_output(dsidev); | |
5480 | ||
5481 | pm_runtime_disable(&dsidev->dev); | |
5482 | ||
5483 | if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { | |
5484 | regulator_disable(dsi->vdds_dsi_reg); | |
5485 | dsi->vdds_dsi_enabled = false; | |
5486 | } | |
5487 | } | |
5488 | ||
5489 | static const struct component_ops dsi_component_ops = { | |
5490 | .bind = dsi_bind, | |
5491 | .unbind = dsi_unbind, | |
5492 | }; | |
5493 | ||
5494 | static int dsi_probe(struct platform_device *pdev) | |
5495 | { | |
5496 | return component_add(&pdev->dev, &dsi_component_ops); | |
5497 | } | |
5498 | ||
dc6b77ba | 5499 | static void dsi_remove(struct platform_device *pdev) |
f76ee892 TV |
5500 | { |
5501 | component_del(&pdev->dev, &dsi_component_ops); | |
f76ee892 TV |
5502 | } |
5503 | ||
5504 | static int dsi_runtime_suspend(struct device *dev) | |
5505 | { | |
5506 | struct platform_device *pdev = to_platform_device(dev); | |
5507 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
5508 | ||
5509 | dsi->is_enabled = false; | |
5510 | /* ensure the irq handler sees the is_enabled value */ | |
5511 | smp_wmb(); | |
5512 | /* wait for current handler to finish before turning the DSI off */ | |
5513 | synchronize_irq(dsi->irq); | |
5514 | ||
5515 | dispc_runtime_put(); | |
5516 | ||
5517 | return 0; | |
5518 | } | |
5519 | ||
5520 | static int dsi_runtime_resume(struct device *dev) | |
5521 | { | |
5522 | struct platform_device *pdev = to_platform_device(dev); | |
5523 | struct dsi_data *dsi = dsi_get_dsidrv_data(pdev); | |
5524 | int r; | |
5525 | ||
5526 | r = dispc_runtime_get(); | |
5527 | if (r) | |
5528 | return r; | |
5529 | ||
5530 | dsi->is_enabled = true; | |
5531 | /* ensure the irq handler sees the is_enabled value */ | |
5532 | smp_wmb(); | |
5533 | ||
5534 | return 0; | |
5535 | } | |
5536 | ||
5537 | static const struct dev_pm_ops dsi_pm_ops = { | |
5538 | .runtime_suspend = dsi_runtime_suspend, | |
5539 | .runtime_resume = dsi_runtime_resume, | |
5540 | }; | |
5541 | ||
5542 | static const struct dsi_module_id_data dsi_of_data_omap3[] = { | |
5543 | { .address = 0x4804fc00, .id = 0, }, | |
5544 | { }, | |
5545 | }; | |
5546 | ||
5547 | static const struct dsi_module_id_data dsi_of_data_omap4[] = { | |
5548 | { .address = 0x58004000, .id = 0, }, | |
5549 | { .address = 0x58005000, .id = 1, }, | |
5550 | { }, | |
5551 | }; | |
5552 | ||
5553 | static const struct dsi_module_id_data dsi_of_data_omap5[] = { | |
5554 | { .address = 0x58004000, .id = 0, }, | |
5555 | { .address = 0x58009000, .id = 1, }, | |
5556 | { }, | |
5557 | }; | |
5558 | ||
5559 | static const struct of_device_id dsi_of_match[] = { | |
5560 | { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, }, | |
5561 | { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, }, | |
5562 | { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, }, | |
5563 | {}, | |
5564 | }; | |
5565 | ||
5566 | static struct platform_driver omap_dsihw_driver = { | |
5567 | .probe = dsi_probe, | |
dc6b77ba | 5568 | .remove_new = dsi_remove, |
f76ee892 TV |
5569 | .driver = { |
5570 | .name = "omapdss_dsi", | |
5571 | .pm = &dsi_pm_ops, | |
5572 | .of_match_table = dsi_of_match, | |
5573 | .suppress_bind_attrs = true, | |
5574 | }, | |
5575 | }; | |
5576 | ||
5577 | int __init dsi_init_platform_driver(void) | |
5578 | { | |
5579 | return platform_driver_register(&omap_dsihw_driver); | |
5580 | } | |
5581 | ||
5582 | void dsi_uninit_platform_driver(void) | |
5583 | { | |
5584 | platform_driver_unregister(&omap_dsihw_driver); | |
5585 | } |