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f5bab222 TV |
1 | /* |
2 | * HDMI driver for OMAP5 | |
3 | * | |
4 | * Copyright (C) 2014 Texas Instruments Incorporated | |
5 | * | |
6 | * Authors: | |
7 | * Yong Zhi | |
8 | * Mythri pk | |
9 | * Archit Taneja <archit@ti.com> | |
10 | * Tomi Valkeinen <tomi.valkeinen@ti.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License version 2 as published by | |
14 | * the Free Software Foundation. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along with | |
22 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | */ | |
24 | ||
25 | #define DSS_SUBSYS_NAME "HDMI" | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/err.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/mutex.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/platform_device.h> | |
36 | #include <linux/pm_runtime.h> | |
37 | #include <linux/clk.h> | |
38 | #include <linux/gpio.h> | |
39 | #include <linux/regulator/consumer.h> | |
736e60dd | 40 | #include <linux/component.h> |
f5bab222 | 41 | #include <video/omapdss.h> |
45302d7e | 42 | #include <sound/omap-hdmi-audio.h> |
f5bab222 TV |
43 | |
44 | #include "hdmi5_core.h" | |
45 | #include "dss.h" | |
46 | #include "dss_features.h" | |
47 | ||
945514b5 | 48 | static struct omap_hdmi hdmi; |
f5bab222 TV |
49 | |
50 | static int hdmi_runtime_get(void) | |
51 | { | |
52 | int r; | |
53 | ||
54 | DSSDBG("hdmi_runtime_get\n"); | |
55 | ||
56 | r = pm_runtime_get_sync(&hdmi.pdev->dev); | |
57 | WARN_ON(r < 0); | |
58 | if (r < 0) | |
59 | return r; | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | static void hdmi_runtime_put(void) | |
65 | { | |
66 | int r; | |
67 | ||
68 | DSSDBG("hdmi_runtime_put\n"); | |
69 | ||
70 | r = pm_runtime_put_sync(&hdmi.pdev->dev); | |
71 | WARN_ON(r < 0 && r != -ENOSYS); | |
72 | } | |
73 | ||
74 | static irqreturn_t hdmi_irq_handler(int irq, void *data) | |
75 | { | |
76 | struct hdmi_wp_data *wp = data; | |
77 | u32 irqstatus; | |
78 | ||
79 | irqstatus = hdmi_wp_get_irqstatus(wp); | |
80 | hdmi_wp_set_irqstatus(wp, irqstatus); | |
81 | ||
82 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && | |
83 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
84 | u32 v; | |
85 | /* | |
86 | * If we get both connect and disconnect interrupts at the same | |
87 | * time, turn off the PHY, clear interrupts, and restart, which | |
88 | * raises connect interrupt if a cable is connected, or nothing | |
89 | * if cable is not connected. | |
90 | */ | |
91 | ||
92 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); | |
93 | ||
94 | /* | |
95 | * We always get bogus CONNECT & DISCONNECT interrupts when | |
96 | * setting the PHY to LDOON. To ignore those, we force the RXDET | |
97 | * line to 0 until the PHY power state has been changed. | |
98 | */ | |
99 | v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); | |
100 | v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ | |
101 | v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ | |
102 | hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); | |
103 | ||
104 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | | |
105 | HDMI_IRQ_LINK_DISCONNECT); | |
106 | ||
107 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
108 | ||
109 | REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); | |
110 | ||
111 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { | |
112 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); | |
113 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { | |
114 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); | |
115 | } | |
116 | ||
117 | return IRQ_HANDLED; | |
118 | } | |
119 | ||
120 | static int hdmi_init_regulator(void) | |
121 | { | |
122 | int r; | |
123 | struct regulator *reg; | |
124 | ||
125 | if (hdmi.vdda_reg != NULL) | |
126 | return 0; | |
127 | ||
128 | reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); | |
129 | if (IS_ERR(reg)) { | |
130 | DSSERR("can't get VDDA regulator\n"); | |
131 | return PTR_ERR(reg); | |
132 | } | |
133 | ||
134 | if (regulator_can_change_voltage(reg)) { | |
135 | r = regulator_set_voltage(reg, 1800000, 1800000); | |
136 | if (r) { | |
137 | devm_regulator_put(reg); | |
138 | DSSWARN("can't set the regulator voltage\n"); | |
139 | return r; | |
140 | } | |
141 | } | |
142 | ||
143 | hdmi.vdda_reg = reg; | |
144 | ||
145 | return 0; | |
146 | } | |
147 | ||
148 | static int hdmi_power_on_core(struct omap_dss_device *dssdev) | |
149 | { | |
150 | int r; | |
151 | ||
152 | r = regulator_enable(hdmi.vdda_reg); | |
153 | if (r) | |
154 | return r; | |
155 | ||
156 | r = hdmi_runtime_get(); | |
157 | if (r) | |
158 | goto err_runtime_get; | |
159 | ||
160 | /* Make selection of HDMI in DSS */ | |
161 | dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); | |
162 | ||
163 | hdmi.core_enabled = true; | |
164 | ||
165 | return 0; | |
166 | ||
167 | err_runtime_get: | |
168 | regulator_disable(hdmi.vdda_reg); | |
169 | ||
170 | return r; | |
171 | } | |
172 | ||
173 | static void hdmi_power_off_core(struct omap_dss_device *dssdev) | |
174 | { | |
175 | hdmi.core_enabled = false; | |
176 | ||
177 | hdmi_runtime_put(); | |
178 | regulator_disable(hdmi.vdda_reg); | |
179 | } | |
180 | ||
181 | static int hdmi_power_on_full(struct omap_dss_device *dssdev) | |
182 | { | |
183 | int r; | |
184 | struct omap_video_timings *p; | |
185 | struct omap_overlay_manager *mgr = hdmi.output.manager; | |
c84c3a5b | 186 | struct dss_pll_clock_info hdmi_cinfo = { 0 }; |
f5bab222 TV |
187 | |
188 | r = hdmi_power_on_core(dssdev); | |
189 | if (r) | |
190 | return r; | |
191 | ||
192 | p = &hdmi.cfg.timings; | |
193 | ||
194 | DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res); | |
195 | ||
c84c3a5b | 196 | hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); |
f5bab222 TV |
197 | |
198 | /* disable and clear irqs */ | |
199 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); | |
200 | hdmi_wp_set_irqstatus(&hdmi.wp, | |
201 | hdmi_wp_get_irqstatus(&hdmi.wp)); | |
202 | ||
c84c3a5b | 203 | r = dss_pll_enable(&hdmi.pll.pll); |
f5bab222 | 204 | if (r) { |
c2fbd061 | 205 | DSSERR("Failed to enable PLL\n"); |
f5bab222 TV |
206 | goto err_pll_enable; |
207 | } | |
208 | ||
c84c3a5b | 209 | r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); |
c2fbd061 TV |
210 | if (r) { |
211 | DSSERR("Failed to configure PLL\n"); | |
212 | goto err_pll_cfg; | |
213 | } | |
214 | ||
c84c3a5b TV |
215 | r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco, |
216 | hdmi_cinfo.clkout[0]); | |
f5bab222 TV |
217 | if (r) { |
218 | DSSDBG("Failed to start PHY\n"); | |
219 | goto err_phy_cfg; | |
220 | } | |
221 | ||
222 | r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON); | |
223 | if (r) | |
224 | goto err_phy_pwr; | |
225 | ||
226 | hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); | |
227 | ||
228 | /* bypass TV gamma table */ | |
229 | dispc_enable_gamma_table(0); | |
230 | ||
231 | /* tv size */ | |
232 | dss_mgr_set_timings(mgr, p); | |
233 | ||
234 | r = hdmi_wp_video_start(&hdmi.wp); | |
235 | if (r) | |
236 | goto err_vid_enable; | |
237 | ||
238 | r = dss_mgr_enable(mgr); | |
239 | if (r) | |
240 | goto err_mgr_enable; | |
241 | ||
242 | hdmi_wp_set_irqenable(&hdmi.wp, | |
243 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); | |
244 | ||
245 | return 0; | |
246 | ||
247 | err_mgr_enable: | |
248 | hdmi_wp_video_stop(&hdmi.wp); | |
249 | err_vid_enable: | |
250 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); | |
251 | err_phy_pwr: | |
252 | err_phy_cfg: | |
c2fbd061 | 253 | err_pll_cfg: |
c84c3a5b | 254 | dss_pll_disable(&hdmi.pll.pll); |
f5bab222 TV |
255 | err_pll_enable: |
256 | hdmi_power_off_core(dssdev); | |
257 | return -EIO; | |
258 | } | |
259 | ||
260 | static void hdmi_power_off_full(struct omap_dss_device *dssdev) | |
261 | { | |
262 | struct omap_overlay_manager *mgr = hdmi.output.manager; | |
263 | ||
264 | hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); | |
265 | ||
266 | dss_mgr_disable(mgr); | |
267 | ||
268 | hdmi_wp_video_stop(&hdmi.wp); | |
269 | ||
270 | hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); | |
271 | ||
c84c3a5b | 272 | dss_pll_disable(&hdmi.pll.pll); |
f5bab222 TV |
273 | |
274 | hdmi_power_off_core(dssdev); | |
275 | } | |
276 | ||
277 | static int hdmi_display_check_timing(struct omap_dss_device *dssdev, | |
278 | struct omap_video_timings *timings) | |
279 | { | |
280 | struct omap_dss_device *out = &hdmi.output; | |
281 | ||
31dd0f4b TV |
282 | /* TODO: proper interlace support */ |
283 | if (timings->interlace) | |
284 | return -EINVAL; | |
285 | ||
f5bab222 TV |
286 | if (!dispc_mgr_timings_ok(out->dispc_channel, timings)) |
287 | return -EINVAL; | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | static void hdmi_display_set_timing(struct omap_dss_device *dssdev, | |
293 | struct omap_video_timings *timings) | |
294 | { | |
f5bab222 TV |
295 | mutex_lock(&hdmi.lock); |
296 | ||
769dcb11 | 297 | hdmi.cfg.timings = *timings; |
f5bab222 | 298 | |
769dcb11 | 299 | dispc_set_tv_pclk(timings->pixelclock); |
f5bab222 TV |
300 | |
301 | mutex_unlock(&hdmi.lock); | |
302 | } | |
303 | ||
304 | static void hdmi_display_get_timings(struct omap_dss_device *dssdev, | |
305 | struct omap_video_timings *timings) | |
306 | { | |
769dcb11 | 307 | *timings = hdmi.cfg.timings; |
f5bab222 TV |
308 | } |
309 | ||
310 | static void hdmi_dump_regs(struct seq_file *s) | |
311 | { | |
312 | mutex_lock(&hdmi.lock); | |
313 | ||
314 | if (hdmi_runtime_get()) { | |
315 | mutex_unlock(&hdmi.lock); | |
316 | return; | |
317 | } | |
318 | ||
319 | hdmi_wp_dump(&hdmi.wp, s); | |
320 | hdmi_pll_dump(&hdmi.pll, s); | |
321 | hdmi_phy_dump(&hdmi.phy, s); | |
322 | hdmi5_core_dump(&hdmi.core, s); | |
323 | ||
324 | hdmi_runtime_put(); | |
325 | mutex_unlock(&hdmi.lock); | |
326 | } | |
327 | ||
328 | static int read_edid(u8 *buf, int len) | |
329 | { | |
330 | int r; | |
331 | int idlemode; | |
332 | ||
333 | mutex_lock(&hdmi.lock); | |
334 | ||
335 | r = hdmi_runtime_get(); | |
336 | BUG_ON(r); | |
337 | ||
338 | idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); | |
339 | /* No-idle mode */ | |
340 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); | |
341 | ||
342 | r = hdmi5_read_edid(&hdmi.core, buf, len); | |
343 | ||
344 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); | |
345 | ||
346 | hdmi_runtime_put(); | |
347 | mutex_unlock(&hdmi.lock); | |
348 | ||
349 | return r; | |
350 | } | |
351 | ||
352 | static int hdmi_display_enable(struct omap_dss_device *dssdev) | |
353 | { | |
354 | struct omap_dss_device *out = &hdmi.output; | |
355 | int r = 0; | |
356 | ||
357 | DSSDBG("ENTER hdmi_display_enable\n"); | |
358 | ||
359 | mutex_lock(&hdmi.lock); | |
360 | ||
361 | if (out == NULL || out->manager == NULL) { | |
362 | DSSERR("failed to enable display: no output/manager\n"); | |
363 | r = -ENODEV; | |
364 | goto err0; | |
365 | } | |
366 | ||
367 | r = hdmi_power_on_full(dssdev); | |
368 | if (r) { | |
369 | DSSERR("failed to power on device\n"); | |
370 | goto err0; | |
371 | } | |
372 | ||
45302d7e JS |
373 | hdmi.display_enabled = true; |
374 | ||
f5bab222 TV |
375 | mutex_unlock(&hdmi.lock); |
376 | return 0; | |
377 | ||
378 | err0: | |
379 | mutex_unlock(&hdmi.lock); | |
380 | return r; | |
381 | } | |
382 | ||
383 | static void hdmi_display_disable(struct omap_dss_device *dssdev) | |
384 | { | |
385 | DSSDBG("Enter hdmi_display_disable\n"); | |
386 | ||
387 | mutex_lock(&hdmi.lock); | |
388 | ||
45302d7e JS |
389 | if (hdmi.audio_pdev && hdmi.audio_abort_cb) |
390 | hdmi.audio_abort_cb(&hdmi.audio_pdev->dev); | |
391 | ||
f5bab222 TV |
392 | hdmi_power_off_full(dssdev); |
393 | ||
45302d7e JS |
394 | hdmi.display_enabled = false; |
395 | ||
f5bab222 TV |
396 | mutex_unlock(&hdmi.lock); |
397 | } | |
398 | ||
399 | static int hdmi_core_enable(struct omap_dss_device *dssdev) | |
400 | { | |
401 | int r = 0; | |
402 | ||
403 | DSSDBG("ENTER omapdss_hdmi_core_enable\n"); | |
404 | ||
405 | mutex_lock(&hdmi.lock); | |
406 | ||
407 | r = hdmi_power_on_core(dssdev); | |
408 | if (r) { | |
409 | DSSERR("failed to power on device\n"); | |
410 | goto err0; | |
411 | } | |
412 | ||
413 | mutex_unlock(&hdmi.lock); | |
414 | return 0; | |
415 | ||
416 | err0: | |
417 | mutex_unlock(&hdmi.lock); | |
418 | return r; | |
419 | } | |
420 | ||
421 | static void hdmi_core_disable(struct omap_dss_device *dssdev) | |
422 | { | |
423 | DSSDBG("Enter omapdss_hdmi_core_disable\n"); | |
424 | ||
425 | mutex_lock(&hdmi.lock); | |
426 | ||
427 | hdmi_power_off_core(dssdev); | |
428 | ||
429 | mutex_unlock(&hdmi.lock); | |
430 | } | |
431 | ||
f5bab222 TV |
432 | static int hdmi_connect(struct omap_dss_device *dssdev, |
433 | struct omap_dss_device *dst) | |
434 | { | |
435 | struct omap_overlay_manager *mgr; | |
436 | int r; | |
437 | ||
438 | r = hdmi_init_regulator(); | |
439 | if (r) | |
440 | return r; | |
441 | ||
442 | mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); | |
443 | if (!mgr) | |
444 | return -ENODEV; | |
445 | ||
446 | r = dss_mgr_connect(mgr, dssdev); | |
447 | if (r) | |
448 | return r; | |
449 | ||
450 | r = omapdss_output_set_device(dssdev, dst); | |
451 | if (r) { | |
452 | DSSERR("failed to connect output to new device: %s\n", | |
453 | dst->name); | |
454 | dss_mgr_disconnect(mgr, dssdev); | |
455 | return r; | |
456 | } | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static void hdmi_disconnect(struct omap_dss_device *dssdev, | |
462 | struct omap_dss_device *dst) | |
463 | { | |
464 | WARN_ON(dst != dssdev->dst); | |
465 | ||
466 | if (dst != dssdev->dst) | |
467 | return; | |
468 | ||
469 | omapdss_output_unset_device(dssdev); | |
470 | ||
471 | if (dssdev->manager) | |
472 | dss_mgr_disconnect(dssdev->manager, dssdev); | |
473 | } | |
474 | ||
475 | static int hdmi_read_edid(struct omap_dss_device *dssdev, | |
476 | u8 *edid, int len) | |
477 | { | |
478 | bool need_enable; | |
479 | int r; | |
480 | ||
481 | need_enable = hdmi.core_enabled == false; | |
482 | ||
483 | if (need_enable) { | |
484 | r = hdmi_core_enable(dssdev); | |
485 | if (r) | |
486 | return r; | |
487 | } | |
488 | ||
489 | r = read_edid(edid, len); | |
490 | ||
491 | if (need_enable) | |
492 | hdmi_core_disable(dssdev); | |
493 | ||
494 | return r; | |
495 | } | |
496 | ||
769dcb11 TV |
497 | static int hdmi_set_infoframe(struct omap_dss_device *dssdev, |
498 | const struct hdmi_avi_infoframe *avi) | |
499 | { | |
500 | hdmi.cfg.infoframe = *avi; | |
501 | return 0; | |
502 | } | |
503 | ||
504 | static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, | |
505 | bool hdmi_mode) | |
506 | { | |
507 | hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; | |
508 | return 0; | |
509 | } | |
510 | ||
f5bab222 TV |
511 | static const struct omapdss_hdmi_ops hdmi_ops = { |
512 | .connect = hdmi_connect, | |
513 | .disconnect = hdmi_disconnect, | |
514 | ||
515 | .enable = hdmi_display_enable, | |
516 | .disable = hdmi_display_disable, | |
517 | ||
518 | .check_timings = hdmi_display_check_timing, | |
519 | .set_timings = hdmi_display_set_timing, | |
520 | .get_timings = hdmi_display_get_timings, | |
521 | ||
522 | .read_edid = hdmi_read_edid, | |
769dcb11 TV |
523 | .set_infoframe = hdmi_set_infoframe, |
524 | .set_hdmi_mode = hdmi_set_hdmi_mode, | |
f5bab222 TV |
525 | }; |
526 | ||
527 | static void hdmi_init_output(struct platform_device *pdev) | |
528 | { | |
529 | struct omap_dss_device *out = &hdmi.output; | |
530 | ||
531 | out->dev = &pdev->dev; | |
532 | out->id = OMAP_DSS_OUTPUT_HDMI; | |
533 | out->output_type = OMAP_DISPLAY_TYPE_HDMI; | |
534 | out->name = "hdmi.0"; | |
535 | out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; | |
536 | out->ops.hdmi = &hdmi_ops; | |
537 | out->owner = THIS_MODULE; | |
538 | ||
539 | omapdss_register_output(out); | |
540 | } | |
541 | ||
39c1b7bf | 542 | static void hdmi_uninit_output(struct platform_device *pdev) |
f5bab222 TV |
543 | { |
544 | struct omap_dss_device *out = &hdmi.output; | |
545 | ||
546 | omapdss_unregister_output(out); | |
547 | } | |
548 | ||
549 | static int hdmi_probe_of(struct platform_device *pdev) | |
550 | { | |
551 | struct device_node *node = pdev->dev.of_node; | |
552 | struct device_node *ep; | |
553 | int r; | |
554 | ||
555 | ep = omapdss_of_get_first_endpoint(node); | |
556 | if (!ep) | |
557 | return 0; | |
558 | ||
559 | r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); | |
560 | if (r) | |
561 | goto err; | |
562 | ||
563 | of_node_put(ep); | |
564 | return 0; | |
565 | ||
566 | err: | |
567 | of_node_put(ep); | |
568 | return r; | |
569 | } | |
570 | ||
45302d7e JS |
571 | /* Audio callbacks */ |
572 | static int hdmi_audio_startup(struct device *dev, | |
573 | void (*abort_cb)(struct device *dev)) | |
574 | { | |
575 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
576 | int ret = 0; | |
577 | ||
578 | mutex_lock(&hd->lock); | |
579 | ||
580 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
581 | ret = -EPERM; | |
582 | goto out; | |
583 | } | |
584 | ||
585 | hd->audio_abort_cb = abort_cb; | |
586 | ||
587 | out: | |
588 | mutex_unlock(&hd->lock); | |
589 | ||
590 | return ret; | |
591 | } | |
592 | ||
593 | static int hdmi_audio_shutdown(struct device *dev) | |
594 | { | |
595 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
596 | ||
597 | mutex_lock(&hd->lock); | |
598 | hd->audio_abort_cb = NULL; | |
599 | mutex_unlock(&hd->lock); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | static int hdmi_audio_start(struct device *dev) | |
605 | { | |
606 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
607 | ||
608 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
609 | WARN_ON(!hd->display_enabled); | |
610 | ||
2d7639bc JS |
611 | /* No-idle while playing audio, store the old value */ |
612 | hd->wp_idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); | |
613 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); | |
614 | ||
45302d7e JS |
615 | hdmi_wp_audio_enable(&hd->wp, true); |
616 | hdmi_wp_audio_core_req_enable(&hd->wp, true); | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
621 | static void hdmi_audio_stop(struct device *dev) | |
622 | { | |
623 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
624 | ||
625 | WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); | |
626 | WARN_ON(!hd->display_enabled); | |
627 | ||
628 | hdmi_wp_audio_core_req_enable(&hd->wp, false); | |
629 | hdmi_wp_audio_enable(&hd->wp, false); | |
2d7639bc JS |
630 | |
631 | /* Playback stopped, restore original idlemode */ | |
632 | REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2); | |
45302d7e JS |
633 | } |
634 | ||
635 | static int hdmi_audio_config(struct device *dev, | |
636 | struct omap_dss_audio *dss_audio) | |
637 | { | |
638 | struct omap_hdmi *hd = dev_get_drvdata(dev); | |
639 | int ret; | |
640 | ||
641 | mutex_lock(&hd->lock); | |
642 | ||
643 | if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { | |
644 | ret = -EPERM; | |
645 | goto out; | |
646 | } | |
647 | ||
648 | ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, | |
649 | hd->cfg.timings.pixelclock); | |
650 | ||
651 | out: | |
652 | mutex_unlock(&hd->lock); | |
653 | ||
654 | return ret; | |
655 | } | |
656 | ||
657 | static const struct omap_hdmi_audio_ops hdmi_audio_ops = { | |
658 | .audio_startup = hdmi_audio_startup, | |
659 | .audio_shutdown = hdmi_audio_shutdown, | |
660 | .audio_start = hdmi_audio_start, | |
661 | .audio_stop = hdmi_audio_stop, | |
662 | .audio_config = hdmi_audio_config, | |
663 | }; | |
664 | ||
665 | static int hdmi_audio_register(struct device *dev) | |
666 | { | |
667 | struct omap_hdmi_audio_pdata pdata = { | |
668 | .dev = dev, | |
669 | .dss_version = omapdss_get_version(), | |
670 | .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), | |
671 | .ops = &hdmi_audio_ops, | |
672 | }; | |
673 | ||
674 | hdmi.audio_pdev = platform_device_register_data( | |
675 | dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO, | |
676 | &pdata, sizeof(pdata)); | |
677 | ||
678 | if (IS_ERR(hdmi.audio_pdev)) | |
679 | return PTR_ERR(hdmi.audio_pdev); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
f5bab222 | 684 | /* HDMI HW IP initialisation */ |
736e60dd | 685 | static int hdmi5_bind(struct device *dev, struct device *master, void *data) |
f5bab222 | 686 | { |
736e60dd | 687 | struct platform_device *pdev = to_platform_device(dev); |
f5bab222 TV |
688 | int r; |
689 | int irq; | |
690 | ||
691 | hdmi.pdev = pdev; | |
945514b5 | 692 | dev_set_drvdata(&pdev->dev, &hdmi); |
f5bab222 TV |
693 | |
694 | mutex_init(&hdmi.lock); | |
695 | ||
696 | if (pdev->dev.of_node) { | |
697 | r = hdmi_probe_of(pdev); | |
698 | if (r) | |
699 | return r; | |
700 | } | |
701 | ||
702 | r = hdmi_wp_init(pdev, &hdmi.wp); | |
703 | if (r) | |
704 | return r; | |
705 | ||
03aafa2c | 706 | r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); |
f5bab222 TV |
707 | if (r) |
708 | return r; | |
709 | ||
710 | r = hdmi_phy_init(pdev, &hdmi.phy); | |
711 | if (r) | |
c84c3a5b | 712 | goto err; |
f5bab222 TV |
713 | |
714 | r = hdmi5_core_init(pdev, &hdmi.core); | |
715 | if (r) | |
c84c3a5b | 716 | goto err; |
f5bab222 TV |
717 | |
718 | irq = platform_get_irq(pdev, 0); | |
719 | if (irq < 0) { | |
720 | DSSERR("platform_get_irq failed\n"); | |
c84c3a5b TV |
721 | r = -ENODEV; |
722 | goto err; | |
f5bab222 TV |
723 | } |
724 | ||
725 | r = devm_request_threaded_irq(&pdev->dev, irq, | |
726 | NULL, hdmi_irq_handler, | |
727 | IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); | |
728 | if (r) { | |
729 | DSSERR("HDMI IRQ request failed\n"); | |
c84c3a5b | 730 | goto err; |
f5bab222 TV |
731 | } |
732 | ||
733 | pm_runtime_enable(&pdev->dev); | |
734 | ||
735 | hdmi_init_output(pdev); | |
736 | ||
45302d7e JS |
737 | r = hdmi_audio_register(&pdev->dev); |
738 | if (r) { | |
739 | DSSERR("Registering HDMI audio failed %d\n", r); | |
740 | hdmi_uninit_output(pdev); | |
741 | pm_runtime_disable(&pdev->dev); | |
742 | return r; | |
743 | } | |
744 | ||
f5bab222 TV |
745 | dss_debugfs_create_file("hdmi", hdmi_dump_regs); |
746 | ||
747 | return 0; | |
c84c3a5b TV |
748 | err: |
749 | hdmi_pll_uninit(&hdmi.pll); | |
750 | return r; | |
f5bab222 TV |
751 | } |
752 | ||
736e60dd | 753 | static void hdmi5_unbind(struct device *dev, struct device *master, void *data) |
f5bab222 | 754 | { |
736e60dd TV |
755 | struct platform_device *pdev = to_platform_device(dev); |
756 | ||
45302d7e JS |
757 | if (hdmi.audio_pdev) |
758 | platform_device_unregister(hdmi.audio_pdev); | |
759 | ||
f5bab222 TV |
760 | hdmi_uninit_output(pdev); |
761 | ||
c84c3a5b TV |
762 | hdmi_pll_uninit(&hdmi.pll); |
763 | ||
f5bab222 | 764 | pm_runtime_disable(&pdev->dev); |
736e60dd TV |
765 | } |
766 | ||
767 | static const struct component_ops hdmi5_component_ops = { | |
768 | .bind = hdmi5_bind, | |
769 | .unbind = hdmi5_unbind, | |
770 | }; | |
f5bab222 | 771 | |
736e60dd TV |
772 | static int hdmi5_probe(struct platform_device *pdev) |
773 | { | |
774 | return component_add(&pdev->dev, &hdmi5_component_ops); | |
775 | } | |
776 | ||
777 | static int hdmi5_remove(struct platform_device *pdev) | |
778 | { | |
779 | component_del(&pdev->dev, &hdmi5_component_ops); | |
f5bab222 TV |
780 | return 0; |
781 | } | |
782 | ||
783 | static int hdmi_runtime_suspend(struct device *dev) | |
784 | { | |
f5bab222 TV |
785 | dispc_runtime_put(); |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static int hdmi_runtime_resume(struct device *dev) | |
791 | { | |
792 | int r; | |
793 | ||
794 | r = dispc_runtime_get(); | |
795 | if (r < 0) | |
796 | return r; | |
797 | ||
f5bab222 TV |
798 | return 0; |
799 | } | |
800 | ||
801 | static const struct dev_pm_ops hdmi_pm_ops = { | |
802 | .runtime_suspend = hdmi_runtime_suspend, | |
803 | .runtime_resume = hdmi_runtime_resume, | |
804 | }; | |
805 | ||
806 | static const struct of_device_id hdmi_of_match[] = { | |
807 | { .compatible = "ti,omap5-hdmi", }, | |
adb5ff83 | 808 | { .compatible = "ti,dra7-hdmi", }, |
f5bab222 TV |
809 | {}, |
810 | }; | |
811 | ||
812 | static struct platform_driver omapdss_hdmihw_driver = { | |
736e60dd TV |
813 | .probe = hdmi5_probe, |
814 | .remove = hdmi5_remove, | |
f5bab222 TV |
815 | .driver = { |
816 | .name = "omapdss_hdmi5", | |
f5bab222 TV |
817 | .pm = &hdmi_pm_ops, |
818 | .of_match_table = hdmi_of_match, | |
422ccbd5 | 819 | .suppress_bind_attrs = true, |
f5bab222 TV |
820 | }, |
821 | }; | |
822 | ||
823 | int __init hdmi5_init_platform_driver(void) | |
824 | { | |
825 | return platform_driver_register(&omapdss_hdmihw_driver); | |
826 | } | |
827 | ||
ede92695 | 828 | void hdmi5_uninit_platform_driver(void) |
f5bab222 TV |
829 | { |
830 | platform_driver_unregister(&omapdss_hdmihw_driver); | |
831 | } |