[linux-2.6-block.git] / drivers / video / fbdev / omap2 / dss / dss.h

/*
 * linux/drivers/video/omap2/dss/dss.h
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * Some code and ideas taken from drivers/video/omap/ driver
 * by Imre Deak.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP2_DSS_H
#define __OMAP2_DSS_H

#include <linux/interrupt.h>

#ifdef pr_fmt
#undef pr_fmt
#endif

#ifdef DSS_SUBSYS_NAME
#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
#else
#define pr_fmt(fmt) fmt
#endif

#define DSSDBG(format, ...) \
	pr_debug(format, ## __VA_ARGS__)

#ifdef DSS_SUBSYS_NAME
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	## __VA_ARGS__)
#else
#define DSSERR(format, ...) \
	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSINFO(format, ...) \
	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
#endif

#ifdef DSS_SUBSYS_NAME
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	## __VA_ARGS__)
#else
#define DSSWARN(format, ...) \
	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
#endif

/* OMAP TRM gives bitfields as start:end, where start is the higher bit
   number. For example 7:0 */
#define FLD_MASK(start, end)	(((1 << ((start) - (end) + 1)) - 1) << (end))
#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
#define FLD_MOD(orig, val, start, end) \
	(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))

enum dss_io_pad_mode {
	DSS_IO_PAD_MODE_RESET,
	DSS_IO_PAD_MODE_RFBI,
	DSS_IO_PAD_MODE_BYPASS,
};

enum dss_hdmi_venc_clk_source_select {
	DSS_VENC_TV_CLK = 0,
	DSS_HDMI_M_PCLK = 1,
};

enum dss_dsi_content_type {
	DSS_DSI_CONTENT_DCS,
	DSS_DSI_CONTENT_GENERIC,
};

enum dss_writeback_channel {
	DSS_WB_LCD1_MGR =	0,
	DSS_WB_LCD2_MGR =	1,
	DSS_WB_TV_MGR =		2,
	DSS_WB_OVL0 =		3,
	DSS_WB_OVL1 =		4,
	DSS_WB_OVL2 =		5,
	DSS_WB_OVL3 =		6,
	DSS_WB_LCD3_MGR =	7,
};

struct dss_pll;

#define DSS_PLL_MAX_HSDIVS 4

/*
 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
 * Type-B PLLs: clkout[0] refers to m2.
 */
struct dss_pll_clock_info {
	/* rates that we get with dividers below */
	unsigned long fint;
	unsigned long clkdco;
	unsigned long clkout[DSS_PLL_MAX_HSDIVS];

	/* dividers */
	u16 n;
	u16 m;
	u32 mf;
	u16 mX[DSS_PLL_MAX_HSDIVS];
	u16 sd;
};

struct dss_pll_ops {
	int (*enable)(struct dss_pll *pll);
	void (*disable)(struct dss_pll *pll);
	int (*set_config)(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
};

struct dss_pll_hw {
	unsigned n_max;
	unsigned m_min;
	unsigned m_max;
	unsigned mX_max;

	unsigned long fint_min, fint_max;
	unsigned long clkdco_min, clkdco_low, clkdco_max;

	u8 n_msb, n_lsb;
	u8 m_msb, m_lsb;
	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];

	bool has_stopmode;
	bool has_freqsel;
	bool has_selfreqdco;
	bool has_refsel;
};

struct dss_pll {
	const char *name;

	struct clk *clkin;
	struct regulator *regulator;

	void __iomem *base;

	const struct dss_pll_hw *hw;

	const struct dss_pll_ops *ops;

	struct dss_pll_clock_info cinfo;
};

struct dispc_clock_info {
	/* rates that we get with dividers below */
	unsigned long lck;
	unsigned long pck;

	/* dividers */
	u16 lck_div;
	u16 pck_div;
};

struct dss_lcd_mgr_config {
	enum dss_io_pad_mode io_pad_mode;

	bool stallmode;
	bool fifohandcheck;

	struct dispc_clock_info clock_info;

	int video_port_width;

	int lcden_sig_polarity;
};

struct seq_file;
struct platform_device;

/* core */
struct platform_device *dss_get_core_pdev(void);
int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));

/* display */
int dss_suspend_all_devices(void);
int dss_resume_all_devices(void);
void dss_disable_all_devices(void);

int display_init_sysfs(struct platform_device *pdev);
void display_uninit_sysfs(struct platform_device *pdev);

/* manager */
int dss_init_overlay_managers(void);
void dss_uninit_overlay_managers(void);
int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
		const struct omap_overlay_manager_info *info);
int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
		const struct omap_video_timings *timings);
int dss_mgr_check(struct omap_overlay_manager *mgr,
		struct omap_overlay_manager_info *info,
		const struct omap_video_timings *mgr_timings,
		const struct dss_lcd_mgr_config *config,
		struct omap_overlay_info **overlay_infos);

static inline bool dss_mgr_is_lcd(enum omap_channel id)
{
	if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
			id == OMAP_DSS_CHANNEL_LCD3)
		return true;
	else
		return false;
}

int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
		struct platform_device *pdev);
void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);

/* overlay */
void dss_init_overlays(struct platform_device *pdev);
void dss_uninit_overlays(struct platform_device *pdev);
void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
int dss_ovl_simple_check(struct omap_overlay *ovl,
		const struct omap_overlay_info *info);
int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
		const struct omap_video_timings *mgr_timings);
bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
		enum omap_color_mode mode);
int dss_overlay_kobj_init(struct omap_overlay *ovl,
		struct platform_device *pdev);
void dss_overlay_kobj_uninit(struct omap_overlay *ovl);

/* DSS */
int dss_init_platform_driver(void) __init;
void dss_uninit_platform_driver(void);

unsigned long dss_get_dispc_clk_rate(void);
int dss_dpi_select_source(int port, enum omap_channel channel);
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);

/* dss-of */
struct device_node *dss_of_port_get_parent_device(struct device_node *port);
u32 dss_of_port_get_port_number(struct device_node *port);

#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
void dss_debug_dump_clocks(struct seq_file *s);
#endif

void dss_sdi_init(int datapairs);
int dss_sdi_enable(void);
void dss_sdi_disable(void);

void dss_select_dsi_clk_source(int dsi_module,
		enum omap_dss_clk_source clk_src);
void dss_select_lcd_clk_source(enum omap_channel channel,
		enum omap_dss_clk_source clk_src);
enum omap_dss_clk_source dss_get_dispc_clk_source(void);
enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);

void dss_set_venc_output(enum omap_dss_venc_type type);
void dss_set_dac_pwrdn_bgz(bool enable);

int dss_set_fck_rate(unsigned long rate);

typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
bool dss_div_calc(unsigned long pck, unsigned long fck_min,
		dss_div_calc_func func, void *data);

/* SDI */
int sdi_init_platform_driver(void) __init;
void sdi_uninit_platform_driver(void) __exit;

#ifdef CONFIG_OMAP2_DSS_SDI
int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init;
void sdi_uninit_port(struct device_node *port) __exit;
#else
static inline int __init sdi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void __exit sdi_uninit_port(struct device_node *port)
{
}
#endif

/* DSI */

#ifdef CONFIG_OMAP2_DSS_DSI

struct dentry;
struct file_operations;

int dsi_init_platform_driver(void) __init;
void dsi_uninit_platform_driver(void) __exit;

void dsi_dump_clocks(struct seq_file *s);

void dsi_irq_handler(void);
u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);

#else
static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
	WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
	return 0;
}
#endif

/* DPI */
int dpi_init_platform_driver(void) __init;
void dpi_uninit_platform_driver(void) __exit;

#ifdef CONFIG_OMAP2_DSS_DPI
int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init;
void dpi_uninit_port(struct device_node *port) __exit;
#else
static inline int __init dpi_init_port(struct platform_device *pdev,
		struct device_node *port)
{
	return 0;
}
static inline void __exit dpi_uninit_port(struct device_node *port)
{
}
#endif

/* DISPC */
int dispc_init_platform_driver(void) __init;
void dispc_uninit_platform_driver(void) __exit;
void dispc_dump_clocks(struct seq_file *s);

void dispc_enable_sidle(void);
void dispc_disable_sidle(void);

void dispc_lcd_enable_signal(bool enable);
void dispc_pck_free_enable(bool enable);
void dispc_enable_fifomerge(bool enable);
void dispc_enable_gamma_table(bool enable);
void dispc_set_loadmode(enum omap_dss_load_mode mode);

typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
		unsigned long pck, void *data);
bool dispc_div_calc(unsigned long dispc,
		unsigned long pck_min, unsigned long pck_max,
		dispc_div_calc_func func, void *data);

bool dispc_mgr_timings_ok(enum omap_channel channel,
		const struct omap_video_timings *timings);
unsigned long dispc_fclk_rate(void);
int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
		struct dispc_clock_info *cinfo);


void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
		u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
		bool manual_update);

unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
unsigned long dispc_core_clk_rate(void);
void dispc_mgr_set_clock_div(enum omap_channel channel,
		const struct dispc_clock_info *cinfo);
int dispc_mgr_get_clock_div(enum omap_channel channel,
		struct dispc_clock_info *cinfo);
void dispc_set_tv_pclk(unsigned long pclk);

u32 dispc_wb_get_framedone_irq(void);
bool dispc_wb_go_busy(void);
void dispc_wb_go(void);
void dispc_wb_enable(bool enable);
bool dispc_wb_is_enabled(void);
void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
		bool mem_to_mem, const struct omap_video_timings *timings);

/* VENC */
int venc_init_platform_driver(void) __init;
void venc_uninit_platform_driver(void) __exit;

/* HDMI */
int hdmi4_init_platform_driver(void) __init;
void hdmi4_uninit_platform_driver(void) __exit;

int hdmi5_init_platform_driver(void) __init;
void hdmi5_uninit_platform_driver(void) __exit;

/* RFBI */
int rfbi_init_platform_driver(void) __init;
void rfbi_uninit_platform_driver(void) __exit;


#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
{
	int b;
	for (b = 0; b < 32; ++b) {
		if (irqstatus & (1 << b))
			irq_arr[b]++;
	}
}
#endif

/* PLL */
typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
		unsigned long clkdco, void *data);
typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
		void *data);

int dss_pll_register(struct dss_pll *pll);
void dss_pll_unregister(struct dss_pll *pll);
struct dss_pll *dss_pll_find(const char *name);
int dss_pll_enable(struct dss_pll *pll);
void dss_pll_disable(struct dss_pll *pll);
int dss_pll_set_config(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);

bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
		unsigned long out_min, unsigned long out_max,
		dss_hsdiv_calc_func func, void *data);
bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
		unsigned long pll_min, unsigned long pll_max,
		dss_pll_calc_func func, void *data);
int dss_pll_write_config_type_a(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);
int dss_pll_write_config_type_b(struct dss_pll *pll,
		const struct dss_pll_clock_info *cinfo);

#endif
Commit	Line	Data
559d6701 TV	1	/*
	2	* linux/drivers/video/omap2/dss/dss.h
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
	5	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	6	*
	7	* Some code and ideas taken from drivers/video/omap/ driver
	8	* by Imre Deak.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along with
	20	* this program. If not, see <http://www.gnu.org/licenses/>.
	21	*/
	22
	23	#ifndef __OMAP2_DSS_H
	24	#define __OMAP2_DSS_H
	25
96e2e637 TV	26	#include <linux/interrupt.h>
96e2e637 TV	27
702d267e CM	28	#ifdef pr_fmt
702d267e CM	29	#undef pr_fmt
559d6701 TV	30	#endif
559d6701 TV	31
702d267e CM	32	#ifdef DSS_SUBSYS_NAME
	33	#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
	34	#else
	35	#define pr_fmt(fmt) fmt
559d6701 TV	36	#endif
559d6701 TV	37
702d267e CM	38	#define DSSDBG(format, ...) \
702d267e CM	39	pr_debug(format, ## __VA_ARGS__)
559d6701 TV	40
	41	#ifdef DSS_SUBSYS_NAME
	42	#define DSSERR(format, ...) \
	43	printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
	44	## __VA_ARGS__)
	45	#else
	46	#define DSSERR(format, ...) \
	47	printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
	48	#endif
	49
	50	#ifdef DSS_SUBSYS_NAME
	51	#define DSSINFO(format, ...) \
	52	printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
	53	## __VA_ARGS__)
	54	#else
	55	#define DSSINFO(format, ...) \
	56	printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
	57	#endif
	58
	59	#ifdef DSS_SUBSYS_NAME
	60	#define DSSWARN(format, ...) \
	61	printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
	62	## __VA_ARGS__)
	63	#else
	64	#define DSSWARN(format, ...) \
	65	printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
	66	#endif
	67
	68	/* OMAP TRM gives bitfields as start:end, where start is the higher bit
	69	number. For example 7:0 */
	70	#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
	71	#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
	72	#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
	73	#define FLD_MOD(orig, val, start, end) \
	74	(((orig) & ~FLD_MASK(start, end)) \| FLD_VAL(val, start, end))
	75
569969d6 AT	76	enum dss_io_pad_mode {
	77	DSS_IO_PAD_MODE_RESET,
	78	DSS_IO_PAD_MODE_RFBI,
	79	DSS_IO_PAD_MODE_BYPASS,
559d6701 TV	80	};
559d6701 TV	81
7ed024aa M	82	enum dss_hdmi_venc_clk_source_select {
	83	DSS_VENC_TV_CLK = 0,
	84	DSS_HDMI_M_PCLK = 1,
	85	};
	86
6ff8aa31 AT	87	enum dss_dsi_content_type {
	88	DSS_DSI_CONTENT_DCS,
	89	DSS_DSI_CONTENT_GENERIC,
	90	};
	91
d9ac773c AT	92	enum dss_writeback_channel {
	93	DSS_WB_LCD1_MGR = 0,
	94	DSS_WB_LCD2_MGR = 1,
	95	DSS_WB_TV_MGR = 2,
	96	DSS_WB_OVL0 = 3,
	97	DSS_WB_OVL1 = 4,
	98	DSS_WB_OVL2 = 5,
	99	DSS_WB_OVL3 = 6,
	100	DSS_WB_LCD3_MGR = 7,
	101	};
	102
0a20170a TV	103	struct dss_pll;
	104
	105	#define DSS_PLL_MAX_HSDIVS 4
	106
	107	/*
	108	* Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
	109	* Type-B PLLs: clkout[0] refers to m2.
	110	*/
	111	struct dss_pll_clock_info {
	112	/* rates that we get with dividers below */
	113	unsigned long fint;
	114	unsigned long clkdco;
	115	unsigned long clkout[DSS_PLL_MAX_HSDIVS];
	116
	117	/* dividers */
	118	u16 n;
	119	u16 m;
	120	u32 mf;
	121	u16 mX[DSS_PLL_MAX_HSDIVS];
	122	u16 sd;
	123	};
	124
	125	struct dss_pll_ops {
	126	int (enable)(struct dss_pll pll);
	127	void (disable)(struct dss_pll pll);
	128	int (set_config)(struct dss_pll pll,
	129	const struct dss_pll_clock_info *cinfo);
	130	};
	131
	132	struct dss_pll_hw {
	133	unsigned n_max;
	134	unsigned m_min;
	135	unsigned m_max;
	136	unsigned mX_max;
	137
	138	unsigned long fint_min, fint_max;
	139	unsigned long clkdco_min, clkdco_low, clkdco_max;
	140
	141	u8 n_msb, n_lsb;
	142	u8 m_msb, m_lsb;
	143	u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
	144
	145	bool has_stopmode;
	146	bool has_freqsel;
	147	bool has_selfreqdco;
	148	bool has_refsel;
	149	};
	150
	151	struct dss_pll {
	152	const char *name;
	153
	154	struct clk *clkin;
	155	struct regulator *regulator;
	156
	157	void __iomem *base;
	158
	159	const struct dss_pll_hw *hw;
	160
	161	const struct dss_pll_ops *ops;
	162
	163	struct dss_pll_clock_info cinfo;
	164	};
	165
559d6701 TV	166	struct dispc_clock_info {
	167	/* rates that we get with dividers below */
	168	unsigned long lck;
	169	unsigned long pck;
	170
	171	/* dividers */
	172	u16 lck_div;
	173	u16 pck_div;
	174	};
	175
c56fb3ef AT	176	struct dss_lcd_mgr_config {
	177	enum dss_io_pad_mode io_pad_mode;
	178
	179	bool stallmode;
	180	bool fifohandcheck;
	181
	182	struct dispc_clock_info clock_info;
	183
	184	int video_port_width;
	185
	186	int lcden_sig_polarity;
	187	};
	188
559d6701 TV	189	struct seq_file;
	190	struct platform_device;
	191
	192	/* core */
8f46efad	193	struct platform_device *dss_get_core_pdev(void);
00928eaf TV	194	int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
00928eaf TV	195	void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
a8081d31	196	int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
e40402cf	197	int dss_debugfs_create_file(const char name, void (write)(struct seq_file *));
559d6701 TV	198
	199	/* display */
	200	int dss_suspend_all_devices(void);
	201	int dss_resume_all_devices(void);
	202	void dss_disable_all_devices(void);
	203
94140f0d TV	204	int display_init_sysfs(struct platform_device *pdev);
94140f0d TV	205	void display_uninit_sysfs(struct platform_device *pdev);
559d6701 TV	206
559d6701 TV	207	/* manager */
7f7cdbd6 TV	208	int dss_init_overlay_managers(void);
	209	void dss_uninit_overlay_managers(void);
	210	int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
	211	void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
54540d41 TV	212	int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
54540d41 TV	213	const struct omap_overlay_manager_info *info);
b917fa39 AT	214	int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
b917fa39 AT	215	const struct omap_video_timings *timings);
6ac48d1e	216	int dss_mgr_check(struct omap_overlay_manager *mgr,
6ac48d1e	217	struct omap_overlay_manager_info *info,
228b2134	218	const struct omap_video_timings *mgr_timings,
6e543595	219	const struct dss_lcd_mgr_config *config,
6ac48d1e	220	struct omap_overlay_info **overlay_infos);
559d6701	221
f476ae9d AT	222	static inline bool dss_mgr_is_lcd(enum omap_channel id)
	223	{
	224	if (id == OMAP_DSS_CHANNEL_LCD \|\| id == OMAP_DSS_CHANNEL_LCD2 \|\|
	225	id == OMAP_DSS_CHANNEL_LCD3)
	226	return true;
	227	else
	228	return false;
	229	}
	230
f6a0492e TV	231	int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
	232	struct platform_device *pdev);
	233	void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
	234
559d6701 TV	235	/* overlay */
	236	void dss_init_overlays(struct platform_device *pdev);
	237	void dss_uninit_overlays(struct platform_device *pdev);
559d6701	238	void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
54540d41 TV	239	int dss_ovl_simple_check(struct omap_overlay *ovl,
54540d41 TV	240	const struct omap_overlay_info *info);
228b2134 AT	241	int dss_ovl_check(struct omap_overlay ovl, struct omap_overlay_info info,
228b2134 AT	242	const struct omap_video_timings *mgr_timings);
6c6f510a AT	243	bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
6c6f510a AT	244	enum omap_color_mode mode);
91691516 TV	245	int dss_overlay_kobj_init(struct omap_overlay *ovl,
	246	struct platform_device *pdev);
	247	void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
559d6701 TV	248
559d6701 TV	249	/* DSS */
6e7e8f06	250	int dss_init_platform_driver(void) __init;
96c401bc	251	void dss_uninit_platform_driver(void);
559d6701	252
5aaee69d	253	unsigned long dss_get_dispc_clk_rate(void);
064c2a47	254	int dss_dpi_select_source(int port, enum omap_channel channel);
7ed024aa	255	void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
4a61e267	256	enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
89a35e51	257	const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
8b9cb3a8	258	void dss_dump_clocks(struct seq_file *s);
559d6701	259
ef691ff4 AT	260	/* dss-of */
	261	struct device_node dss_of_port_get_parent_device(struct device_node port);
	262	u32 dss_of_port_get_port_number(struct device_node *port);
	263
1b3bcb33	264	#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
8b9cb3a8 SG	265	void dss_debug_dump_clocks(struct seq_file *s);
8b9cb3a8 SG	266	#endif
559d6701	267
889b4fd7	268	void dss_sdi_init(int datapairs);
559d6701 TV	269	int dss_sdi_enable(void);
	270	void dss_sdi_disable(void);
	271
5a8b572d AT	272	void dss_select_dsi_clk_source(int dsi_module,
5a8b572d AT	273	enum omap_dss_clk_source clk_src);
ea75159e	274	void dss_select_lcd_clk_source(enum omap_channel channel,
89a35e51 AT	275	enum omap_dss_clk_source clk_src);
89a35e51 AT	276	enum omap_dss_clk_source dss_get_dispc_clk_source(void);
5a8b572d	277	enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
89a35e51	278	enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
2f18c4d8	279
559d6701 TV	280	void dss_set_venc_output(enum omap_dss_venc_type type);
	281	void dss_set_dac_pwrdn_bgz(bool enable);
	282
d0f58bd3	283	int dss_set_fck_rate(unsigned long rate);
559d6701	284
d0f58bd3	285	typedef bool (dss_div_calc_func)(unsigned long fck, void data);
688af02d TV	286	bool dss_div_calc(unsigned long pck, unsigned long fck_min,
688af02d TV	287	dss_div_calc_func func, void *data);
43417823	288
559d6701	289	/* SDI */
6e7e8f06 TV	290	int sdi_init_platform_driver(void) __init;
6e7e8f06 TV	291	void sdi_uninit_platform_driver(void) __exit;
559d6701	292
387ce9f2	293	#ifdef CONFIG_OMAP2_DSS_SDI
2ecef246	294	int sdi_init_port(struct platform_device pdev, struct device_node port) __init;
387ce9f2 AT	295	void sdi_uninit_port(struct device_node *port) __exit;
	296	#else
	297	static inline int __init sdi_init_port(struct platform_device *pdev,
	298	struct device_node *port)
	299	{
	300	return 0;
	301	}
	302	static inline void __exit sdi_uninit_port(struct device_node *port)
	303	{
	304	}
	305	#endif
2ecef246	306
559d6701	307	/* DSI */
989c79a8	308
368a148e	309	#ifdef CONFIG_OMAP2_DSS_DSI
5a8b572d AT	310
	311	struct dentry;
	312	struct file_operations;
	313
6e7e8f06 TV	314	int dsi_init_platform_driver(void) __init;
6e7e8f06 TV	315	void dsi_uninit_platform_driver(void) __exit;
559d6701 TV	316
559d6701 TV	317	void dsi_dump_clocks(struct seq_file *s);
559d6701	318
559d6701	319	void dsi_irq_handler(void);
a3b3cc2b AT	320	u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
a3b3cc2b AT	321
368a148e	322	#else
a3b3cc2b AT	323	static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
	324	{
	325	WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
	326	return 0;
	327	}
368a148e	328	#endif
559d6701 TV	329
559d6701 TV	330	/* DPI */
6e7e8f06 TV	331	int dpi_init_platform_driver(void) __init;
6e7e8f06 TV	332	void dpi_uninit_platform_driver(void) __exit;
559d6701	333
387ce9f2	334	#ifdef CONFIG_OMAP2_DSS_DPI
2ecef246	335	int dpi_init_port(struct platform_device pdev, struct device_node port) __init;
80eb6751	336	void dpi_uninit_port(struct device_node *port) __exit;
387ce9f2 AT	337	#else
	338	static inline int __init dpi_init_port(struct platform_device *pdev,
	339	struct device_node *port)
	340	{
	341	return 0;
	342	}
	343	static inline void __exit dpi_uninit_port(struct device_node *port)
	344	{
	345	}
	346	#endif
2ecef246	347
559d6701	348	/* DISPC */
6e7e8f06 TV	349	int dispc_init_platform_driver(void) __init;
6e7e8f06 TV	350	void dispc_uninit_platform_driver(void) __exit;
559d6701	351	void dispc_dump_clocks(struct seq_file *s);
559d6701 TV	352
	353	void dispc_enable_sidle(void);
	354	void dispc_disable_sidle(void);
	355
559d6701 TV	356	void dispc_lcd_enable_signal(bool enable);
559d6701 TV	357	void dispc_pck_free_enable(bool enable);
cd295aeb TV	358	void dispc_enable_fifomerge(bool enable);
	359	void dispc_enable_gamma_table(bool enable);
	360	void dispc_set_loadmode(enum omap_dss_load_mode mode);
	361
7c284e6e TV	362	typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
	363	unsigned long pck, void *data);
	364	bool dispc_div_calc(unsigned long dispc,
	365	unsigned long pck_min, unsigned long pck_max,
	366	dispc_div_calc_func func, void *data);
	367
8f366162	368	bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39	369	const struct omap_video_timings *timings);
cd295aeb	370	unsigned long dispc_fclk_rate(void);
cd295aeb TV	371	int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
	372	struct dispc_clock_info *cinfo);
	373
	374
6f04e1bf	375	void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
83fa2f2e	376	void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4 TV	377	u32 fifo_low, u32 fifo_high, bool use_fifomerge,
3568f2a4 TV	378	bool manual_update);
348be69d	379
cd295aeb TV	380	unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
cd295aeb TV	381	unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
8b53d991	382	unsigned long dispc_core_clk_rate(void);
f0d08f89	383	void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1	384	const struct dispc_clock_info *cinfo);
26d9dd0d	385	int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde	386	struct dispc_clock_info *cinfo);
5391e87d	387	void dispc_set_tv_pclk(unsigned long pclk);
559d6701	388
0b23e5b8 AT	389	u32 dispc_wb_get_framedone_irq(void);
	390	bool dispc_wb_go_busy(void);
	391	void dispc_wb_go(void);
	392	void dispc_wb_enable(bool enable);
	393	bool dispc_wb_is_enabled(void);
d9ac773c	394	void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
749feffa	395	int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7	396	bool mem_to_mem, const struct omap_video_timings *timings);
d9ac773c	397
559d6701	398	/* VENC */
6e7e8f06 TV	399	int venc_init_platform_driver(void) __init;
6e7e8f06 TV	400	void venc_uninit_platform_driver(void) __exit;
559d6701	401
c3198a5e	402	/* HDMI */
ef26958a AT	403	int hdmi4_init_platform_driver(void) __init;
ef26958a AT	404	void hdmi4_uninit_platform_driver(void) __exit;
c3198a5e	405
f5bab222 TV	406	int hdmi5_init_platform_driver(void) __init;
	407	void hdmi5_uninit_platform_driver(void) __exit;
	408
559d6701	409	/* RFBI */
6e7e8f06 TV	410	int rfbi_init_platform_driver(void) __init;
6e7e8f06 TV	411	void rfbi_uninit_platform_driver(void) __exit;
559d6701	412
dfc0fd8d TV	413
	414	#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
	415	static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
	416	{
	417	int b;
	418	for (b = 0; b < 32; ++b) {
	419	if (irqstatus & (1 << b))
	420	irq_arr[b]++;
	421	}
	422	}
	423	#endif
	424
0a20170a TV	425	/* PLL */
	426	typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
	427	unsigned long clkdco, void *data);
	428	typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
	429	void *data);
	430
	431	int dss_pll_register(struct dss_pll *pll);
	432	void dss_pll_unregister(struct dss_pll *pll);
	433	struct dss_pll dss_pll_find(const char name);
	434	int dss_pll_enable(struct dss_pll *pll);
	435	void dss_pll_disable(struct dss_pll *pll);
	436	int dss_pll_set_config(struct dss_pll *pll,
	437	const struct dss_pll_clock_info *cinfo);
	438
	439	bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco,
	440	unsigned long out_min, unsigned long out_max,
	441	dss_hsdiv_calc_func func, void *data);
	442	bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin,
	443	unsigned long pll_min, unsigned long pll_max,
	444	dss_pll_calc_func func, void *data);
	445	int dss_pll_write_config_type_a(struct dss_pll *pll,
	446	const struct dss_pll_clock_info *cinfo);
	447	int dss_pll_write_config_type_b(struct dss_pll *pll,
	448	const struct dss_pll_clock_info *cinfo);
	449
559d6701	450	#endif