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1da177e4 LT |
1 | /* |
2 | * drivers/video/aty/radeon_base.c | |
3 | * | |
4 | * framebuffer driver for ATI Radeon chipset video boards | |
5 | * | |
6 | * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org> | |
7 | * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org> | |
8 | * | |
9 | * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net> | |
10 | * | |
11 | * Special thanks to ATI DevRel team for their hardware donations. | |
12 | * | |
13 | * ...Insert GPL boilerplate here... | |
14 | * | |
15 | * Significant portions of this driver apdated from XFree86 Radeon | |
16 | * driver which has the following copyright notice: | |
17 | * | |
18 | * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and | |
19 | * VA Linux Systems Inc., Fremont, California. | |
20 | * | |
21 | * All Rights Reserved. | |
22 | * | |
23 | * Permission is hereby granted, free of charge, to any person obtaining | |
24 | * a copy of this software and associated documentation files (the | |
25 | * "Software"), to deal in the Software without restriction, including | |
26 | * without limitation on the rights to use, copy, modify, merge, | |
27 | * publish, distribute, sublicense, and/or sell copies of the Software, | |
28 | * and to permit persons to whom the Software is furnished to do so, | |
29 | * subject to the following conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice (including the | |
32 | * next paragraph) shall be included in all copies or substantial | |
33 | * portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
37 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR | |
39 | * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
41 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
42 | * DEALINGS IN THE SOFTWARE. | |
43 | * | |
44 | * XFree86 driver authors: | |
45 | * | |
46 | * Kevin E. Martin <martin@xfree86.org> | |
47 | * Rickard E. Faith <faith@valinux.com> | |
48 | * Alan Hourihane <alanh@fairlite.demon.co.uk> | |
49 | * | |
50 | */ | |
51 | ||
52 | ||
53 | #define RADEON_VERSION "0.2.0" | |
54 | ||
b0313f89 JD |
55 | #include "radeonfb.h" |
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/moduleparam.h> | |
59 | #include <linux/kernel.h> | |
60 | #include <linux/errno.h> | |
61 | #include <linux/string.h> | |
e7a18c9c | 62 | #include <linux/ctype.h> |
1da177e4 | 63 | #include <linux/mm.h> |
1da177e4 LT |
64 | #include <linux/slab.h> |
65 | #include <linux/delay.h> | |
66 | #include <linux/time.h> | |
67 | #include <linux/fb.h> | |
68 | #include <linux/ioport.h> | |
69 | #include <linux/init.h> | |
70 | #include <linux/pci.h> | |
71 | #include <linux/vmalloc.h> | |
72 | #include <linux/device.h> | |
1da177e4 LT |
73 | |
74 | #include <asm/io.h> | |
84902b7a | 75 | #include <linux/uaccess.h> |
1da177e4 | 76 | |
758ddd1d | 77 | #ifdef CONFIG_PPC |
1da177e4 | 78 | |
1da177e4 LT |
79 | #include "../macmodes.h" |
80 | ||
1da177e4 LT |
81 | #ifdef CONFIG_BOOTX_TEXT |
82 | #include <asm/btext.h> | |
83 | #endif | |
84 | ||
758ddd1d | 85 | #endif /* CONFIG_PPC */ |
1da177e4 | 86 | |
1da177e4 LT |
87 | #include <video/radeon.h> |
88 | #include <linux/radeonfb.h> | |
89 | ||
90 | #include "../edid.h" // MOVE THAT TO include/video | |
91 | #include "ati_ids.h" | |
1da177e4 LT |
92 | |
93 | #define MAX_MAPPED_VRAM (2048*2048*4) | |
94 | #define MIN_MAPPED_VRAM (1024*768*1) | |
95 | ||
96 | #define CHIP_DEF(id, family, flags) \ | |
97 | { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } | |
98 | ||
cac9559e | 99 | static const struct pci_device_id radeonfb_pci_table[] = { |
dd144713 | 100 | /* Radeon Xpress 200m */ |
101 | CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
106c4a9c | 102 | CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), |
1da177e4 LT |
103 | /* Mobility M6 */ |
104 | CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
105 | CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
106 | /* Radeon VE/7000 */ | |
107 | CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2), | |
108 | CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2), | |
183dee0f | 109 | CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2), |
1da177e4 LT |
110 | /* Radeon IGP320M (U1) */ |
111 | CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
112 | /* Radeon IGP320 (A3) */ | |
113 | CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
114 | /* IGP330M/340M/350M (U2) */ | |
115 | CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
116 | /* IGP330/340/350 (A4) */ | |
117 | CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
118 | /* Mobility 7000 IGP */ | |
119 | CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
120 | /* 7000 IGP (A4+) */ | |
121 | CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
122 | /* 8500 AIW */ | |
123 | CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2), | |
124 | CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2), | |
125 | /* 8700/8800 */ | |
126 | CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2), | |
127 | /* 8500 */ | |
128 | CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2), | |
129 | /* 9100 */ | |
130 | CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2), | |
131 | /* Mobility M7 */ | |
132 | CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
133 | CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
134 | /* 7500 */ | |
135 | CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2), | |
136 | CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2), | |
137 | /* Mobility M9 */ | |
138 | CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
139 | CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
140 | CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
141 | CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
142 | /* 9000/Pro */ | |
143 | CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2), | |
144 | CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2), | |
0b693eaf SB |
145 | |
146 | CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
1da177e4 LT |
147 | /* Mobility 9100 IGP (U3) */ |
148 | CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
149 | CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), | |
150 | /* 9100 IGP (A5) */ | |
151 | CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
152 | CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP), | |
153 | /* Mobility 9200 (M9+) */ | |
154 | CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
155 | CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
156 | /* 9200 */ | |
157 | CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2), | |
158 | CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2), | |
159 | CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2), | |
160 | CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2), | |
161 | /* 9500 */ | |
162 | CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2), | |
163 | CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2), | |
164 | /* 9600TX / FireGL Z1 */ | |
165 | CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2), | |
166 | CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2), | |
167 | /* 9700/9500/Pro/FireGL X1 */ | |
168 | CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2), | |
169 | CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2), | |
170 | CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2), | |
171 | CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2), | |
172 | /* Mobility M10/M11 */ | |
173 | CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
174 | CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
175 | CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
176 | CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
177 | CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
178 | CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
179 | /* 9600/FireGL T2 */ | |
180 | CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2), | |
181 | CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2), | |
182 | CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2), | |
183 | CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2), | |
184 | CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2), | |
185 | CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2), | |
186 | /* 9800/Pro/FileGL X2 */ | |
187 | CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2), | |
188 | CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2), | |
189 | CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2), | |
190 | CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2), | |
191 | CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2), | |
192 | CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2), | |
193 | CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2), | |
194 | CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2), | |
195 | /* Newer stuff */ | |
196 | CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2), | |
197 | CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2), | |
198 | CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
199 | CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
200 | CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2), | |
201 | CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2), | |
3050d45c | 202 | CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2), |
1da177e4 LT |
203 | CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2), |
204 | CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2), | |
205 | CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
206 | CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
207 | CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2), | |
208 | CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2), | |
209 | CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2), | |
210 | CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2), | |
211 | CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2), | |
212 | CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2), | |
213 | CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), | |
214 | CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2), | |
215 | CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2), | |
216 | CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2), | |
217 | CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2), | |
218 | CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2), | |
219 | CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2), | |
220 | CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2), | |
221 | CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2), | |
222 | CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2), | |
223 | /* Original Radeon/7200 */ | |
224 | CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0), | |
225 | CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0), | |
226 | CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0), | |
227 | CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0), | |
228 | { 0, } | |
229 | }; | |
230 | MODULE_DEVICE_TABLE(pci, radeonfb_pci_table); | |
231 | ||
232 | ||
233 | typedef struct { | |
234 | u16 reg; | |
235 | u32 val; | |
236 | } reg_val; | |
237 | ||
238 | ||
239 | /* these common regs are cleared before mode setting so they do not | |
240 | * interfere with anything | |
241 | */ | |
242 | static reg_val common_regs[] = { | |
243 | { OVR_CLR, 0 }, | |
244 | { OVR_WID_LEFT_RIGHT, 0 }, | |
245 | { OVR_WID_TOP_BOTTOM, 0 }, | |
246 | { OV0_SCALE_CNTL, 0 }, | |
247 | { SUBPIC_CNTL, 0 }, | |
248 | { VIPH_CONTROL, 0 }, | |
249 | { I2C_CNTL_1, 0 }, | |
250 | { GEN_INT_CNTL, 0 }, | |
251 | { CAP0_TRIG_CNTL, 0 }, | |
252 | { CAP1_TRIG_CNTL, 0 }, | |
253 | }; | |
254 | ||
255 | /* | |
256 | * globals | |
257 | */ | |
258 | ||
259 | static char *mode_option; | |
260 | static char *monitor_layout; | |
90ab5ee9 | 261 | static bool noaccel = 0; |
1da177e4 | 262 | static int default_dynclk = -2; |
90ab5ee9 RR |
263 | static bool nomodeset = 0; |
264 | static bool ignore_edid = 0; | |
265 | static bool mirror = 0; | |
1da177e4 | 266 | static int panel_yres = 0; |
90ab5ee9 RR |
267 | static bool force_dfp = 0; |
268 | static bool force_measure_pll = 0; | |
90ab5ee9 | 269 | static bool nomtrr = 0; |
90ab5ee9 RR |
270 | static bool force_sleep; |
271 | static bool ignore_devlist; | |
202d4e60 RP |
272 | #ifdef CONFIG_PMAC_BACKLIGHT |
273 | static int backlight = 1; | |
274 | #else | |
275 | static int backlight = 0; | |
276 | #endif | |
1da177e4 | 277 | |
08bfb453 DV |
278 | /* Note about this function: we have some rare cases where we must not schedule, |
279 | * this typically happen with our special "wake up early" hook which allows us to | |
280 | * wake up the graphic chip (and thus get the console back) before everything else | |
281 | * on some machines that support that mechanism. At this point, interrupts are off | |
282 | * and scheduling is not permitted | |
1da177e4 | 283 | */ |
08bfb453 DV |
284 | void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms) |
285 | { | |
286 | if (rinfo->no_schedule || oops_in_progress) | |
287 | mdelay(ms); | |
288 | else | |
289 | msleep(ms); | |
290 | } | |
291 | ||
292 | void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo) | |
293 | { | |
294 | /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ | |
295 | (void)INREG(CLOCK_CNTL_DATA); | |
296 | (void)INREG(CRTC_GEN_CNTL); | |
297 | } | |
298 | ||
299 | void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo) | |
300 | { | |
301 | if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { | |
302 | /* we can't deal with posted writes here ... */ | |
303 | _radeon_msleep(rinfo, 5); | |
304 | } | |
305 | if (rinfo->errata & CHIP_ERRATA_R300_CG) { | |
306 | u32 save, tmp; | |
307 | save = INREG(CLOCK_CNTL_INDEX); | |
308 | tmp = save & ~(0x3f | PLL_WR_EN); | |
309 | OUTREG(CLOCK_CNTL_INDEX, tmp); | |
310 | tmp = INREG(CLOCK_CNTL_DATA); | |
311 | OUTREG(CLOCK_CNTL_INDEX, save); | |
312 | } | |
313 | } | |
314 | ||
315 | void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask) | |
316 | { | |
317 | unsigned long flags; | |
318 | unsigned int tmp; | |
319 | ||
320 | spin_lock_irqsave(&rinfo->reg_lock, flags); | |
321 | tmp = INREG(addr); | |
322 | tmp &= (mask); | |
323 | tmp |= (val); | |
324 | OUTREG(addr, tmp); | |
325 | spin_unlock_irqrestore(&rinfo->reg_lock, flags); | |
326 | } | |
327 | ||
328 | u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) | |
329 | { | |
330 | u32 data; | |
331 | ||
332 | OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); | |
333 | radeon_pll_errata_after_index(rinfo); | |
334 | data = INREG(CLOCK_CNTL_DATA); | |
335 | radeon_pll_errata_after_data(rinfo); | |
336 | return data; | |
337 | } | |
338 | ||
339 | void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val) | |
340 | { | |
341 | OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); | |
342 | radeon_pll_errata_after_index(rinfo); | |
343 | OUTREG(CLOCK_CNTL_DATA, val); | |
344 | radeon_pll_errata_after_data(rinfo); | |
345 | } | |
346 | ||
347 | void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, | |
348 | u32 val, u32 mask) | |
349 | { | |
350 | unsigned int tmp; | |
351 | ||
352 | tmp = __INPLL(rinfo, index); | |
353 | tmp &= (mask); | |
354 | tmp |= (val); | |
355 | __OUTPLL(rinfo, index, tmp); | |
356 | } | |
357 | ||
358 | void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) | |
359 | { | |
360 | int i; | |
361 | ||
362 | for (i=0; i<2000000; i++) { | |
363 | if ((INREG(RBBM_STATUS) & 0x7f) >= entries) | |
364 | return; | |
365 | udelay(1); | |
366 | } | |
367 | printk(KERN_ERR "radeonfb: FIFO Timeout !\n"); | |
368 | } | |
369 | ||
370 | void radeon_engine_flush(struct radeonfb_info *rinfo) | |
371 | { | |
372 | int i; | |
373 | ||
374 | /* Initiate flush */ | |
375 | OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
376 | ~RB2D_DC_FLUSH_ALL); | |
377 | ||
378 | /* Ensure FIFO is empty, ie, make sure the flush commands | |
379 | * has reached the cache | |
380 | */ | |
381 | _radeon_fifo_wait(rinfo, 64); | |
382 | ||
383 | /* Wait for the flush to complete */ | |
384 | for (i=0; i < 2000000; i++) { | |
385 | if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
386 | return; | |
387 | udelay(1); | |
388 | } | |
389 | printk(KERN_ERR "radeonfb: Flush Timeout !\n"); | |
390 | } | |
391 | ||
392 | void _radeon_engine_idle(struct radeonfb_info *rinfo) | |
393 | { | |
394 | int i; | |
395 | ||
396 | /* ensure FIFO is empty before waiting for idle */ | |
397 | _radeon_fifo_wait(rinfo, 64); | |
398 | ||
399 | for (i=0; i<2000000; i++) { | |
400 | if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { | |
401 | radeon_engine_flush(rinfo); | |
402 | return; | |
403 | } | |
404 | udelay(1); | |
405 | } | |
406 | printk(KERN_ERR "radeonfb: Idle Timeout !\n"); | |
407 | } | |
408 | ||
409 | ||
1da177e4 | 410 | |
1da177e4 LT |
411 | static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) |
412 | { | |
413 | if (!rinfo->bios_seg) | |
414 | return; | |
415 | pci_unmap_rom(dev, rinfo->bios_seg); | |
416 | } | |
417 | ||
48c68c4f | 418 | static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev) |
1da177e4 LT |
419 | { |
420 | void __iomem *rom; | |
421 | u16 dptr; | |
422 | u8 rom_type; | |
423 | size_t rom_size; | |
424 | ||
425 | /* If this is a primary card, there is a shadow copy of the | |
426 | * ROM somewhere in the first meg. We will just ignore the copy | |
427 | * and use the ROM directly. | |
428 | */ | |
429 | ||
430 | /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ | |
431 | unsigned int temp; | |
432 | temp = INREG(MPP_TB_CONFIG); | |
433 | temp &= 0x00ffffffu; | |
434 | temp |= 0x04 << 24; | |
435 | OUTREG(MPP_TB_CONFIG, temp); | |
436 | temp = INREG(MPP_TB_CONFIG); | |
437 | ||
438 | rom = pci_map_rom(dev, &rom_size); | |
439 | if (!rom) { | |
440 | printk(KERN_ERR "radeonfb (%s): ROM failed to map\n", | |
441 | pci_name(rinfo->pdev)); | |
442 | return -ENOMEM; | |
443 | } | |
444 | ||
445 | rinfo->bios_seg = rom; | |
446 | ||
447 | /* Very simple test to make sure it appeared */ | |
448 | if (BIOS_IN16(0) != 0xaa55) { | |
3b4abffb OH |
449 | printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x " |
450 | "should be 0xaa55\n", | |
451 | pci_name(rinfo->pdev), BIOS_IN16(0)); | |
1da177e4 LT |
452 | goto failed; |
453 | } | |
454 | /* Look for the PCI data to check the ROM type */ | |
455 | dptr = BIOS_IN16(0x18); | |
456 | ||
457 | /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM | |
458 | * for now, until I've verified this works everywhere. The goal here is more | |
459 | * to phase out Open Firmware images. | |
460 | * | |
461 | * Currently, we only look at the first PCI data, we could iteratre and deal with | |
462 | * them all, and we should use fb_bios_start relative to start of image and not | |
463 | * relative start of ROM, but so far, I never found a dual-image ATI card | |
464 | * | |
465 | * typedef struct { | |
466 | * u32 signature; + 0x00 | |
467 | * u16 vendor; + 0x04 | |
468 | * u16 device; + 0x06 | |
469 | * u16 reserved_1; + 0x08 | |
470 | * u16 dlen; + 0x0a | |
471 | * u8 drevision; + 0x0c | |
472 | * u8 class_hi; + 0x0d | |
473 | * u16 class_lo; + 0x0e | |
474 | * u16 ilen; + 0x10 | |
475 | * u16 irevision; + 0x12 | |
476 | * u8 type; + 0x14 | |
477 | * u8 indicator; + 0x15 | |
478 | * u16 reserved_2; + 0x16 | |
479 | * } pci_data_t; | |
480 | */ | |
481 | if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) { | |
482 | printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM" | |
483 | "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); | |
484 | goto anyway; | |
485 | } | |
486 | rom_type = BIOS_IN8(dptr + 0x14); | |
487 | switch(rom_type) { | |
488 | case 0: | |
489 | printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n"); | |
490 | break; | |
491 | case 1: | |
492 | printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n"); | |
493 | goto failed; | |
494 | case 2: | |
495 | printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); | |
496 | goto failed; | |
497 | default: | |
498 | printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type); | |
499 | goto failed; | |
500 | } | |
501 | anyway: | |
502 | /* Locate the flat panel infos, do some sanity checking !!! */ | |
503 | rinfo->fp_bios_start = BIOS_IN16(0x48); | |
504 | return 0; | |
505 | ||
506 | failed: | |
507 | rinfo->bios_seg = NULL; | |
508 | radeon_unmap_ROM(rinfo, dev); | |
509 | return -ENXIO; | |
510 | } | |
511 | ||
512 | #ifdef CONFIG_X86 | |
48c68c4f | 513 | static int radeon_find_mem_vbios(struct radeonfb_info *rinfo) |
1da177e4 LT |
514 | { |
515 | /* I simplified this code as we used to miss the signatures in | |
516 | * a lot of case. It's now closer to XFree, we just don't check | |
517 | * for signatures at all... Something better will have to be done | |
518 | * if we end up having conflicts | |
519 | */ | |
520 | u32 segstart; | |
521 | void __iomem *rom_base = NULL; | |
522 | ||
523 | for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { | |
524 | rom_base = ioremap(segstart, 0x10000); | |
525 | if (rom_base == NULL) | |
526 | return -ENOMEM; | |
527 | if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa) | |
528 | break; | |
529 | iounmap(rom_base); | |
530 | rom_base = NULL; | |
531 | } | |
532 | if (rom_base == NULL) | |
533 | return -ENXIO; | |
534 | ||
535 | /* Locate the flat panel infos, do some sanity checking !!! */ | |
536 | rinfo->bios_seg = rom_base; | |
537 | rinfo->fp_bios_start = BIOS_IN16(0x48); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | #endif | |
542 | ||
758ddd1d | 543 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 LT |
544 | /* |
545 | * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device | |
546 | * tree. Hopefully, ATI OF driver is kind enough to fill these | |
547 | */ | |
48c68c4f | 548 | static int radeon_read_xtal_OF(struct radeonfb_info *rinfo) |
1da177e4 LT |
549 | { |
550 | struct device_node *dp = rinfo->of_node; | |
b04e3dd4 | 551 | const u32 *val; |
1da177e4 LT |
552 | |
553 | if (dp == NULL) | |
554 | return -ENODEV; | |
40cd3a45 | 555 | val = of_get_property(dp, "ATY,RefCLK", NULL); |
1da177e4 LT |
556 | if (!val || !*val) { |
557 | printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n"); | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
561 | rinfo->pll.ref_clk = (*val) / 10; | |
562 | ||
40cd3a45 | 563 | val = of_get_property(dp, "ATY,SCLK", NULL); |
1da177e4 LT |
564 | if (val && *val) |
565 | rinfo->pll.sclk = (*val) / 10; | |
566 | ||
40cd3a45 | 567 | val = of_get_property(dp, "ATY,MCLK", NULL); |
1da177e4 LT |
568 | if (val && *val) |
569 | rinfo->pll.mclk = (*val) / 10; | |
570 | ||
571 | return 0; | |
572 | } | |
758ddd1d | 573 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
1da177e4 LT |
574 | |
575 | /* | |
576 | * Read PLL infos from chip registers | |
577 | */ | |
48c68c4f | 578 | static int radeon_probe_pll_params(struct radeonfb_info *rinfo) |
1da177e4 LT |
579 | { |
580 | unsigned char ppll_div_sel; | |
581 | unsigned Ns, Nm, M; | |
582 | unsigned sclk, mclk, tmp, ref_div; | |
583 | int hTotal, vTotal, num, denom, m, n; | |
584 | unsigned long long hz, vclk; | |
585 | long xtal; | |
63a4be93 AB |
586 | ktime_t start_time, stop_time; |
587 | u64 total_usecs; | |
1da177e4 LT |
588 | int i; |
589 | ||
590 | /* Ugh, we cut interrupts, bad bad bad, but we want some precision | |
591 | * here, so... --BenH | |
592 | */ | |
593 | ||
594 | /* Flush PCI buffers ? */ | |
017fb98e | 595 | tmp = INREG16(DEVICE_ID); |
1da177e4 LT |
596 | |
597 | local_irq_disable(); | |
598 | ||
599 | for(i=0; i<1000000; i++) | |
600 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) | |
601 | break; | |
602 | ||
63a4be93 | 603 | start_time = ktime_get(); |
1da177e4 LT |
604 | |
605 | for(i=0; i<1000000; i++) | |
606 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0) | |
607 | break; | |
608 | ||
609 | for(i=0; i<1000000; i++) | |
610 | if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0) | |
611 | break; | |
612 | ||
63a4be93 | 613 | stop_time = ktime_get(); |
1da177e4 LT |
614 | |
615 | local_irq_enable(); | |
616 | ||
63a4be93 AB |
617 | total_usecs = ktime_us_delta(stop_time, start_time); |
618 | if (total_usecs >= 10 * USEC_PER_SEC || total_usecs == 0) | |
1da177e4 | 619 | return -1; |
63a4be93 | 620 | hz = USEC_PER_SEC/(u32)total_usecs; |
1da177e4 LT |
621 | |
622 | hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8; | |
623 | vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1); | |
624 | vclk = (long long)hTotal * (long long)vTotal * hz; | |
625 | ||
626 | switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) { | |
627 | case 0: | |
628 | default: | |
629 | num = 1; | |
630 | denom = 1; | |
631 | break; | |
632 | case 1: | |
633 | n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff); | |
634 | m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); | |
635 | num = 2*n; | |
636 | denom = 2*m; | |
637 | break; | |
638 | case 2: | |
639 | n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff); | |
640 | m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff); | |
641 | num = 2*n; | |
642 | denom = 2*m; | |
643 | break; | |
644 | } | |
645 | ||
646 | ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3; | |
647 | radeon_pll_errata_after_index(rinfo); | |
648 | ||
649 | n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff); | |
650 | m = (INPLL(PPLL_REF_DIV) & 0x3ff); | |
651 | ||
652 | num *= n; | |
653 | denom *= m; | |
654 | ||
655 | switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { | |
656 | case 1: | |
657 | denom *= 2; | |
658 | break; | |
659 | case 2: | |
660 | denom *= 4; | |
661 | break; | |
662 | case 3: | |
663 | denom *= 8; | |
664 | break; | |
665 | case 4: | |
666 | denom *= 3; | |
667 | break; | |
668 | case 6: | |
669 | denom *= 6; | |
670 | break; | |
671 | case 7: | |
672 | denom *= 12; | |
673 | break; | |
674 | } | |
675 | ||
676 | vclk *= denom; | |
677 | do_div(vclk, 1000 * num); | |
678 | xtal = vclk; | |
679 | ||
680 | if ((xtal > 26900) && (xtal < 27100)) | |
681 | xtal = 2700; | |
682 | else if ((xtal > 14200) && (xtal < 14400)) | |
683 | xtal = 1432; | |
684 | else if ((xtal > 29400) && (xtal < 29600)) | |
685 | xtal = 2950; | |
686 | else { | |
687 | printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal); | |
688 | return -1; | |
689 | } | |
690 | ||
691 | tmp = INPLL(M_SPLL_REF_FB_DIV); | |
692 | ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; | |
693 | ||
694 | Ns = (tmp & 0xff0000) >> 16; | |
695 | Nm = (tmp & 0xff00) >> 8; | |
696 | M = (tmp & 0xff); | |
697 | sclk = round_div((2 * Ns * xtal), (2 * M)); | |
698 | mclk = round_div((2 * Nm * xtal), (2 * M)); | |
699 | ||
700 | /* we're done, hopefully these are sane values */ | |
701 | rinfo->pll.ref_clk = xtal; | |
702 | rinfo->pll.ref_div = ref_div; | |
703 | rinfo->pll.sclk = sclk; | |
704 | rinfo->pll.mclk = mclk; | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /* | |
4a4efbde | 710 | * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) |
1da177e4 | 711 | */ |
48c68c4f | 712 | static void radeon_get_pllinfo(struct radeonfb_info *rinfo) |
1da177e4 LT |
713 | { |
714 | /* | |
715 | * In the case nothing works, these are defaults; they are mostly | |
716 | * incomplete, however. It does provide ppll_max and _min values | |
717 | * even for most other methods, however. | |
718 | */ | |
719 | switch (rinfo->chipset) { | |
720 | case PCI_DEVICE_ID_ATI_RADEON_QW: | |
721 | case PCI_DEVICE_ID_ATI_RADEON_QX: | |
722 | rinfo->pll.ppll_max = 35000; | |
723 | rinfo->pll.ppll_min = 12000; | |
724 | rinfo->pll.mclk = 23000; | |
725 | rinfo->pll.sclk = 23000; | |
726 | rinfo->pll.ref_clk = 2700; | |
727 | break; | |
728 | case PCI_DEVICE_ID_ATI_RADEON_QL: | |
729 | case PCI_DEVICE_ID_ATI_RADEON_QN: | |
730 | case PCI_DEVICE_ID_ATI_RADEON_QO: | |
731 | case PCI_DEVICE_ID_ATI_RADEON_Ql: | |
732 | case PCI_DEVICE_ID_ATI_RADEON_BB: | |
733 | rinfo->pll.ppll_max = 35000; | |
734 | rinfo->pll.ppll_min = 12000; | |
735 | rinfo->pll.mclk = 27500; | |
736 | rinfo->pll.sclk = 27500; | |
737 | rinfo->pll.ref_clk = 2700; | |
738 | break; | |
739 | case PCI_DEVICE_ID_ATI_RADEON_Id: | |
740 | case PCI_DEVICE_ID_ATI_RADEON_Ie: | |
741 | case PCI_DEVICE_ID_ATI_RADEON_If: | |
742 | case PCI_DEVICE_ID_ATI_RADEON_Ig: | |
743 | rinfo->pll.ppll_max = 35000; | |
744 | rinfo->pll.ppll_min = 12000; | |
745 | rinfo->pll.mclk = 25000; | |
746 | rinfo->pll.sclk = 25000; | |
747 | rinfo->pll.ref_clk = 2700; | |
748 | break; | |
749 | case PCI_DEVICE_ID_ATI_RADEON_ND: | |
750 | case PCI_DEVICE_ID_ATI_RADEON_NE: | |
751 | case PCI_DEVICE_ID_ATI_RADEON_NF: | |
752 | case PCI_DEVICE_ID_ATI_RADEON_NG: | |
753 | rinfo->pll.ppll_max = 40000; | |
754 | rinfo->pll.ppll_min = 20000; | |
755 | rinfo->pll.mclk = 27000; | |
756 | rinfo->pll.sclk = 27000; | |
757 | rinfo->pll.ref_clk = 2700; | |
758 | break; | |
759 | case PCI_DEVICE_ID_ATI_RADEON_QD: | |
760 | case PCI_DEVICE_ID_ATI_RADEON_QE: | |
761 | case PCI_DEVICE_ID_ATI_RADEON_QF: | |
762 | case PCI_DEVICE_ID_ATI_RADEON_QG: | |
763 | default: | |
764 | rinfo->pll.ppll_max = 35000; | |
765 | rinfo->pll.ppll_min = 12000; | |
766 | rinfo->pll.mclk = 16600; | |
767 | rinfo->pll.sclk = 16600; | |
768 | rinfo->pll.ref_clk = 2700; | |
769 | break; | |
770 | } | |
771 | rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; | |
772 | ||
773 | ||
758ddd1d | 774 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 | 775 | /* |
4a4efbde | 776 | * Retrieve PLL infos from Open Firmware first |
1da177e4 LT |
777 | */ |
778 | if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) { | |
4a4efbde | 779 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n"); |
1da177e4 LT |
780 | goto found; |
781 | } | |
758ddd1d | 782 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
1da177e4 LT |
783 | |
784 | /* | |
785 | * Check out if we have an X86 which gave us some PLL informations | |
4a4efbde | 786 | * and if yes, retrieve them |
1da177e4 LT |
787 | */ |
788 | if (!force_measure_pll && rinfo->bios_seg) { | |
789 | u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); | |
790 | ||
791 | rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); | |
792 | rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); | |
793 | rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); | |
794 | rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); | |
795 | rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); | |
796 | rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); | |
797 | ||
4a4efbde | 798 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); |
1da177e4 LT |
799 | goto found; |
800 | } | |
801 | ||
802 | /* | |
803 | * We didn't get PLL parameters from either OF or BIOS, we try to | |
804 | * probe them | |
805 | */ | |
806 | if (radeon_probe_pll_params(rinfo) == 0) { | |
4a4efbde | 807 | printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n"); |
1da177e4 LT |
808 | goto found; |
809 | } | |
810 | ||
811 | /* | |
812 | * Fall back to already-set defaults... | |
813 | */ | |
814 | printk(KERN_INFO "radeonfb: Used default PLL infos\n"); | |
815 | ||
816 | found: | |
817 | /* | |
4a4efbde | 818 | * Some methods fail to retrieve SCLK and MCLK values, we apply default |
3e621019 PM |
819 | * settings in this case (200Mhz). If that really happens often, we |
820 | * could fetch from registers instead... | |
1da177e4 LT |
821 | */ |
822 | if (rinfo->pll.mclk == 0) | |
823 | rinfo->pll.mclk = 20000; | |
824 | if (rinfo->pll.sclk == 0) | |
825 | rinfo->pll.sclk = 20000; | |
826 | ||
827 | printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", | |
828 | rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, | |
829 | rinfo->pll.ref_div, | |
830 | rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, | |
831 | rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); | |
832 | printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); | |
833 | } | |
834 | ||
835 | static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info) | |
836 | { | |
837 | struct radeonfb_info *rinfo = info->par; | |
838 | struct fb_var_screeninfo v; | |
839 | int nom, den; | |
840 | unsigned int pitch; | |
841 | ||
842 | if (radeon_match_mode(rinfo, &v, var)) | |
843 | return -EINVAL; | |
844 | ||
845 | switch (v.bits_per_pixel) { | |
846 | case 0 ... 8: | |
847 | v.bits_per_pixel = 8; | |
848 | break; | |
849 | case 9 ... 16: | |
850 | v.bits_per_pixel = 16; | |
851 | break; | |
852 | case 17 ... 24: | |
853 | #if 0 /* Doesn't seem to work */ | |
854 | v.bits_per_pixel = 24; | |
855 | break; | |
856 | #endif | |
857 | return -EINVAL; | |
858 | case 25 ... 32: | |
859 | v.bits_per_pixel = 32; | |
860 | break; | |
861 | default: | |
862 | return -EINVAL; | |
863 | } | |
864 | ||
865 | switch (var_to_depth(&v)) { | |
866 | case 8: | |
867 | nom = den = 1; | |
868 | v.red.offset = v.green.offset = v.blue.offset = 0; | |
869 | v.red.length = v.green.length = v.blue.length = 8; | |
870 | v.transp.offset = v.transp.length = 0; | |
871 | break; | |
872 | case 15: | |
873 | nom = 2; | |
874 | den = 1; | |
875 | v.red.offset = 10; | |
876 | v.green.offset = 5; | |
877 | v.blue.offset = 0; | |
878 | v.red.length = v.green.length = v.blue.length = 5; | |
879 | v.transp.offset = v.transp.length = 0; | |
880 | break; | |
881 | case 16: | |
882 | nom = 2; | |
883 | den = 1; | |
884 | v.red.offset = 11; | |
885 | v.green.offset = 5; | |
886 | v.blue.offset = 0; | |
887 | v.red.length = 5; | |
888 | v.green.length = 6; | |
889 | v.blue.length = 5; | |
890 | v.transp.offset = v.transp.length = 0; | |
891 | break; | |
892 | case 24: | |
893 | nom = 4; | |
894 | den = 1; | |
895 | v.red.offset = 16; | |
896 | v.green.offset = 8; | |
897 | v.blue.offset = 0; | |
898 | v.red.length = v.blue.length = v.green.length = 8; | |
899 | v.transp.offset = v.transp.length = 0; | |
900 | break; | |
901 | case 32: | |
902 | nom = 4; | |
903 | den = 1; | |
904 | v.red.offset = 16; | |
905 | v.green.offset = 8; | |
906 | v.blue.offset = 0; | |
907 | v.red.length = v.blue.length = v.green.length = 8; | |
908 | v.transp.offset = 24; | |
909 | v.transp.length = 8; | |
910 | break; | |
911 | default: | |
912 | printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n", | |
913 | var->xres, var->yres, var->bits_per_pixel); | |
914 | return -EINVAL; | |
915 | } | |
916 | ||
917 | if (v.yres_virtual < v.yres) | |
918 | v.yres_virtual = v.yres; | |
919 | if (v.xres_virtual < v.xres) | |
920 | v.xres_virtual = v.xres; | |
921 | ||
922 | ||
923 | /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree | |
924 | * with some panels, though I don't quite like this solution | |
925 | */ | |
926 | if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { | |
927 | v.xres_virtual = v.xres_virtual & ~7ul; | |
928 | } else { | |
929 | pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f) | |
930 | & ~(0x3f)) >> 6; | |
931 | v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8); | |
932 | } | |
933 | ||
934 | if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) | |
935 | return -EINVAL; | |
936 | ||
937 | if (v.xres_virtual < v.xres) | |
938 | v.xres = v.xres_virtual; | |
939 | ||
1da177e4 LT |
940 | if (v.xoffset > v.xres_virtual - v.xres) |
941 | v.xoffset = v.xres_virtual - v.xres - 1; | |
942 | ||
943 | if (v.yoffset > v.yres_virtual - v.yres) | |
944 | v.yoffset = v.yres_virtual - v.yres - 1; | |
945 | ||
946 | v.red.msb_right = v.green.msb_right = v.blue.msb_right = | |
947 | v.transp.offset = v.transp.length = | |
948 | v.transp.msb_right = 0; | |
949 | ||
950 | memcpy(var, &v, sizeof(v)); | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | ||
956 | static int radeonfb_pan_display (struct fb_var_screeninfo *var, | |
957 | struct fb_info *info) | |
958 | { | |
959 | struct radeonfb_info *rinfo = info->par; | |
960 | ||
0e03f856 LP |
961 | if ((var->xoffset + info->var.xres > info->var.xres_virtual) |
962 | || (var->yoffset + info->var.yres > info->var.yres_virtual)) | |
963 | return -EINVAL; | |
1da177e4 LT |
964 | |
965 | if (rinfo->asleep) | |
966 | return 0; | |
967 | ||
6c34bc29 | 968 | radeon_fifo_wait(2); |
0e03f856 LP |
969 | OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + |
970 | var->xoffset * info->var.bits_per_pixel / 8) & ~7); | |
1da177e4 LT |
971 | return 0; |
972 | } | |
973 | ||
974 | ||
67a6680d CH |
975 | static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd, |
976 | unsigned long arg) | |
1da177e4 LT |
977 | { |
978 | struct radeonfb_info *rinfo = info->par; | |
979 | unsigned int tmp; | |
980 | u32 value = 0; | |
981 | int rc; | |
982 | ||
983 | switch (cmd) { | |
984 | /* | |
985 | * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's | |
986 | * and do something better using 2nd CRTC instead of just hackish | |
987 | * routing to second output | |
988 | */ | |
989 | case FBIO_RADEON_SET_MIRROR: | |
990 | if (!rinfo->is_mobility) | |
991 | return -EINVAL; | |
992 | ||
993 | rc = get_user(value, (__u32 __user *)arg); | |
994 | ||
995 | if (rc) | |
996 | return rc; | |
997 | ||
6c34bc29 | 998 | radeon_fifo_wait(2); |
1da177e4 LT |
999 | if (value & 0x01) { |
1000 | tmp = INREG(LVDS_GEN_CNTL); | |
1001 | ||
1002 | tmp |= (LVDS_ON | LVDS_BLON); | |
1003 | } else { | |
1004 | tmp = INREG(LVDS_GEN_CNTL); | |
1005 | ||
1006 | tmp &= ~(LVDS_ON | LVDS_BLON); | |
1007 | } | |
1008 | ||
1009 | OUTREG(LVDS_GEN_CNTL, tmp); | |
1010 | ||
1011 | if (value & 0x02) { | |
1012 | tmp = INREG(CRTC_EXT_CNTL); | |
1013 | tmp |= CRTC_CRT_ON; | |
1014 | ||
1015 | mirror = 1; | |
1016 | } else { | |
1017 | tmp = INREG(CRTC_EXT_CNTL); | |
1018 | tmp &= ~CRTC_CRT_ON; | |
1019 | ||
1020 | mirror = 0; | |
1021 | } | |
1022 | ||
1023 | OUTREG(CRTC_EXT_CNTL, tmp); | |
1024 | ||
1025 | return 0; | |
1026 | case FBIO_RADEON_GET_MIRROR: | |
1027 | if (!rinfo->is_mobility) | |
1028 | return -EINVAL; | |
1029 | ||
1030 | tmp = INREG(LVDS_GEN_CNTL); | |
1031 | if ((LVDS_ON | LVDS_BLON) & tmp) | |
1032 | value |= 0x01; | |
1033 | ||
1034 | tmp = INREG(CRTC_EXT_CNTL); | |
1035 | if (CRTC_CRT_ON & tmp) | |
1036 | value |= 0x02; | |
1037 | ||
1038 | return put_user(value, (__u32 __user *)arg); | |
1039 | default: | |
1040 | return -EINVAL; | |
1041 | } | |
1042 | ||
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | ||
1047 | int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch) | |
1048 | { | |
1049 | u32 val; | |
1050 | u32 tmp_pix_clks; | |
1051 | int unblank = 0; | |
1052 | ||
1053 | if (rinfo->lock_blank) | |
1054 | return 0; | |
1055 | ||
6c34bc29 | 1056 | radeon_engine_idle(); |
1da177e4 LT |
1057 | |
1058 | val = INREG(CRTC_EXT_CNTL); | |
1059 | val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | | |
1060 | CRTC_VSYNC_DIS); | |
1061 | switch (blank) { | |
1062 | case FB_BLANK_VSYNC_SUSPEND: | |
1063 | val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS); | |
1064 | break; | |
1065 | case FB_BLANK_HSYNC_SUSPEND: | |
1066 | val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS); | |
1067 | break; | |
1068 | case FB_BLANK_POWERDOWN: | |
1069 | val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | | |
1070 | CRTC_HSYNC_DIS); | |
1071 | break; | |
1072 | case FB_BLANK_NORMAL: | |
1073 | val |= CRTC_DISPLAY_DIS; | |
1074 | break; | |
1075 | case FB_BLANK_UNBLANK: | |
1076 | default: | |
1077 | unblank = 1; | |
1078 | } | |
1079 | OUTREG(CRTC_EXT_CNTL, val); | |
1080 | ||
1081 | ||
1082 | switch (rinfo->mon1_type) { | |
1083 | case MT_DFP: | |
1084 | if (unblank) | |
1085 | OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN), | |
1086 | ~(FP_FPON | FP_TMDS_EN)); | |
1087 | else { | |
1088 | if (mode_switch || blank == FB_BLANK_NORMAL) | |
1089 | break; | |
1090 | OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN)); | |
1091 | } | |
1092 | break; | |
1093 | case MT_LCD: | |
1094 | del_timer_sync(&rinfo->lvds_timer); | |
1095 | val = INREG(LVDS_GEN_CNTL); | |
1096 | if (unblank) { | |
1097 | u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON | |
1098 | | LVDS_EN | (rinfo->init_state.lvds_gen_cntl | |
1099 | & (LVDS_DIGON | LVDS_BL_MOD_EN)); | |
1100 | if ((val ^ target_val) == LVDS_DISPLAY_DIS) | |
1101 | OUTREG(LVDS_GEN_CNTL, target_val); | |
1102 | else if ((val ^ target_val) != 0) { | |
1103 | OUTREG(LVDS_GEN_CNTL, target_val | |
1104 | & ~(LVDS_ON | LVDS_BL_MOD_EN)); | |
1105 | rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; | |
1106 | rinfo->init_state.lvds_gen_cntl |= | |
1107 | target_val & LVDS_STATE_MASK; | |
1108 | if (mode_switch) { | |
1109 | radeon_msleep(rinfo->panel_info.pwr_delay); | |
1110 | OUTREG(LVDS_GEN_CNTL, target_val); | |
1111 | } | |
1112 | else { | |
1113 | rinfo->pending_lvds_gen_cntl = target_val; | |
1114 | mod_timer(&rinfo->lvds_timer, | |
1115 | jiffies + | |
1116 | msecs_to_jiffies(rinfo->panel_info.pwr_delay)); | |
1117 | } | |
1118 | } | |
1119 | } else { | |
1120 | val |= LVDS_DISPLAY_DIS; | |
1121 | OUTREG(LVDS_GEN_CNTL, val); | |
1122 | ||
1123 | /* We don't do a full switch-off on a simple mode switch */ | |
1124 | if (mode_switch || blank == FB_BLANK_NORMAL) | |
1125 | break; | |
1126 | ||
1127 | /* Asic bug, when turning off LVDS_ON, we have to make sure | |
1128 | * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off | |
1129 | */ | |
1130 | tmp_pix_clks = INPLL(PIXCLKS_CNTL); | |
1131 | if (rinfo->is_mobility || rinfo->is_IGP) | |
1132 | OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb); | |
1133 | val &= ~(LVDS_BL_MOD_EN); | |
1134 | OUTREG(LVDS_GEN_CNTL, val); | |
1135 | udelay(100); | |
1136 | val &= ~(LVDS_ON | LVDS_EN); | |
1137 | OUTREG(LVDS_GEN_CNTL, val); | |
1138 | val &= ~LVDS_DIGON; | |
1139 | rinfo->pending_lvds_gen_cntl = val; | |
1140 | mod_timer(&rinfo->lvds_timer, | |
1141 | jiffies + | |
1142 | msecs_to_jiffies(rinfo->panel_info.pwr_delay)); | |
1143 | rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; | |
1144 | rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; | |
1145 | if (rinfo->is_mobility || rinfo->is_IGP) | |
1146 | OUTPLL(PIXCLKS_CNTL, tmp_pix_clks); | |
1147 | } | |
1148 | break; | |
1149 | case MT_CRT: | |
1150 | // todo: powerdown DAC | |
1151 | default: | |
1152 | break; | |
1153 | } | |
1154 | ||
7ab87670 | 1155 | return 0; |
1da177e4 LT |
1156 | } |
1157 | ||
1158 | static int radeonfb_blank (int blank, struct fb_info *info) | |
1159 | { | |
1160 | struct radeonfb_info *rinfo = info->par; | |
1161 | ||
1162 | if (rinfo->asleep) | |
1163 | return 0; | |
6c34bc29 | 1164 | |
1da177e4 LT |
1165 | return radeon_screen_blank(rinfo, blank, 0); |
1166 | } | |
1167 | ||
71494376 BH |
1168 | static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green, |
1169 | unsigned blue, unsigned transp, | |
1170 | struct radeonfb_info *rinfo) | |
1da177e4 | 1171 | { |
1da177e4 LT |
1172 | u32 pindex; |
1173 | unsigned int i; | |
71494376 BH |
1174 | |
1175 | ||
1da177e4 | 1176 | if (regno > 255) |
db77ec27 | 1177 | return -EINVAL; |
1da177e4 LT |
1178 | |
1179 | red >>= 8; | |
1180 | green >>= 8; | |
1181 | blue >>= 8; | |
1182 | rinfo->palette[regno].red = red; | |
1183 | rinfo->palette[regno].green = green; | |
1184 | rinfo->palette[regno].blue = blue; | |
1185 | ||
1186 | /* default */ | |
1187 | pindex = regno; | |
1188 | ||
1189 | if (!rinfo->asleep) { | |
6c34bc29 LT |
1190 | radeon_fifo_wait(9); |
1191 | ||
1da177e4 LT |
1192 | if (rinfo->bpp == 16) { |
1193 | pindex = regno * 8; | |
1194 | ||
1195 | if (rinfo->depth == 16 && regno > 63) | |
db77ec27 | 1196 | return -EINVAL; |
1da177e4 | 1197 | if (rinfo->depth == 15 && regno > 31) |
db77ec27 | 1198 | return -EINVAL; |
1da177e4 | 1199 | |
71494376 BH |
1200 | /* For 565, the green component is mixed one order |
1201 | * below | |
1202 | */ | |
1da177e4 LT |
1203 | if (rinfo->depth == 16) { |
1204 | OUTREG(PALETTE_INDEX, pindex>>1); | |
71494376 BH |
1205 | OUTREG(PALETTE_DATA, |
1206 | (rinfo->palette[regno>>1].red << 16) | | |
1207 | (green << 8) | | |
1208 | (rinfo->palette[regno>>1].blue)); | |
1da177e4 LT |
1209 | green = rinfo->palette[regno<<1].green; |
1210 | } | |
1211 | } | |
1212 | ||
1213 | if (rinfo->depth != 16 || regno < 32) { | |
1214 | OUTREG(PALETTE_INDEX, pindex); | |
71494376 BH |
1215 | OUTREG(PALETTE_DATA, (red << 16) | |
1216 | (green << 8) | blue); | |
1da177e4 | 1217 | } |
1da177e4 LT |
1218 | } |
1219 | if (regno < 16) { | |
71494376 | 1220 | u32 *pal = rinfo->info->pseudo_palette; |
1da177e4 LT |
1221 | switch (rinfo->depth) { |
1222 | case 15: | |
1223 | pal[regno] = (regno << 10) | (regno << 5) | regno; | |
1224 | break; | |
1225 | case 16: | |
1226 | pal[regno] = (regno << 11) | (regno << 5) | regno; | |
1227 | break; | |
1228 | case 24: | |
1229 | pal[regno] = (regno << 16) | (regno << 8) | regno; | |
1230 | break; | |
1231 | case 32: | |
1232 | i = (regno << 8) | regno; | |
1233 | pal[regno] = (i << 16) | i; | |
1234 | break; | |
1235 | } | |
1236 | } | |
1237 | return 0; | |
1238 | } | |
1239 | ||
71494376 BH |
1240 | static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green, |
1241 | unsigned blue, unsigned transp, | |
1242 | struct fb_info *info) | |
1243 | { | |
1244 | struct radeonfb_info *rinfo = info->par; | |
1245 | u32 dac_cntl2, vclk_cntl = 0; | |
1246 | int rc; | |
1247 | ||
1248 | if (!rinfo->asleep) { | |
1249 | if (rinfo->is_mobility) { | |
1250 | vclk_cntl = INPLL(VCLK_ECP_CNTL); | |
1251 | OUTPLL(VCLK_ECP_CNTL, | |
1252 | vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); | |
1253 | } | |
1254 | ||
1255 | /* Make sure we are on first palette */ | |
1256 | if (rinfo->has_CRTC2) { | |
1257 | dac_cntl2 = INREG(DAC_CNTL2); | |
1258 | dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; | |
1259 | OUTREG(DAC_CNTL2, dac_cntl2); | |
1260 | } | |
1261 | } | |
1262 | ||
1263 | rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo); | |
1264 | ||
1265 | if (!rinfo->asleep && rinfo->is_mobility) | |
1266 | OUTPLL(VCLK_ECP_CNTL, vclk_cntl); | |
1267 | ||
1268 | return rc; | |
1269 | } | |
1270 | ||
1271 | static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info) | |
1272 | { | |
1273 | struct radeonfb_info *rinfo = info->par; | |
1274 | u16 *red, *green, *blue, *transp; | |
1275 | u32 dac_cntl2, vclk_cntl = 0; | |
1276 | int i, start, rc = 0; | |
1277 | ||
1278 | if (!rinfo->asleep) { | |
1279 | if (rinfo->is_mobility) { | |
1280 | vclk_cntl = INPLL(VCLK_ECP_CNTL); | |
1281 | OUTPLL(VCLK_ECP_CNTL, | |
1282 | vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb); | |
1283 | } | |
1284 | ||
1285 | /* Make sure we are on first palette */ | |
1286 | if (rinfo->has_CRTC2) { | |
1287 | dac_cntl2 = INREG(DAC_CNTL2); | |
1288 | dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL; | |
1289 | OUTREG(DAC_CNTL2, dac_cntl2); | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | red = cmap->red; | |
1294 | green = cmap->green; | |
1295 | blue = cmap->blue; | |
1296 | transp = cmap->transp; | |
1297 | start = cmap->start; | |
1298 | ||
1299 | for (i = 0; i < cmap->len; i++) { | |
1300 | u_int hred, hgreen, hblue, htransp = 0xffff; | |
1301 | ||
1302 | hred = *red++; | |
1303 | hgreen = *green++; | |
1304 | hblue = *blue++; | |
1305 | if (transp) | |
1306 | htransp = *transp++; | |
1307 | rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp, | |
1308 | rinfo); | |
1309 | if (rc) | |
1310 | break; | |
1311 | } | |
1312 | ||
1313 | if (!rinfo->asleep && rinfo->is_mobility) | |
1314 | OUTPLL(VCLK_ECP_CNTL, vclk_cntl); | |
1315 | ||
1316 | return rc; | |
1317 | } | |
1da177e4 LT |
1318 | |
1319 | static void radeon_save_state (struct radeonfb_info *rinfo, | |
1320 | struct radeon_regs *save) | |
1321 | { | |
1322 | /* CRTC regs */ | |
1323 | save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); | |
1324 | save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); | |
1325 | save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); | |
1326 | save->dac_cntl = INREG(DAC_CNTL); | |
1327 | save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); | |
1328 | save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); | |
1329 | save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); | |
1330 | save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); | |
1331 | save->crtc_pitch = INREG(CRTC_PITCH); | |
1332 | save->surface_cntl = INREG(SURFACE_CNTL); | |
1333 | ||
1334 | /* FP regs */ | |
1335 | save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); | |
1336 | save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); | |
1337 | save->fp_gen_cntl = INREG(FP_GEN_CNTL); | |
1338 | save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); | |
1339 | save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); | |
1340 | save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); | |
1341 | save->fp_vert_stretch = INREG(FP_VERT_STRETCH); | |
1342 | save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); | |
1343 | save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); | |
1344 | save->tmds_crc = INREG(TMDS_CRC); | |
1345 | save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); | |
1346 | save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); | |
1347 | ||
1348 | /* PLL regs */ | |
1349 | save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; | |
1350 | radeon_pll_errata_after_index(rinfo); | |
1351 | save->ppll_div_3 = INPLL(PPLL_DIV_3); | |
1352 | save->ppll_ref_div = INPLL(PPLL_REF_DIV); | |
1353 | } | |
1354 | ||
1355 | ||
1356 | static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) | |
1357 | { | |
1358 | int i; | |
1359 | ||
6c34bc29 LT |
1360 | radeon_fifo_wait(20); |
1361 | ||
1da177e4 LT |
1362 | /* Workaround from XFree */ |
1363 | if (rinfo->is_mobility) { | |
83e61f71 | 1364 | /* A temporal workaround for the occasional blanking on certain laptop |
1da177e4 LT |
1365 | * panels. This appears to related to the PLL divider registers |
1366 | * (fail to lock?). It occurs even when all dividers are the same | |
1367 | * with their old settings. In this case we really don't need to | |
1368 | * fiddle with PLL registers. By doing this we can avoid the blanking | |
1369 | * problem with some panels. | |
1370 | */ | |
1371 | if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && | |
1372 | (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & | |
1373 | (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { | |
1374 | /* We still have to force a switch to selected PPLL div thanks to | |
1375 | * an XFree86 driver bug which will switch it away in some cases | |
1376 | * even when using UseFDev */ | |
1377 | OUTREGP(CLOCK_CNTL_INDEX, | |
1378 | mode->clk_cntl_index & PPLL_DIV_SEL_MASK, | |
1379 | ~PPLL_DIV_SEL_MASK); | |
1380 | radeon_pll_errata_after_index(rinfo); | |
1381 | radeon_pll_errata_after_data(rinfo); | |
1382 | return; | |
1383 | } | |
1384 | } | |
1385 | ||
1386 | /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ | |
1387 | OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); | |
1388 | ||
1389 | /* Reset PPLL & enable atomic update */ | |
1390 | OUTPLLP(PPLL_CNTL, | |
1391 | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, | |
1392 | ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); | |
1393 | ||
1394 | /* Switch to selected PPLL divider */ | |
1395 | OUTREGP(CLOCK_CNTL_INDEX, | |
1396 | mode->clk_cntl_index & PPLL_DIV_SEL_MASK, | |
1397 | ~PPLL_DIV_SEL_MASK); | |
1398 | radeon_pll_errata_after_index(rinfo); | |
1399 | radeon_pll_errata_after_data(rinfo); | |
1400 | ||
1401 | /* Set PPLL ref. div */ | |
a6c0c37d | 1402 | if (IS_R300_VARIANT(rinfo) || |
1da177e4 | 1403 | rinfo->family == CHIP_FAMILY_RS300 || |
a6c0c37d BH |
1404 | rinfo->family == CHIP_FAMILY_RS400 || |
1405 | rinfo->family == CHIP_FAMILY_RS480) { | |
1da177e4 LT |
1406 | if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { |
1407 | /* When restoring console mode, use saved PPLL_REF_DIV | |
1408 | * setting. | |
1409 | */ | |
1410 | OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); | |
1411 | } else { | |
1412 | /* R300 uses ref_div_acc field as real ref divider */ | |
1413 | OUTPLLP(PPLL_REF_DIV, | |
1414 | (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), | |
1415 | ~R300_PPLL_REF_DIV_ACC_MASK); | |
1416 | } | |
1417 | } else | |
1418 | OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); | |
1419 | ||
1420 | /* Set PPLL divider 3 & post divider*/ | |
1421 | OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); | |
1422 | OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); | |
1423 | ||
1424 | /* Write update */ | |
1425 | while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) | |
1426 | ; | |
1427 | OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); | |
1428 | ||
1429 | /* Wait read update complete */ | |
1430 | /* FIXME: Certain revisions of R300 can't recover here. Not sure of | |
1431 | the cause yet, but this workaround will mask the problem for now. | |
1432 | Other chips usually will pass at the very first test, so the | |
1433 | workaround shouldn't have any effect on them. */ | |
1434 | for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) | |
1435 | ; | |
1436 | ||
1437 | OUTPLL(HTOTAL_CNTL, 0); | |
1438 | ||
1439 | /* Clear reset & atomic update */ | |
1440 | OUTPLLP(PPLL_CNTL, 0, | |
1441 | ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); | |
1442 | ||
1443 | /* We may want some locking ... oh well */ | |
1444 | radeon_msleep(5); | |
1445 | ||
1446 | /* Switch back VCLK source to PPLL */ | |
1447 | OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); | |
1448 | } | |
1449 | ||
1450 | /* | |
1451 | * Timer function for delayed LVDS panel power up/down | |
1452 | */ | |
6c789357 | 1453 | static void radeon_lvds_timer_func(struct timer_list *t) |
1da177e4 | 1454 | { |
6c789357 | 1455 | struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer); |
1da177e4 | 1456 | |
6c34bc29 | 1457 | radeon_engine_idle(); |
1da177e4 LT |
1458 | |
1459 | OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); | |
1460 | } | |
1461 | ||
1462 | /* | |
1463 | * Apply a video mode. This will apply the whole register set, including | |
1464 | * the PLL registers, to the card | |
1465 | */ | |
1466 | void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, | |
1467 | int regs_only) | |
1468 | { | |
1469 | int i; | |
1470 | int primary_mon = PRIMARY_MONITOR(rinfo); | |
1471 | ||
1472 | if (nomodeset) | |
1473 | return; | |
1474 | ||
1475 | if (!regs_only) | |
1476 | radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0); | |
1477 | ||
6c34bc29 | 1478 | radeon_fifo_wait(31); |
1da177e4 LT |
1479 | for (i=0; i<10; i++) |
1480 | OUTREG(common_regs[i].reg, common_regs[i].val); | |
1481 | ||
1482 | /* Apply surface registers */ | |
1483 | for (i=0; i<8; i++) { | |
1484 | OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); | |
1485 | OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); | |
1486 | OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); | |
1487 | } | |
1488 | ||
1489 | OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); | |
1490 | OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, | |
1491 | ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); | |
1492 | OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); | |
1493 | OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); | |
1494 | OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); | |
1495 | OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); | |
1496 | OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); | |
1497 | OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); | |
1498 | OUTREG(CRTC_OFFSET, 0); | |
1499 | OUTREG(CRTC_OFFSET_CNTL, 0); | |
1500 | OUTREG(CRTC_PITCH, mode->crtc_pitch); | |
1501 | OUTREG(SURFACE_CNTL, mode->surface_cntl); | |
1502 | ||
1503 | radeon_write_pll_regs(rinfo, mode); | |
1504 | ||
1505 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
6c34bc29 | 1506 | radeon_fifo_wait(10); |
1da177e4 LT |
1507 | OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); |
1508 | OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); | |
1509 | OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); | |
1510 | OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); | |
1511 | OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); | |
1512 | OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); | |
1513 | OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); | |
1514 | OUTREG(TMDS_CRC, mode->tmds_crc); | |
1515 | OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); | |
1516 | } | |
1517 | ||
1518 | if (!regs_only) | |
1519 | radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0); | |
1520 | ||
6c34bc29 | 1521 | radeon_fifo_wait(2); |
1da177e4 LT |
1522 | OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); |
1523 | ||
1524 | return; | |
1525 | } | |
1526 | ||
1527 | /* | |
1528 | * Calculate the PLL values for a given mode | |
1529 | */ | |
1530 | static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, | |
1531 | unsigned long freq) | |
1532 | { | |
0c09dd05 | 1533 | static const struct { |
1da177e4 LT |
1534 | int divider; |
1535 | int bitvalue; | |
1536 | } *post_div, | |
1537 | post_divs[] = { | |
1538 | { 1, 0 }, | |
1539 | { 2, 1 }, | |
1540 | { 4, 2 }, | |
1541 | { 8, 3 }, | |
1542 | { 3, 4 }, | |
1543 | { 16, 5 }, | |
1544 | { 6, 6 }, | |
1545 | { 12, 7 }, | |
1546 | { 0, 0 }, | |
1547 | }; | |
1548 | int fb_div, pll_output_freq = 0; | |
1549 | int uses_dvo = 0; | |
1550 | ||
1551 | /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm | |
1552 | * not sure which model starts having FP2_GEN_CNTL, I assume anything more | |
1553 | * recent than an r(v)100... | |
1554 | */ | |
1555 | #if 1 | |
1556 | /* XXX I had reports of flicker happening with the cinema display | |
1557 | * on TMDS1 that seem to be fixed if I also forbit odd dividers in | |
1558 | * this case. This could just be a bandwidth calculation issue, I | |
1559 | * haven't implemented the bandwidth code yet, but in the meantime, | |
1560 | * forcing uses_dvo to 1 fixes it and shouln't have bad side effects, | |
1561 | * I haven't seen a case were were absolutely needed an odd PLL | |
1562 | * divider. I'll find a better fix once I have more infos on the | |
1563 | * real cause of the problem. | |
1564 | */ | |
1565 | while (rinfo->has_CRTC2) { | |
1566 | u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL); | |
1567 | u32 disp_output_cntl; | |
1568 | int source; | |
1569 | ||
1570 | /* FP2 path not enabled */ | |
1571 | if ((fp2_gen_cntl & FP2_ON) == 0) | |
1572 | break; | |
1573 | /* Not all chip revs have the same format for this register, | |
1574 | * extract the source selection | |
1575 | */ | |
a6c0c37d | 1576 | if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { |
1da177e4 LT |
1577 | source = (fp2_gen_cntl >> 10) & 0x3; |
1578 | /* sourced from transform unit, check for transform unit | |
1579 | * own source | |
1580 | */ | |
1581 | if (source == 3) { | |
1582 | disp_output_cntl = INREG(DISP_OUTPUT_CNTL); | |
1583 | source = (disp_output_cntl >> 12) & 0x3; | |
1584 | } | |
1585 | } else | |
1586 | source = (fp2_gen_cntl >> 13) & 0x1; | |
1587 | /* sourced from CRTC2 -> exit */ | |
1588 | if (source == 1) | |
1589 | break; | |
1590 | ||
1591 | /* so we end up on CRTC1, let's set uses_dvo to 1 now */ | |
1592 | uses_dvo = 1; | |
1593 | break; | |
1594 | } | |
1595 | #else | |
1596 | uses_dvo = 1; | |
1597 | #endif | |
1598 | if (freq > rinfo->pll.ppll_max) | |
1599 | freq = rinfo->pll.ppll_max; | |
1600 | if (freq*12 < rinfo->pll.ppll_min) | |
1601 | freq = rinfo->pll.ppll_min / 12; | |
bc3bf466 | 1602 | pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n", |
1da177e4 LT |
1603 | freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); |
1604 | ||
1605 | for (post_div = &post_divs[0]; post_div->divider; ++post_div) { | |
1606 | pll_output_freq = post_div->divider * freq; | |
1607 | /* If we output to the DVO port (external TMDS), we don't allow an | |
1608 | * odd PLL divider as those aren't supported on this path | |
1609 | */ | |
1610 | if (uses_dvo && (post_div->divider & 1)) | |
1611 | continue; | |
1612 | if (pll_output_freq >= rinfo->pll.ppll_min && | |
1613 | pll_output_freq <= rinfo->pll.ppll_max) | |
1614 | break; | |
1615 | } | |
1616 | ||
1617 | /* If we fall through the bottom, try the "default value" | |
1618 | given by the terminal post_div->bitvalue */ | |
1619 | if ( !post_div->divider ) { | |
1620 | post_div = &post_divs[post_div->bitvalue]; | |
1621 | pll_output_freq = post_div->divider * freq; | |
1622 | } | |
bc3bf466 | 1623 | pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", |
1da177e4 LT |
1624 | rinfo->pll.ref_div, rinfo->pll.ref_clk, |
1625 | pll_output_freq); | |
1626 | ||
1627 | /* If we fall through the bottom, try the "default value" | |
1628 | given by the terminal post_div->bitvalue */ | |
1629 | if ( !post_div->divider ) { | |
1630 | post_div = &post_divs[post_div->bitvalue]; | |
1631 | pll_output_freq = post_div->divider * freq; | |
1632 | } | |
bc3bf466 | 1633 | pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n", |
1da177e4 LT |
1634 | rinfo->pll.ref_div, rinfo->pll.ref_clk, |
1635 | pll_output_freq); | |
1636 | ||
1637 | fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, | |
1638 | rinfo->pll.ref_clk); | |
1639 | regs->ppll_ref_div = rinfo->pll.ref_div; | |
1640 | regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); | |
1641 | ||
bc3bf466 JD |
1642 | pr_debug("post div = 0x%x\n", post_div->bitvalue); |
1643 | pr_debug("fb_div = 0x%x\n", fb_div); | |
1644 | pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); | |
1da177e4 LT |
1645 | } |
1646 | ||
1647 | static int radeonfb_set_par(struct fb_info *info) | |
1648 | { | |
1649 | struct radeonfb_info *rinfo = info->par; | |
1650 | struct fb_var_screeninfo *mode = &info->var; | |
1651 | struct radeon_regs *newmode; | |
1652 | int hTotal, vTotal, hSyncStart, hSyncEnd, | |
1653 | hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync; | |
1654 | u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5}; | |
1655 | u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5}; | |
1656 | u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock; | |
1657 | int i, freq; | |
1658 | int format = 0; | |
1659 | int nopllcalc = 0; | |
1660 | int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid; | |
1661 | int primary_mon = PRIMARY_MONITOR(rinfo); | |
1662 | int depth = var_to_depth(mode); | |
1663 | int use_rmx = 0; | |
1664 | ||
1665 | newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL); | |
1666 | if (!newmode) | |
1667 | return -ENOMEM; | |
1668 | ||
1669 | /* We always want engine to be idle on a mode switch, even | |
1670 | * if we won't actually change the mode | |
1671 | */ | |
6c34bc29 | 1672 | radeon_engine_idle(); |
1da177e4 LT |
1673 | |
1674 | hSyncStart = mode->xres + mode->right_margin; | |
1675 | hSyncEnd = hSyncStart + mode->hsync_len; | |
1676 | hTotal = hSyncEnd + mode->left_margin; | |
1677 | ||
1678 | vSyncStart = mode->yres + mode->lower_margin; | |
1679 | vSyncEnd = vSyncStart + mode->vsync_len; | |
1680 | vTotal = vSyncEnd + mode->upper_margin; | |
1681 | pixClock = mode->pixclock; | |
1682 | ||
1683 | sync = mode->sync; | |
1684 | h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; | |
1685 | v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; | |
1686 | ||
1687 | if (primary_mon == MT_DFP || primary_mon == MT_LCD) { | |
1688 | if (rinfo->panel_info.xres < mode->xres) | |
1689 | mode->xres = rinfo->panel_info.xres; | |
1690 | if (rinfo->panel_info.yres < mode->yres) | |
1691 | mode->yres = rinfo->panel_info.yres; | |
1692 | ||
1693 | hTotal = mode->xres + rinfo->panel_info.hblank; | |
1694 | hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; | |
1695 | hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; | |
1696 | ||
1697 | vTotal = mode->yres + rinfo->panel_info.vblank; | |
1698 | vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; | |
1699 | vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; | |
1700 | ||
1701 | h_sync_pol = !rinfo->panel_info.hAct_high; | |
1702 | v_sync_pol = !rinfo->panel_info.vAct_high; | |
1703 | ||
1704 | pixClock = 100000000 / rinfo->panel_info.clock; | |
1705 | ||
1706 | if (rinfo->panel_info.use_bios_dividers) { | |
1707 | nopllcalc = 1; | |
1708 | newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | | |
1709 | (rinfo->panel_info.post_divider << 16); | |
1710 | newmode->ppll_ref_div = rinfo->panel_info.ref_divider; | |
1711 | } | |
1712 | } | |
1713 | dotClock = 1000000000 / pixClock; | |
1714 | freq = dotClock / 10; /* x100 */ | |
1715 | ||
bc3bf466 | 1716 | pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n", |
1da177e4 | 1717 | hSyncStart, hSyncEnd, hTotal); |
bc3bf466 | 1718 | pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n", |
1da177e4 LT |
1719 | vSyncStart, vSyncEnd, vTotal); |
1720 | ||
1721 | hsync_wid = (hSyncEnd - hSyncStart) / 8; | |
1722 | vsync_wid = vSyncEnd - vSyncStart; | |
1723 | if (hsync_wid == 0) | |
1724 | hsync_wid = 1; | |
1725 | else if (hsync_wid > 0x3f) /* max */ | |
1726 | hsync_wid = 0x3f; | |
1727 | ||
1728 | if (vsync_wid == 0) | |
1729 | vsync_wid = 1; | |
1730 | else if (vsync_wid > 0x1f) /* max */ | |
1731 | vsync_wid = 0x1f; | |
1732 | ||
1733 | hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; | |
1734 | vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; | |
1735 | ||
1736 | cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; | |
1737 | ||
1738 | format = radeon_get_dstbpp(depth); | |
1739 | bytpp = mode->bits_per_pixel >> 3; | |
1740 | ||
1741 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) | |
1742 | hsync_fudge = hsync_fudge_fp[format-1]; | |
1743 | else | |
1744 | hsync_fudge = hsync_adj_tab[format-1]; | |
1745 | ||
1746 | hsync_start = hSyncStart - 8 + hsync_fudge; | |
1747 | ||
1748 | newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | | |
1749 | (format << 8); | |
1750 | ||
1751 | /* Clear auto-center etc... */ | |
1752 | newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; | |
1753 | newmode->crtc_more_cntl &= 0xfffffff0; | |
1754 | ||
1755 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
1756 | newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; | |
1757 | if (mirror) | |
1758 | newmode->crtc_ext_cntl |= CRTC_CRT_ON; | |
1759 | ||
1760 | newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | | |
1761 | CRTC_INTERLACE_EN); | |
1762 | } else { | |
1763 | newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | | |
1764 | CRTC_CRT_ON; | |
1765 | } | |
1766 | ||
1767 | newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | | |
1768 | DAC_8BIT_EN; | |
1769 | ||
1770 | newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | | |
1771 | (((mode->xres / 8) - 1) << 16)); | |
1772 | ||
1773 | newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | | |
1774 | (hsync_wid << 16) | (h_sync_pol << 23)); | |
1775 | ||
1776 | newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | | |
1777 | ((mode->yres - 1) << 16); | |
1778 | ||
1779 | newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | | |
1780 | (vsync_wid << 16) | (v_sync_pol << 23)); | |
1781 | ||
1782 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { | |
1783 | /* We first calculate the engine pitch */ | |
1784 | rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) | |
1785 | & ~(0x3f)) >> 6; | |
1786 | ||
1787 | /* Then, re-multiply it to get the CRTC pitch */ | |
1788 | newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); | |
1789 | } else | |
1790 | newmode->crtc_pitch = (mode->xres_virtual >> 3); | |
1791 | ||
1792 | newmode->crtc_pitch |= (newmode->crtc_pitch << 16); | |
1793 | ||
1794 | /* | |
1795 | * It looks like recent chips have a problem with SURFACE_CNTL, | |
1796 | * setting SURF_TRANSLATION_DIS completely disables the | |
1797 | * swapper as well, so we leave it unset now. | |
1798 | */ | |
1799 | newmode->surface_cntl = 0; | |
1800 | ||
1801 | #if defined(__BIG_ENDIAN) | |
1802 | ||
1803 | /* Setup swapping on both apertures, though we currently | |
1804 | * only use aperture 0, enabling swapper on aperture 1 | |
1805 | * won't harm | |
1806 | */ | |
1807 | switch (mode->bits_per_pixel) { | |
1808 | case 16: | |
1809 | newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; | |
1810 | newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; | |
1811 | break; | |
1812 | case 24: | |
1813 | case 32: | |
1814 | newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; | |
1815 | newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; | |
1816 | break; | |
1817 | } | |
1818 | #endif | |
1819 | ||
1820 | /* Clear surface registers */ | |
1821 | for (i=0; i<8; i++) { | |
1822 | newmode->surf_lower_bound[i] = 0; | |
1823 | newmode->surf_upper_bound[i] = 0x1f; | |
1824 | newmode->surf_info[i] = 0; | |
1825 | } | |
1826 | ||
bc3bf466 | 1827 | pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n", |
1da177e4 | 1828 | newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); |
bc3bf466 | 1829 | pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n", |
1da177e4 LT |
1830 | newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); |
1831 | ||
1832 | rinfo->bpp = mode->bits_per_pixel; | |
1833 | rinfo->depth = depth; | |
1834 | ||
bc3bf466 JD |
1835 | pr_debug("pixclock = %lu\n", (unsigned long)pixClock); |
1836 | pr_debug("freq = %lu\n", (unsigned long)freq); | |
1da177e4 LT |
1837 | |
1838 | /* We use PPLL_DIV_3 */ | |
1839 | newmode->clk_cntl_index = 0x300; | |
1840 | ||
1841 | /* Calculate PPLL value if necessary */ | |
1842 | if (!nopllcalc) | |
1843 | radeon_calc_pll_regs(rinfo, newmode, freq); | |
1844 | ||
1845 | newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; | |
1846 | ||
1847 | if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) { | |
1848 | unsigned int hRatio, vRatio; | |
1849 | ||
1850 | if (mode->xres > rinfo->panel_info.xres) | |
1851 | mode->xres = rinfo->panel_info.xres; | |
1852 | if (mode->yres > rinfo->panel_info.yres) | |
1853 | mode->yres = rinfo->panel_info.yres; | |
1854 | ||
1855 | newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) | |
1856 | << HORZ_PANEL_SHIFT); | |
1857 | newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) | |
1858 | << VERT_PANEL_SHIFT); | |
1859 | ||
1860 | if (mode->xres != rinfo->panel_info.xres) { | |
1861 | hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, | |
1862 | rinfo->panel_info.xres); | |
1863 | newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | | |
1864 | (newmode->fp_horz_stretch & | |
1865 | (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH | | |
1866 | HORZ_AUTO_RATIO_INC))); | |
1867 | newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | | |
1868 | HORZ_STRETCH_ENABLE); | |
1869 | use_rmx = 1; | |
1870 | } | |
1871 | newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; | |
1872 | ||
1873 | if (mode->yres != rinfo->panel_info.yres) { | |
1874 | vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, | |
1875 | rinfo->panel_info.yres); | |
1876 | newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | | |
1877 | (newmode->fp_vert_stretch & | |
1878 | (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED))); | |
1879 | newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | | |
1880 | VERT_STRETCH_ENABLE); | |
1881 | use_rmx = 1; | |
1882 | } | |
1883 | newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; | |
1884 | ||
1885 | newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) | |
1886 | ~(FP_SEL_CRTC2 | | |
1887 | FP_RMX_HVSYNC_CONTROL_EN | | |
1888 | FP_DFP_SYNC_SEL | | |
1889 | FP_CRT_SYNC_SEL | | |
1890 | FP_CRTC_LOCK_8DOT | | |
1891 | FP_USE_SHADOW_EN | | |
1892 | FP_CRTC_USE_SHADOW_VEND | | |
1893 | FP_CRT_SYNC_ALT)); | |
1894 | ||
1895 | newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | | |
1896 | FP_CRTC_DONT_SHADOW_HEND | | |
1897 | FP_PANEL_FORMAT); | |
1898 | ||
1899 | if (IS_R300_VARIANT(rinfo) || | |
1900 | (rinfo->family == CHIP_FAMILY_R200)) { | |
1901 | newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; | |
1902 | if (use_rmx) | |
1903 | newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; | |
1904 | else | |
1905 | newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; | |
1906 | } else | |
1907 | newmode->fp_gen_cntl |= FP_SEL_CRTC1; | |
1908 | ||
1909 | newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; | |
1910 | newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; | |
1911 | newmode->tmds_crc = rinfo->init_state.tmds_crc; | |
1912 | newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; | |
1913 | ||
1914 | if (primary_mon == MT_LCD) { | |
1915 | newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); | |
1916 | newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); | |
1917 | } else { | |
1918 | /* DFP */ | |
1919 | newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); | |
1920 | newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); | |
1921 | /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */ | |
1922 | if (IS_R300_VARIANT(rinfo) || | |
1923 | (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) | |
1924 | newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; | |
1925 | else | |
1926 | newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; | |
1927 | newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; | |
1928 | } | |
1929 | ||
1930 | newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | | |
1931 | (((mode->xres / 8) - 1) << 16)); | |
1932 | newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | | |
1933 | ((mode->yres - 1) << 16); | |
1934 | newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | | |
1935 | (hsync_wid << 16) | (h_sync_pol << 23)); | |
1936 | newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | | |
1937 | (vsync_wid << 16) | (v_sync_pol << 23)); | |
1938 | } | |
1939 | ||
1940 | /* do it! */ | |
1941 | if (!rinfo->asleep) { | |
1942 | memcpy(&rinfo->state, newmode, sizeof(*newmode)); | |
1943 | radeon_write_mode (rinfo, newmode, 0); | |
1944 | /* (re)initialize the engine */ | |
1945 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1946 | radeonfb_engine_init (rinfo); | |
1947 | } | |
1948 | /* Update fix */ | |
1949 | if (!(info->flags & FBINFO_HWACCEL_DISABLED)) | |
1950 | info->fix.line_length = rinfo->pitch*64; | |
1951 | else | |
1952 | info->fix.line_length = mode->xres_virtual | |
1953 | * ((mode->bits_per_pixel + 1) / 8); | |
1954 | info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR | |
1955 | : FB_VISUAL_DIRECTCOLOR; | |
1956 | ||
1957 | #ifdef CONFIG_BOOTX_TEXT | |
1958 | /* Update debug text engine */ | |
1959 | btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, | |
1960 | rinfo->depth, info->fix.line_length); | |
1961 | #endif | |
1962 | ||
1963 | kfree(newmode); | |
1964 | return 0; | |
1965 | } | |
1966 | ||
6c34bc29 | 1967 | |
1da177e4 LT |
1968 | static struct fb_ops radeonfb_ops = { |
1969 | .owner = THIS_MODULE, | |
1970 | .fb_check_var = radeonfb_check_var, | |
1971 | .fb_set_par = radeonfb_set_par, | |
1972 | .fb_setcolreg = radeonfb_setcolreg, | |
71494376 | 1973 | .fb_setcmap = radeonfb_setcmap, |
1da177e4 LT |
1974 | .fb_pan_display = radeonfb_pan_display, |
1975 | .fb_blank = radeonfb_blank, | |
1976 | .fb_ioctl = radeonfb_ioctl, | |
1977 | .fb_sync = radeonfb_sync, | |
1978 | .fb_fillrect = radeonfb_fillrect, | |
1979 | .fb_copyarea = radeonfb_copyarea, | |
1980 | .fb_imageblit = radeonfb_imageblit, | |
1da177e4 LT |
1981 | }; |
1982 | ||
1983 | ||
48c68c4f | 1984 | static int radeon_set_fbinfo(struct radeonfb_info *rinfo) |
1da177e4 LT |
1985 | { |
1986 | struct fb_info *info = rinfo->info; | |
1987 | ||
1988 | info->par = rinfo; | |
1989 | info->pseudo_palette = rinfo->pseudo_palette; | |
1990 | info->flags = FBINFO_DEFAULT | |
1991 | | FBINFO_HWACCEL_COPYAREA | |
1992 | | FBINFO_HWACCEL_FILLRECT | |
1993 | | FBINFO_HWACCEL_XPAN | |
1994 | | FBINFO_HWACCEL_YPAN; | |
1995 | info->fbops = &radeonfb_ops; | |
1996 | info->screen_base = rinfo->fb_base; | |
1997 | info->screen_size = rinfo->mapped_vram; | |
1998 | /* Fill fix common fields */ | |
1999 | strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); | |
2000 | info->fix.smem_start = rinfo->fb_base_phys; | |
2001 | info->fix.smem_len = rinfo->video_ram; | |
2002 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
2003 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
2004 | info->fix.xpanstep = 8; | |
2005 | info->fix.ypanstep = 1; | |
2006 | info->fix.ywrapstep = 0; | |
2007 | info->fix.type_aux = 0; | |
2008 | info->fix.mmio_start = rinfo->mmio_base_phys; | |
2009 | info->fix.mmio_len = RADEON_REGSIZE; | |
2010 | info->fix.accel = FB_ACCEL_ATI_RADEON; | |
2011 | ||
2012 | fb_alloc_cmap(&info->cmap, 256, 0); | |
2013 | ||
2014 | if (noaccel) | |
2015 | info->flags |= FBINFO_HWACCEL_DISABLED; | |
2016 | ||
2017 | return 0; | |
2018 | } | |
2019 | ||
1da177e4 LT |
2020 | /* |
2021 | * This reconfigure the card's internal memory map. In theory, we'd like | |
2022 | * to setup the card's memory at the same address as it's PCI bus address, | |
2023 | * and the AGP aperture right after that so that system RAM on 32 bits | |
2024 | * machines at least, is directly accessible. However, doing so would | |
2025 | * conflict with the current XFree drivers... | |
2026 | * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree | |
2027 | * on the proper way to set this up and duplicate this here. In the meantime, | |
2028 | * I put the card's memory at 0 in card space and AGP at some random high | |
2029 | * local (0xe0000000 for now) that will be changed by XFree/DRI anyway | |
2030 | */ | |
758ddd1d | 2031 | #ifdef CONFIG_PPC |
1da177e4 LT |
2032 | #undef SET_MC_FB_FROM_APERTURE |
2033 | static void fixup_memory_mappings(struct radeonfb_info *rinfo) | |
2034 | { | |
2035 | u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0; | |
2036 | u32 save_crtc_ext_cntl; | |
2037 | u32 aper_base, aper_size; | |
2038 | u32 agp_base; | |
2039 | ||
2040 | /* First, we disable display to avoid interfering */ | |
2041 | if (rinfo->has_CRTC2) { | |
2042 | save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL); | |
2043 | OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B); | |
2044 | } | |
2045 | save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL); | |
2046 | save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL); | |
2047 | ||
2048 | OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS); | |
2049 | OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B); | |
2050 | mdelay(100); | |
2051 | ||
fe86175b RD |
2052 | aper_base = INREG(CNFG_APER_0_BASE); |
2053 | aper_size = INREG(CNFG_APER_SIZE); | |
1da177e4 LT |
2054 | |
2055 | #ifdef SET_MC_FB_FROM_APERTURE | |
2056 | /* Set framebuffer to be at the same address as set in PCI BAR */ | |
2057 | OUTREG(MC_FB_LOCATION, | |
2058 | ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); | |
2059 | rinfo->fb_local_base = aper_base; | |
2060 | #else | |
2061 | OUTREG(MC_FB_LOCATION, 0x7fff0000); | |
2062 | rinfo->fb_local_base = 0; | |
2063 | #endif | |
2064 | agp_base = aper_base + aper_size; | |
2065 | if (agp_base & 0xf0000000) | |
2066 | agp_base = (aper_base | 0x0fffffff) + 1; | |
2067 | ||
2068 | /* Set AGP to be just after the framebuffer on a 256Mb boundary. This | |
2069 | * assumes the FB isn't mapped to 0xf0000000 or above, but this is | |
2070 | * always the case on PPCs afaik. | |
2071 | */ | |
2072 | #ifdef SET_MC_FB_FROM_APERTURE | |
2073 | OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16)); | |
2074 | #else | |
2075 | OUTREG(MC_AGP_LOCATION, 0xffffe000); | |
2076 | #endif | |
2077 | ||
2078 | /* Fixup the display base addresses & engine offsets while we | |
2079 | * are at it as well | |
2080 | */ | |
2081 | #ifdef SET_MC_FB_FROM_APERTURE | |
2082 | OUTREG(DISPLAY_BASE_ADDR, aper_base); | |
2083 | if (rinfo->has_CRTC2) | |
2084 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base); | |
2085 | OUTREG(OV0_BASE_ADDR, aper_base); | |
2086 | #else | |
2087 | OUTREG(DISPLAY_BASE_ADDR, 0); | |
2088 | if (rinfo->has_CRTC2) | |
2089 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0); | |
2090 | OUTREG(OV0_BASE_ADDR, 0); | |
2091 | #endif | |
2092 | mdelay(100); | |
2093 | ||
2094 | /* Restore display settings */ | |
2095 | OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl); | |
2096 | OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl); | |
2097 | if (rinfo->has_CRTC2) | |
2098 | OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl); | |
2099 | ||
bc3bf466 | 2100 | pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n", |
1da177e4 LT |
2101 | aper_base, |
2102 | ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), | |
2103 | 0xffff0000 | (agp_base >> 16)); | |
2104 | } | |
758ddd1d | 2105 | #endif /* CONFIG_PPC */ |
1da177e4 LT |
2106 | |
2107 | ||
2108 | static void radeon_identify_vram(struct radeonfb_info *rinfo) | |
2109 | { | |
2110 | u32 tmp; | |
2111 | ||
2112 | /* framebuffer size */ | |
2113 | if ((rinfo->family == CHIP_FAMILY_RS100) || | |
2114 | (rinfo->family == CHIP_FAMILY_RS200) || | |
dd144713 | 2115 | (rinfo->family == CHIP_FAMILY_RS300) || |
0b693eaf | 2116 | (rinfo->family == CHIP_FAMILY_RC410) || |
a6c0c37d | 2117 | (rinfo->family == CHIP_FAMILY_RS400) || |
dd144713 | 2118 | (rinfo->family == CHIP_FAMILY_RS480) ) { |
1da177e4 LT |
2119 | u32 tom = INREG(NB_TOM); |
2120 | tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); | |
2121 | ||
6c34bc29 | 2122 | radeon_fifo_wait(6); |
1da177e4 LT |
2123 | OUTREG(MC_FB_LOCATION, tom); |
2124 | OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | |
2125 | OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); | |
2126 | OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); | |
2127 | ||
2128 | /* This is supposed to fix the crtc2 noise problem. */ | |
2129 | OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); | |
2130 | ||
2131 | if ((rinfo->family == CHIP_FAMILY_RS100) || | |
2132 | (rinfo->family == CHIP_FAMILY_RS200)) { | |
2133 | /* This is to workaround the asic bug for RMX, some versions | |
ff0c2642 | 2134 | of BIOS doesn't have this register initialized correctly. |
1da177e4 LT |
2135 | */ |
2136 | OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, | |
2137 | ~CRTC_H_CUTOFF_ACTIVE_EN); | |
2138 | } | |
2139 | } else { | |
fe86175b | 2140 | tmp = INREG(CNFG_MEMSIZE); |
1da177e4 LT |
2141 | } |
2142 | ||
2143 | /* mem size is bits [28:0], mask off the rest */ | |
fe86175b | 2144 | rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; |
1da177e4 LT |
2145 | |
2146 | /* | |
2147 | * Hack to get around some busted production M6's | |
2148 | * reporting no ram | |
2149 | */ | |
2150 | if (rinfo->video_ram == 0) { | |
2151 | switch (rinfo->pdev->device) { | |
2152 | case PCI_CHIP_RADEON_LY: | |
2153 | case PCI_CHIP_RADEON_LZ: | |
2154 | rinfo->video_ram = 8192 * 1024; | |
2155 | break; | |
2156 | default: | |
2157 | break; | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | ||
2162 | /* | |
2163 | * Now try to identify VRAM type | |
2164 | */ | |
2165 | if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || | |
2166 | (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) | |
2167 | rinfo->vram_ddr = 1; | |
2168 | else | |
2169 | rinfo->vram_ddr = 0; | |
2170 | ||
2171 | tmp = INREG(MEM_CNTL); | |
2172 | if (IS_R300_VARIANT(rinfo)) { | |
2173 | tmp &= R300_MEM_NUM_CHANNELS_MASK; | |
2174 | switch (tmp) { | |
2175 | case 0: rinfo->vram_width = 64; break; | |
2176 | case 1: rinfo->vram_width = 128; break; | |
2177 | case 2: rinfo->vram_width = 256; break; | |
2178 | default: rinfo->vram_width = 128; break; | |
2179 | } | |
2180 | } else if ((rinfo->family == CHIP_FAMILY_RV100) || | |
2181 | (rinfo->family == CHIP_FAMILY_RS100) || | |
2182 | (rinfo->family == CHIP_FAMILY_RS200)){ | |
2183 | if (tmp & RV100_MEM_HALF_MODE) | |
2184 | rinfo->vram_width = 32; | |
2185 | else | |
2186 | rinfo->vram_width = 64; | |
2187 | } else { | |
2188 | if (tmp & MEM_NUM_CHANNELS_MASK) | |
2189 | rinfo->vram_width = 128; | |
2190 | else | |
2191 | rinfo->vram_width = 64; | |
2192 | } | |
2193 | ||
2194 | /* This may not be correct, as some cards can have half of channel disabled | |
2195 | * ToDo: identify these cases | |
2196 | */ | |
2197 | ||
bc3bf466 | 2198 | pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n", |
1da177e4 LT |
2199 | pci_name(rinfo->pdev), |
2200 | rinfo->video_ram / 1024, | |
2201 | rinfo->vram_ddr ? "DDR" : "SDRAM", | |
2202 | rinfo->vram_width); | |
2203 | } | |
2204 | ||
2205 | /* | |
2206 | * Sysfs | |
2207 | */ | |
2208 | ||
2209 | static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid) | |
2210 | { | |
a882ef47 | 2211 | return memory_read_from_buffer(buf, count, &off, edid, EDID_LENGTH); |
1da177e4 LT |
2212 | } |
2213 | ||
2214 | ||
2c3c8bea | 2215 | static ssize_t radeon_show_edid1(struct file *filp, struct kobject *kobj, |
91a69029 ZR |
2216 | struct bin_attribute *bin_attr, |
2217 | char *buf, loff_t off, size_t count) | |
1da177e4 LT |
2218 | { |
2219 | struct device *dev = container_of(kobj, struct device, kobj); | |
2220 | struct pci_dev *pdev = to_pci_dev(dev); | |
2221 | struct fb_info *info = pci_get_drvdata(pdev); | |
2222 | struct radeonfb_info *rinfo = info->par; | |
2223 | ||
2224 | return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); | |
2225 | } | |
2226 | ||
2227 | ||
2c3c8bea | 2228 | static ssize_t radeon_show_edid2(struct file *filp, struct kobject *kobj, |
91a69029 ZR |
2229 | struct bin_attribute *bin_attr, |
2230 | char *buf, loff_t off, size_t count) | |
1da177e4 LT |
2231 | { |
2232 | struct device *dev = container_of(kobj, struct device, kobj); | |
2233 | struct pci_dev *pdev = to_pci_dev(dev); | |
2234 | struct fb_info *info = pci_get_drvdata(pdev); | |
2235 | struct radeonfb_info *rinfo = info->par; | |
2236 | ||
2237 | return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); | |
2238 | } | |
2239 | ||
598b2eed | 2240 | static const struct bin_attribute edid1_attr = { |
1da177e4 LT |
2241 | .attr = { |
2242 | .name = "edid1", | |
1da177e4 LT |
2243 | .mode = 0444, |
2244 | }, | |
2245 | .size = EDID_LENGTH, | |
2246 | .read = radeon_show_edid1, | |
2247 | }; | |
2248 | ||
598b2eed | 2249 | static const struct bin_attribute edid2_attr = { |
1da177e4 LT |
2250 | .attr = { |
2251 | .name = "edid2", | |
1da177e4 LT |
2252 | .mode = 0444, |
2253 | }, | |
2254 | .size = EDID_LENGTH, | |
2255 | .read = radeon_show_edid2, | |
2256 | }; | |
2257 | ||
069ee21a MM |
2258 | static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) |
2259 | { | |
2260 | struct apertures_struct *ap; | |
2261 | ||
2262 | ap = alloc_apertures(1); | |
2263 | if (!ap) | |
2264 | return -ENOMEM; | |
2265 | ||
2266 | ap->ranges[0].base = pci_resource_start(pdev, 0); | |
2267 | ap->ranges[0].size = pci_resource_len(pdev, 0); | |
2268 | ||
2269 | remove_conflicting_framebuffers(ap, KBUILD_MODNAME, false); | |
2270 | ||
2271 | kfree(ap); | |
2272 | ||
2273 | return 0; | |
2274 | } | |
1da177e4 | 2275 | |
48c68c4f GKH |
2276 | static int radeonfb_pci_register(struct pci_dev *pdev, |
2277 | const struct pci_device_id *ent) | |
1da177e4 LT |
2278 | { |
2279 | struct fb_info *info; | |
2280 | struct radeonfb_info *rinfo; | |
2281 | int ret; | |
e7a18c9c | 2282 | unsigned char c1, c2; |
fcea8030 | 2283 | int err = 0; |
1da177e4 | 2284 | |
bc3bf466 | 2285 | pr_debug("radeonfb_pci_register BEGIN\n"); |
1da177e4 LT |
2286 | |
2287 | /* Enable device in PCI config */ | |
2288 | ret = pci_enable_device(pdev); | |
2289 | if (ret < 0) { | |
2290 | printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n", | |
2291 | pci_name(pdev)); | |
2292 | goto err_out; | |
2293 | } | |
2294 | ||
2295 | info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); | |
2296 | if (!info) { | |
2297 | printk (KERN_ERR "radeonfb (%s): could not allocate memory\n", | |
2298 | pci_name(pdev)); | |
2299 | ret = -ENOMEM; | |
2300 | goto err_disable; | |
2301 | } | |
2302 | rinfo = info->par; | |
2303 | rinfo->info = info; | |
2304 | rinfo->pdev = pdev; | |
2305 | ||
2306 | spin_lock_init(&rinfo->reg_lock); | |
6c789357 | 2307 | timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0); |
1da177e4 | 2308 | |
e7a18c9c AH |
2309 | c1 = ent->device >> 8; |
2310 | c2 = ent->device & 0xff; | |
2311 | if (isprint(c1) && isprint(c2)) | |
2312 | snprintf(rinfo->name, sizeof(rinfo->name), | |
2313 | "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); | |
2314 | else | |
2315 | snprintf(rinfo->name, sizeof(rinfo->name), | |
2316 | "ATI Radeon %x", ent->device & 0xffff); | |
2317 | ||
1da177e4 LT |
2318 | rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; |
2319 | rinfo->chipset = pdev->device; | |
2320 | rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; | |
2321 | rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; | |
2322 | rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; | |
2323 | ||
2324 | /* Set base addrs */ | |
2325 | rinfo->fb_base_phys = pci_resource_start (pdev, 0); | |
2326 | rinfo->mmio_base_phys = pci_resource_start (pdev, 2); | |
2327 | ||
069ee21a MM |
2328 | ret = radeon_kick_out_firmware_fb(pdev); |
2329 | if (ret) | |
2330 | return ret; | |
2331 | ||
1da177e4 | 2332 | /* request the mem regions */ |
5251bffc | 2333 | ret = pci_request_region(pdev, 0, "radeonfb framebuffer"); |
1da177e4 | 2334 | if (ret < 0) { |
5251bffc DB |
2335 | printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n", |
2336 | pci_name(rinfo->pdev)); | |
1da177e4 LT |
2337 | goto err_release_fb; |
2338 | } | |
2339 | ||
5251bffc DB |
2340 | ret = pci_request_region(pdev, 2, "radeonfb mmio"); |
2341 | if (ret < 0) { | |
2342 | printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n", | |
2343 | pci_name(rinfo->pdev)); | |
2344 | goto err_release_pci0; | |
2345 | } | |
2346 | ||
1da177e4 LT |
2347 | /* map the regions */ |
2348 | rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); | |
2349 | if (!rinfo->mmio_base) { | |
5251bffc DB |
2350 | printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n", |
2351 | pci_name(rinfo->pdev)); | |
1da177e4 | 2352 | ret = -EIO; |
5251bffc | 2353 | goto err_release_pci2; |
1da177e4 LT |
2354 | } |
2355 | ||
2356 | rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; | |
2357 | ||
2358 | /* | |
2359 | * Check for errata | |
2360 | */ | |
2361 | rinfo->errata = 0; | |
2362 | if (rinfo->family == CHIP_FAMILY_R300 && | |
fe86175b | 2363 | (INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) |
1da177e4 LT |
2364 | == CFG_ATI_REV_A11) |
2365 | rinfo->errata |= CHIP_ERRATA_R300_CG; | |
2366 | ||
2367 | if (rinfo->family == CHIP_FAMILY_RV200 || | |
2368 | rinfo->family == CHIP_FAMILY_RS200) | |
2369 | rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; | |
2370 | ||
2371 | if (rinfo->family == CHIP_FAMILY_RV100 || | |
2372 | rinfo->family == CHIP_FAMILY_RS100 || | |
2373 | rinfo->family == CHIP_FAMILY_RS200) | |
2374 | rinfo->errata |= CHIP_ERRATA_PLL_DELAY; | |
2375 | ||
758ddd1d | 2376 | #if defined(CONFIG_PPC) || defined(CONFIG_SPARC) |
1da177e4 LT |
2377 | /* On PPC, we obtain the OF device-node pointer to the firmware |
2378 | * data for this chip | |
2379 | */ | |
2380 | rinfo->of_node = pci_device_to_OF_node(pdev); | |
2381 | if (rinfo->of_node == NULL) | |
2382 | printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n", | |
2383 | pci_name(rinfo->pdev)); | |
2384 | ||
758ddd1d KH |
2385 | #endif /* CONFIG_PPC || CONFIG_SPARC */ |
2386 | #ifdef CONFIG_PPC | |
1da177e4 LT |
2387 | /* On PPC, the firmware sets up a memory mapping that tends |
2388 | * to cause lockups when enabling the engine. We reconfigure | |
2389 | * the card internal memory mappings properly | |
2390 | */ | |
2391 | fixup_memory_mappings(rinfo); | |
758ddd1d | 2392 | #endif /* CONFIG_PPC */ |
1da177e4 LT |
2393 | |
2394 | /* Get VRAM size and type */ | |
2395 | radeon_identify_vram(rinfo); | |
2396 | ||
2397 | rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); | |
2398 | ||
2399 | do { | |
5e200b53 LR |
2400 | rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, |
2401 | rinfo->mapped_vram); | |
5e2daeb3 HH |
2402 | } while (rinfo->fb_base == NULL && |
2403 | ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); | |
1da177e4 | 2404 | |
8d5f7b43 BH |
2405 | if (rinfo->fb_base == NULL) { |
2406 | printk (KERN_ERR "radeonfb (%s): cannot map FB\n", | |
2407 | pci_name(rinfo->pdev)); | |
1da177e4 LT |
2408 | ret = -EIO; |
2409 | goto err_unmap_rom; | |
2410 | } | |
2411 | ||
bc3bf466 | 2412 | pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), |
1da177e4 LT |
2413 | rinfo->mapped_vram/1024); |
2414 | ||
2415 | /* | |
4a4efbde | 2416 | * Map the BIOS ROM if any and retrieve PLL parameters from |
1da177e4 LT |
2417 | * the BIOS. We skip that on mobility chips as the real panel |
2418 | * values we need aren't in the ROM but in the BIOS image in | |
2419 | * memory. This is definitely not the best meacnism though, | |
2420 | * we really need the arch code to tell us which is the "primary" | |
2421 | * video adapter to use the memory image (or better, the arch | |
2422 | * should provide us a copy of the BIOS image to shield us from | |
2423 | * archs who would store that elsewhere and/or could initialize | |
2424 | * more than one adapter during boot). | |
2425 | */ | |
2426 | if (!rinfo->is_mobility) | |
2427 | radeon_map_ROM(rinfo, pdev); | |
2428 | ||
2429 | /* | |
2430 | * On x86, the primary display on laptop may have it's BIOS | |
2431 | * ROM elsewhere, try to locate it at the legacy memory hole. | |
2432 | * We probably need to make sure this is the primary display, | |
2433 | * but that is difficult without some arch support. | |
2434 | */ | |
2435 | #ifdef CONFIG_X86 | |
2436 | if (rinfo->bios_seg == NULL) | |
2437 | radeon_find_mem_vbios(rinfo); | |
2438 | #endif | |
2439 | ||
2440 | /* If both above failed, try the BIOS ROM again for mobility | |
2441 | * chips | |
2442 | */ | |
2443 | if (rinfo->bios_seg == NULL && rinfo->is_mobility) | |
2444 | radeon_map_ROM(rinfo, pdev); | |
2445 | ||
2446 | /* Get informations about the board's PLL */ | |
2447 | radeon_get_pllinfo(rinfo); | |
2448 | ||
2449 | #ifdef CONFIG_FB_RADEON_I2C | |
2450 | /* Register I2C bus */ | |
2451 | radeon_create_i2c_busses(rinfo); | |
2452 | #endif | |
2453 | ||
2454 | /* set all the vital stuff */ | |
2455 | radeon_set_fbinfo (rinfo); | |
2456 | ||
2457 | /* Probe screen types */ | |
2458 | radeon_probe_screens(rinfo, monitor_layout, ignore_edid); | |
2459 | ||
2460 | /* Build mode list, check out panel native model */ | |
2461 | radeon_check_modes(rinfo, mode_option); | |
2462 | ||
2463 | /* Register some sysfs stuff (should be done better) */ | |
2464 | if (rinfo->mon1_EDID) | |
fcea8030 TB |
2465 | err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, |
2466 | &edid1_attr); | |
1da177e4 | 2467 | if (rinfo->mon2_EDID) |
fcea8030 TB |
2468 | err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, |
2469 | &edid2_attr); | |
2470 | if (err) | |
6f9655b1 JP |
2471 | pr_warn("%s() Creating sysfs files failed, continuing\n", |
2472 | __func__); | |
1da177e4 LT |
2473 | |
2474 | /* save current mode regs before we switch into the new one | |
2475 | * so we can restore this upon __exit | |
2476 | */ | |
2477 | radeon_save_state (rinfo, &rinfo->init_state); | |
2478 | memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); | |
2479 | ||
2480 | /* Setup Power Management capabilities */ | |
2481 | if (default_dynclk < -1) { | |
2482 | /* -2 is special: means ON on mobility chips and do not | |
2483 | * change on others | |
2484 | */ | |
994aad25 | 2485 | radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); |
1da177e4 | 2486 | } else |
994aad25 | 2487 | radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep); |
1da177e4 LT |
2488 | |
2489 | pci_set_drvdata(pdev, info); | |
2490 | ||
2491 | /* Register with fbdev layer */ | |
2492 | ret = register_framebuffer(info); | |
2493 | if (ret < 0) { | |
2494 | printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n", | |
2495 | pci_name(rinfo->pdev)); | |
2496 | goto err_unmap_fb; | |
2497 | } | |
2498 | ||
5e200b53 LR |
2499 | if (!nomtrr) |
2500 | rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, | |
2501 | rinfo->video_ram); | |
1da177e4 | 2502 | |
202d4e60 RP |
2503 | if (backlight) |
2504 | radeonfb_bl_init(rinfo); | |
1da177e4 LT |
2505 | |
2506 | printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); | |
2507 | ||
2508 | if (rinfo->bios_seg) | |
2509 | radeon_unmap_ROM(rinfo, pdev); | |
bc3bf466 | 2510 | pr_debug("radeonfb_pci_register END\n"); |
1da177e4 LT |
2511 | |
2512 | return 0; | |
2513 | err_unmap_fb: | |
2514 | iounmap(rinfo->fb_base); | |
2515 | err_unmap_rom: | |
2516 | kfree(rinfo->mon1_EDID); | |
2517 | kfree(rinfo->mon2_EDID); | |
2518 | if (rinfo->mon1_modedb) | |
2519 | fb_destroy_modedb(rinfo->mon1_modedb); | |
2520 | fb_dealloc_cmap(&info->cmap); | |
2521 | #ifdef CONFIG_FB_RADEON_I2C | |
2522 | radeon_delete_i2c_busses(rinfo); | |
2523 | #endif | |
2524 | if (rinfo->bios_seg) | |
2525 | radeon_unmap_ROM(rinfo, pdev); | |
2526 | iounmap(rinfo->mmio_base); | |
5251bffc DB |
2527 | err_release_pci2: |
2528 | pci_release_region(pdev, 2); | |
2529 | err_release_pci0: | |
2530 | pci_release_region(pdev, 0); | |
1da177e4 | 2531 | err_release_fb: |
5251bffc | 2532 | framebuffer_release(info); |
1da177e4 | 2533 | err_disable: |
1da177e4 LT |
2534 | err_out: |
2535 | return ret; | |
2536 | } | |
2537 | ||
2538 | ||
2539 | ||
48c68c4f | 2540 | static void radeonfb_pci_unregister(struct pci_dev *pdev) |
1da177e4 LT |
2541 | { |
2542 | struct fb_info *info = pci_get_drvdata(pdev); | |
2543 | struct radeonfb_info *rinfo = info->par; | |
2544 | ||
2545 | if (!rinfo) | |
2546 | return; | |
5474c120 | 2547 | |
1da177e4 LT |
2548 | radeonfb_pm_exit(rinfo); |
2549 | ||
3ca34fcb JS |
2550 | if (rinfo->mon1_EDID) |
2551 | sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); | |
2552 | if (rinfo->mon2_EDID) | |
2553 | sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); | |
2554 | ||
1da177e4 LT |
2555 | #if 0 |
2556 | /* restore original state | |
2557 | * | |
2558 | * Doesn't quite work yet, I suspect if we come from a legacy | |
2559 | * VGA mode (or worse, text mode), we need to do some VGA black | |
2560 | * magic here that I know nothing about. --BenH | |
2561 | */ | |
2562 | radeon_write_mode (rinfo, &rinfo->init_state, 1); | |
2563 | #endif | |
2564 | ||
2565 | del_timer_sync(&rinfo->lvds_timer); | |
5e200b53 | 2566 | arch_phys_wc_del(rinfo->wc_cookie); |
1da177e4 LT |
2567 | unregister_framebuffer(info); |
2568 | ||
37ce69a5 RP |
2569 | radeonfb_bl_exit(rinfo); |
2570 | ||
1da177e4 LT |
2571 | iounmap(rinfo->mmio_base); |
2572 | iounmap(rinfo->fb_base); | |
2573 | ||
5251bffc DB |
2574 | pci_release_region(pdev, 2); |
2575 | pci_release_region(pdev, 0); | |
1da177e4 LT |
2576 | |
2577 | kfree(rinfo->mon1_EDID); | |
2578 | kfree(rinfo->mon2_EDID); | |
2579 | if (rinfo->mon1_modedb) | |
2580 | fb_destroy_modedb(rinfo->mon1_modedb); | |
2581 | #ifdef CONFIG_FB_RADEON_I2C | |
2582 | radeon_delete_i2c_busses(rinfo); | |
2583 | #endif | |
2584 | fb_dealloc_cmap(&info->cmap); | |
2585 | framebuffer_release(info); | |
1da177e4 LT |
2586 | } |
2587 | ||
2588 | ||
2589 | static struct pci_driver radeonfb_driver = { | |
2590 | .name = "radeonfb", | |
2591 | .id_table = radeonfb_pci_table, | |
2592 | .probe = radeonfb_pci_register, | |
48c68c4f | 2593 | .remove = radeonfb_pci_unregister, |
1da177e4 LT |
2594 | #ifdef CONFIG_PM |
2595 | .suspend = radeonfb_pci_suspend, | |
2596 | .resume = radeonfb_pci_resume, | |
2597 | #endif /* CONFIG_PM */ | |
2598 | }; | |
2599 | ||
2600 | #ifndef MODULE | |
2601 | static int __init radeonfb_setup (char *options) | |
2602 | { | |
2603 | char *this_opt; | |
2604 | ||
2605 | if (!options || !*options) | |
2606 | return 0; | |
2607 | ||
2608 | while ((this_opt = strsep (&options, ",")) != NULL) { | |
2609 | if (!*this_opt) | |
2610 | continue; | |
2611 | ||
2612 | if (!strncmp(this_opt, "noaccel", 7)) { | |
2613 | noaccel = 1; | |
2614 | } else if (!strncmp(this_opt, "mirror", 6)) { | |
2615 | mirror = 1; | |
2616 | } else if (!strncmp(this_opt, "force_dfp", 9)) { | |
2617 | force_dfp = 1; | |
2618 | } else if (!strncmp(this_opt, "panel_yres:", 11)) { | |
2619 | panel_yres = simple_strtoul((this_opt+11), NULL, 0); | |
202d4e60 RP |
2620 | } else if (!strncmp(this_opt, "backlight:", 10)) { |
2621 | backlight = simple_strtoul(this_opt+10, NULL, 0); | |
1da177e4 LT |
2622 | } else if (!strncmp(this_opt, "nomtrr", 6)) { |
2623 | nomtrr = 1; | |
1da177e4 LT |
2624 | } else if (!strncmp(this_opt, "nomodeset", 9)) { |
2625 | nomodeset = 1; | |
2626 | } else if (!strncmp(this_opt, "force_measure_pll", 17)) { | |
2627 | force_measure_pll = 1; | |
2628 | } else if (!strncmp(this_opt, "ignore_edid", 11)) { | |
2629 | ignore_edid = 1; | |
994aad25 VB |
2630 | #if defined(CONFIG_PM) && defined(CONFIG_X86) |
2631 | } else if (!strncmp(this_opt, "force_sleep", 11)) { | |
2632 | force_sleep = 1; | |
2633 | } else if (!strncmp(this_opt, "ignore_devlist", 14)) { | |
2634 | ignore_devlist = 1; | |
2635 | #endif | |
1da177e4 LT |
2636 | } else |
2637 | mode_option = this_opt; | |
2638 | } | |
2639 | return 0; | |
2640 | } | |
2641 | #endif /* MODULE */ | |
2642 | ||
2643 | static int __init radeonfb_init (void) | |
2644 | { | |
2645 | #ifndef MODULE | |
2646 | char *option = NULL; | |
2647 | ||
2648 | if (fb_get_options("radeonfb", &option)) | |
2649 | return -ENODEV; | |
2650 | radeonfb_setup(option); | |
2651 | #endif | |
2652 | return pci_register_driver (&radeonfb_driver); | |
2653 | } | |
2654 | ||
2655 | ||
2656 | static void __exit radeonfb_exit (void) | |
2657 | { | |
2658 | pci_unregister_driver (&radeonfb_driver); | |
2659 | } | |
2660 | ||
2661 | module_init(radeonfb_init); | |
2662 | module_exit(radeonfb_exit); | |
2663 | ||
2664 | MODULE_AUTHOR("Ani Joshi"); | |
2665 | MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset"); | |
2666 | MODULE_LICENSE("GPL"); | |
2667 | module_param(noaccel, bool, 0); | |
2668 | module_param(default_dynclk, int, 0); | |
2669 | MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on"); | |
2670 | MODULE_PARM_DESC(noaccel, "bool: disable acceleration"); | |
2671 | module_param(nomodeset, bool, 0); | |
2672 | MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode"); | |
2673 | module_param(mirror, bool, 0); | |
2674 | MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors"); | |
2675 | module_param(force_dfp, bool, 0); | |
2676 | MODULE_PARM_DESC(force_dfp, "bool: force display to dfp"); | |
2677 | module_param(ignore_edid, bool, 0); | |
2678 | MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe"); | |
2679 | module_param(monitor_layout, charp, 0); | |
2680 | MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)"); | |
2681 | module_param(force_measure_pll, bool, 0); | |
2682 | MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)"); | |
1da177e4 LT |
2683 | module_param(nomtrr, bool, 0); |
2684 | MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers"); | |
1da177e4 LT |
2685 | module_param(panel_yres, int, 0); |
2686 | MODULE_PARM_DESC(panel_yres, "int: set panel yres"); | |
2687 | module_param(mode_option, charp, 0); | |
2688 | MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); | |
994aad25 VB |
2689 | #if defined(CONFIG_PM) && defined(CONFIG_X86) |
2690 | module_param(force_sleep, bool, 0); | |
2691 | MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware"); | |
2692 | module_param(ignore_devlist, bool, 0); | |
2693 | MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops"); | |
2694 | #endif |