Commit | Line | Data |
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4ed824d9 SR |
1 | /* |
2 | * Copyright (C) 2008-2009 MontaVista Software Inc. | |
3 | * Copyright (C) 2008-2009 Texas Instruments Inc | |
4 | * | |
5 | * Based on the LCD driver for TI Avalanche processors written by | |
6 | * Ajay Singh and Shalom Hai. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option)any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/fb.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/device.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/uaccess.h> | |
4ed824d9 SR |
29 | #include <linux/interrupt.h> |
30 | #include <linux/clk.h> | |
e04e5483 | 31 | #include <linux/cpufreq.h> |
1d3c6c7b | 32 | #include <linux/console.h> |
deb95c6c | 33 | #include <linux/spinlock.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
a0239073 | 35 | #include <linux/delay.h> |
3b9cc4ea | 36 | #include <linux/lcm.h> |
4ed824d9 | 37 | #include <video/da8xx-fb.h> |
12fa8350 | 38 | #include <asm/div64.h> |
4ed824d9 SR |
39 | |
40 | #define DRIVER_NAME "da8xx_lcdc" | |
41 | ||
c6daf05b MP |
42 | #define LCD_VERSION_1 1 |
43 | #define LCD_VERSION_2 2 | |
44 | ||
4ed824d9 | 45 | /* LCD Status Register */ |
1f9c3e1f | 46 | #define LCD_END_OF_FRAME1 BIT(9) |
4ed824d9 | 47 | #define LCD_END_OF_FRAME0 BIT(8) |
1f9c3e1f | 48 | #define LCD_PL_LOAD_DONE BIT(6) |
4ed824d9 SR |
49 | #define LCD_FIFO_UNDERFLOW BIT(5) |
50 | #define LCD_SYNC_LOST BIT(2) | |
51 | ||
52 | /* LCD DMA Control Register */ | |
53 | #define LCD_DMA_BURST_SIZE(x) ((x) << 4) | |
54 | #define LCD_DMA_BURST_1 0x0 | |
55 | #define LCD_DMA_BURST_2 0x1 | |
56 | #define LCD_DMA_BURST_4 0x2 | |
57 | #define LCD_DMA_BURST_8 0x3 | |
58 | #define LCD_DMA_BURST_16 0x4 | |
c6daf05b MP |
59 | #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2) |
60 | #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8) | |
61 | #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9) | |
4ed824d9 SR |
62 | #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0) |
63 | ||
64 | /* LCD Control Register */ | |
65 | #define LCD_CLK_DIVISOR(x) ((x) << 8) | |
66 | #define LCD_RASTER_MODE 0x01 | |
67 | ||
68 | /* LCD Raster Control Register */ | |
69 | #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20) | |
70 | #define PALETTE_AND_DATA 0x00 | |
71 | #define PALETTE_ONLY 0x01 | |
1f9c3e1f | 72 | #define DATA_ONLY 0x02 |
4ed824d9 SR |
73 | |
74 | #define LCD_MONO_8BIT_MODE BIT(9) | |
75 | #define LCD_RASTER_ORDER BIT(8) | |
76 | #define LCD_TFT_MODE BIT(7) | |
c6daf05b MP |
77 | #define LCD_V1_UNDERFLOW_INT_ENA BIT(6) |
78 | #define LCD_V2_UNDERFLOW_INT_ENA BIT(5) | |
79 | #define LCD_V1_PL_INT_ENA BIT(4) | |
80 | #define LCD_V2_PL_INT_ENA BIT(6) | |
4ed824d9 SR |
81 | #define LCD_MONOCHROME_MODE BIT(1) |
82 | #define LCD_RASTER_ENABLE BIT(0) | |
83 | #define LCD_TFT_ALT_ENABLE BIT(23) | |
84 | #define LCD_STN_565_ENABLE BIT(24) | |
c6daf05b MP |
85 | #define LCD_V2_DMA_CLK_EN BIT(2) |
86 | #define LCD_V2_LIDD_CLK_EN BIT(1) | |
87 | #define LCD_V2_CORE_CLK_EN BIT(0) | |
88 | #define LCD_V2_LPP_B10 26 | |
1a2b750c MP |
89 | #define LCD_V2_TFT_24BPP_MODE BIT(25) |
90 | #define LCD_V2_TFT_24BPP_UNPACK BIT(26) | |
4ed824d9 SR |
91 | |
92 | /* LCD Raster Timing 2 Register */ | |
93 | #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16) | |
94 | #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8) | |
95 | #define LCD_SYNC_CTRL BIT(25) | |
96 | #define LCD_SYNC_EDGE BIT(24) | |
97 | #define LCD_INVERT_PIXEL_CLOCK BIT(22) | |
98 | #define LCD_INVERT_LINE_CLOCK BIT(21) | |
99 | #define LCD_INVERT_FRAME_CLOCK BIT(20) | |
100 | ||
101 | /* LCD Block */ | |
c6daf05b | 102 | #define LCD_PID_REG 0x0 |
4ed824d9 SR |
103 | #define LCD_CTRL_REG 0x4 |
104 | #define LCD_STAT_REG 0x8 | |
105 | #define LCD_RASTER_CTRL_REG 0x28 | |
106 | #define LCD_RASTER_TIMING_0_REG 0x2C | |
107 | #define LCD_RASTER_TIMING_1_REG 0x30 | |
108 | #define LCD_RASTER_TIMING_2_REG 0x34 | |
109 | #define LCD_DMA_CTRL_REG 0x40 | |
110 | #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44 | |
111 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48 | |
1f9c3e1f MA |
112 | #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C |
113 | #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50 | |
114 | ||
c6daf05b MP |
115 | /* Interrupt Registers available only in Version 2 */ |
116 | #define LCD_RAW_STAT_REG 0x58 | |
117 | #define LCD_MASKED_STAT_REG 0x5c | |
118 | #define LCD_INT_ENABLE_SET_REG 0x60 | |
119 | #define LCD_INT_ENABLE_CLR_REG 0x64 | |
120 | #define LCD_END_OF_INT_IND_REG 0x68 | |
121 | ||
122 | /* Clock registers available only on Version 2 */ | |
123 | #define LCD_CLK_ENABLE_REG 0x6c | |
124 | #define LCD_CLK_RESET_REG 0x70 | |
74a0efde | 125 | #define LCD_CLK_MAIN_RESET BIT(3) |
c6daf05b | 126 | |
1f9c3e1f | 127 | #define LCD_NUM_BUFFERS 2 |
4ed824d9 SR |
128 | |
129 | #define WSI_TIMEOUT 50 | |
130 | #define PALETTE_SIZE 256 | |
131 | #define LEFT_MARGIN 64 | |
132 | #define RIGHT_MARGIN 64 | |
133 | #define UPPER_MARGIN 32 | |
134 | #define LOWER_MARGIN 32 | |
135 | ||
136 | static resource_size_t da8xx_fb_reg_base; | |
137 | static struct resource *lcdc_regs; | |
c6daf05b MP |
138 | static unsigned int lcd_revision; |
139 | static irq_handler_t lcdc_irq_handler; | |
4ed824d9 SR |
140 | |
141 | static inline unsigned int lcdc_read(unsigned int addr) | |
142 | { | |
143 | return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr)); | |
144 | } | |
145 | ||
146 | static inline void lcdc_write(unsigned int val, unsigned int addr) | |
147 | { | |
148 | __raw_writel(val, da8xx_fb_reg_base + (addr)); | |
149 | } | |
150 | ||
151 | struct da8xx_fb_par { | |
4ed824d9 SR |
152 | resource_size_t p_palette_base; |
153 | unsigned char *v_palette_base; | |
1f9c3e1f MA |
154 | dma_addr_t vram_phys; |
155 | unsigned long vram_size; | |
156 | void *vram_virt; | |
157 | unsigned int dma_start; | |
158 | unsigned int dma_end; | |
4ed824d9 SR |
159 | struct clk *lcdc_clk; |
160 | int irq; | |
4ed824d9 | 161 | unsigned int palette_sz; |
8097b174 | 162 | unsigned int pxl_clk; |
36113804 | 163 | int blank; |
1f9c3e1f MA |
164 | wait_queue_head_t vsync_wait; |
165 | int vsync_flag; | |
166 | int vsync_timeout; | |
deb95c6c MP |
167 | spinlock_t lock_for_chan_update; |
168 | ||
169 | /* | |
170 | * LCDC has 2 ping pong DMA channels, channel 0 | |
171 | * and channel 1. | |
172 | */ | |
173 | unsigned int which_dma_channel_done; | |
e04e5483 C |
174 | #ifdef CONFIG_CPU_FREQ |
175 | struct notifier_block freq_transition; | |
f820917a | 176 | unsigned int lcd_fck_rate; |
e04e5483 | 177 | #endif |
36113804 | 178 | void (*panel_power_ctrl)(int); |
1a2b750c | 179 | u32 pseudo_palette[16]; |
4ed824d9 SR |
180 | }; |
181 | ||
182 | /* Variable Screen Information */ | |
183 | static struct fb_var_screeninfo da8xx_fb_var __devinitdata = { | |
184 | .xoffset = 0, | |
185 | .yoffset = 0, | |
186 | .transp = {0, 0, 0}, | |
187 | .nonstd = 0, | |
188 | .activate = 0, | |
189 | .height = -1, | |
190 | .width = -1, | |
4ed824d9 SR |
191 | .accel_flags = 0, |
192 | .left_margin = LEFT_MARGIN, | |
193 | .right_margin = RIGHT_MARGIN, | |
194 | .upper_margin = UPPER_MARGIN, | |
195 | .lower_margin = LOWER_MARGIN, | |
196 | .sync = 0, | |
197 | .vmode = FB_VMODE_NONINTERLACED | |
198 | }; | |
199 | ||
200 | static struct fb_fix_screeninfo da8xx_fb_fix __devinitdata = { | |
201 | .id = "DA8xx FB Drv", | |
202 | .type = FB_TYPE_PACKED_PIXELS, | |
203 | .type_aux = 0, | |
204 | .visual = FB_VISUAL_PSEUDOCOLOR, | |
1f9c3e1f | 205 | .xpanstep = 0, |
4ed824d9 | 206 | .ypanstep = 1, |
1f9c3e1f | 207 | .ywrapstep = 0, |
4ed824d9 SR |
208 | .accel = FB_ACCEL_NONE |
209 | }; | |
210 | ||
211 | struct da8xx_panel { | |
212 | const char name[25]; /* Full name <vendor>_<model> */ | |
213 | unsigned short width; | |
214 | unsigned short height; | |
215 | int hfp; /* Horizontal front porch */ | |
216 | int hbp; /* Horizontal back porch */ | |
217 | int hsw; /* Horizontal Sync Pulse Width */ | |
218 | int vfp; /* Vertical front porch */ | |
219 | int vbp; /* Vertical back porch */ | |
220 | int vsw; /* Vertical Sync Pulse Width */ | |
8097b174 | 221 | unsigned int pxl_clk; /* Pixel clock */ |
2f93e8f4 | 222 | unsigned char invert_pxl_clk; /* Invert Pixel clock */ |
4ed824d9 SR |
223 | }; |
224 | ||
225 | static struct da8xx_panel known_lcd_panels[] = { | |
226 | /* Sharp LCD035Q3DG01 */ | |
227 | [0] = { | |
228 | .name = "Sharp_LCD035Q3DG01", | |
229 | .width = 320, | |
230 | .height = 240, | |
231 | .hfp = 8, | |
232 | .hbp = 6, | |
233 | .hsw = 0, | |
234 | .vfp = 2, | |
235 | .vbp = 2, | |
236 | .vsw = 0, | |
8097b174 | 237 | .pxl_clk = 4608000, |
2f93e8f4 | 238 | .invert_pxl_clk = 1, |
4ed824d9 SR |
239 | }, |
240 | /* Sharp LK043T1DG01 */ | |
241 | [1] = { | |
242 | .name = "Sharp_LK043T1DG01", | |
243 | .width = 480, | |
244 | .height = 272, | |
245 | .hfp = 2, | |
246 | .hbp = 2, | |
247 | .hsw = 41, | |
248 | .vfp = 2, | |
249 | .vbp = 2, | |
250 | .vsw = 10, | |
8097b174 | 251 | .pxl_clk = 7833600, |
2f93e8f4 | 252 | .invert_pxl_clk = 0, |
4ed824d9 | 253 | }, |
f413070e AG |
254 | [2] = { |
255 | /* Hitachi SP10Q010 */ | |
256 | .name = "SP10Q010", | |
257 | .width = 320, | |
258 | .height = 240, | |
259 | .hfp = 10, | |
260 | .hbp = 10, | |
261 | .hsw = 10, | |
262 | .vfp = 10, | |
263 | .vbp = 10, | |
264 | .vsw = 10, | |
265 | .pxl_clk = 7833600, | |
266 | .invert_pxl_clk = 0, | |
267 | }, | |
4ed824d9 SR |
268 | }; |
269 | ||
36113804 C |
270 | /* Enable the Raster Engine of the LCD Controller */ |
271 | static inline void lcd_enable_raster(void) | |
272 | { | |
273 | u32 reg; | |
274 | ||
92b4e450 MP |
275 | /* Put LCDC in reset for several cycles */ |
276 | if (lcd_revision == LCD_VERSION_2) | |
277 | /* Write 1 to reset LCDC */ | |
278 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
279 | mdelay(1); | |
280 | ||
74a0efde MP |
281 | /* Bring LCDC out of reset */ |
282 | if (lcd_revision == LCD_VERSION_2) | |
283 | lcdc_write(0, LCD_CLK_RESET_REG); | |
92b4e450 | 284 | mdelay(1); |
74a0efde | 285 | |
92b4e450 | 286 | /* Above reset sequence doesnot reset register context */ |
36113804 C |
287 | reg = lcdc_read(LCD_RASTER_CTRL_REG); |
288 | if (!(reg & LCD_RASTER_ENABLE)) | |
289 | lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); | |
290 | } | |
291 | ||
4ed824d9 | 292 | /* Disable the Raster Engine of the LCD Controller */ |
36113804 | 293 | static inline void lcd_disable_raster(void) |
4ed824d9 | 294 | { |
4ed824d9 SR |
295 | u32 reg; |
296 | ||
297 | reg = lcdc_read(LCD_RASTER_CTRL_REG); | |
2f93e8f4 | 298 | if (reg & LCD_RASTER_ENABLE) |
4ed824d9 | 299 | lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG); |
4ed824d9 SR |
300 | } |
301 | ||
302 | static void lcd_blit(int load_mode, struct da8xx_fb_par *par) | |
303 | { | |
1f9c3e1f MA |
304 | u32 start; |
305 | u32 end; | |
306 | u32 reg_ras; | |
307 | u32 reg_dma; | |
c6daf05b | 308 | u32 reg_int; |
1f9c3e1f MA |
309 | |
310 | /* init reg to clear PLM (loading mode) fields */ | |
311 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
312 | reg_ras &= ~(3 << 20); | |
313 | ||
314 | reg_dma = lcdc_read(LCD_DMA_CTRL_REG); | |
315 | ||
316 | if (load_mode == LOAD_DATA) { | |
317 | start = par->dma_start; | |
318 | end = par->dma_end; | |
319 | ||
320 | reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY); | |
c6daf05b MP |
321 | if (lcd_revision == LCD_VERSION_1) { |
322 | reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA; | |
323 | } else { | |
324 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
325 | LCD_V2_END_OF_FRAME0_INT_ENA | | |
326 | LCD_V2_END_OF_FRAME1_INT_ENA; | |
327 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
328 | } | |
1f9c3e1f MA |
329 | reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE; |
330 | ||
331 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
332 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
333 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
334 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
335 | } else if (load_mode == LOAD_PALETTE) { | |
336 | start = par->p_palette_base; | |
337 | end = start + par->palette_sz - 1; | |
338 | ||
339 | reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY); | |
c6daf05b MP |
340 | |
341 | if (lcd_revision == LCD_VERSION_1) { | |
342 | reg_ras |= LCD_V1_PL_INT_ENA; | |
343 | } else { | |
344 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
345 | LCD_V2_PL_INT_ENA; | |
346 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
347 | } | |
1f9c3e1f MA |
348 | |
349 | lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
350 | lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
351 | } | |
4ed824d9 | 352 | |
1f9c3e1f MA |
353 | lcdc_write(reg_dma, LCD_DMA_CTRL_REG); |
354 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); | |
4ed824d9 | 355 | |
1f9c3e1f MA |
356 | /* |
357 | * The Raster enable bit must be set after all other control fields are | |
358 | * set. | |
359 | */ | |
360 | lcd_enable_raster(); | |
4ed824d9 SR |
361 | } |
362 | ||
fb8fa943 MP |
363 | /* Configure the Burst Size and fifo threhold of DMA */ |
364 | static int lcd_cfg_dma(int burst_size, int fifo_th) | |
4ed824d9 SR |
365 | { |
366 | u32 reg; | |
367 | ||
368 | reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001; | |
369 | switch (burst_size) { | |
370 | case 1: | |
371 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1); | |
372 | break; | |
373 | case 2: | |
374 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2); | |
375 | break; | |
376 | case 4: | |
377 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4); | |
378 | break; | |
379 | case 8: | |
380 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8); | |
381 | break; | |
382 | case 16: | |
383 | reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16); | |
384 | break; | |
385 | default: | |
386 | return -EINVAL; | |
387 | } | |
fb8fa943 MP |
388 | |
389 | reg |= (fifo_th << 8); | |
390 | ||
2f93e8f4 | 391 | lcdc_write(reg, LCD_DMA_CTRL_REG); |
4ed824d9 SR |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void lcd_cfg_ac_bias(int period, int transitions_per_int) | |
397 | { | |
398 | u32 reg; | |
399 | ||
400 | /* Set the AC Bias Period and Number of Transisitons per Interrupt */ | |
401 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000; | |
402 | reg |= LCD_AC_BIAS_FREQUENCY(period) | | |
403 | LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int); | |
404 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
405 | } | |
406 | ||
407 | static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, | |
408 | int front_porch) | |
409 | { | |
410 | u32 reg; | |
411 | ||
412 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; | |
413 | reg |= ((back_porch & 0xff) << 24) | |
414 | | ((front_porch & 0xff) << 16) | |
415 | | ((pulse_width & 0x3f) << 10); | |
416 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); | |
417 | } | |
418 | ||
419 | static void lcd_cfg_vertical_sync(int back_porch, int pulse_width, | |
420 | int front_porch) | |
421 | { | |
422 | u32 reg; | |
423 | ||
424 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff; | |
425 | reg |= ((back_porch & 0xff) << 24) | |
426 | | ((front_porch & 0xff) << 16) | |
427 | | ((pulse_width & 0x3f) << 10); | |
428 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
429 | } | |
430 | ||
431 | static int lcd_cfg_display(const struct lcd_ctrl_config *cfg) | |
432 | { | |
433 | u32 reg; | |
c6daf05b | 434 | u32 reg_int; |
4ed824d9 SR |
435 | |
436 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE | | |
437 | LCD_MONO_8BIT_MODE | | |
438 | LCD_MONOCHROME_MODE); | |
439 | ||
440 | switch (cfg->p_disp_panel->panel_shade) { | |
441 | case MONOCHROME: | |
442 | reg |= LCD_MONOCHROME_MODE; | |
443 | if (cfg->mono_8bit_mode) | |
444 | reg |= LCD_MONO_8BIT_MODE; | |
445 | break; | |
446 | case COLOR_ACTIVE: | |
447 | reg |= LCD_TFT_MODE; | |
448 | if (cfg->tft_alt_mode) | |
449 | reg |= LCD_TFT_ALT_ENABLE; | |
450 | break; | |
451 | ||
452 | case COLOR_PASSIVE: | |
453 | if (cfg->stn_565_mode) | |
454 | reg |= LCD_STN_565_ENABLE; | |
455 | break; | |
456 | ||
457 | default: | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | /* enable additional interrupts here */ | |
c6daf05b MP |
462 | if (lcd_revision == LCD_VERSION_1) { |
463 | reg |= LCD_V1_UNDERFLOW_INT_ENA; | |
464 | } else { | |
465 | reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) | | |
466 | LCD_V2_UNDERFLOW_INT_ENA; | |
467 | lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG); | |
468 | } | |
4ed824d9 SR |
469 | |
470 | lcdc_write(reg, LCD_RASTER_CTRL_REG); | |
471 | ||
472 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
473 | ||
474 | if (cfg->sync_ctrl) | |
475 | reg |= LCD_SYNC_CTRL; | |
476 | else | |
477 | reg &= ~LCD_SYNC_CTRL; | |
478 | ||
479 | if (cfg->sync_edge) | |
480 | reg |= LCD_SYNC_EDGE; | |
481 | else | |
482 | reg &= ~LCD_SYNC_EDGE; | |
483 | ||
4ed824d9 SR |
484 | if (cfg->invert_line_clock) |
485 | reg |= LCD_INVERT_LINE_CLOCK; | |
486 | else | |
487 | reg &= ~LCD_INVERT_LINE_CLOCK; | |
488 | ||
489 | if (cfg->invert_frm_clock) | |
490 | reg |= LCD_INVERT_FRAME_CLOCK; | |
491 | else | |
492 | reg &= ~LCD_INVERT_FRAME_CLOCK; | |
493 | ||
494 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, | |
500 | u32 bpp, u32 raster_order) | |
501 | { | |
1f9c3e1f | 502 | u32 reg; |
4ed824d9 | 503 | |
1a2b750c MP |
504 | if (bpp > 16 && lcd_revision == LCD_VERSION_1) |
505 | return -EINVAL; | |
506 | ||
4ed824d9 SR |
507 | /* Set the Panel Width */ |
508 | /* Pixels per line = (PPL + 1)*16 */ | |
4d740801 MP |
509 | if (lcd_revision == LCD_VERSION_1) { |
510 | /* | |
511 | * 0x3F in bits 4..9 gives max horizontal resolution = 1024 | |
512 | * pixels. | |
513 | */ | |
514 | width &= 0x3f0; | |
515 | } else { | |
516 | /* | |
517 | * 0x7F in bits 4..10 gives max horizontal resolution = 2048 | |
518 | * pixels. | |
519 | */ | |
520 | width &= 0x7f0; | |
521 | } | |
522 | ||
4ed824d9 SR |
523 | reg = lcdc_read(LCD_RASTER_TIMING_0_REG); |
524 | reg &= 0xfffffc00; | |
4d740801 MP |
525 | if (lcd_revision == LCD_VERSION_1) { |
526 | reg |= ((width >> 4) - 1) << 4; | |
527 | } else { | |
528 | width = (width >> 4) - 1; | |
529 | reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3); | |
530 | } | |
4ed824d9 SR |
531 | lcdc_write(reg, LCD_RASTER_TIMING_0_REG); |
532 | ||
533 | /* Set the Panel Height */ | |
4d740801 | 534 | /* Set bits 9:0 of Lines Per Pixel */ |
4ed824d9 SR |
535 | reg = lcdc_read(LCD_RASTER_TIMING_1_REG); |
536 | reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); | |
537 | lcdc_write(reg, LCD_RASTER_TIMING_1_REG); | |
538 | ||
4d740801 MP |
539 | /* Set bit 10 of Lines Per Pixel */ |
540 | if (lcd_revision == LCD_VERSION_2) { | |
541 | reg = lcdc_read(LCD_RASTER_TIMING_2_REG); | |
542 | reg |= ((height - 1) & 0x400) << 16; | |
543 | lcdc_write(reg, LCD_RASTER_TIMING_2_REG); | |
544 | } | |
545 | ||
4ed824d9 SR |
546 | /* Set the Raster Order of the Frame Buffer */ |
547 | reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8); | |
548 | if (raster_order) | |
549 | reg |= LCD_RASTER_ORDER; | |
1a2b750c MP |
550 | |
551 | par->palette_sz = 16 * 2; | |
4ed824d9 SR |
552 | |
553 | switch (bpp) { | |
554 | case 1: | |
555 | case 2: | |
556 | case 4: | |
557 | case 16: | |
1a2b750c MP |
558 | break; |
559 | case 24: | |
560 | reg |= LCD_V2_TFT_24BPP_MODE; | |
561 | case 32: | |
562 | reg |= LCD_V2_TFT_24BPP_UNPACK; | |
4ed824d9 SR |
563 | break; |
564 | ||
565 | case 8: | |
566 | par->palette_sz = 256 * 2; | |
567 | break; | |
568 | ||
569 | default: | |
570 | return -EINVAL; | |
571 | } | |
572 | ||
1a2b750c MP |
573 | lcdc_write(reg, LCD_RASTER_CTRL_REG); |
574 | ||
4ed824d9 SR |
575 | return 0; |
576 | } | |
577 | ||
1a2b750c | 578 | #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16) |
4ed824d9 SR |
579 | static int fb_setcolreg(unsigned regno, unsigned red, unsigned green, |
580 | unsigned blue, unsigned transp, | |
581 | struct fb_info *info) | |
582 | { | |
583 | struct da8xx_fb_par *par = info->par; | |
1f9c3e1f | 584 | unsigned short *palette = (unsigned short *) par->v_palette_base; |
4ed824d9 | 585 | u_short pal; |
1f9c3e1f | 586 | int update_hw = 0; |
4ed824d9 SR |
587 | |
588 | if (regno > 255) | |
589 | return 1; | |
590 | ||
591 | if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) | |
592 | return 1; | |
593 | ||
1a2b750c MP |
594 | if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
595 | return -EINVAL; | |
f413070e | 596 | |
1a2b750c MP |
597 | switch (info->fix.visual) { |
598 | case FB_VISUAL_TRUECOLOR: | |
599 | red = CNVT_TOHW(red, info->var.red.length); | |
600 | green = CNVT_TOHW(green, info->var.green.length); | |
601 | blue = CNVT_TOHW(blue, info->var.blue.length); | |
602 | break; | |
603 | case FB_VISUAL_PSEUDOCOLOR: | |
604 | switch (info->var.bits_per_pixel) { | |
605 | case 4: | |
606 | if (regno > 15) | |
607 | return -EINVAL; | |
608 | ||
609 | if (info->var.grayscale) { | |
610 | pal = regno; | |
611 | } else { | |
612 | red >>= 4; | |
613 | green >>= 8; | |
614 | blue >>= 12; | |
615 | ||
616 | pal = red & 0x0f00; | |
617 | pal |= green & 0x00f0; | |
618 | pal |= blue & 0x000f; | |
619 | } | |
620 | if (regno == 0) | |
621 | pal |= 0x2000; | |
622 | palette[regno] = pal; | |
623 | break; | |
624 | ||
625 | case 8: | |
f413070e AG |
626 | red >>= 4; |
627 | green >>= 8; | |
628 | blue >>= 12; | |
629 | ||
630 | pal = (red & 0x0f00); | |
631 | pal |= (green & 0x00f0); | |
632 | pal |= (blue & 0x000f); | |
4ed824d9 | 633 | |
1a2b750c MP |
634 | if (palette[regno] != pal) { |
635 | update_hw = 1; | |
636 | palette[regno] = pal; | |
637 | } | |
638 | break; | |
1f9c3e1f | 639 | } |
1a2b750c MP |
640 | break; |
641 | } | |
4ed824d9 | 642 | |
1a2b750c MP |
643 | /* Truecolor has hardware independent palette */ |
644 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
645 | u32 v; | |
4ed824d9 | 646 | |
1a2b750c MP |
647 | if (regno > 15) |
648 | return -EINVAL; | |
649 | ||
650 | v = (red << info->var.red.offset) | | |
651 | (green << info->var.green.offset) | | |
652 | (blue << info->var.blue.offset); | |
653 | ||
654 | switch (info->var.bits_per_pixel) { | |
655 | case 16: | |
656 | ((u16 *) (info->pseudo_palette))[regno] = v; | |
657 | break; | |
658 | case 24: | |
659 | case 32: | |
660 | ((u32 *) (info->pseudo_palette))[regno] = v; | |
661 | break; | |
662 | } | |
1f9c3e1f MA |
663 | if (palette[0] != 0x4000) { |
664 | update_hw = 1; | |
665 | palette[0] = 0x4000; | |
666 | } | |
4ed824d9 SR |
667 | } |
668 | ||
1f9c3e1f MA |
669 | /* Update the palette in the h/w as needed. */ |
670 | if (update_hw) | |
671 | lcd_blit(LOAD_PALETTE, par); | |
672 | ||
4ed824d9 SR |
673 | return 0; |
674 | } | |
1a2b750c | 675 | #undef CNVT_TOHW |
4ed824d9 | 676 | |
2f93e8f4 | 677 | static void lcd_reset(struct da8xx_fb_par *par) |
4ed824d9 | 678 | { |
4ed824d9 | 679 | /* Disable the Raster if previously Enabled */ |
36113804 | 680 | lcd_disable_raster(); |
4ed824d9 SR |
681 | |
682 | /* DMA has to be disabled */ | |
683 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
684 | lcdc_write(0, LCD_RASTER_CTRL_REG); | |
c6daf05b | 685 | |
74a0efde | 686 | if (lcd_revision == LCD_VERSION_2) { |
c6daf05b | 687 | lcdc_write(0, LCD_INT_ENABLE_SET_REG); |
74a0efde MP |
688 | /* Write 1 to reset */ |
689 | lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG); | |
690 | lcdc_write(0, LCD_CLK_RESET_REG); | |
691 | } | |
4ed824d9 SR |
692 | } |
693 | ||
8097b174 C |
694 | static void lcd_calc_clk_divider(struct da8xx_fb_par *par) |
695 | { | |
696 | unsigned int lcd_clk, div; | |
697 | ||
698 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
699 | div = lcd_clk / par->pxl_clk; | |
700 | ||
701 | /* Configure the LCD clock divisor. */ | |
702 | lcdc_write(LCD_CLK_DIVISOR(div) | | |
703 | (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG); | |
c6daf05b MP |
704 | |
705 | if (lcd_revision == LCD_VERSION_2) | |
706 | lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN | | |
707 | LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG); | |
708 | ||
8097b174 C |
709 | } |
710 | ||
4ed824d9 SR |
711 | static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg, |
712 | struct da8xx_panel *panel) | |
713 | { | |
714 | u32 bpp; | |
715 | int ret = 0; | |
716 | ||
2f93e8f4 | 717 | lcd_reset(par); |
4ed824d9 | 718 | |
8097b174 C |
719 | /* Calculate the divider */ |
720 | lcd_calc_clk_divider(par); | |
4ed824d9 | 721 | |
2f93e8f4 SR |
722 | if (panel->invert_pxl_clk) |
723 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) | | |
724 | LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
725 | else | |
726 | lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) & | |
727 | ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG); | |
728 | ||
fb8fa943 MP |
729 | /* Configure the DMA burst size and fifo threshold. */ |
730 | ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th); | |
4ed824d9 SR |
731 | if (ret < 0) |
732 | return ret; | |
733 | ||
734 | /* Configure the AC bias properties. */ | |
735 | lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); | |
736 | ||
737 | /* Configure the vertical and horizontal sync properties. */ | |
738 | lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); | |
739 | lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); | |
740 | ||
741 | /* Configure for disply */ | |
742 | ret = lcd_cfg_display(cfg); | |
743 | if (ret < 0) | |
744 | return ret; | |
745 | ||
746 | if (QVGA != cfg->p_disp_panel->panel_type) | |
747 | return -EINVAL; | |
748 | ||
749 | if (cfg->bpp <= cfg->p_disp_panel->max_bpp && | |
750 | cfg->bpp >= cfg->p_disp_panel->min_bpp) | |
751 | bpp = cfg->bpp; | |
752 | else | |
753 | bpp = cfg->p_disp_panel->max_bpp; | |
754 | if (bpp == 12) | |
755 | bpp = 16; | |
756 | ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, | |
757 | (unsigned int)panel->height, bpp, | |
758 | cfg->raster_order); | |
759 | if (ret < 0) | |
760 | return ret; | |
761 | ||
762 | /* Configure FDD */ | |
763 | lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) | | |
764 | (cfg->fdd << 12), LCD_RASTER_CTRL_REG); | |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
c6daf05b MP |
769 | /* IRQ handler for version 2 of LCDC */ |
770 | static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) | |
771 | { | |
772 | struct da8xx_fb_par *par = arg; | |
773 | u32 stat = lcdc_read(LCD_MASKED_STAT_REG); | |
c6daf05b MP |
774 | |
775 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
776 | lcd_disable_raster(); | |
777 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
778 | lcd_enable_raster(); | |
779 | } else if (stat & LCD_PL_LOAD_DONE) { | |
780 | /* | |
781 | * Must disable raster before changing state of any control bit. | |
782 | * And also must be disabled before clearing the PL loading | |
783 | * interrupt via the following write to the status register. If | |
784 | * this is done after then one gets multiple PL done interrupts. | |
785 | */ | |
786 | lcd_disable_raster(); | |
787 | ||
788 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
789 | ||
8a81dccd MP |
790 | /* Disable PL completion interrupt */ |
791 | lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG); | |
c6daf05b MP |
792 | |
793 | /* Setup and start data loading mode */ | |
794 | lcd_blit(LOAD_DATA, par); | |
795 | } else { | |
796 | lcdc_write(stat, LCD_MASKED_STAT_REG); | |
797 | ||
798 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 799 | par->which_dma_channel_done = 0; |
c6daf05b MP |
800 | lcdc_write(par->dma_start, |
801 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
802 | lcdc_write(par->dma_end, | |
803 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
804 | par->vsync_flag = 1; | |
805 | wake_up_interruptible(&par->vsync_wait); | |
806 | } | |
807 | ||
808 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 809 | par->which_dma_channel_done = 1; |
c6daf05b MP |
810 | lcdc_write(par->dma_start, |
811 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
812 | lcdc_write(par->dma_end, | |
813 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
814 | par->vsync_flag = 1; | |
815 | wake_up_interruptible(&par->vsync_wait); | |
816 | } | |
817 | } | |
818 | ||
819 | lcdc_write(0, LCD_END_OF_INT_IND_REG); | |
820 | return IRQ_HANDLED; | |
821 | } | |
822 | ||
823 | /* IRQ handler for version 1 LCDC */ | |
824 | static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg) | |
4ed824d9 | 825 | { |
1f9c3e1f | 826 | struct da8xx_fb_par *par = arg; |
4ed824d9 | 827 | u32 stat = lcdc_read(LCD_STAT_REG); |
1f9c3e1f | 828 | u32 reg_ras; |
4ed824d9 SR |
829 | |
830 | if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) { | |
36113804 | 831 | lcd_disable_raster(); |
4ed824d9 | 832 | lcdc_write(stat, LCD_STAT_REG); |
36113804 | 833 | lcd_enable_raster(); |
1f9c3e1f MA |
834 | } else if (stat & LCD_PL_LOAD_DONE) { |
835 | /* | |
836 | * Must disable raster before changing state of any control bit. | |
837 | * And also must be disabled before clearing the PL loading | |
838 | * interrupt via the following write to the status register. If | |
839 | * this is done after then one gets multiple PL done interrupts. | |
840 | */ | |
841 | lcd_disable_raster(); | |
842 | ||
4ed824d9 SR |
843 | lcdc_write(stat, LCD_STAT_REG); |
844 | ||
1f9c3e1f MA |
845 | /* Disable PL completion inerrupt */ |
846 | reg_ras = lcdc_read(LCD_RASTER_CTRL_REG); | |
c6daf05b | 847 | reg_ras &= ~LCD_V1_PL_INT_ENA; |
1f9c3e1f MA |
848 | lcdc_write(reg_ras, LCD_RASTER_CTRL_REG); |
849 | ||
850 | /* Setup and start data loading mode */ | |
851 | lcd_blit(LOAD_DATA, par); | |
852 | } else { | |
853 | lcdc_write(stat, LCD_STAT_REG); | |
854 | ||
855 | if (stat & LCD_END_OF_FRAME0) { | |
deb95c6c | 856 | par->which_dma_channel_done = 0; |
1f9c3e1f MA |
857 | lcdc_write(par->dma_start, |
858 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
859 | lcdc_write(par->dma_end, | |
860 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
861 | par->vsync_flag = 1; | |
862 | wake_up_interruptible(&par->vsync_wait); | |
863 | } | |
864 | ||
865 | if (stat & LCD_END_OF_FRAME1) { | |
deb95c6c | 866 | par->which_dma_channel_done = 1; |
1f9c3e1f MA |
867 | lcdc_write(par->dma_start, |
868 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
869 | lcdc_write(par->dma_end, | |
870 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
871 | par->vsync_flag = 1; | |
872 | wake_up_interruptible(&par->vsync_wait); | |
873 | } | |
874 | } | |
875 | ||
4ed824d9 SR |
876 | return IRQ_HANDLED; |
877 | } | |
878 | ||
879 | static int fb_check_var(struct fb_var_screeninfo *var, | |
880 | struct fb_info *info) | |
881 | { | |
882 | int err = 0; | |
883 | ||
1a2b750c MP |
884 | if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1) |
885 | return -EINVAL; | |
886 | ||
4ed824d9 SR |
887 | switch (var->bits_per_pixel) { |
888 | case 1: | |
889 | case 8: | |
890 | var->red.offset = 0; | |
891 | var->red.length = 8; | |
892 | var->green.offset = 0; | |
893 | var->green.length = 8; | |
894 | var->blue.offset = 0; | |
895 | var->blue.length = 8; | |
896 | var->transp.offset = 0; | |
897 | var->transp.length = 0; | |
f413070e | 898 | var->nonstd = 0; |
4ed824d9 SR |
899 | break; |
900 | case 4: | |
901 | var->red.offset = 0; | |
902 | var->red.length = 4; | |
903 | var->green.offset = 0; | |
904 | var->green.length = 4; | |
905 | var->blue.offset = 0; | |
906 | var->blue.length = 4; | |
907 | var->transp.offset = 0; | |
908 | var->transp.length = 0; | |
f413070e | 909 | var->nonstd = FB_NONSTD_REV_PIX_IN_B; |
4ed824d9 SR |
910 | break; |
911 | case 16: /* RGB 565 */ | |
3510b8f7 | 912 | var->red.offset = 11; |
4ed824d9 SR |
913 | var->red.length = 5; |
914 | var->green.offset = 5; | |
915 | var->green.length = 6; | |
3510b8f7 | 916 | var->blue.offset = 0; |
4ed824d9 SR |
917 | var->blue.length = 5; |
918 | var->transp.offset = 0; | |
919 | var->transp.length = 0; | |
f413070e | 920 | var->nonstd = 0; |
4ed824d9 | 921 | break; |
1a2b750c MP |
922 | case 24: |
923 | var->red.offset = 16; | |
924 | var->red.length = 8; | |
925 | var->green.offset = 8; | |
926 | var->green.length = 8; | |
927 | var->blue.offset = 0; | |
928 | var->blue.length = 8; | |
929 | var->nonstd = 0; | |
930 | break; | |
931 | case 32: | |
932 | var->transp.offset = 24; | |
933 | var->transp.length = 8; | |
934 | var->red.offset = 16; | |
935 | var->red.length = 8; | |
936 | var->green.offset = 8; | |
937 | var->green.length = 8; | |
938 | var->blue.offset = 0; | |
939 | var->blue.length = 8; | |
940 | var->nonstd = 0; | |
941 | break; | |
4ed824d9 SR |
942 | default: |
943 | err = -EINVAL; | |
944 | } | |
945 | ||
946 | var->red.msb_right = 0; | |
947 | var->green.msb_right = 0; | |
948 | var->blue.msb_right = 0; | |
949 | var->transp.msb_right = 0; | |
950 | return err; | |
951 | } | |
952 | ||
e04e5483 C |
953 | #ifdef CONFIG_CPU_FREQ |
954 | static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb, | |
955 | unsigned long val, void *data) | |
956 | { | |
957 | struct da8xx_fb_par *par; | |
e04e5483 C |
958 | |
959 | par = container_of(nb, struct da8xx_fb_par, freq_transition); | |
f820917a MP |
960 | if (val == CPUFREQ_POSTCHANGE) { |
961 | if (par->lcd_fck_rate != clk_get_rate(par->lcdc_clk)) { | |
962 | par->lcd_fck_rate = clk_get_rate(par->lcdc_clk); | |
963 | lcd_disable_raster(); | |
964 | lcd_calc_clk_divider(par); | |
965 | lcd_enable_raster(); | |
966 | } | |
e04e5483 C |
967 | } |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
972 | static inline int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par) | |
973 | { | |
974 | par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition; | |
975 | ||
976 | return cpufreq_register_notifier(&par->freq_transition, | |
977 | CPUFREQ_TRANSITION_NOTIFIER); | |
978 | } | |
979 | ||
980 | static inline void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par) | |
981 | { | |
982 | cpufreq_unregister_notifier(&par->freq_transition, | |
983 | CPUFREQ_TRANSITION_NOTIFIER); | |
984 | } | |
985 | #endif | |
986 | ||
4ed824d9 SR |
987 | static int __devexit fb_remove(struct platform_device *dev) |
988 | { | |
989 | struct fb_info *info = dev_get_drvdata(&dev->dev); | |
4ed824d9 SR |
990 | |
991 | if (info) { | |
992 | struct da8xx_fb_par *par = info->par; | |
993 | ||
e04e5483 C |
994 | #ifdef CONFIG_CPU_FREQ |
995 | lcd_da8xx_cpufreq_deregister(par); | |
996 | #endif | |
36113804 C |
997 | if (par->panel_power_ctrl) |
998 | par->panel_power_ctrl(0); | |
999 | ||
1000 | lcd_disable_raster(); | |
4ed824d9 SR |
1001 | lcdc_write(0, LCD_RASTER_CTRL_REG); |
1002 | ||
1003 | /* disable DMA */ | |
1004 | lcdc_write(0, LCD_DMA_CTRL_REG); | |
1005 | ||
1006 | unregister_framebuffer(info); | |
1007 | fb_dealloc_cmap(&info->cmap); | |
1f9c3e1f MA |
1008 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, |
1009 | par->p_palette_base); | |
1010 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, | |
1011 | par->vram_phys); | |
4ed824d9 SR |
1012 | free_irq(par->irq, par); |
1013 | clk_disable(par->lcdc_clk); | |
1014 | clk_put(par->lcdc_clk); | |
1015 | framebuffer_release(info); | |
1016 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
1017 | release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); | |
1018 | ||
1019 | } | |
2f93e8f4 | 1020 | return 0; |
4ed824d9 SR |
1021 | } |
1022 | ||
1f9c3e1f MA |
1023 | /* |
1024 | * Function to wait for vertical sync which for this LCD peripheral | |
1025 | * translates into waiting for the current raster frame to complete. | |
1026 | */ | |
1027 | static int fb_wait_for_vsync(struct fb_info *info) | |
1028 | { | |
1029 | struct da8xx_fb_par *par = info->par; | |
1030 | int ret; | |
1031 | ||
1032 | /* | |
1033 | * Set flag to 0 and wait for isr to set to 1. It would seem there is a | |
25985edc | 1034 | * race condition here where the ISR could have occurred just before or |
1f9c3e1f MA |
1035 | * just after this set. But since we are just coarsely waiting for |
1036 | * a frame to complete then that's OK. i.e. if the frame completed | |
1037 | * just before this code executed then we have to wait another full | |
1038 | * frame time but there is no way to avoid such a situation. On the | |
1039 | * other hand if the frame completed just after then we don't need | |
1040 | * to wait long at all. Either way we are guaranteed to return to the | |
1041 | * user immediately after a frame completion which is all that is | |
1042 | * required. | |
1043 | */ | |
1044 | par->vsync_flag = 0; | |
1045 | ret = wait_event_interruptible_timeout(par->vsync_wait, | |
1046 | par->vsync_flag != 0, | |
1047 | par->vsync_timeout); | |
1048 | if (ret < 0) | |
1049 | return ret; | |
1050 | if (ret == 0) | |
1051 | return -ETIMEDOUT; | |
1052 | ||
1053 | return 0; | |
1054 | } | |
1055 | ||
4ed824d9 SR |
1056 | static int fb_ioctl(struct fb_info *info, unsigned int cmd, |
1057 | unsigned long arg) | |
1058 | { | |
1059 | struct lcd_sync_arg sync_arg; | |
1060 | ||
1061 | switch (cmd) { | |
1062 | case FBIOGET_CONTRAST: | |
1063 | case FBIOPUT_CONTRAST: | |
1064 | case FBIGET_BRIGHTNESS: | |
1065 | case FBIPUT_BRIGHTNESS: | |
1066 | case FBIGET_COLOR: | |
1067 | case FBIPUT_COLOR: | |
2f93e8f4 | 1068 | return -ENOTTY; |
4ed824d9 SR |
1069 | case FBIPUT_HSYNC: |
1070 | if (copy_from_user(&sync_arg, (char *)arg, | |
1071 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1072 | return -EFAULT; |
4ed824d9 SR |
1073 | lcd_cfg_horizontal_sync(sync_arg.back_porch, |
1074 | sync_arg.pulse_width, | |
1075 | sync_arg.front_porch); | |
1076 | break; | |
1077 | case FBIPUT_VSYNC: | |
1078 | if (copy_from_user(&sync_arg, (char *)arg, | |
1079 | sizeof(struct lcd_sync_arg))) | |
2f93e8f4 | 1080 | return -EFAULT; |
4ed824d9 SR |
1081 | lcd_cfg_vertical_sync(sync_arg.back_porch, |
1082 | sync_arg.pulse_width, | |
1083 | sync_arg.front_porch); | |
1084 | break; | |
1f9c3e1f MA |
1085 | case FBIO_WAITFORVSYNC: |
1086 | return fb_wait_for_vsync(info); | |
4ed824d9 SR |
1087 | default: |
1088 | return -EINVAL; | |
1089 | } | |
1090 | return 0; | |
1091 | } | |
1092 | ||
312d9715 C |
1093 | static int cfb_blank(int blank, struct fb_info *info) |
1094 | { | |
1095 | struct da8xx_fb_par *par = info->par; | |
1096 | int ret = 0; | |
1097 | ||
1098 | if (par->blank == blank) | |
1099 | return 0; | |
1100 | ||
1101 | par->blank = blank; | |
1102 | switch (blank) { | |
1103 | case FB_BLANK_UNBLANK: | |
f7c848b6 MP |
1104 | lcd_enable_raster(); |
1105 | ||
312d9715 C |
1106 | if (par->panel_power_ctrl) |
1107 | par->panel_power_ctrl(1); | |
312d9715 | 1108 | break; |
99a647d1 YY |
1109 | case FB_BLANK_NORMAL: |
1110 | case FB_BLANK_VSYNC_SUSPEND: | |
1111 | case FB_BLANK_HSYNC_SUSPEND: | |
312d9715 C |
1112 | case FB_BLANK_POWERDOWN: |
1113 | if (par->panel_power_ctrl) | |
1114 | par->panel_power_ctrl(0); | |
1115 | ||
1116 | lcd_disable_raster(); | |
1117 | break; | |
1118 | default: | |
1119 | ret = -EINVAL; | |
1120 | } | |
1121 | ||
1122 | return ret; | |
1123 | } | |
1124 | ||
1f9c3e1f MA |
1125 | /* |
1126 | * Set new x,y offsets in the virtual display for the visible area and switch | |
1127 | * to the new mode. | |
1128 | */ | |
1129 | static int da8xx_pan_display(struct fb_var_screeninfo *var, | |
1130 | struct fb_info *fbi) | |
1131 | { | |
1132 | int ret = 0; | |
1133 | struct fb_var_screeninfo new_var; | |
1134 | struct da8xx_fb_par *par = fbi->par; | |
1135 | struct fb_fix_screeninfo *fix = &fbi->fix; | |
1136 | unsigned int end; | |
1137 | unsigned int start; | |
deb95c6c | 1138 | unsigned long irq_flags; |
1f9c3e1f MA |
1139 | |
1140 | if (var->xoffset != fbi->var.xoffset || | |
1141 | var->yoffset != fbi->var.yoffset) { | |
1142 | memcpy(&new_var, &fbi->var, sizeof(new_var)); | |
1143 | new_var.xoffset = var->xoffset; | |
1144 | new_var.yoffset = var->yoffset; | |
1145 | if (fb_check_var(&new_var, fbi)) | |
1146 | ret = -EINVAL; | |
1147 | else { | |
1148 | memcpy(&fbi->var, &new_var, sizeof(new_var)); | |
1149 | ||
1150 | start = fix->smem_start + | |
1151 | new_var.yoffset * fix->line_length + | |
e6c4d3d4 LP |
1152 | new_var.xoffset * fbi->var.bits_per_pixel / 8; |
1153 | end = start + fbi->var.yres * fix->line_length - 1; | |
1f9c3e1f MA |
1154 | par->dma_start = start; |
1155 | par->dma_end = end; | |
deb95c6c MP |
1156 | spin_lock_irqsave(&par->lock_for_chan_update, |
1157 | irq_flags); | |
1158 | if (par->which_dma_channel_done == 0) { | |
1159 | lcdc_write(par->dma_start, | |
1160 | LCD_DMA_FRM_BUF_BASE_ADDR_0_REG); | |
1161 | lcdc_write(par->dma_end, | |
1162 | LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG); | |
1163 | } else if (par->which_dma_channel_done == 1) { | |
1164 | lcdc_write(par->dma_start, | |
1165 | LCD_DMA_FRM_BUF_BASE_ADDR_1_REG); | |
1166 | lcdc_write(par->dma_end, | |
1167 | LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG); | |
1168 | } | |
1169 | spin_unlock_irqrestore(&par->lock_for_chan_update, | |
1170 | irq_flags); | |
1f9c3e1f MA |
1171 | } |
1172 | } | |
1173 | ||
1174 | return ret; | |
1175 | } | |
1176 | ||
4ed824d9 SR |
1177 | static struct fb_ops da8xx_fb_ops = { |
1178 | .owner = THIS_MODULE, | |
1179 | .fb_check_var = fb_check_var, | |
1180 | .fb_setcolreg = fb_setcolreg, | |
1f9c3e1f | 1181 | .fb_pan_display = da8xx_pan_display, |
4ed824d9 SR |
1182 | .fb_ioctl = fb_ioctl, |
1183 | .fb_fillrect = cfb_fillrect, | |
1184 | .fb_copyarea = cfb_copyarea, | |
1185 | .fb_imageblit = cfb_imageblit, | |
312d9715 | 1186 | .fb_blank = cfb_blank, |
4ed824d9 SR |
1187 | }; |
1188 | ||
12fa8350 MP |
1189 | /* Calculate and return pixel clock period in pico seconds */ |
1190 | static unsigned int da8xxfb_pixel_clk_period(struct da8xx_fb_par *par) | |
1191 | { | |
1192 | unsigned int lcd_clk, div; | |
1193 | unsigned int configured_pix_clk; | |
1194 | unsigned long long pix_clk_period_picosec = 1000000000000ULL; | |
1195 | ||
1196 | lcd_clk = clk_get_rate(par->lcdc_clk); | |
1197 | div = lcd_clk / par->pxl_clk; | |
1198 | configured_pix_clk = (lcd_clk / div); | |
1199 | ||
1200 | do_div(pix_clk_period_picosec, configured_pix_clk); | |
1201 | ||
1202 | return pix_clk_period_picosec; | |
1203 | } | |
1204 | ||
1db41e03 | 1205 | static int __devinit fb_probe(struct platform_device *device) |
4ed824d9 SR |
1206 | { |
1207 | struct da8xx_lcdc_platform_data *fb_pdata = | |
1208 | device->dev.platform_data; | |
1209 | struct lcd_ctrl_config *lcd_cfg; | |
1210 | struct da8xx_panel *lcdc_info; | |
1211 | struct fb_info *da8xx_fb_info; | |
1212 | struct clk *fb_clk = NULL; | |
1213 | struct da8xx_fb_par *par; | |
1214 | resource_size_t len; | |
1215 | int ret, i; | |
3b9cc4ea | 1216 | unsigned long ulcm; |
4ed824d9 SR |
1217 | |
1218 | if (fb_pdata == NULL) { | |
1219 | dev_err(&device->dev, "Can not get platform data\n"); | |
1220 | return -ENOENT; | |
1221 | } | |
1222 | ||
1223 | lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0); | |
1224 | if (!lcdc_regs) { | |
1225 | dev_err(&device->dev, | |
1226 | "Can not get memory resource for LCD controller\n"); | |
1227 | return -ENOENT; | |
1228 | } | |
1229 | ||
1230 | len = resource_size(lcdc_regs); | |
1231 | ||
1232 | lcdc_regs = request_mem_region(lcdc_regs->start, len, lcdc_regs->name); | |
1233 | if (!lcdc_regs) | |
1234 | return -EBUSY; | |
1235 | ||
1236 | da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len); | |
1237 | if (!da8xx_fb_reg_base) { | |
1238 | ret = -EBUSY; | |
1239 | goto err_request_mem; | |
1240 | } | |
1241 | ||
1242 | fb_clk = clk_get(&device->dev, NULL); | |
1243 | if (IS_ERR(fb_clk)) { | |
1244 | dev_err(&device->dev, "Can not get device clock\n"); | |
1245 | ret = -ENODEV; | |
1246 | goto err_ioremap; | |
1247 | } | |
1248 | ret = clk_enable(fb_clk); | |
1249 | if (ret) | |
1250 | goto err_clk_put; | |
1251 | ||
c6daf05b MP |
1252 | /* Determine LCD IP Version */ |
1253 | switch (lcdc_read(LCD_PID_REG)) { | |
1254 | case 0x4C100102: | |
1255 | lcd_revision = LCD_VERSION_1; | |
1256 | break; | |
1257 | case 0x4F200800: | |
1258 | lcd_revision = LCD_VERSION_2; | |
1259 | break; | |
1260 | default: | |
1261 | dev_warn(&device->dev, "Unknown PID Reg value 0x%x, " | |
1262 | "defaulting to LCD revision 1\n", | |
1263 | lcdc_read(LCD_PID_REG)); | |
1264 | lcd_revision = LCD_VERSION_1; | |
1265 | break; | |
1266 | } | |
1267 | ||
4ed824d9 SR |
1268 | for (i = 0, lcdc_info = known_lcd_panels; |
1269 | i < ARRAY_SIZE(known_lcd_panels); | |
1270 | i++, lcdc_info++) { | |
1271 | if (strcmp(fb_pdata->type, lcdc_info->name) == 0) | |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | if (i == ARRAY_SIZE(known_lcd_panels)) { | |
1276 | dev_err(&device->dev, "GLCD: No valid panel found\n"); | |
dd04a6b3 | 1277 | ret = -ENODEV; |
4ed824d9 SR |
1278 | goto err_clk_disable; |
1279 | } else | |
1280 | dev_info(&device->dev, "GLCD: Found %s panel\n", | |
1281 | fb_pdata->type); | |
1282 | ||
1283 | lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data; | |
1284 | ||
1285 | da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par), | |
1286 | &device->dev); | |
1287 | if (!da8xx_fb_info) { | |
1288 | dev_dbg(&device->dev, "Memory allocation failed for fb_info\n"); | |
1289 | ret = -ENOMEM; | |
1290 | goto err_clk_disable; | |
1291 | } | |
1292 | ||
1293 | par = da8xx_fb_info->par; | |
8097b174 | 1294 | par->lcdc_clk = fb_clk; |
f820917a MP |
1295 | #ifdef CONFIG_CPU_FREQ |
1296 | par->lcd_fck_rate = clk_get_rate(fb_clk); | |
1297 | #endif | |
8097b174 | 1298 | par->pxl_clk = lcdc_info->pxl_clk; |
36113804 C |
1299 | if (fb_pdata->panel_power_ctrl) { |
1300 | par->panel_power_ctrl = fb_pdata->panel_power_ctrl; | |
1301 | par->panel_power_ctrl(1); | |
1302 | } | |
4ed824d9 SR |
1303 | |
1304 | if (lcd_init(par, lcd_cfg, lcdc_info) < 0) { | |
1305 | dev_err(&device->dev, "lcd_init failed\n"); | |
1306 | ret = -EFAULT; | |
1307 | goto err_release_fb; | |
1308 | } | |
1309 | ||
1310 | /* allocate frame buffer */ | |
1f9c3e1f | 1311 | par->vram_size = lcdc_info->width * lcdc_info->height * lcd_cfg->bpp; |
3b9cc4ea AN |
1312 | ulcm = lcm((lcdc_info->width * lcd_cfg->bpp)/8, PAGE_SIZE); |
1313 | par->vram_size = roundup(par->vram_size/8, ulcm); | |
1f9c3e1f MA |
1314 | par->vram_size = par->vram_size * LCD_NUM_BUFFERS; |
1315 | ||
1316 | par->vram_virt = dma_alloc_coherent(NULL, | |
1317 | par->vram_size, | |
1318 | (resource_size_t *) &par->vram_phys, | |
1319 | GFP_KERNEL | GFP_DMA); | |
1320 | if (!par->vram_virt) { | |
4ed824d9 SR |
1321 | dev_err(&device->dev, |
1322 | "GLCD: kmalloc for frame buffer failed\n"); | |
1323 | ret = -EINVAL; | |
1324 | goto err_release_fb; | |
1325 | } | |
1326 | ||
1f9c3e1f MA |
1327 | da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt; |
1328 | da8xx_fb_fix.smem_start = par->vram_phys; | |
1329 | da8xx_fb_fix.smem_len = par->vram_size; | |
1330 | da8xx_fb_fix.line_length = (lcdc_info->width * lcd_cfg->bpp) / 8; | |
1331 | ||
1332 | par->dma_start = par->vram_phys; | |
1333 | par->dma_end = par->dma_start + lcdc_info->height * | |
1334 | da8xx_fb_fix.line_length - 1; | |
1335 | ||
1336 | /* allocate palette buffer */ | |
1337 | par->v_palette_base = dma_alloc_coherent(NULL, | |
1338 | PALETTE_SIZE, | |
1339 | (resource_size_t *) | |
1340 | &par->p_palette_base, | |
1341 | GFP_KERNEL | GFP_DMA); | |
1342 | if (!par->v_palette_base) { | |
1343 | dev_err(&device->dev, | |
1344 | "GLCD: kmalloc for palette buffer failed\n"); | |
1345 | ret = -EINVAL; | |
1346 | goto err_release_fb_mem; | |
1347 | } | |
1348 | memset(par->v_palette_base, 0, PALETTE_SIZE); | |
4ed824d9 | 1349 | |
4ed824d9 SR |
1350 | par->irq = platform_get_irq(device, 0); |
1351 | if (par->irq < 0) { | |
1352 | ret = -ENOENT; | |
1f9c3e1f | 1353 | goto err_release_pl_mem; |
4ed824d9 SR |
1354 | } |
1355 | ||
4ed824d9 SR |
1356 | /* Initialize par */ |
1357 | da8xx_fb_info->var.bits_per_pixel = lcd_cfg->bpp; | |
1358 | ||
1359 | da8xx_fb_var.xres = lcdc_info->width; | |
1360 | da8xx_fb_var.xres_virtual = lcdc_info->width; | |
1361 | ||
1f9c3e1f MA |
1362 | da8xx_fb_var.yres = lcdc_info->height; |
1363 | da8xx_fb_var.yres_virtual = lcdc_info->height * LCD_NUM_BUFFERS; | |
4ed824d9 SR |
1364 | |
1365 | da8xx_fb_var.grayscale = | |
1366 | lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; | |
1367 | da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; | |
1368 | ||
1369 | da8xx_fb_var.hsync_len = lcdc_info->hsw; | |
1370 | da8xx_fb_var.vsync_len = lcdc_info->vsw; | |
084e104b AG |
1371 | da8xx_fb_var.right_margin = lcdc_info->hfp; |
1372 | da8xx_fb_var.left_margin = lcdc_info->hbp; | |
1373 | da8xx_fb_var.lower_margin = lcdc_info->vfp; | |
1374 | da8xx_fb_var.upper_margin = lcdc_info->vbp; | |
12fa8350 | 1375 | da8xx_fb_var.pixclock = da8xxfb_pixel_clk_period(par); |
4ed824d9 SR |
1376 | |
1377 | /* Initialize fbinfo */ | |
1378 | da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; | |
1379 | da8xx_fb_info->fix = da8xx_fb_fix; | |
1380 | da8xx_fb_info->var = da8xx_fb_var; | |
1381 | da8xx_fb_info->fbops = &da8xx_fb_ops; | |
1382 | da8xx_fb_info->pseudo_palette = par->pseudo_palette; | |
3510b8f7 SR |
1383 | da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? |
1384 | FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; | |
4ed824d9 SR |
1385 | |
1386 | ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0); | |
1387 | if (ret) | |
93c176f3 | 1388 | goto err_release_pl_mem; |
4ed824d9 SR |
1389 | da8xx_fb_info->cmap.len = par->palette_sz; |
1390 | ||
4ed824d9 SR |
1391 | /* initialize var_screeninfo */ |
1392 | da8xx_fb_var.activate = FB_ACTIVATE_FORCE; | |
1393 | fb_set_var(da8xx_fb_info, &da8xx_fb_var); | |
1394 | ||
1395 | dev_set_drvdata(&device->dev, da8xx_fb_info); | |
1f9c3e1f MA |
1396 | |
1397 | /* initialize the vsync wait queue */ | |
1398 | init_waitqueue_head(&par->vsync_wait); | |
1399 | par->vsync_timeout = HZ / 5; | |
deb95c6c MP |
1400 | par->which_dma_channel_done = -1; |
1401 | spin_lock_init(&par->lock_for_chan_update); | |
1f9c3e1f | 1402 | |
4ed824d9 SR |
1403 | /* Register the Frame Buffer */ |
1404 | if (register_framebuffer(da8xx_fb_info) < 0) { | |
1405 | dev_err(&device->dev, | |
1406 | "GLCD: Frame Buffer Registration Failed!\n"); | |
1407 | ret = -EINVAL; | |
1408 | goto err_dealloc_cmap; | |
1409 | } | |
1410 | ||
e04e5483 C |
1411 | #ifdef CONFIG_CPU_FREQ |
1412 | ret = lcd_da8xx_cpufreq_register(par); | |
1413 | if (ret) { | |
1414 | dev_err(&device->dev, "failed to register cpufreq\n"); | |
1415 | goto err_cpu_freq; | |
1416 | } | |
1417 | #endif | |
93c176f3 | 1418 | |
c6daf05b MP |
1419 | if (lcd_revision == LCD_VERSION_1) |
1420 | lcdc_irq_handler = lcdc_irq_handler_rev01; | |
1421 | else | |
1422 | lcdc_irq_handler = lcdc_irq_handler_rev02; | |
1423 | ||
1424 | ret = request_irq(par->irq, lcdc_irq_handler, 0, | |
1425 | DRIVER_NAME, par); | |
93c176f3 CA |
1426 | if (ret) |
1427 | goto irq_freq; | |
4ed824d9 SR |
1428 | return 0; |
1429 | ||
93c176f3 | 1430 | irq_freq: |
e04e5483 | 1431 | #ifdef CONFIG_CPU_FREQ |
360c202b | 1432 | lcd_da8xx_cpufreq_deregister(par); |
e04e5483 | 1433 | err_cpu_freq: |
3a84409c | 1434 | #endif |
e04e5483 | 1435 | unregister_framebuffer(da8xx_fb_info); |
e04e5483 | 1436 | |
4ed824d9 SR |
1437 | err_dealloc_cmap: |
1438 | fb_dealloc_cmap(&da8xx_fb_info->cmap); | |
1439 | ||
1f9c3e1f MA |
1440 | err_release_pl_mem: |
1441 | dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base, | |
1442 | par->p_palette_base); | |
1443 | ||
4ed824d9 | 1444 | err_release_fb_mem: |
1f9c3e1f | 1445 | dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys); |
4ed824d9 SR |
1446 | |
1447 | err_release_fb: | |
1448 | framebuffer_release(da8xx_fb_info); | |
1449 | ||
1450 | err_clk_disable: | |
1451 | clk_disable(fb_clk); | |
1452 | ||
1453 | err_clk_put: | |
1454 | clk_put(fb_clk); | |
1455 | ||
1456 | err_ioremap: | |
1457 | iounmap((void __iomem *)da8xx_fb_reg_base); | |
1458 | ||
1459 | err_request_mem: | |
1460 | release_mem_region(lcdc_regs->start, len); | |
1461 | ||
1462 | return ret; | |
1463 | } | |
1464 | ||
1465 | #ifdef CONFIG_PM | |
1466 | static int fb_suspend(struct platform_device *dev, pm_message_t state) | |
1467 | { | |
1d3c6c7b C |
1468 | struct fb_info *info = platform_get_drvdata(dev); |
1469 | struct da8xx_fb_par *par = info->par; | |
1470 | ||
ac751efa | 1471 | console_lock(); |
1d3c6c7b C |
1472 | if (par->panel_power_ctrl) |
1473 | par->panel_power_ctrl(0); | |
1474 | ||
1475 | fb_set_suspend(info, 1); | |
1476 | lcd_disable_raster(); | |
1477 | clk_disable(par->lcdc_clk); | |
ac751efa | 1478 | console_unlock(); |
1d3c6c7b C |
1479 | |
1480 | return 0; | |
4ed824d9 SR |
1481 | } |
1482 | static int fb_resume(struct platform_device *dev) | |
1483 | { | |
1d3c6c7b C |
1484 | struct fb_info *info = platform_get_drvdata(dev); |
1485 | struct da8xx_fb_par *par = info->par; | |
1486 | ||
ac751efa | 1487 | console_lock(); |
f7c848b6 MP |
1488 | clk_enable(par->lcdc_clk); |
1489 | lcd_enable_raster(); | |
1490 | ||
1d3c6c7b C |
1491 | if (par->panel_power_ctrl) |
1492 | par->panel_power_ctrl(1); | |
1493 | ||
1d3c6c7b | 1494 | fb_set_suspend(info, 0); |
ac751efa | 1495 | console_unlock(); |
1d3c6c7b C |
1496 | |
1497 | return 0; | |
4ed824d9 SR |
1498 | } |
1499 | #else | |
1500 | #define fb_suspend NULL | |
1501 | #define fb_resume NULL | |
1502 | #endif | |
1503 | ||
1504 | static struct platform_driver da8xx_fb_driver = { | |
1505 | .probe = fb_probe, | |
1db41e03 | 1506 | .remove = __devexit_p(fb_remove), |
4ed824d9 SR |
1507 | .suspend = fb_suspend, |
1508 | .resume = fb_resume, | |
1509 | .driver = { | |
1510 | .name = DRIVER_NAME, | |
1511 | .owner = THIS_MODULE, | |
1512 | }, | |
1513 | }; | |
1514 | ||
1515 | static int __init da8xx_fb_init(void) | |
1516 | { | |
1517 | return platform_driver_register(&da8xx_fb_driver); | |
1518 | } | |
1519 | ||
1520 | static void __exit da8xx_fb_cleanup(void) | |
1521 | { | |
1522 | platform_driver_unregister(&da8xx_fb_driver); | |
1523 | } | |
1524 | ||
1525 | module_init(da8xx_fb_init); | |
1526 | module_exit(da8xx_fb_cleanup); | |
1527 | ||
1528 | MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx"); | |
1529 | MODULE_AUTHOR("Texas Instruments"); | |
1530 | MODULE_LICENSE("GPL"); |