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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[linux-block.git] / drivers / video / cg6.c
CommitLineData
1da177e4
LT		 1/* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
2 *
50312ce9 3 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
5 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 *
8 * Driver layout based loosely on tgafb.c, see that file for credits.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/fb.h>
19#include <linux/mm.h>
20
21#include <asm/io.h>
50312ce9
DM		 22#include <asm/prom.h>
23#include <asm/of_device.h>
1da177e4
LT		 24#include <asm/fbio.h>
25
26#include "sbuslib.h"
27
28/*
29 * Local functions.
30 */
31
32static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
33 unsigned, struct fb_info *);
34static int cg6_blank(int, struct fb_info *);
35
36static void cg6_imageblit(struct fb_info *, const struct fb_image *);
37static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
38static int cg6_sync(struct fb_info *);
216d526c 39static int cg6_mmap(struct fb_info *, struct vm_area_struct *);
67a6680d 40static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long);
1da177e4
LT		 41
42/*
43 * Frame buffer operations
44 */
45
46static struct fb_ops cg6_ops = {
47 .owner = THIS_MODULE,
48 .fb_setcolreg = cg6_setcolreg,
49 .fb_blank = cg6_blank,
50 .fb_fillrect = cg6_fillrect,
51 .fb_copyarea = cfb_copyarea,
52 .fb_imageblit = cg6_imageblit,
53 .fb_sync = cg6_sync,
54 .fb_mmap = cg6_mmap,
55 .fb_ioctl = cg6_ioctl,
9ffb83bc
CH		 56#ifdef CONFIG_COMPAT
57 .fb_compat_ioctl = sbusfb_compat_ioctl,
58#endif
1da177e4
LT		 59};
60
61/* Offset of interesting structures in the OBIO space */
62/*
63 * Brooktree is the video dac and is funny to program on the cg6.
64 * (it's even funnier on the cg3)
65 * The FBC could be the frame buffer control
66 * The FHC could is the frame buffer hardware control.
67 */
68#define CG6_ROM_OFFSET 0x0UL
69#define CG6_BROOKTREE_OFFSET 0x200000UL
70#define CG6_DHC_OFFSET 0x240000UL
71#define CG6_ALT_OFFSET 0x280000UL
72#define CG6_FHC_OFFSET 0x300000UL
73#define CG6_THC_OFFSET 0x301000UL
74#define CG6_FBC_OFFSET 0x700000UL
75#define CG6_TEC_OFFSET 0x701000UL
76#define CG6_RAM_OFFSET 0x800000UL
77
78/* FHC definitions */
79#define CG6_FHC_FBID_SHIFT 24
80#define CG6_FHC_FBID_MASK 255
81#define CG6_FHC_REV_SHIFT 20
82#define CG6_FHC_REV_MASK 15
83#define CG6_FHC_FROP_DISABLE (1 << 19)
84#define CG6_FHC_ROW_DISABLE (1 << 18)
85#define CG6_FHC_SRC_DISABLE (1 << 17)
86#define CG6_FHC_DST_DISABLE (1 << 16)
87#define CG6_FHC_RESET (1 << 15)
88#define CG6_FHC_LITTLE_ENDIAN (1 << 13)
89#define CG6_FHC_RES_MASK (3 << 11)
90#define CG6_FHC_1024 (0 << 11)
91#define CG6_FHC_1152 (1 << 11)
92#define CG6_FHC_1280 (2 << 11)
93#define CG6_FHC_1600 (3 << 11)
94#define CG6_FHC_CPU_MASK (3 << 9)
95#define CG6_FHC_CPU_SPARC (0 << 9)
96#define CG6_FHC_CPU_68020 (1 << 9)
97#define CG6_FHC_CPU_386 (2 << 9)
98#define CG6_FHC_TEST (1 << 8)
99#define CG6_FHC_TEST_X_SHIFT 4
100#define CG6_FHC_TEST_X_MASK 15
101#define CG6_FHC_TEST_Y_SHIFT 0
102#define CG6_FHC_TEST_Y_MASK 15
103
104/* FBC mode definitions */
105#define CG6_FBC_BLIT_IGNORE 0x00000000
106#define CG6_FBC_BLIT_NOSRC 0x00100000
107#define CG6_FBC_BLIT_SRC 0x00200000
108#define CG6_FBC_BLIT_ILLEGAL 0x00300000
109#define CG6_FBC_BLIT_MASK 0x00300000
110
111#define CG6_FBC_VBLANK 0x00080000
112
113#define CG6_FBC_MODE_IGNORE 0x00000000
114#define CG6_FBC_MODE_COLOR8 0x00020000
115#define CG6_FBC_MODE_COLOR1 0x00040000
116#define CG6_FBC_MODE_HRMONO 0x00060000
117#define CG6_FBC_MODE_MASK 0x00060000
118
119#define CG6_FBC_DRAW_IGNORE 0x00000000
120#define CG6_FBC_DRAW_RENDER 0x00008000
121#define CG6_FBC_DRAW_PICK 0x00010000
122#define CG6_FBC_DRAW_ILLEGAL 0x00018000
123#define CG6_FBC_DRAW_MASK 0x00018000
124
125#define CG6_FBC_BWRITE0_IGNORE 0x00000000
126#define CG6_FBC_BWRITE0_ENABLE 0x00002000
127#define CG6_FBC_BWRITE0_DISABLE 0x00004000
128#define CG6_FBC_BWRITE0_ILLEGAL 0x00006000
129#define CG6_FBC_BWRITE0_MASK 0x00006000
130
131#define CG6_FBC_BWRITE1_IGNORE 0x00000000
132#define CG6_FBC_BWRITE1_ENABLE 0x00000800
133#define CG6_FBC_BWRITE1_DISABLE 0x00001000
134#define CG6_FBC_BWRITE1_ILLEGAL 0x00001800
135#define CG6_FBC_BWRITE1_MASK 0x00001800
136
137#define CG6_FBC_BREAD_IGNORE 0x00000000
138#define CG6_FBC_BREAD_0 0x00000200
139#define CG6_FBC_BREAD_1 0x00000400
140#define CG6_FBC_BREAD_ILLEGAL 0x00000600
141#define CG6_FBC_BREAD_MASK 0x00000600
142
143#define CG6_FBC_BDISP_IGNORE 0x00000000
144#define CG6_FBC_BDISP_0 0x00000080
145#define CG6_FBC_BDISP_1 0x00000100
146#define CG6_FBC_BDISP_ILLEGAL 0x00000180
147#define CG6_FBC_BDISP_MASK 0x00000180
148
149#define CG6_FBC_INDEX_MOD 0x00000040
150#define CG6_FBC_INDEX_MASK 0x00000030
151
152/* THC definitions */
153#define CG6_THC_MISC_REV_SHIFT 16
154#define CG6_THC_MISC_REV_MASK 15
155#define CG6_THC_MISC_RESET (1 << 12)
156#define CG6_THC_MISC_VIDEO (1 << 10)
157#define CG6_THC_MISC_SYNC (1 << 9)
158#define CG6_THC_MISC_VSYNC (1 << 8)
159#define CG6_THC_MISC_SYNC_ENAB (1 << 7)
160#define CG6_THC_MISC_CURS_RES (1 << 6)
161#define CG6_THC_MISC_INT_ENAB (1 << 5)
162#define CG6_THC_MISC_INT (1 << 4)
163#define CG6_THC_MISC_INIT 0x9f
164
165/* The contents are unknown */
166struct cg6_tec {
50312ce9
DM		 167 int tec_matrix;
168 int tec_clip;
169 int tec_vdc;
1da177e4
LT		 170};
171
172struct cg6_thc {
50312ce9
DM		 173 u32 thc_pad0[512];
174 u32 thc_hs; /* hsync timing */
175 u32 thc_hsdvs;
176 u32 thc_hd;
177 u32 thc_vs; /* vsync timing */
178 u32 thc_vd;
179 u32 thc_refresh;
180 u32 thc_misc;
181 u32 thc_pad1[56];
182 u32 thc_cursxy; /* cursor x,y position (16 bits each) */
183 u32 thc_cursmask[32]; /* cursor mask bits */
184 u32 thc_cursbits[32]; /* what to show where mask enabled */
1da177e4
LT		 185};
186
187struct cg6_fbc {
50312ce9
DM		 188 u32 xxx0[1];
189 u32 mode;
190 u32 clip;
191 u32 xxx1[1];
192 u32 s;
193 u32 draw;
194 u32 blit;
195 u32 font;
196 u32 xxx2[24];
197 u32 x0, y0, z0, color0;
198 u32 x1, y1, z1, color1;
199 u32 x2, y2, z2, color2;
200 u32 x3, y3, z3, color3;
201 u32 offx, offy;
202 u32 xxx3[2];
203 u32 incx, incy;
204 u32 xxx4[2];
205 u32 clipminx, clipminy;
206 u32 xxx5[2];
207 u32 clipmaxx, clipmaxy;
208 u32 xxx6[2];
209 u32 fg;
210 u32 bg;
211 u32 alu;
212 u32 pm;
213 u32 pixelm;
214 u32 xxx7[2];
215 u32 patalign;
216 u32 pattern[8];
217 u32 xxx8[432];
218 u32 apointx, apointy, apointz;
219 u32 xxx9[1];
220 u32 rpointx, rpointy, rpointz;
221 u32 xxx10[5];
222 u32 pointr, pointg, pointb, pointa;
223 u32 alinex, aliney, alinez;
224 u32 xxx11[1];
225 u32 rlinex, rliney, rlinez;
226 u32 xxx12[5];
227 u32 liner, lineg, lineb, linea;
228 u32 atrix, atriy, atriz;
229 u32 xxx13[1];
230 u32 rtrix, rtriy, rtriz;
231 u32 xxx14[5];
232 u32 trir, trig, trib, tria;
233 u32 aquadx, aquady, aquadz;
234 u32 xxx15[1];
235 u32 rquadx, rquady, rquadz;
236 u32 xxx16[5];
237 u32 quadr, quadg, quadb, quada;
238 u32 arectx, arecty, arectz;
239 u32 xxx17[1];
240 u32 rrectx, rrecty, rrectz;
241 u32 xxx18[5];
242 u32 rectr, rectg, rectb, recta;
1da177e4
LT		 243};
244
245struct bt_regs {
50312ce9
DM		 246 u32 addr;
247 u32 color_map;
248 u32 control;
249 u32 cursor;
1da177e4
LT		 250};
251
252struct cg6_par {
253 spinlock_t lock;
254 struct bt_regs __iomem *bt;
255 struct cg6_fbc __iomem *fbc;
256 struct cg6_thc __iomem *thc;
257 struct cg6_tec __iomem *tec;
50312ce9 258 u32 __iomem *fhc;
1da177e4
LT		 259
260 u32 flags;
261#define CG6_FLAG_BLANKED 0x00000001
262
263 unsigned long physbase;
50312ce9 264 unsigned long which_io;
1da177e4 265 unsigned long fbsize;
1da177e4
LT		 266};
267
268static int cg6_sync(struct fb_info *info)
269{
270 struct cg6_par *par = (struct cg6_par *) info->par;
271 struct cg6_fbc __iomem *fbc = par->fbc;
272 int limit = 10000;
273
274 do {
275 if (!(sbus_readl(&fbc->s) & 0x10000000))
276 break;
277 udelay(10);
278 } while (--limit > 0);
279
280 return 0;
281}
282
283/**
284 * cg6_fillrect - REQUIRED function. Can use generic routines if
285 * non acclerated hardware and packed pixel based.
286 * Draws a rectangle on the screen.
287 *
288 * @info: frame buffer structure that represents a single frame buffer
289 * @rect: structure defining the rectagle and operation.
290 */
291static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
292{
293 struct cg6_par *par = (struct cg6_par *) info->par;
294 struct cg6_fbc __iomem *fbc = par->fbc;
295 unsigned long flags;
296 s32 val;
297
298 /* XXX doesn't handle ROP_XOR */
299
300 spin_lock_irqsave(&par->lock, flags);
301 cg6_sync(info);
302 sbus_writel(rect->color, &fbc->fg);
303 sbus_writel(~(u32)0, &fbc->pixelm);
304 sbus_writel(0xea80ff00, &fbc->alu);
305 sbus_writel(0, &fbc->s);
306 sbus_writel(0, &fbc->clip);
307 sbus_writel(~(u32)0, &fbc->pm);
308 sbus_writel(rect->dy, &fbc->arecty);
309 sbus_writel(rect->dx, &fbc->arectx);
310 sbus_writel(rect->dy + rect->height, &fbc->arecty);
311 sbus_writel(rect->dx + rect->width, &fbc->arectx);
312 do {
313 val = sbus_readl(&fbc->draw);
314 } while (val < 0 && (val & 0x20000000));
315 spin_unlock_irqrestore(&par->lock, flags);
316}
317
318/**
319 * cg6_imageblit - REQUIRED function. Can use generic routines if
320 * non acclerated hardware and packed pixel based.
321 * Copies a image from system memory to the screen.
322 *
323 * @info: frame buffer structure that represents a single frame buffer
324 * @image: structure defining the image.
325 */
326static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
327{
328 struct cg6_par *par = (struct cg6_par *) info->par;
329 struct cg6_fbc __iomem *fbc = par->fbc;
330 const u8 *data = image->data;
331 unsigned long flags;
332 u32 x, y;
333 int i, width;
334
335 if (image->depth > 1) {
336 cfb_imageblit(info, image);
337 return;
338 }
339
340 spin_lock_irqsave(&par->lock, flags);
341
342 cg6_sync(info);
343
344 sbus_writel(image->fg_color, &fbc->fg);
345 sbus_writel(image->bg_color, &fbc->bg);
346 sbus_writel(0x140000, &fbc->mode);
347 sbus_writel(0xe880fc30, &fbc->alu);
348 sbus_writel(~(u32)0, &fbc->pixelm);
349 sbus_writel(0, &fbc->s);
350 sbus_writel(0, &fbc->clip);
351 sbus_writel(0xff, &fbc->pm);
352 sbus_writel(32, &fbc->incx);
353 sbus_writel(0, &fbc->incy);
354
355 x = image->dx;
356 y = image->dy;
357 for (i = 0; i < image->height; i++) {
358 width = image->width;
359
360 while (width >= 32) {
361 u32 val;
362
363 sbus_writel(y, &fbc->y0);
364 sbus_writel(x, &fbc->x0);
365 sbus_writel(x + 32 - 1, &fbc->x1);
366
367 val = ((u32)data[0] << 24) |
368 ((u32)data[1] << 16) |
369 ((u32)data[2] << 8) |
370 ((u32)data[3] << 0);
371 sbus_writel(val, &fbc->font);
372
373 data += 4;
374 x += 32;
375 width -= 32;
376 }
377 if (width) {
378 u32 val;
379
380 sbus_writel(y, &fbc->y0);
381 sbus_writel(x, &fbc->x0);
382 sbus_writel(x + width - 1, &fbc->x1);
383 if (width <= 8) {
384 val = (u32) data[0] << 24;
385 data += 1;
386 } else if (width <= 16) {
387 val = ((u32) data[0] << 24) |
388 ((u32) data[1] << 16);
389 data += 2;
390 } else {
391 val = ((u32) data[0] << 24) |
392 ((u32) data[1] << 16) |
393 ((u32) data[2] << 8);
394 data += 3;
395 }
396 sbus_writel(val, &fbc->font);
397 }
398
399 y += 1;
400 x = image->dx;
401 }
402
403 spin_unlock_irqrestore(&par->lock, flags);
404}
405
406/**
407 * cg6_setcolreg - Optional function. Sets a color register.
408 * @regno: boolean, 0 copy local, 1 get_user() function
409 * @red: frame buffer colormap structure
410 * @green: The green value which can be up to 16 bits wide
411 * @blue: The blue value which can be up to 16 bits wide.
412 * @transp: If supported the alpha value which can be up to 16 bits wide.
413 * @info: frame buffer info structure
414 */
415static int cg6_setcolreg(unsigned regno,
416 unsigned red, unsigned green, unsigned blue,
417 unsigned transp, struct fb_info *info)
418{
419 struct cg6_par *par = (struct cg6_par *) info->par;
420 struct bt_regs __iomem *bt = par->bt;
421 unsigned long flags;
422
423 if (regno >= 256)
424 return 1;
425
426 red >>= 8;
427 green >>= 8;
428 blue >>= 8;
429
430 spin_lock_irqsave(&par->lock, flags);
431
432 sbus_writel((u32)regno << 24, &bt->addr);
433 sbus_writel((u32)red << 24, &bt->color_map);
434 sbus_writel((u32)green << 24, &bt->color_map);
435 sbus_writel((u32)blue << 24, &bt->color_map);
436
437 spin_unlock_irqrestore(&par->lock, flags);
438
439 return 0;
440}
441
442/**
443 * cg6_blank - Optional function. Blanks the display.
444 * @blank_mode: the blank mode we want.
445 * @info: frame buffer structure that represents a single frame buffer
446 */
447static int
448cg6_blank(int blank, struct fb_info *info)
449{
450 struct cg6_par *par = (struct cg6_par *) info->par;
451 struct cg6_thc __iomem *thc = par->thc;
452 unsigned long flags;
453 u32 val;
454
455 spin_lock_irqsave(&par->lock, flags);
456
457 switch (blank) {
458 case FB_BLANK_UNBLANK: /* Unblanking */
459 val = sbus_readl(&thc->thc_misc);
460 val |= CG6_THC_MISC_VIDEO;
461 sbus_writel(val, &thc->thc_misc);
462 par->flags &= ~CG6_FLAG_BLANKED;
463 break;
464
465 case FB_BLANK_NORMAL: /* Normal blanking */
466 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
467 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
468 case FB_BLANK_POWERDOWN: /* Poweroff */
469 val = sbus_readl(&thc->thc_misc);
470 val &= ~CG6_THC_MISC_VIDEO;
471 sbus_writel(val, &thc->thc_misc);
472 par->flags |= CG6_FLAG_BLANKED;
473 break;
474 }
475
476 spin_unlock_irqrestore(&par->lock, flags);
477
478 return 0;
479}
480
481static struct sbus_mmap_map cg6_mmap_map[] = {
482 {
483 .voff = CG6_FBC,
484 .poff = CG6_FBC_OFFSET,
485 .size = PAGE_SIZE
486 },
487 {
488 .voff = CG6_TEC,
489 .poff = CG6_TEC_OFFSET,
490 .size = PAGE_SIZE
491 },
492 {
493 .voff = CG6_BTREGS,
494 .poff = CG6_BROOKTREE_OFFSET,
495 .size = PAGE_SIZE
496 },
497 {
498 .voff = CG6_FHC,
499 .poff = CG6_FHC_OFFSET,
500 .size = PAGE_SIZE
501 },
502 {
503 .voff = CG6_THC,
504 .poff = CG6_THC_OFFSET,
505 .size = PAGE_SIZE
506 },
507 {
508 .voff = CG6_ROM,
509 .poff = CG6_ROM_OFFSET,
510 .size = 0x10000
511 },
512 {
513 .voff = CG6_RAM,
514 .poff = CG6_RAM_OFFSET,
515 .size = SBUS_MMAP_FBSIZE(1)
516 },
517 {
518 .voff = CG6_DHC,
519 .poff = CG6_DHC_OFFSET,
520 .size = 0x40000
521 },
522 { .size = 0 }
523};
524
216d526c 525static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma)
1da177e4
LT		 526{
527 struct cg6_par *par = (struct cg6_par *)info->par;
528
529 return sbusfb_mmap_helper(cg6_mmap_map,
530 par->physbase, par->fbsize,
50312ce9 531 par->which_io, vma);
1da177e4
LT		 532}
533
67a6680d 534static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
1da177e4
LT		 535{
536 struct cg6_par *par = (struct cg6_par *) info->par;
537
538 return sbusfb_ioctl_helper(cmd, arg, info,
539 FBTYPE_SUNFAST_COLOR, 8, par->fbsize);
540}
541
542/*
543 * Initialisation
544 */
545
546static void
547cg6_init_fix(struct fb_info *info, int linebytes)
548{
549 struct cg6_par *par = (struct cg6_par *)info->par;
550 const char *cg6_cpu_name, *cg6_card_name;
551 u32 conf;
552
553 conf = sbus_readl(par->fhc);
554 switch(conf & CG6_FHC_CPU_MASK) {
555 case CG6_FHC_CPU_SPARC:
556 cg6_cpu_name = "sparc";
557 break;
558 case CG6_FHC_CPU_68020:
559 cg6_cpu_name = "68020";
560 break;
561 default:
562 cg6_cpu_name = "i386";
563 break;
564 };
565 if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
566 if (par->fbsize <= 0x100000) {
567 cg6_card_name = "TGX";
568 } else {
569 cg6_card_name = "TGX+";
570 }
571 } else {
572 if (par->fbsize <= 0x100000) {
573 cg6_card_name = "GX";
574 } else {
575 cg6_card_name = "GX+";
576 }
577 }
578
579 sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
580 info->fix.id[sizeof(info->fix.id)-1] = 0;
581
582 info->fix.type = FB_TYPE_PACKED_PIXELS;
583 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
584
585 info->fix.line_length = linebytes;
586
587 info->fix.accel = FB_ACCEL_SUN_CGSIX;
588}
589
590/* Initialize Brooktree DAC */
591static void cg6_bt_init(struct cg6_par *par)
592{
593 struct bt_regs __iomem *bt = par->bt;
594
595 sbus_writel(0x04 << 24, &bt->addr); /* color planes */
596 sbus_writel(0xff << 24, &bt->control);
597 sbus_writel(0x05 << 24, &bt->addr);
598 sbus_writel(0x00 << 24, &bt->control);
599 sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */
600 sbus_writel(0x73 << 24, &bt->control);
601 sbus_writel(0x07 << 24, &bt->addr);
602 sbus_writel(0x00 << 24, &bt->control);
603}
604
605static void cg6_chip_init(struct fb_info *info)
606{
607 struct cg6_par *par = (struct cg6_par *) info->par;
608 struct cg6_tec __iomem *tec = par->tec;
609 struct cg6_fbc __iomem *fbc = par->fbc;
806f7bf6 610 u32 rev, conf, mode;
1da177e4
LT		 611 int i;
612
613 /* Turn off stuff in the Transform Engine. */
614 sbus_writel(0, &tec->tec_matrix);
615 sbus_writel(0, &tec->tec_clip);
616 sbus_writel(0, &tec->tec_vdc);
617
618 /* Take care of bugs in old revisions. */
619 rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
620 if (rev < 5) {
621 conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
622 CG6_FHC_CPU_68020 | CG6_FHC_TEST |
623 (11 << CG6_FHC_TEST_X_SHIFT) |
624 (11 << CG6_FHC_TEST_Y_SHIFT);
625 if (rev < 2)
626 conf |= CG6_FHC_DST_DISABLE;
627 sbus_writel(conf, par->fhc);
628 }
629
630 /* Set things in the FBC. Bad things appear to happen if we do
631 * back to back store/loads on the mode register, so copy it
632 * out instead. */
633 mode = sbus_readl(&fbc->mode);
634 do {
635 i = sbus_readl(&fbc->s);
636 } while (i & 0x10000000);
637 mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
638 CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
639 CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
640 CG6_FBC_BDISP_MASK);
641 mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
642 CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
643 CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
644 CG6_FBC_BDISP_0);
645 sbus_writel(mode, &fbc->mode);
646
647 sbus_writel(0, &fbc->clip);
648 sbus_writel(0, &fbc->offx);
649 sbus_writel(0, &fbc->offy);
650 sbus_writel(0, &fbc->clipminx);
651 sbus_writel(0, &fbc->clipminy);
652 sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
653 sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
1da177e4
LT		 654}
655
656struct all_info {
657 struct fb_info info;
658 struct cg6_par par;
1da177e4 659};
1da177e4 660
e3a411a3 661static void cg6_unmap_regs(struct of_device *op, struct all_info *all)
1da177e4 662{
50312ce9 663 if (all->par.fbc)
e3a411a3 664 of_iounmap(&op->resource[0], all->par.fbc, 4096);
50312ce9 665 if (all->par.tec)
e3a411a3
DM		 666 of_iounmap(&op->resource[0],
667 all->par.tec, sizeof(struct cg6_tec));
50312ce9 668 if (all->par.thc)
e3a411a3
DM		 669 of_iounmap(&op->resource[0],
670 all->par.thc, sizeof(struct cg6_thc));
50312ce9 671 if (all->par.bt)
e3a411a3
DM		 672 of_iounmap(&op->resource[0],
673 all->par.bt, sizeof(struct bt_regs));
50312ce9 674 if (all->par.fhc)
e3a411a3
DM		 675 of_iounmap(&op->resource[0],
676 all->par.fhc, sizeof(u32));
50312ce9
DM		 677
678 if (all->info.screen_base)
e3a411a3
DM		 679 of_iounmap(&op->resource[0],
680 all->info.screen_base, all->par.fbsize);
50312ce9 681}
1da177e4 682
50312ce9
DM		 683static int __devinit cg6_init_one(struct of_device *op)
684{
685 struct device_node *dp = op->node;
686 struct all_info *all;
687 int linebytes, err;
1da177e4 688
50312ce9
DM		 689 all = kzalloc(sizeof(*all), GFP_KERNEL);
690 if (!all)
691 return -ENOMEM;
1da177e4
LT		 692
693 spin_lock_init(&all->par.lock);
1da177e4 694
50312ce9
DM		 695 all->par.physbase = op->resource[0].start;
696 all->par.which_io = op->resource[0].flags & IORESOURCE_BITS;
1da177e4 697
50312ce9 698 sbusfb_fill_var(&all->info.var, dp->node, 8);
1da177e4
LT		 699 all->info.var.red.length = 8;
700 all->info.var.green.length = 8;
701 all->info.var.blue.length = 8;
702
50312ce9
DM		 703 linebytes = of_getintprop_default(dp, "linebytes",
704 all->info.var.xres);
1da177e4 705 all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
50312ce9 706 if (of_find_property(dp, "dblbuf", NULL))
1da177e4
LT		 707 all->par.fbsize *= 4;
708
50312ce9
DM		 709 all->par.fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET,
710 4096, "cgsix fbc");
711 all->par.tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET,
712 sizeof(struct cg6_tec), "cgsix tec");
713 all->par.thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET,
714 sizeof(struct cg6_thc), "cgsix thc");
715 all->par.bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET,
716 sizeof(struct bt_regs), "cgsix dac");
717 all->par.fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET,
718 sizeof(u32), "cgsix fhc");
1da177e4
LT		 719
720 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT |
721 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
722 all->info.fbops = &cg6_ops;
50312ce9
DM		 723
724 all->info.screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET,
725 all->par.fbsize, "cgsix ram");
726 if (!all->par.fbc || !all->par.tec || !all->par.thc ||
727 !all->par.bt || !all->par.fhc || !all->info.screen_base) {
e3a411a3 728 cg6_unmap_regs(op, all);
50312ce9
DM		 729 kfree(all);
730 return -ENOMEM;
731 }
732
1da177e4
LT		 733 all->info.par = &all->par;
734
735 all->info.var.accel_flags = FB_ACCELF_TEXT;
736
737 cg6_bt_init(&all->par);
738 cg6_chip_init(&all->info);
739 cg6_blank(0, &all->info);
740
741 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
e3a411a3 742 cg6_unmap_regs(op, all);
1da177e4 743 kfree(all);
50312ce9 744 return -ENOMEM;
1da177e4
LT		 745 }
746
747 fb_set_cmap(&all->info.cmap, &all->info);
748 cg6_init_fix(&all->info, linebytes);
749
50312ce9
DM		 750 err = register_framebuffer(&all->info);
751 if (err < 0) {
e3a411a3 752 cg6_unmap_regs(op, all);
1da177e4
LT		 753 fb_dealloc_cmap(&all->info.cmap);
754 kfree(all);
50312ce9 755 return err;
1da177e4
LT		 756 }
757
50312ce9 758 dev_set_drvdata(&op->dev, all);
1da177e4 759
50312ce9
DM		 760 printk("%s: CGsix [%s] at %lx:%lx\n",
761 dp->full_name,
1da177e4 762 all->info.fix.id,
50312ce9
DM		 763 all->par.which_io, all->par.physbase);
764
765 return 0;
1da177e4
LT		 766}
767
50312ce9 768static int __devinit cg6_probe(struct of_device *dev, const struct of_device_id *match)
1da177e4 769{
50312ce9 770 struct of_device *op = to_of_device(&dev->dev);
1da177e4 771
50312ce9
DM		 772 return cg6_init_one(op);
773}
1da177e4 774
e3a411a3 775static int __devexit cg6_remove(struct of_device *op)
50312ce9 776{
e3a411a3 777 struct all_info *all = dev_get_drvdata(&op->dev);
50312ce9
DM		 778
779 unregister_framebuffer(&all->info);
780 fb_dealloc_cmap(&all->info.cmap);
781
e3a411a3 782 cg6_unmap_regs(op, all);
50312ce9
DM		 783
784 kfree(all);
785
e3a411a3 786 dev_set_drvdata(&op->dev, NULL);
1da177e4
LT		 787
788 return 0;
789}
790
50312ce9
DM		 791static struct of_device_id cg6_match[] = {
792 {
793 .name = "cgsix",
794 },
795 {
796 .name = "cgthree+",
797 },
798 {},
799};
800MODULE_DEVICE_TABLE(of, cg6_match);
1da177e4 801
50312ce9
DM		 802static struct of_platform_driver cg6_driver = {
803 .name = "cg6",
804 .match_table = cg6_match,
805 .probe = cg6_probe,
806 .remove = __devexit_p(cg6_remove),
807};
1da177e4 808
50312ce9
DM		 809static int __init cg6_init(void)
810{
811 if (fb_get_options("cg6fb", NULL))
812 return -ENODEV;
813
814 return of_register_driver(&cg6_driver, &of_bus_type);
1da177e4
LT		 815}
816
50312ce9 817static void __exit cg6_exit(void)
1da177e4 818{
50312ce9 819 of_unregister_driver(&cg6_driver);
1da177e4
LT		 820}
821
822module_init(cg6_init);
1da177e4 823module_exit(cg6_exit);
1da177e4
LT		 824
825MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
50312ce9
DM		 826MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
827MODULE_VERSION("2.0");
1da177e4 828MODULE_LICENSE("GPL");
Linux 6.x block layer and io_uring tree(s)