[linux-2.6-block.git] / drivers / video / cg3.c

/* cg3.c: CGTHREE frame buffer driver
 *
 * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
 *
 * Driver layout based loosely on tgafb.c, see that file for credits.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/fb.h>
#include <linux/mm.h>
#include <linux/of_device.h>

#include <asm/io.h>
#include <asm/fbio.h>

#include "sbuslib.h"

/*
 * Local functions.
 */

static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
			 unsigned, struct fb_info *);
static int cg3_blank(int, struct fb_info *);

static int cg3_mmap(struct fb_info *, struct vm_area_struct *);
static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);

/*
 *  Frame buffer operations
 */

static struct fb_ops cg3_ops = {
	.owner			= THIS_MODULE,
	.fb_setcolreg		= cg3_setcolreg,
	.fb_blank		= cg3_blank,
	.fb_fillrect		= cfb_fillrect,
	.fb_copyarea		= cfb_copyarea,
	.fb_imageblit		= cfb_imageblit,
	.fb_mmap		= cg3_mmap,
	.fb_ioctl		= cg3_ioctl,
#ifdef CONFIG_COMPAT
	.fb_compat_ioctl	= sbusfb_compat_ioctl,
#endif
};


/* Control Register Constants */
#define CG3_CR_ENABLE_INTS      0x80
#define CG3_CR_ENABLE_VIDEO     0x40
#define CG3_CR_ENABLE_TIMING    0x20
#define CG3_CR_ENABLE_CURCMP    0x10
#define CG3_CR_XTAL_MASK        0x0c
#define CG3_CR_DIVISOR_MASK     0x03

/* Status Register Constants */
#define CG3_SR_PENDING_INT      0x80
#define CG3_SR_RES_MASK         0x70
#define CG3_SR_1152_900_76_A    0x40
#define CG3_SR_1152_900_76_B    0x60
#define CG3_SR_ID_MASK          0x0f
#define CG3_SR_ID_COLOR         0x01
#define CG3_SR_ID_MONO          0x02
#define CG3_SR_ID_MONO_ECL      0x03

enum cg3_type {
	CG3_AT_66HZ = 0,
	CG3_AT_76HZ,
	CG3_RDI
};

struct bt_regs {
	u32 addr;
	u32 color_map;
	u32 control;
	u32 cursor;
};

struct cg3_regs {
	struct bt_regs	cmap;
	u8	control;
	u8	status;
	u8	cursor_start;
	u8	cursor_end;
	u8	h_blank_start;
	u8	h_blank_end;
	u8	h_sync_start;
	u8	h_sync_end;
	u8	comp_sync_end;
	u8	v_blank_start_high;
	u8	v_blank_start_low;
	u8	v_blank_end;
	u8	v_sync_start;
	u8	v_sync_end;
	u8	xfer_holdoff_start;
	u8	xfer_holdoff_end;
};

/* Offset of interesting structures in the OBIO space */
#define CG3_REGS_OFFSET	     0x400000UL
#define CG3_RAM_OFFSET	     0x800000UL

struct cg3_par {
	spinlock_t		lock;
	struct cg3_regs		__iomem *regs;
	u32			sw_cmap[((256 * 3) + 3) / 4];

	u32			flags;
#define CG3_FLAG_BLANKED	0x00000001
#define CG3_FLAG_RDI		0x00000002

	unsigned long		physbase;
	unsigned long		which_io;
	unsigned long		fbsize;
};

/**
 *      cg3_setcolreg - Optional function. Sets a color register.
 *      @regno: boolean, 0 copy local, 1 get_user() function
 *      @red: frame buffer colormap structure
 *      @green: The green value which can be up to 16 bits wide
 *      @blue:  The blue value which can be up to 16 bits wide.
 *      @transp: If supported the alpha value which can be up to 16 bits wide.
 *      @info: frame buffer info structure
 *
 * The cg3 palette is loaded with 4 color values at each time
 * so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
 * We keep a sw copy of the hw cmap to assist us in this esoteric
 * loading procedure.
 */
static int cg3_setcolreg(unsigned regno,
			 unsigned red, unsigned green, unsigned blue,
			 unsigned transp, struct fb_info *info)
{
	struct cg3_par *par = (struct cg3_par *) info->par;
	struct bt_regs __iomem *bt = &par->regs->cmap;
	unsigned long flags;
	u32 *p32;
	u8 *p8;
	int count;

	if (regno >= 256)
		return 1;

	red >>= 8;
	green >>= 8;
	blue >>= 8;

	spin_lock_irqsave(&par->lock, flags);

	p8 = (u8 *)par->sw_cmap + (regno * 3);
	p8[0] = red;
	p8[1] = green;
	p8[2] = blue;

#define D4M3(x) ((((x)>>2)<<1) + ((x)>>2))      /* (x/4)*3 */
#define D4M4(x) ((x)&~0x3)                      /* (x/4)*4 */

	count = 3;
	p32 = &par->sw_cmap[D4M3(regno)];
	sbus_writel(D4M4(regno), &bt->addr);
	while (count--)
		sbus_writel(*p32++, &bt->color_map);

#undef D4M3
#undef D4M4

	spin_unlock_irqrestore(&par->lock, flags);

	return 0;
}

/**
 *      cg3_blank - Optional function.  Blanks the display.
 *      @blank_mode: the blank mode we want.
 *      @info: frame buffer structure that represents a single frame buffer
 */
static int cg3_blank(int blank, struct fb_info *info)
{
	struct cg3_par *par = (struct cg3_par *) info->par;
	struct cg3_regs __iomem *regs = par->regs;
	unsigned long flags;
	u8 val;

	spin_lock_irqsave(&par->lock, flags);

	switch (blank) {
	case FB_BLANK_UNBLANK: /* Unblanking */
		val = sbus_readb(&regs->control);
		val |= CG3_CR_ENABLE_VIDEO;
		sbus_writeb(val, &regs->control);
		par->flags &= ~CG3_FLAG_BLANKED;
		break;

	case FB_BLANK_NORMAL: /* Normal blanking */
	case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
	case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
	case FB_BLANK_POWERDOWN: /* Poweroff */
		val = sbus_readb(&regs->control);
		val &= ~CG3_CR_ENABLE_VIDEO;
		sbus_writeb(val, &regs->control);
		par->flags |= CG3_FLAG_BLANKED;
		break;
	}

	spin_unlock_irqrestore(&par->lock, flags);

	return 0;
}

static struct sbus_mmap_map cg3_mmap_map[] = {
	{
		.voff	= CG3_MMAP_OFFSET,
		.poff	= CG3_RAM_OFFSET,
		.size	= SBUS_MMAP_FBSIZE(1)
	},
	{ .size = 0 }
};

static int cg3_mmap(struct fb_info *info, struct vm_area_struct *vma)
{
	struct cg3_par *par = (struct cg3_par *)info->par;

	return sbusfb_mmap_helper(cg3_mmap_map,
				  par->physbase, par->fbsize,
				  par->which_io,
				  vma);
}

static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
{
	struct cg3_par *par = (struct cg3_par *) info->par;

	return sbusfb_ioctl_helper(cmd, arg, info,
				   FBTYPE_SUN3COLOR, 8, par->fbsize);
}

/*
 *  Initialisation
 */

static void __devinit cg3_init_fix(struct fb_info *info, int linebytes,
				   struct device_node *dp)
{
	strlcpy(info->fix.id, dp->name, sizeof(info->fix.id));

	info->fix.type = FB_TYPE_PACKED_PIXELS;
	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;

	info->fix.line_length = linebytes;

	info->fix.accel = FB_ACCEL_SUN_CGTHREE;
}

static void __devinit cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
					      struct device_node *dp)
{
	const char *params;
	char *p;
	int ww, hh;

	params = of_get_property(dp, "params", NULL);
	if (params) {
		ww = simple_strtoul(params, &p, 10);
		if (ww && *p == 'x') {
			hh = simple_strtoul(p + 1, &p, 10);
			if (hh && *p == '-') {
				if (var->xres != ww ||
				    var->yres != hh) {
					var->xres = var->xres_virtual = ww;
					var->yres = var->yres_virtual = hh;
				}
			}
		}
	}
}

static u8 cg3regvals_66hz[] __devinitdata = {	/* 1152 x 900, 66 Hz */
	0x14, 0xbb,	0x15, 0x2b,	0x16, 0x04,	0x17, 0x14,
	0x18, 0xae,	0x19, 0x03,	0x1a, 0xa8,	0x1b, 0x24,
	0x1c, 0x01,	0x1d, 0x05,	0x1e, 0xff,	0x1f, 0x01,
	0x10, 0x20,	0
};

static u8 cg3regvals_76hz[] __devinitdata = {	/* 1152 x 900, 76 Hz */
	0x14, 0xb7,	0x15, 0x27,	0x16, 0x03,	0x17, 0x0f,
	0x18, 0xae,	0x19, 0x03,	0x1a, 0xae,	0x1b, 0x2a,
	0x1c, 0x01,	0x1d, 0x09,	0x1e, 0xff,	0x1f, 0x01,
	0x10, 0x24,	0
};

static u8 cg3regvals_rdi[] __devinitdata = {	/* 640 x 480, cgRDI */
	0x14, 0x70,	0x15, 0x20,	0x16, 0x08,	0x17, 0x10,
	0x18, 0x06,	0x19, 0x02,	0x1a, 0x31,	0x1b, 0x51,
	0x1c, 0x06,	0x1d, 0x0c,	0x1e, 0xff,	0x1f, 0x01,
	0x10, 0x22,	0
};

static u8 *cg3_regvals[] __devinitdata = {
	cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
};

static u_char cg3_dacvals[] __devinitdata = {
	4, 0xff,	5, 0x00,	6, 0x70,	7, 0x00,	0
};

static int __devinit cg3_do_default_mode(struct cg3_par *par)
{
	enum cg3_type type;
	u8 *p;

	if (par->flags & CG3_FLAG_RDI)
		type = CG3_RDI;
	else {
		u8 status = sbus_readb(&par->regs->status), mon;
		if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
			mon = status & CG3_SR_RES_MASK;
			if (mon == CG3_SR_1152_900_76_A ||
			    mon == CG3_SR_1152_900_76_B)
				type = CG3_AT_76HZ;
			else
				type = CG3_AT_66HZ;
		} else {
			printk(KERN_ERR "cgthree: can't handle SR %02x\n",
			       status);
			return -EINVAL;
		}
	}

	for (p = cg3_regvals[type]; *p; p += 2) {
		u8 __iomem *regp = &((u8 __iomem *)par->regs)[p[0]];
		sbus_writeb(p[1], regp);
	}
	for (p = cg3_dacvals; *p; p += 2) {
		u8 __iomem *regp;

		regp = (u8 __iomem *)&par->regs->cmap.addr;
		sbus_writeb(p[0], regp);
		regp = (u8 __iomem *)&par->regs->cmap.control;
		sbus_writeb(p[1], regp);
	}
	return 0;
}

static int __devinit cg3_probe(struct of_device *op,
			       const struct of_device_id *match)
{
	struct device_node *dp = op->node;
	struct fb_info *info;
	struct cg3_par *par;
	int linebytes, err;

	info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);

	err = -ENOMEM;
	if (!info)
		goto out_err;
	par = info->par;

	spin_lock_init(&par->lock);

	par->physbase = op->resource[0].start;
	par->which_io = op->resource[0].flags & IORESOURCE_BITS;

	sbusfb_fill_var(&info->var, dp, 8);
	info->var.red.length = 8;
	info->var.green.length = 8;
	info->var.blue.length = 8;
	if (!strcmp(dp->name, "cgRDI"))
		par->flags |= CG3_FLAG_RDI;
	if (par->flags & CG3_FLAG_RDI)
		cg3_rdi_maybe_fixup_var(&info->var, dp);

	linebytes = of_getintprop_default(dp, "linebytes",
					  info->var.xres);
	par->fbsize = PAGE_ALIGN(linebytes * info->var.yres);

	par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
			       sizeof(struct cg3_regs), "cg3 regs");
	if (!par->regs)
		goto out_release_fb;

	info->flags = FBINFO_DEFAULT;
	info->fbops = &cg3_ops;
	info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
				       par->fbsize, "cg3 ram");
	if (!info->screen_base)
		goto out_unmap_regs;

	cg3_blank(FB_BLANK_UNBLANK, info);

	if (!of_find_property(dp, "width", NULL)) {
		err = cg3_do_default_mode(par);
		if (err)
			goto out_unmap_screen;
	}

	if (fb_alloc_cmap(&info->cmap, 256, 0))
		goto out_unmap_screen;

	fb_set_cmap(&info->cmap, info);

	cg3_init_fix(info, linebytes, dp);

	err = register_framebuffer(info);
	if (err < 0)
		goto out_dealloc_cmap;

	dev_set_drvdata(&op->dev, info);

	printk(KERN_INFO "%s: cg3 at %lx:%lx\n",
	       dp->full_name, par->which_io, par->physbase);

	return 0;

out_dealloc_cmap:
	fb_dealloc_cmap(&info->cmap);

out_unmap_screen:
	of_iounmap(&op->resource[0], info->screen_base, par->fbsize);

out_unmap_regs:
	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));

out_release_fb:
	framebuffer_release(info);

out_err:
	return err;
}

static int __devexit cg3_remove(struct of_device *op)
{
	struct fb_info *info = dev_get_drvdata(&op->dev);
	struct cg3_par *par = info->par;

	unregister_framebuffer(info);
	fb_dealloc_cmap(&info->cmap);

	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
	of_iounmap(&op->resource[0], info->screen_base, par->fbsize);

	framebuffer_release(info);

	dev_set_drvdata(&op->dev, NULL);

	return 0;
}

static const struct of_device_id cg3_match[] = {
	{
		.name = "cgthree",
	},
	{
		.name = "cgRDI",
	},
	{},
};
MODULE_DEVICE_TABLE(of, cg3_match);

static struct of_platform_driver cg3_driver = {
	.name		= "cg3",
	.match_table	= cg3_match,
	.probe		= cg3_probe,
	.remove		= __devexit_p(cg3_remove),
};

static int __init cg3_init(void)
{
	if (fb_get_options("cg3fb", NULL))
		return -ENODEV;

	return of_register_driver(&cg3_driver, &of_bus_type);
}

static void __exit cg3_exit(void)
{
	of_unregister_driver(&cg3_driver);
}

module_init(cg3_init);
module_exit(cg3_exit);

MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
MODULE_VERSION("2.0");
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/* cg3.c: CGTHREE frame buffer driver
1da177e4 LT	2	*
50312ce9	3	* Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	* Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
	5	* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
	6	* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
	7	*
	8	* Driver layout based loosely on tgafb.c, see that file for credits.
	9	*/
	10
	11	#include <linux/module.h>
	12	#include <linux/kernel.h>
	13	#include <linux/errno.h>
	14	#include <linux/string.h>
	15	#include <linux/slab.h>
	16	#include <linux/delay.h>
	17	#include <linux/init.h>
	18	#include <linux/fb.h>
	19	#include <linux/mm.h>
6cd5a86b	20	#include <linux/of_device.h>
1da177e4 LT	21
1da177e4 LT	22	#include <asm/io.h>
1da177e4 LT	23	#include <asm/fbio.h>
	24
	25	#include "sbuslib.h"
	26
	27	/*
	28	* Local functions.
	29	*/
	30
	31	static int cg3_setcolreg(unsigned, unsigned, unsigned, unsigned,
	32	unsigned, struct fb_info *);
	33	static int cg3_blank(int, struct fb_info *);
	34
216d526c	35	static int cg3_mmap(struct fb_info , struct vm_area_struct );
67a6680d	36	static int cg3_ioctl(struct fb_info *, unsigned int, unsigned long);
1da177e4 LT	37
	38	/*
	39	* Frame buffer operations
	40	*/
	41
	42	static struct fb_ops cg3_ops = {
	43	.owner = THIS_MODULE,
	44	.fb_setcolreg = cg3_setcolreg,
	45	.fb_blank = cg3_blank,
	46	.fb_fillrect = cfb_fillrect,
	47	.fb_copyarea = cfb_copyarea,
	48	.fb_imageblit = cfb_imageblit,
	49	.fb_mmap = cg3_mmap,
	50	.fb_ioctl = cg3_ioctl,
9ffb83bc CH	51	#ifdef CONFIG_COMPAT
	52	.fb_compat_ioctl = sbusfb_compat_ioctl,
	53	#endif
1da177e4 LT	54	};
	55
	56
	57	/* Control Register Constants */
	58	#define CG3_CR_ENABLE_INTS 0x80
	59	#define CG3_CR_ENABLE_VIDEO 0x40
	60	#define CG3_CR_ENABLE_TIMING 0x20
	61	#define CG3_CR_ENABLE_CURCMP 0x10
	62	#define CG3_CR_XTAL_MASK 0x0c
	63	#define CG3_CR_DIVISOR_MASK 0x03
	64
	65	/* Status Register Constants */
	66	#define CG3_SR_PENDING_INT 0x80
	67	#define CG3_SR_RES_MASK 0x70
	68	#define CG3_SR_1152_900_76_A 0x40
	69	#define CG3_SR_1152_900_76_B 0x60
	70	#define CG3_SR_ID_MASK 0x0f
	71	#define CG3_SR_ID_COLOR 0x01
	72	#define CG3_SR_ID_MONO 0x02
	73	#define CG3_SR_ID_MONO_ECL 0x03
	74
	75	enum cg3_type {
	76	CG3_AT_66HZ = 0,
	77	CG3_AT_76HZ,
	78	CG3_RDI
	79	};
	80
	81	struct bt_regs {
50312ce9 DM	82	u32 addr;
	83	u32 color_map;
	84	u32 control;
	85	u32 cursor;
1da177e4 LT	86	};
	87
	88	struct cg3_regs {
	89	struct bt_regs cmap;
50312ce9 DM	90	u8 control;
	91	u8 status;
	92	u8 cursor_start;
	93	u8 cursor_end;
	94	u8 h_blank_start;
	95	u8 h_blank_end;
	96	u8 h_sync_start;
	97	u8 h_sync_end;
	98	u8 comp_sync_end;
	99	u8 v_blank_start_high;
	100	u8 v_blank_start_low;
	101	u8 v_blank_end;
	102	u8 v_sync_start;
	103	u8 v_sync_end;
	104	u8 xfer_holdoff_start;
	105	u8 xfer_holdoff_end;
1da177e4 LT	106	};
	107
	108	/* Offset of interesting structures in the OBIO space */
	109	#define CG3_REGS_OFFSET 0x400000UL
	110	#define CG3_RAM_OFFSET 0x800000UL
	111
	112	struct cg3_par {
	113	spinlock_t lock;
	114	struct cg3_regs __iomem *regs;
	115	u32 sw_cmap[((256 * 3) + 3) / 4];
	116
	117	u32 flags;
	118	#define CG3_FLAG_BLANKED 0x00000001
	119	#define CG3_FLAG_RDI 0x00000002
	120
	121	unsigned long physbase;
50312ce9	122	unsigned long which_io;
1da177e4	123	unsigned long fbsize;
1da177e4 LT	124	};
	125
	126	/**
	127	* cg3_setcolreg - Optional function. Sets a color register.
	128	* @regno: boolean, 0 copy local, 1 get_user() function
	129	* @red: frame buffer colormap structure
	130	* @green: The green value which can be up to 16 bits wide
	131	* @blue: The blue value which can be up to 16 bits wide.
	132	* @transp: If supported the alpha value which can be up to 16 bits wide.
	133	* @info: frame buffer info structure
	134	*
	135	* The cg3 palette is loaded with 4 color values at each time
	136	* so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on.
	137	* We keep a sw copy of the hw cmap to assist us in this esoteric
	138	* loading procedure.
	139	*/
	140	static int cg3_setcolreg(unsigned regno,
	141	unsigned red, unsigned green, unsigned blue,
	142	unsigned transp, struct fb_info *info)
	143	{
	144	struct cg3_par par = (struct cg3_par ) info->par;
	145	struct bt_regs __iomem *bt = &par->regs->cmap;
	146	unsigned long flags;
	147	u32 *p32;
	148	u8 *p8;
	149	int count;
	150
	151	if (regno >= 256)
	152	return 1;
	153
	154	red >>= 8;
	155	green >>= 8;
	156	blue >>= 8;
	157
	158	spin_lock_irqsave(&par->lock, flags);
	159
	160	p8 = (u8 )par->sw_cmap + (regno 3);
	161	p8[0] = red;
	162	p8[1] = green;
	163	p8[2] = blue;
	164
	165	#define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)3 /
	166	#define D4M4(x) ((x)&~0x3) /* (x/4)4 /
	167
	168	count = 3;
	169	p32 = &par->sw_cmap[D4M3(regno)];
	170	sbus_writel(D4M4(regno), &bt->addr);
	171	while (count--)
	172	sbus_writel(*p32++, &bt->color_map);
	173
	174	#undef D4M3
	175	#undef D4M4
	176
	177	spin_unlock_irqrestore(&par->lock, flags);
	178
	179	return 0;
	180	}
	181
	182	/**
	183	* cg3_blank - Optional function. Blanks the display.
	184	* @blank_mode: the blank mode we want.
	185	* @info: frame buffer structure that represents a single frame buffer
	186	*/
a7177514	187	static int cg3_blank(int blank, struct fb_info *info)
1da177e4 LT	188	{
	189	struct cg3_par par = (struct cg3_par ) info->par;
	190	struct cg3_regs __iomem *regs = par->regs;
	191	unsigned long flags;
	192	u8 val;
	193
	194	spin_lock_irqsave(&par->lock, flags);
	195
	196	switch (blank) {
	197	case FB_BLANK_UNBLANK: /* Unblanking */
	198	val = sbus_readb(&regs->control);
	199	val \|= CG3_CR_ENABLE_VIDEO;
	200	sbus_writeb(val, &regs->control);
	201	par->flags &= ~CG3_FLAG_BLANKED;
	202	break;
	203
	204	case FB_BLANK_NORMAL: /* Normal blanking */
	205	case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
	206	case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
	207	case FB_BLANK_POWERDOWN: /* Poweroff */
	208	val = sbus_readb(&regs->control);
	209	val &= ~CG3_CR_ENABLE_VIDEO;
	210	sbus_writeb(val, &regs->control);
	211	par->flags \|= CG3_FLAG_BLANKED;
	212	break;
	213	}
	214
	215	spin_unlock_irqrestore(&par->lock, flags);
	216
	217	return 0;
	218	}
	219
	220	static struct sbus_mmap_map cg3_mmap_map[] = {
	221	{
	222	.voff = CG3_MMAP_OFFSET,
	223	.poff = CG3_RAM_OFFSET,
	224	.size = SBUS_MMAP_FBSIZE(1)
	225	},
	226	{ .size = 0 }
	227	};
	228
216d526c	229	static int cg3_mmap(struct fb_info info, struct vm_area_struct vma)
1da177e4 LT	230	{
	231	struct cg3_par par = (struct cg3_par )info->par;
	232
	233	return sbusfb_mmap_helper(cg3_mmap_map,
	234	par->physbase, par->fbsize,
50312ce9	235	par->which_io,
1da177e4 LT	236	vma);
	237	}
	238
67a6680d	239	static int cg3_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
1da177e4 LT	240	{
	241	struct cg3_par par = (struct cg3_par ) info->par;
	242
	243	return sbusfb_ioctl_helper(cmd, arg, info,
	244	FBTYPE_SUN3COLOR, 8, par->fbsize);
	245	}
	246
	247	/*
	248	* Initialisation
	249	*/
	250
a7177514 RR	251	static void __devinit cg3_init_fix(struct fb_info *info, int linebytes,
a7177514 RR	252	struct device_node *dp)
1da177e4	253	{
50312ce9	254	strlcpy(info->fix.id, dp->name, sizeof(info->fix.id));
1da177e4 LT	255
	256	info->fix.type = FB_TYPE_PACKED_PIXELS;
	257	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
	258
	259	info->fix.line_length = linebytes;
	260
	261	info->fix.accel = FB_ACCEL_SUN_CGTHREE;
	262	}
	263
a7177514 RR	264	static void __devinit cg3_rdi_maybe_fixup_var(struct fb_var_screeninfo *var,
a7177514 RR	265	struct device_node *dp)
1da177e4	266	{
ccf0dec6	267	const char *params;
1da177e4 LT	268	char *p;
	269	int ww, hh;
	270
50312ce9 DM	271	params = of_get_property(dp, "params", NULL);
	272	if (params) {
	273	ww = simple_strtoul(params, &p, 10);
1da177e4 LT	274	if (ww && *p == 'x') {
	275	hh = simple_strtoul(p + 1, &p, 10);
	276	if (hh && *p == '-') {
	277	if (var->xres != ww \|\|
	278	var->yres != hh) {
	279	var->xres = var->xres_virtual = ww;
	280	var->yres = var->yres_virtual = hh;
	281	}
	282	}
	283	}
	284	}
	285	}
	286
a7177514	287	static u8 cg3regvals_66hz[] __devinitdata = { /* 1152 x 900, 66 Hz */
1da177e4 LT	288	0x14, 0xbb, 0x15, 0x2b, 0x16, 0x04, 0x17, 0x14,
	289	0x18, 0xae, 0x19, 0x03, 0x1a, 0xa8, 0x1b, 0x24,
	290	0x1c, 0x01, 0x1d, 0x05, 0x1e, 0xff, 0x1f, 0x01,
	291	0x10, 0x20, 0
	292	};
	293
a7177514	294	static u8 cg3regvals_76hz[] __devinitdata = { /* 1152 x 900, 76 Hz */
1da177e4 LT	295	0x14, 0xb7, 0x15, 0x27, 0x16, 0x03, 0x17, 0x0f,
	296	0x18, 0xae, 0x19, 0x03, 0x1a, 0xae, 0x1b, 0x2a,
	297	0x1c, 0x01, 0x1d, 0x09, 0x1e, 0xff, 0x1f, 0x01,
	298	0x10, 0x24, 0
	299	};
	300
a7177514	301	static u8 cg3regvals_rdi[] __devinitdata = { /* 640 x 480, cgRDI */
1da177e4 LT	302	0x14, 0x70, 0x15, 0x20, 0x16, 0x08, 0x17, 0x10,
	303	0x18, 0x06, 0x19, 0x02, 0x1a, 0x31, 0x1b, 0x51,
	304	0x1c, 0x06, 0x1d, 0x0c, 0x1e, 0xff, 0x1f, 0x01,
	305	0x10, 0x22, 0
	306	};
	307
a7177514	308	static u8 *cg3_regvals[] __devinitdata = {
1da177e4 LT	309	cg3regvals_66hz, cg3regvals_76hz, cg3regvals_rdi
	310	};
	311
a7177514	312	static u_char cg3_dacvals[] __devinitdata = {
1da177e4 LT	313	4, 0xff, 5, 0x00, 6, 0x70, 7, 0x00, 0
	314	};
	315
6c8f5b90	316	static int __devinit cg3_do_default_mode(struct cg3_par *par)
1da177e4 LT	317	{
	318	enum cg3_type type;
	319	u8 *p;
	320
	321	if (par->flags & CG3_FLAG_RDI)
	322	type = CG3_RDI;
	323	else {
	324	u8 status = sbus_readb(&par->regs->status), mon;
	325	if ((status & CG3_SR_ID_MASK) == CG3_SR_ID_COLOR) {
	326	mon = status & CG3_SR_RES_MASK;
	327	if (mon == CG3_SR_1152_900_76_A \|\|
	328	mon == CG3_SR_1152_900_76_B)
	329	type = CG3_AT_76HZ;
	330	else
	331	type = CG3_AT_66HZ;
	332	} else {
6c8f5b90 DM	333	printk(KERN_ERR "cgthree: can't handle SR %02x\n",
	334	status);
	335	return -EINVAL;
1da177e4 LT	336	}
	337	}
	338
	339	for (p = cg3_regvals[type]; *p; p += 2) {
	340	u8 __iomem regp = &((u8 __iomem )par->regs)[p[0]];
	341	sbus_writeb(p[1], regp);
	342	}
	343	for (p = cg3_dacvals; *p; p += 2) {
50312ce9	344	u8 __iomem *regp;
1da177e4	345
50312ce9	346	regp = (u8 __iomem *)&par->regs->cmap.addr;
1da177e4	347	sbus_writeb(p[0], regp);
50312ce9	348	regp = (u8 __iomem *)&par->regs->cmap.control;
1da177e4 LT	349	sbus_writeb(p[1], regp);
1da177e4 LT	350	}
6c8f5b90	351	return 0;
1da177e4 LT	352	}
1da177e4 LT	353
c7f439b9 DM	354	static int __devinit cg3_probe(struct of_device *op,
c7f439b9 DM	355	const struct of_device_id *match)
1da177e4	356	{
50312ce9	357	struct device_node *dp = op->node;
c7f439b9 DM	358	struct fb_info *info;
c7f439b9 DM	359	struct cg3_par *par;
50312ce9	360	int linebytes, err;
1da177e4	361
c7f439b9	362	info = framebuffer_alloc(sizeof(struct cg3_par), &op->dev);
1da177e4	363
c7f439b9 DM	364	err = -ENOMEM;
	365	if (!info)
	366	goto out_err;
	367	par = info->par;
1da177e4	368
c7f439b9	369	spin_lock_init(&par->lock);
1da177e4	370
c7f439b9 DM	371	par->physbase = op->resource[0].start;
	372	par->which_io = op->resource[0].flags & IORESOURCE_BITS;
	373
6cd5a86b	374	sbusfb_fill_var(&info->var, dp, 8);
c7f439b9 DM	375	info->var.red.length = 8;
	376	info->var.green.length = 8;
	377	info->var.blue.length = 8;
50312ce9	378	if (!strcmp(dp->name, "cgRDI"))
c7f439b9 DM	379	par->flags \|= CG3_FLAG_RDI;
	380	if (par->flags & CG3_FLAG_RDI)
	381	cg3_rdi_maybe_fixup_var(&info->var, dp);
1da177e4	382
50312ce9	383	linebytes = of_getintprop_default(dp, "linebytes",
c7f439b9 DM	384	info->var.xres);
c7f439b9 DM	385	par->fbsize = PAGE_ALIGN(linebytes * info->var.yres);
1da177e4	386
c7f439b9 DM	387	par->regs = of_ioremap(&op->resource[0], CG3_REGS_OFFSET,
	388	sizeof(struct cg3_regs), "cg3 regs");
	389	if (!par->regs)
	390	goto out_release_fb;
1da177e4	391
c7f439b9 DM	392	info->flags = FBINFO_DEFAULT;
	393	info->fbops = &cg3_ops;
	394	info->screen_base = of_ioremap(&op->resource[0], CG3_RAM_OFFSET,
	395	par->fbsize, "cg3 ram");
	396	if (!info->screen_base)
	397	goto out_unmap_regs;
1da177e4	398
59f7137a	399	cg3_blank(FB_BLANK_UNBLANK, info);
1da177e4	400
6c8f5b90 DM	401	if (!of_find_property(dp, "width", NULL)) {
	402	err = cg3_do_default_mode(par);
	403	if (err)
	404	goto out_unmap_screen;
	405	}
c7f439b9 DM	406
	407	if (fb_alloc_cmap(&info->cmap, 256, 0))
	408	goto out_unmap_screen;
	409
	410	fb_set_cmap(&info->cmap, info);
1da177e4	411
c7f439b9 DM	412	cg3_init_fix(info, linebytes, dp);
	413
	414	err = register_framebuffer(info);
	415	if (err < 0)
	416	goto out_dealloc_cmap;
	417
	418	dev_set_drvdata(&op->dev, info);
50312ce9	419
194f1a68	420	printk(KERN_INFO "%s: cg3 at %lx:%lx\n",
c7f439b9	421	dp->full_name, par->which_io, par->physbase);
1da177e4	422
50312ce9	423	return 0;
1da177e4	424
c7f439b9 DM	425	out_dealloc_cmap:
	426	fb_dealloc_cmap(&info->cmap);
	427
	428	out_unmap_screen:
	429	of_iounmap(&op->resource[0], info->screen_base, par->fbsize);
	430
	431	out_unmap_regs:
	432	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
	433
	434	out_release_fb:
	435	framebuffer_release(info);
1da177e4	436
c7f439b9 DM	437	out_err:
c7f439b9 DM	438	return err;
50312ce9	439	}
1da177e4	440
e3a411a3	441	static int __devexit cg3_remove(struct of_device *op)
50312ce9	442	{
c7f439b9 DM	443	struct fb_info *info = dev_get_drvdata(&op->dev);
c7f439b9 DM	444	struct cg3_par *par = info->par;
50312ce9	445
c7f439b9 DM	446	unregister_framebuffer(info);
c7f439b9 DM	447	fb_dealloc_cmap(&info->cmap);
50312ce9	448
c7f439b9 DM	449	of_iounmap(&op->resource[0], par->regs, sizeof(struct cg3_regs));
c7f439b9 DM	450	of_iounmap(&op->resource[0], info->screen_base, par->fbsize);
50312ce9	451
c7f439b9	452	framebuffer_release(info);
50312ce9	453
e3a411a3	454	dev_set_drvdata(&op->dev, NULL);
1da177e4 LT	455
	456	return 0;
	457	}
	458
fd098316	459	static const struct of_device_id cg3_match[] = {
50312ce9 DM	460	{
	461	.name = "cgthree",
	462	},
	463	{
	464	.name = "cgRDI",
	465	},
	466	{},
	467	};
	468	MODULE_DEVICE_TABLE(of, cg3_match);
1da177e4	469
50312ce9 DM	470	static struct of_platform_driver cg3_driver = {
	471	.name = "cg3",
	472	.match_table = cg3_match,
	473	.probe = cg3_probe,
	474	.remove = __devexit_p(cg3_remove),
	475	};
1da177e4	476
50312ce9 DM	477	static int __init cg3_init(void)
	478	{
	479	if (fb_get_options("cg3fb", NULL))
	480	return -ENODEV;
	481
	482	return of_register_driver(&cg3_driver, &of_bus_type);
1da177e4 LT	483	}
1da177e4 LT	484
50312ce9	485	static void __exit cg3_exit(void)
1da177e4	486	{
50312ce9	487	of_unregister_driver(&cg3_driver);
1da177e4 LT	488	}
	489
	490	module_init(cg3_init);
1da177e4	491	module_exit(cg3_exit);
1da177e4 LT	492
1da177e4 LT	493	MODULE_DESCRIPTION("framebuffer driver for CGthree chipsets");
50312ce9 DM	494	MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
50312ce9 DM	495	MODULE_VERSION("2.0");
1da177e4	496	MODULE_LICENSE("GPL");