Commit | Line | Data |
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9cfe4a93 MH |
1 | /* |
2 | * Blackfin LCD Framebuffer driver SHARP LQ035Q1DH02 | |
3 | * | |
4 | * Copyright 2008-2009 Analog Devices Inc. | |
5 | * Licensed under the GPL-2 or later. | |
6 | */ | |
7 | ||
8 | #define DRIVER_NAME "bfin-lq035q1" | |
9 | #define pr_fmt(fmt) DRIVER_NAME ": " fmt | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/string.h> | |
15 | #include <linux/fb.h> | |
bc856a62 | 16 | #include <linux/gpio.h> |
5a0e3ad6 | 17 | #include <linux/slab.h> |
9cfe4a93 MH |
18 | #include <linux/init.h> |
19 | #include <linux/types.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/backlight.h> | |
23 | #include <linux/lcd.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/spi/spi.h> | |
9cfe4a93 MH |
27 | |
28 | #include <asm/blackfin.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/dma.h> | |
31 | #include <asm/portmux.h> | |
32 | #include <asm/gptimers.h> | |
33 | ||
34 | #include <asm/bfin-lq035q1.h> | |
35 | ||
36 | #if defined(BF533_FAMILY) || defined(BF538_FAMILY) | |
37 | #define TIMER_HSYNC_id TIMER1_id | |
38 | #define TIMER_HSYNCbit TIMER1bit | |
39 | #define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 | |
40 | #define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 | |
41 | #define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 | |
42 | ||
43 | #define TIMER_VSYNC_id TIMER2_id | |
44 | #define TIMER_VSYNCbit TIMER2bit | |
45 | #define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN2 | |
46 | #define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL2 | |
47 | #define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF2 | |
48 | #else | |
49 | #define TIMER_HSYNC_id TIMER0_id | |
50 | #define TIMER_HSYNCbit TIMER0bit | |
51 | #define TIMER_HSYNC_STATUS_TRUN TIMER_STATUS_TRUN0 | |
52 | #define TIMER_HSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL0 | |
53 | #define TIMER_HSYNC_STATUS_TOVF TIMER_STATUS_TOVF0 | |
54 | ||
55 | #define TIMER_VSYNC_id TIMER1_id | |
56 | #define TIMER_VSYNCbit TIMER1bit | |
57 | #define TIMER_VSYNC_STATUS_TRUN TIMER_STATUS_TRUN1 | |
58 | #define TIMER_VSYNC_STATUS_TIMIL TIMER_STATUS_TIMIL1 | |
59 | #define TIMER_VSYNC_STATUS_TOVF TIMER_STATUS_TOVF1 | |
60 | #endif | |
61 | ||
62 | #define LCD_X_RES 320 /* Horizontal Resolution */ | |
63 | #define LCD_Y_RES 240 /* Vertical Resolution */ | |
64 | #define DMA_BUS_SIZE 16 | |
fbd65e0e | 65 | #define U_LINE 4 /* Blanking Lines */ |
9cfe4a93 | 66 | |
9cfe4a93 MH |
67 | |
68 | /* Interface 16/18-bit TFT over an 8-bit wide PPI using a small Programmable Logic Device (CPLD) | |
69 | * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 | |
70 | */ | |
71 | ||
9cfe4a93 MH |
72 | |
73 | #define BFIN_LCD_NBR_PALETTE_ENTRIES 256 | |
74 | ||
75 | #define PPI_TX_MODE 0x2 | |
76 | #define PPI_XFER_TYPE_11 0xC | |
77 | #define PPI_PORT_CFG_01 0x10 | |
78 | #define PPI_POLS_1 0x8000 | |
79 | ||
9cfe4a93 MH |
80 | #define LQ035_INDEX 0x74 |
81 | #define LQ035_DATA 0x76 | |
82 | ||
83 | #define LQ035_DRIVER_OUTPUT_CTL 0x1 | |
84 | #define LQ035_SHUT_CTL 0x11 | |
85 | ||
86 | #define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV) | |
87 | #define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK) | |
88 | ||
89 | #define LQ035_SHUT (1 << 0) /* Shutdown */ | |
90 | #define LQ035_ON (0 << 0) /* Shutdown */ | |
91 | ||
92 | struct bfin_lq035q1fb_info { | |
93 | struct fb_info *fb; | |
94 | struct device *dev; | |
95 | struct spi_driver spidrv; | |
96 | struct bfin_lq035q1fb_disp_info *disp_info; | |
97 | unsigned char *fb_buffer; /* RGB Buffer */ | |
98 | dma_addr_t dma_handle; | |
99 | int lq035_open_cnt; | |
100 | int irq; | |
101 | spinlock_t lock; /* lock */ | |
102 | u32 pseudo_pal[16]; | |
fbd65e0e MH |
103 | |
104 | u32 lcd_bpp; | |
105 | u32 h_actpix; | |
106 | u32 h_period; | |
107 | u32 h_pulse; | |
108 | u32 h_start; | |
109 | u32 v_lines; | |
110 | u32 v_pulse; | |
111 | u32 v_period; | |
9cfe4a93 MH |
112 | }; |
113 | ||
114 | static int nocursor; | |
115 | module_param(nocursor, int, 0644); | |
116 | MODULE_PARM_DESC(nocursor, "cursor enable/disable"); | |
117 | ||
118 | struct spi_control { | |
119 | unsigned short mode; | |
120 | }; | |
121 | ||
122 | static int lq035q1_control(struct spi_device *spi, unsigned char reg, unsigned short value) | |
123 | { | |
124 | int ret; | |
125 | u8 regs[3] = { LQ035_INDEX, 0, 0 }; | |
126 | u8 dat[3] = { LQ035_DATA, 0, 0 }; | |
127 | ||
128 | if (!spi) | |
129 | return -ENODEV; | |
130 | ||
131 | regs[2] = reg; | |
132 | dat[1] = value >> 8; | |
133 | dat[2] = value & 0xFF; | |
134 | ||
135 | ret = spi_write(spi, regs, ARRAY_SIZE(regs)); | |
136 | ret |= spi_write(spi, dat, ARRAY_SIZE(dat)); | |
137 | return ret; | |
138 | } | |
139 | ||
48c68c4f | 140 | static int lq035q1_spidev_probe(struct spi_device *spi) |
9cfe4a93 MH |
141 | { |
142 | int ret; | |
143 | struct spi_control *ctl; | |
144 | struct bfin_lq035q1fb_info *info = container_of(spi->dev.driver, | |
145 | struct bfin_lq035q1fb_info, | |
146 | spidrv.driver); | |
147 | ||
148 | ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); | |
149 | ||
150 | if (!ctl) | |
151 | return -ENOMEM; | |
152 | ||
153 | ctl->mode = (info->disp_info->mode & | |
154 | LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT; | |
155 | ||
156 | ret = lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); | |
157 | ret |= lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); | |
a8c908d3 JL |
158 | if (ret) { |
159 | kfree(ctl); | |
9cfe4a93 | 160 | return ret; |
a8c908d3 | 161 | } |
9cfe4a93 MH |
162 | |
163 | spi_set_drvdata(spi, ctl); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static int lq035q1_spidev_remove(struct spi_device *spi) | |
169 | { | |
170 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); | |
171 | } | |
172 | ||
173 | #ifdef CONFIG_PM | |
174 | static int lq035q1_spidev_suspend(struct spi_device *spi, pm_message_t state) | |
175 | { | |
176 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); | |
177 | } | |
178 | ||
179 | static int lq035q1_spidev_resume(struct spi_device *spi) | |
180 | { | |
181 | int ret; | |
182 | struct spi_control *ctl = spi_get_drvdata(spi); | |
183 | ||
184 | ret = lq035q1_control(spi, LQ035_DRIVER_OUTPUT_CTL, ctl->mode); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | return lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_ON); | |
189 | } | |
190 | #else | |
191 | # define lq035q1_spidev_suspend NULL | |
192 | # define lq035q1_spidev_resume NULL | |
193 | #endif | |
194 | ||
195 | /* Power down all displays on reboot, poweroff or halt */ | |
196 | static void lq035q1_spidev_shutdown(struct spi_device *spi) | |
197 | { | |
198 | lq035q1_control(spi, LQ035_SHUT_CTL, LQ035_SHUT); | |
199 | } | |
200 | ||
201 | static int lq035q1_backlight(struct bfin_lq035q1fb_info *info, unsigned arg) | |
202 | { | |
203 | if (info->disp_info->use_bl) | |
204 | gpio_set_value(info->disp_info->gpio_bl, arg); | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
fbd65e0e MH |
209 | static int bfin_lq035q1_calc_timing(struct bfin_lq035q1fb_info *fbi) |
210 | { | |
211 | unsigned long clocks_per_pix, cpld_pipeline_delay_cor; | |
212 | ||
213 | /* | |
214 | * Interface 16/18-bit TFT over an 8-bit wide PPI using a small | |
215 | * Programmable Logic Device (CPLD) | |
216 | * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165 | |
217 | */ | |
218 | ||
219 | switch (fbi->disp_info->ppi_mode) { | |
220 | case USE_RGB565_16_BIT_PPI: | |
221 | fbi->lcd_bpp = 16; | |
222 | clocks_per_pix = 1; | |
223 | cpld_pipeline_delay_cor = 0; | |
224 | break; | |
225 | case USE_RGB565_8_BIT_PPI: | |
226 | fbi->lcd_bpp = 16; | |
227 | clocks_per_pix = 2; | |
228 | cpld_pipeline_delay_cor = 3; | |
229 | break; | |
230 | case USE_RGB888_8_BIT_PPI: | |
231 | fbi->lcd_bpp = 24; | |
232 | clocks_per_pix = 3; | |
233 | cpld_pipeline_delay_cor = 5; | |
234 | break; | |
235 | default: | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | /* | |
240 | * HS and VS timing parameters (all in number of PPI clk ticks) | |
241 | */ | |
242 | ||
243 | fbi->h_actpix = (LCD_X_RES * clocks_per_pix); /* active horizontal pixel */ | |
244 | fbi->h_period = (336 * clocks_per_pix); /* HS period */ | |
245 | fbi->h_pulse = (2 * clocks_per_pix); /* HS pulse width */ | |
246 | fbi->h_start = (7 * clocks_per_pix + cpld_pipeline_delay_cor); /* first valid pixel */ | |
247 | ||
248 | fbi->v_lines = (LCD_Y_RES + U_LINE); /* total vertical lines */ | |
249 | fbi->v_pulse = (2 * clocks_per_pix); /* VS pulse width (1-5 H_PERIODs) */ | |
250 | fbi->v_period = (fbi->h_period * fbi->v_lines); /* VS period */ | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
9cfe4a93 MH |
255 | static void bfin_lq035q1_config_ppi(struct bfin_lq035q1fb_info *fbi) |
256 | { | |
fbd65e0e MH |
257 | unsigned ppi_pmode; |
258 | ||
259 | if (fbi->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI) | |
260 | ppi_pmode = DLEN_16; | |
261 | else | |
262 | ppi_pmode = (DLEN_8 | PACK_EN); | |
263 | ||
264 | bfin_write_PPI_DELAY(fbi->h_start); | |
265 | bfin_write_PPI_COUNT(fbi->h_actpix - 1); | |
266 | bfin_write_PPI_FRAME(fbi->v_lines); | |
9cfe4a93 MH |
267 | |
268 | bfin_write_PPI_CONTROL(PPI_TX_MODE | /* output mode , PORT_DIR */ | |
269 | PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ | |
270 | PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ | |
fbd65e0e | 271 | ppi_pmode | /* 8/16 bit data length / PACK_EN? */ |
9cfe4a93 MH |
272 | PPI_POLS_1); /* faling edge syncs POLS */ |
273 | } | |
274 | ||
275 | static inline void bfin_lq035q1_disable_ppi(void) | |
276 | { | |
277 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN); | |
278 | } | |
279 | ||
280 | static inline void bfin_lq035q1_enable_ppi(void) | |
281 | { | |
282 | bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN); | |
283 | } | |
284 | ||
285 | static void bfin_lq035q1_start_timers(void) | |
286 | { | |
287 | enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit); | |
288 | } | |
289 | ||
290 | static void bfin_lq035q1_stop_timers(void) | |
291 | { | |
292 | disable_gptimers(TIMER_HSYNCbit | TIMER_VSYNCbit); | |
293 | ||
294 | set_gptimer_status(0, TIMER_HSYNC_STATUS_TRUN | TIMER_VSYNC_STATUS_TRUN | | |
295 | TIMER_HSYNC_STATUS_TIMIL | TIMER_VSYNC_STATUS_TIMIL | | |
296 | TIMER_HSYNC_STATUS_TOVF | TIMER_VSYNC_STATUS_TOVF); | |
297 | ||
298 | } | |
299 | ||
fbd65e0e | 300 | static void bfin_lq035q1_init_timers(struct bfin_lq035q1fb_info *fbi) |
9cfe4a93 MH |
301 | { |
302 | ||
303 | bfin_lq035q1_stop_timers(); | |
304 | ||
fbd65e0e MH |
305 | set_gptimer_period(TIMER_HSYNC_id, fbi->h_period); |
306 | set_gptimer_pwidth(TIMER_HSYNC_id, fbi->h_pulse); | |
9cfe4a93 MH |
307 | set_gptimer_config(TIMER_HSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | |
308 | TIMER_TIN_SEL | TIMER_CLK_SEL| | |
309 | TIMER_EMU_RUN); | |
310 | ||
fbd65e0e MH |
311 | set_gptimer_period(TIMER_VSYNC_id, fbi->v_period); |
312 | set_gptimer_pwidth(TIMER_VSYNC_id, fbi->v_pulse); | |
9cfe4a93 MH |
313 | set_gptimer_config(TIMER_VSYNC_id, TIMER_MODE_PWM | TIMER_PERIOD_CNT | |
314 | TIMER_TIN_SEL | TIMER_CLK_SEL | | |
315 | TIMER_EMU_RUN); | |
316 | ||
317 | } | |
318 | ||
319 | static void bfin_lq035q1_config_dma(struct bfin_lq035q1fb_info *fbi) | |
320 | { | |
321 | ||
fbd65e0e | 322 | |
9cfe4a93 MH |
323 | set_dma_config(CH_PPI, |
324 | set_bfin_dma_config(DIR_READ, DMA_FLOW_AUTO, | |
325 | INTR_DISABLE, DIMENSION_2D, | |
326 | DATA_SIZE_16, | |
327 | DMA_NOSYNC_KEEP_DMA_BUF)); | |
fbd65e0e | 328 | set_dma_x_count(CH_PPI, (LCD_X_RES * fbi->lcd_bpp) / DMA_BUS_SIZE); |
9cfe4a93 | 329 | set_dma_x_modify(CH_PPI, DMA_BUS_SIZE / 8); |
fbd65e0e | 330 | set_dma_y_count(CH_PPI, fbi->v_lines); |
9cfe4a93 MH |
331 | |
332 | set_dma_y_modify(CH_PPI, DMA_BUS_SIZE / 8); | |
333 | set_dma_start_addr(CH_PPI, (unsigned long)fbi->fb_buffer); | |
334 | ||
335 | } | |
336 | ||
9cfe4a93 MH |
337 | static const u16 ppi0_req_16[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, |
338 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, | |
339 | P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, | |
340 | P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, | |
341 | P_PPI0_D9, P_PPI0_D10, P_PPI0_D11, | |
342 | P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, | |
343 | P_PPI0_D15, 0}; | |
fbd65e0e MH |
344 | |
345 | static const u16 ppi0_req_8[] = {P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, | |
9cfe4a93 MH |
346 | P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, |
347 | P_PPI0_D3, P_PPI0_D4, P_PPI0_D5, | |
348 | P_PPI0_D6, P_PPI0_D7, 0}; | |
9cfe4a93 | 349 | |
fbd65e0e | 350 | static inline void bfin_lq035q1_free_ports(unsigned ppi16) |
9cfe4a93 | 351 | { |
fbd65e0e MH |
352 | if (ppi16) |
353 | peripheral_free_list(ppi0_req_16); | |
354 | else | |
355 | peripheral_free_list(ppi0_req_8); | |
356 | ||
9cfe4a93 MH |
357 | if (ANOMALY_05000400) |
358 | gpio_free(P_IDENT(P_PPI0_FS3)); | |
359 | } | |
360 | ||
48c68c4f GKH |
361 | static int bfin_lq035q1_request_ports(struct platform_device *pdev, |
362 | unsigned ppi16) | |
9cfe4a93 | 363 | { |
fbd65e0e | 364 | int ret; |
9cfe4a93 MH |
365 | /* ANOMALY_05000400 - PPI Does Not Start Properly In Specific Mode: |
366 | * Drive PPI_FS3 Low | |
367 | */ | |
368 | if (ANOMALY_05000400) { | |
f8bd4934 JH |
369 | int ret = gpio_request_one(P_IDENT(P_PPI0_FS3), |
370 | GPIOF_OUT_INIT_LOW, "PPI_FS3"); | |
9cfe4a93 MH |
371 | if (ret) |
372 | return ret; | |
9cfe4a93 MH |
373 | } |
374 | ||
fbd65e0e MH |
375 | if (ppi16) |
376 | ret = peripheral_request_list(ppi0_req_16, DRIVER_NAME); | |
377 | else | |
378 | ret = peripheral_request_list(ppi0_req_8, DRIVER_NAME); | |
379 | ||
380 | if (ret) { | |
9cfe4a93 MH |
381 | dev_err(&pdev->dev, "requesting peripherals failed\n"); |
382 | return -EFAULT; | |
383 | } | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
388 | static int bfin_lq035q1_fb_open(struct fb_info *info, int user) | |
389 | { | |
390 | struct bfin_lq035q1fb_info *fbi = info->par; | |
391 | ||
392 | spin_lock(&fbi->lock); | |
393 | fbi->lq035_open_cnt++; | |
394 | ||
395 | if (fbi->lq035_open_cnt <= 1) { | |
396 | ||
397 | bfin_lq035q1_disable_ppi(); | |
398 | SSYNC(); | |
399 | ||
400 | bfin_lq035q1_config_dma(fbi); | |
401 | bfin_lq035q1_config_ppi(fbi); | |
fbd65e0e | 402 | bfin_lq035q1_init_timers(fbi); |
9cfe4a93 MH |
403 | |
404 | /* start dma */ | |
405 | enable_dma(CH_PPI); | |
406 | bfin_lq035q1_enable_ppi(); | |
407 | bfin_lq035q1_start_timers(); | |
408 | lq035q1_backlight(fbi, 1); | |
409 | } | |
410 | ||
411 | spin_unlock(&fbi->lock); | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | static int bfin_lq035q1_fb_release(struct fb_info *info, int user) | |
417 | { | |
418 | struct bfin_lq035q1fb_info *fbi = info->par; | |
419 | ||
420 | spin_lock(&fbi->lock); | |
421 | ||
422 | fbi->lq035_open_cnt--; | |
423 | ||
424 | if (fbi->lq035_open_cnt <= 0) { | |
425 | lq035q1_backlight(fbi, 0); | |
426 | bfin_lq035q1_disable_ppi(); | |
427 | SSYNC(); | |
428 | disable_dma(CH_PPI); | |
429 | bfin_lq035q1_stop_timers(); | |
430 | } | |
431 | ||
432 | spin_unlock(&fbi->lock); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | static int bfin_lq035q1_fb_check_var(struct fb_var_screeninfo *var, | |
438 | struct fb_info *info) | |
439 | { | |
fbd65e0e MH |
440 | struct bfin_lq035q1fb_info *fbi = info->par; |
441 | ||
442 | if (var->bits_per_pixel == fbi->lcd_bpp) { | |
9cfe4a93 MH |
443 | var->red.offset = info->var.red.offset; |
444 | var->green.offset = info->var.green.offset; | |
445 | var->blue.offset = info->var.blue.offset; | |
446 | var->red.length = info->var.red.length; | |
447 | var->green.length = info->var.green.length; | |
448 | var->blue.length = info->var.blue.length; | |
449 | var->transp.offset = 0; | |
450 | var->transp.length = 0; | |
451 | var->transp.msb_right = 0; | |
452 | var->red.msb_right = 0; | |
453 | var->green.msb_right = 0; | |
454 | var->blue.msb_right = 0; | |
fbd65e0e | 455 | } else { |
9cfe4a93 MH |
456 | pr_debug("%s: depth not supported: %u BPP\n", __func__, |
457 | var->bits_per_pixel); | |
458 | return -EINVAL; | |
459 | } | |
460 | ||
461 | if (info->var.xres != var->xres || info->var.yres != var->yres || | |
462 | info->var.xres_virtual != var->xres_virtual || | |
463 | info->var.yres_virtual != var->yres_virtual) { | |
464 | pr_debug("%s: Resolution not supported: X%u x Y%u \n", | |
465 | __func__, var->xres, var->yres); | |
466 | return -EINVAL; | |
467 | } | |
468 | ||
469 | /* | |
470 | * Memory limit | |
471 | */ | |
472 | ||
473 | if ((info->fix.line_length * var->yres_virtual) > info->fix.smem_len) { | |
474 | pr_debug("%s: Memory Limit requested yres_virtual = %u\n", | |
475 | __func__, var->yres_virtual); | |
476 | return -ENOMEM; | |
477 | } | |
478 | ||
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | int bfin_lq035q1_fb_cursor(struct fb_info *info, struct fb_cursor *cursor) | |
484 | { | |
485 | if (nocursor) | |
486 | return 0; | |
487 | else | |
488 | return -EINVAL; /* just to force soft_cursor() call */ | |
489 | } | |
490 | ||
491 | static int bfin_lq035q1_fb_setcolreg(u_int regno, u_int red, u_int green, | |
492 | u_int blue, u_int transp, | |
493 | struct fb_info *info) | |
494 | { | |
495 | if (regno >= BFIN_LCD_NBR_PALETTE_ENTRIES) | |
496 | return -EINVAL; | |
497 | ||
498 | if (info->var.grayscale) { | |
499 | /* grayscale = 0.30*R + 0.59*G + 0.11*B */ | |
500 | red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; | |
501 | } | |
502 | ||
503 | if (info->fix.visual == FB_VISUAL_TRUECOLOR) { | |
504 | ||
505 | u32 value; | |
506 | /* Place color in the pseudopalette */ | |
507 | if (regno > 16) | |
508 | return -EINVAL; | |
509 | ||
510 | red >>= (16 - info->var.red.length); | |
511 | green >>= (16 - info->var.green.length); | |
512 | blue >>= (16 - info->var.blue.length); | |
513 | ||
514 | value = (red << info->var.red.offset) | | |
515 | (green << info->var.green.offset) | | |
516 | (blue << info->var.blue.offset); | |
517 | value &= 0xFFFFFF; | |
518 | ||
519 | ((u32 *) (info->pseudo_palette))[regno] = value; | |
520 | ||
521 | } | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
526 | static struct fb_ops bfin_lq035q1_fb_ops = { | |
527 | .owner = THIS_MODULE, | |
528 | .fb_open = bfin_lq035q1_fb_open, | |
529 | .fb_release = bfin_lq035q1_fb_release, | |
530 | .fb_check_var = bfin_lq035q1_fb_check_var, | |
531 | .fb_fillrect = cfb_fillrect, | |
532 | .fb_copyarea = cfb_copyarea, | |
533 | .fb_imageblit = cfb_imageblit, | |
534 | .fb_cursor = bfin_lq035q1_fb_cursor, | |
535 | .fb_setcolreg = bfin_lq035q1_fb_setcolreg, | |
536 | }; | |
537 | ||
538 | static irqreturn_t bfin_lq035q1_irq_error(int irq, void *dev_id) | |
539 | { | |
540 | /*struct bfin_lq035q1fb_info *info = (struct bfin_lq035q1fb_info *)dev_id;*/ | |
541 | ||
542 | u16 status = bfin_read_PPI_STATUS(); | |
543 | bfin_write_PPI_STATUS(-1); | |
544 | ||
545 | if (status) { | |
546 | bfin_lq035q1_disable_ppi(); | |
547 | disable_dma(CH_PPI); | |
548 | ||
549 | /* start dma */ | |
550 | enable_dma(CH_PPI); | |
551 | bfin_lq035q1_enable_ppi(); | |
552 | bfin_write_PPI_STATUS(-1); | |
553 | } | |
554 | ||
555 | return IRQ_HANDLED; | |
556 | } | |
557 | ||
48c68c4f | 558 | static int bfin_lq035q1_probe(struct platform_device *pdev) |
9cfe4a93 MH |
559 | { |
560 | struct bfin_lq035q1fb_info *info; | |
561 | struct fb_info *fbinfo; | |
fbd65e0e | 562 | u32 active_video_mem_offset; |
9cfe4a93 MH |
563 | int ret; |
564 | ||
565 | ret = request_dma(CH_PPI, DRIVER_NAME"_CH_PPI"); | |
566 | if (ret < 0) { | |
567 | dev_err(&pdev->dev, "PPI DMA unavailable\n"); | |
568 | goto out1; | |
569 | } | |
570 | ||
571 | fbinfo = framebuffer_alloc(sizeof(*info), &pdev->dev); | |
572 | if (!fbinfo) { | |
573 | ret = -ENOMEM; | |
574 | goto out2; | |
575 | } | |
576 | ||
577 | info = fbinfo->par; | |
578 | info->fb = fbinfo; | |
579 | info->dev = &pdev->dev; | |
232703fb | 580 | spin_lock_init(&info->lock); |
9cfe4a93 MH |
581 | |
582 | info->disp_info = pdev->dev.platform_data; | |
583 | ||
584 | platform_set_drvdata(pdev, fbinfo); | |
585 | ||
fbd65e0e MH |
586 | ret = bfin_lq035q1_calc_timing(info); |
587 | if (ret < 0) { | |
588 | dev_err(&pdev->dev, "Failed PPI Mode\n"); | |
589 | goto out3; | |
590 | } | |
591 | ||
9cfe4a93 MH |
592 | strcpy(fbinfo->fix.id, DRIVER_NAME); |
593 | ||
594 | fbinfo->fix.type = FB_TYPE_PACKED_PIXELS; | |
595 | fbinfo->fix.type_aux = 0; | |
596 | fbinfo->fix.xpanstep = 0; | |
597 | fbinfo->fix.ypanstep = 0; | |
598 | fbinfo->fix.ywrapstep = 0; | |
599 | fbinfo->fix.accel = FB_ACCEL_NONE; | |
600 | fbinfo->fix.visual = FB_VISUAL_TRUECOLOR; | |
601 | ||
602 | fbinfo->var.nonstd = 0; | |
603 | fbinfo->var.activate = FB_ACTIVATE_NOW; | |
604 | fbinfo->var.height = -1; | |
605 | fbinfo->var.width = -1; | |
606 | fbinfo->var.accel_flags = 0; | |
607 | fbinfo->var.vmode = FB_VMODE_NONINTERLACED; | |
608 | ||
609 | fbinfo->var.xres = LCD_X_RES; | |
610 | fbinfo->var.xres_virtual = LCD_X_RES; | |
611 | fbinfo->var.yres = LCD_Y_RES; | |
612 | fbinfo->var.yres_virtual = LCD_Y_RES; | |
fbd65e0e | 613 | fbinfo->var.bits_per_pixel = info->lcd_bpp; |
9cfe4a93 MH |
614 | |
615 | if (info->disp_info->mode & LQ035_BGR) { | |
fbd65e0e MH |
616 | if (info->lcd_bpp == 24) { |
617 | fbinfo->var.red.offset = 0; | |
618 | fbinfo->var.green.offset = 8; | |
619 | fbinfo->var.blue.offset = 16; | |
620 | } else { | |
621 | fbinfo->var.red.offset = 0; | |
622 | fbinfo->var.green.offset = 5; | |
623 | fbinfo->var.blue.offset = 11; | |
624 | } | |
9cfe4a93 | 625 | } else { |
fbd65e0e MH |
626 | if (info->lcd_bpp == 24) { |
627 | fbinfo->var.red.offset = 16; | |
628 | fbinfo->var.green.offset = 8; | |
629 | fbinfo->var.blue.offset = 0; | |
630 | } else { | |
631 | fbinfo->var.red.offset = 11; | |
632 | fbinfo->var.green.offset = 5; | |
633 | fbinfo->var.blue.offset = 0; | |
634 | } | |
9cfe4a93 MH |
635 | } |
636 | ||
637 | fbinfo->var.transp.offset = 0; | |
638 | ||
fbd65e0e MH |
639 | if (info->lcd_bpp == 24) { |
640 | fbinfo->var.red.length = 8; | |
641 | fbinfo->var.green.length = 8; | |
642 | fbinfo->var.blue.length = 8; | |
643 | } else { | |
644 | fbinfo->var.red.length = 5; | |
645 | fbinfo->var.green.length = 6; | |
646 | fbinfo->var.blue.length = 5; | |
647 | } | |
9cfe4a93 MH |
648 | |
649 | fbinfo->var.transp.length = 0; | |
650 | ||
fbd65e0e MH |
651 | active_video_mem_offset = ((U_LINE / 2) * LCD_X_RES * (info->lcd_bpp / 8)); |
652 | ||
653 | fbinfo->fix.smem_len = LCD_X_RES * LCD_Y_RES * info->lcd_bpp / 8 | |
654 | + active_video_mem_offset; | |
9cfe4a93 MH |
655 | |
656 | fbinfo->fix.line_length = fbinfo->var.xres_virtual * | |
657 | fbinfo->var.bits_per_pixel / 8; | |
658 | ||
659 | ||
660 | fbinfo->fbops = &bfin_lq035q1_fb_ops; | |
661 | fbinfo->flags = FBINFO_FLAG_DEFAULT; | |
662 | ||
663 | info->fb_buffer = | |
664 | dma_alloc_coherent(NULL, fbinfo->fix.smem_len, &info->dma_handle, | |
665 | GFP_KERNEL); | |
666 | ||
667 | if (NULL == info->fb_buffer) { | |
668 | dev_err(&pdev->dev, "couldn't allocate dma buffer\n"); | |
669 | ret = -ENOMEM; | |
670 | goto out3; | |
671 | } | |
672 | ||
fbd65e0e MH |
673 | fbinfo->screen_base = (void *)info->fb_buffer + active_video_mem_offset; |
674 | fbinfo->fix.smem_start = (int)info->fb_buffer + active_video_mem_offset; | |
9cfe4a93 MH |
675 | |
676 | fbinfo->fbops = &bfin_lq035q1_fb_ops; | |
677 | ||
678 | fbinfo->pseudo_palette = &info->pseudo_pal; | |
679 | ||
680 | ret = fb_alloc_cmap(&fbinfo->cmap, BFIN_LCD_NBR_PALETTE_ENTRIES, 0); | |
681 | if (ret < 0) { | |
682 | dev_err(&pdev->dev, "failed to allocate colormap (%d entries)\n", | |
683 | BFIN_LCD_NBR_PALETTE_ENTRIES); | |
684 | goto out4; | |
685 | } | |
686 | ||
fbd65e0e MH |
687 | ret = bfin_lq035q1_request_ports(pdev, |
688 | info->disp_info->ppi_mode == USE_RGB565_16_BIT_PPI); | |
9cfe4a93 MH |
689 | if (ret) { |
690 | dev_err(&pdev->dev, "couldn't request gpio port\n"); | |
691 | goto out6; | |
692 | } | |
693 | ||
694 | info->irq = platform_get_irq(pdev, 0); | |
695 | if (info->irq < 0) { | |
696 | ret = -EINVAL; | |
697 | goto out7; | |
698 | } | |
699 | ||
f8798ccb | 700 | ret = request_irq(info->irq, bfin_lq035q1_irq_error, 0, |
9cfe4a93 MH |
701 | DRIVER_NAME" PPI ERROR", info); |
702 | if (ret < 0) { | |
703 | dev_err(&pdev->dev, "unable to request PPI ERROR IRQ\n"); | |
704 | goto out7; | |
705 | } | |
706 | ||
707 | info->spidrv.driver.name = DRIVER_NAME"-spi"; | |
708 | info->spidrv.probe = lq035q1_spidev_probe; | |
48c68c4f | 709 | info->spidrv.remove = lq035q1_spidev_remove; |
9cfe4a93 MH |
710 | info->spidrv.shutdown = lq035q1_spidev_shutdown; |
711 | info->spidrv.suspend = lq035q1_spidev_suspend; | |
712 | info->spidrv.resume = lq035q1_spidev_resume; | |
713 | ||
714 | ret = spi_register_driver(&info->spidrv); | |
715 | if (ret < 0) { | |
716 | dev_err(&pdev->dev, "couldn't register SPI Interface\n"); | |
717 | goto out8; | |
718 | } | |
719 | ||
720 | if (info->disp_info->use_bl) { | |
f8bd4934 JH |
721 | ret = gpio_request_one(info->disp_info->gpio_bl, |
722 | GPIOF_OUT_INIT_LOW, "LQ035 Backlight"); | |
9cfe4a93 MH |
723 | |
724 | if (ret) { | |
725 | dev_err(&pdev->dev, "failed to request GPIO %d\n", | |
726 | info->disp_info->gpio_bl); | |
727 | goto out9; | |
728 | } | |
9cfe4a93 MH |
729 | } |
730 | ||
731 | ret = register_framebuffer(fbinfo); | |
732 | if (ret < 0) { | |
733 | dev_err(&pdev->dev, "unable to register framebuffer\n"); | |
734 | goto out10; | |
735 | } | |
736 | ||
737 | dev_info(&pdev->dev, "%dx%d %d-bit RGB FrameBuffer initialized\n", | |
fbd65e0e | 738 | LCD_X_RES, LCD_Y_RES, info->lcd_bpp); |
9cfe4a93 MH |
739 | |
740 | return 0; | |
741 | ||
742 | out10: | |
743 | if (info->disp_info->use_bl) | |
744 | gpio_free(info->disp_info->gpio_bl); | |
745 | out9: | |
746 | spi_unregister_driver(&info->spidrv); | |
747 | out8: | |
748 | free_irq(info->irq, info); | |
749 | out7: | |
fbd65e0e MH |
750 | bfin_lq035q1_free_ports(info->disp_info->ppi_mode == |
751 | USE_RGB565_16_BIT_PPI); | |
9cfe4a93 MH |
752 | out6: |
753 | fb_dealloc_cmap(&fbinfo->cmap); | |
754 | out4: | |
755 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, | |
756 | info->dma_handle); | |
757 | out3: | |
758 | framebuffer_release(fbinfo); | |
759 | out2: | |
760 | free_dma(CH_PPI); | |
761 | out1: | |
762 | platform_set_drvdata(pdev, NULL); | |
763 | ||
764 | return ret; | |
765 | } | |
766 | ||
48c68c4f | 767 | static int bfin_lq035q1_remove(struct platform_device *pdev) |
9cfe4a93 MH |
768 | { |
769 | struct fb_info *fbinfo = platform_get_drvdata(pdev); | |
770 | struct bfin_lq035q1fb_info *info = fbinfo->par; | |
771 | ||
772 | if (info->disp_info->use_bl) | |
773 | gpio_free(info->disp_info->gpio_bl); | |
774 | ||
775 | spi_unregister_driver(&info->spidrv); | |
776 | ||
777 | unregister_framebuffer(fbinfo); | |
778 | ||
779 | free_dma(CH_PPI); | |
780 | free_irq(info->irq, info); | |
781 | ||
782 | if (info->fb_buffer != NULL) | |
783 | dma_free_coherent(NULL, fbinfo->fix.smem_len, info->fb_buffer, | |
784 | info->dma_handle); | |
785 | ||
786 | fb_dealloc_cmap(&fbinfo->cmap); | |
787 | ||
fbd65e0e MH |
788 | bfin_lq035q1_free_ports(info->disp_info->ppi_mode == |
789 | USE_RGB565_16_BIT_PPI); | |
9cfe4a93 MH |
790 | |
791 | platform_set_drvdata(pdev, NULL); | |
792 | framebuffer_release(fbinfo); | |
793 | ||
794 | dev_info(&pdev->dev, "unregistered LCD driver\n"); | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | #ifdef CONFIG_PM | |
800 | static int bfin_lq035q1_suspend(struct device *dev) | |
801 | { | |
802 | struct fb_info *fbinfo = dev_get_drvdata(dev); | |
803 | struct bfin_lq035q1fb_info *info = fbinfo->par; | |
804 | ||
805 | if (info->lq035_open_cnt) { | |
806 | lq035q1_backlight(info, 0); | |
807 | bfin_lq035q1_disable_ppi(); | |
808 | SSYNC(); | |
809 | disable_dma(CH_PPI); | |
810 | bfin_lq035q1_stop_timers(); | |
811 | bfin_write_PPI_STATUS(-1); | |
812 | } | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | static int bfin_lq035q1_resume(struct device *dev) | |
818 | { | |
819 | struct fb_info *fbinfo = dev_get_drvdata(dev); | |
820 | struct bfin_lq035q1fb_info *info = fbinfo->par; | |
821 | ||
822 | if (info->lq035_open_cnt) { | |
823 | bfin_lq035q1_disable_ppi(); | |
824 | SSYNC(); | |
825 | ||
826 | bfin_lq035q1_config_dma(info); | |
827 | bfin_lq035q1_config_ppi(info); | |
fbd65e0e | 828 | bfin_lq035q1_init_timers(info); |
9cfe4a93 MH |
829 | |
830 | /* start dma */ | |
831 | enable_dma(CH_PPI); | |
832 | bfin_lq035q1_enable_ppi(); | |
833 | bfin_lq035q1_start_timers(); | |
834 | lq035q1_backlight(info, 1); | |
835 | } | |
836 | ||
837 | return 0; | |
838 | } | |
839 | ||
840 | static struct dev_pm_ops bfin_lq035q1_dev_pm_ops = { | |
841 | .suspend = bfin_lq035q1_suspend, | |
842 | .resume = bfin_lq035q1_resume, | |
843 | }; | |
844 | #endif | |
845 | ||
846 | static struct platform_driver bfin_lq035q1_driver = { | |
847 | .probe = bfin_lq035q1_probe, | |
48c68c4f | 848 | .remove = bfin_lq035q1_remove, |
9cfe4a93 MH |
849 | .driver = { |
850 | .name = DRIVER_NAME, | |
851 | #ifdef CONFIG_PM | |
852 | .pm = &bfin_lq035q1_dev_pm_ops, | |
853 | #endif | |
854 | }, | |
855 | }; | |
856 | ||
1d90a66f | 857 | module_platform_driver(bfin_lq035q1_driver); |
9cfe4a93 MH |
858 | |
859 | MODULE_DESCRIPTION("Blackfin TFT LCD Driver"); | |
860 | MODULE_LICENSE("GPL"); |