projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sysfs: add parameter "struct bin_attribute *" in .read/.write methods for sysfs binar...
[linux-2.6-block.git] / drivers / video / aty / radeon_base.c
CommitLineData
1da177e4
LT		 1/*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53#define RADEON_VERSION "0.2.0"
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/moduleparam.h>
57#include <linux/kernel.h>
58#include <linux/errno.h>
59#include <linux/string.h>
60#include <linux/mm.h>
1da177e4
LT		 61#include <linux/slab.h>
62#include <linux/delay.h>
63#include <linux/time.h>
64#include <linux/fb.h>
65#include <linux/ioport.h>
66#include <linux/init.h>
67#include <linux/pci.h>
68#include <linux/vmalloc.h>
69#include <linux/device.h>
1da177e4
LT		 70
71#include <asm/io.h>
72#include <asm/uaccess.h>
73
74#ifdef CONFIG_PPC_OF
75
76#include <asm/pci-bridge.h>
77#include "../macmodes.h"
78
1da177e4
LT		 79#ifdef CONFIG_BOOTX_TEXT
80#include <asm/btext.h>
81#endif
82
83#endif /* CONFIG_PPC_OF */
84
85#ifdef CONFIG_MTRR
86#include <asm/mtrr.h>
87#endif
88
89#include <video/radeon.h>
90#include <linux/radeonfb.h>
91
92#include "../edid.h" // MOVE THAT TO include/video
93#include "ati_ids.h"
94#include "radeonfb.h"
95
96#define MAX_MAPPED_VRAM (2048*2048*4)
97#define MIN_MAPPED_VRAM (1024*768*1)
98
99#define CHIP_DEF(id, family, flags) \
100 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
101
102static struct pci_device_id radeonfb_pci_table[] = {
dd144713 103 /* Radeon Xpress 200m */
104 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
1da177e4
LT		 105 /* Mobility M6 */
106 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 /* Radeon VE/7000 */
109 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
110 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
183dee0f 111 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
1da177e4
LT		 112 /* Radeon IGP320M (U1) */
113 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
114 /* Radeon IGP320 (A3) */
115 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
116 /* IGP330M/340M/350M (U2) */
117 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
118 /* IGP330/340/350 (A4) */
119 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
120 /* Mobility 7000 IGP */
121 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 /* 7000 IGP (A4+) */
123 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 /* 8500 AIW */
125 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
126 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
127 /* 8700/8800 */
128 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
129 /* 8500 */
130 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
131 /* 9100 */
132 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
133 /* Mobility M7 */
134 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
135 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 /* 7500 */
137 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
138 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
139 /* Mobility M9 */
140 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
143 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 /* 9000/Pro */
145 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
146 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
147 /* Mobility 9100 IGP (U3) */
148 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
149 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 /* 9100 IGP (A5) */
151 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
152 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
153 /* Mobility 9200 (M9+) */
154 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
155 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 /* 9200 */
157 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
160 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
161 /* 9500 */
162 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
164 /* 9600TX / FireGL Z1 */
165 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
166 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
167 /* 9700/9500/Pro/FireGL X1 */
168 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
172 /* Mobility M10/M11 */
173 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
178 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 /* 9600/FireGL T2 */
180 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
185 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
186 /* 9800/Pro/FileGL X2 */
187 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
195 /* Newer stuff */
196 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
199 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
200 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
204 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
206 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
212 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
213 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
222 /* Original Radeon/7200 */
223 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
224 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
225 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
226 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
227 { 0, }
228};
229MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
230
231
232typedef struct {
233 u16 reg;
234 u32 val;
235} reg_val;
236
237
238/* these common regs are cleared before mode setting so they do not
239 * interfere with anything
240 */
241static reg_val common_regs[] = {
242 { OVR_CLR, 0 },
243 { OVR_WID_LEFT_RIGHT, 0 },
244 { OVR_WID_TOP_BOTTOM, 0 },
245 { OV0_SCALE_CNTL, 0 },
246 { SUBPIC_CNTL, 0 },
247 { VIPH_CONTROL, 0 },
248 { I2C_CNTL_1, 0 },
249 { GEN_INT_CNTL, 0 },
250 { CAP0_TRIG_CNTL, 0 },
251 { CAP1_TRIG_CNTL, 0 },
252};
253
254/*
255 * globals
256 */
257
258static char *mode_option;
259static char *monitor_layout;
260static int noaccel = 0;
261static int default_dynclk = -2;
262static int nomodeset = 0;
263static int ignore_edid = 0;
264static int mirror = 0;
265static int panel_yres = 0;
266static int force_dfp = 0;
267static int force_measure_pll = 0;
268#ifdef CONFIG_MTRR
269static int nomtrr = 0;
270#endif
994aad25
VB		 271static int force_sleep;
272static int ignore_devlist;
202d4e60
RP		 273#ifdef CONFIG_PMAC_BACKLIGHT
274static int backlight = 1;
275#else
276static int backlight = 0;
277#endif
1da177e4
LT		 278
279/*
280 * prototypes
281 */
282
1da177e4
LT		 283static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
284{
285 if (!rinfo->bios_seg)
286 return;
287 pci_unmap_rom(dev, rinfo->bios_seg);
288}
289
290static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
291{
292 void __iomem *rom;
293 u16 dptr;
294 u8 rom_type;
295 size_t rom_size;
296
297 /* If this is a primary card, there is a shadow copy of the
298 * ROM somewhere in the first meg. We will just ignore the copy
299 * and use the ROM directly.
300 */
301
302 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
303 unsigned int temp;
304 temp = INREG(MPP_TB_CONFIG);
305 temp &= 0x00ffffffu;
306 temp |= 0x04 << 24;
307 OUTREG(MPP_TB_CONFIG, temp);
308 temp = INREG(MPP_TB_CONFIG);
309
310 rom = pci_map_rom(dev, &rom_size);
311 if (!rom) {
312 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
313 pci_name(rinfo->pdev));
314 return -ENOMEM;
315 }
316
317 rinfo->bios_seg = rom;
318
319 /* Very simple test to make sure it appeared */
320 if (BIOS_IN16(0) != 0xaa55) {
3b4abffb
OH		 321 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
322 "should be 0xaa55\n",
323 pci_name(rinfo->pdev), BIOS_IN16(0));
1da177e4
LT		 324 goto failed;
325 }
326 /* Look for the PCI data to check the ROM type */
327 dptr = BIOS_IN16(0x18);
328
329 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
330 * for now, until I've verified this works everywhere. The goal here is more
331 * to phase out Open Firmware images.
332 *
333 * Currently, we only look at the first PCI data, we could iteratre and deal with
334 * them all, and we should use fb_bios_start relative to start of image and not
335 * relative start of ROM, but so far, I never found a dual-image ATI card
336 *
337 * typedef struct {
338 * u32 signature; + 0x00
339 * u16 vendor; + 0x04
340 * u16 device; + 0x06
341 * u16 reserved_1; + 0x08
342 * u16 dlen; + 0x0a
343 * u8 drevision; + 0x0c
344 * u8 class_hi; + 0x0d
345 * u16 class_lo; + 0x0e
346 * u16 ilen; + 0x10
347 * u16 irevision; + 0x12
348 * u8 type; + 0x14
349 * u8 indicator; + 0x15
350 * u16 reserved_2; + 0x16
351 * } pci_data_t;
352 */
353 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
354 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
355 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
356 goto anyway;
357 }
358 rom_type = BIOS_IN8(dptr + 0x14);
359 switch(rom_type) {
360 case 0:
361 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
362 break;
363 case 1:
364 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
365 goto failed;
366 case 2:
367 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
368 goto failed;
369 default:
370 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
371 goto failed;
372 }
373 anyway:
374 /* Locate the flat panel infos, do some sanity checking !!! */
375 rinfo->fp_bios_start = BIOS_IN16(0x48);
376 return 0;
377
378 failed:
379 rinfo->bios_seg = NULL;
380 radeon_unmap_ROM(rinfo, dev);
381 return -ENXIO;
382}
383
384#ifdef CONFIG_X86
385static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
386{
387 /* I simplified this code as we used to miss the signatures in
388 * a lot of case. It's now closer to XFree, we just don't check
389 * for signatures at all... Something better will have to be done
390 * if we end up having conflicts
391 */
392 u32 segstart;
393 void __iomem *rom_base = NULL;
394
395 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
396 rom_base = ioremap(segstart, 0x10000);
397 if (rom_base == NULL)
398 return -ENOMEM;
399 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
400 break;
401 iounmap(rom_base);
402 rom_base = NULL;
403 }
404 if (rom_base == NULL)
405 return -ENXIO;
406
407 /* Locate the flat panel infos, do some sanity checking !!! */
408 rinfo->bios_seg = rom_base;
409 rinfo->fp_bios_start = BIOS_IN16(0x48);
410
411 return 0;
412}
413#endif
414
9f47df26 415#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 416/*
417 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
418 * tree. Hopefully, ATI OF driver is kind enough to fill these
419 */
420static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
421{
422 struct device_node *dp = rinfo->of_node;
b04e3dd4 423 const u32 *val;
1da177e4
LT		 424
425 if (dp == NULL)
426 return -ENODEV;
40cd3a45 427 val = of_get_property(dp, "ATY,RefCLK", NULL);
1da177e4
LT		 428 if (!val || !*val) {
429 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
430 return -EINVAL;
431 }
432
433 rinfo->pll.ref_clk = (*val) / 10;
434
40cd3a45 435 val = of_get_property(dp, "ATY,SCLK", NULL);
1da177e4
LT		 436 if (val && *val)
437 rinfo->pll.sclk = (*val) / 10;
438
40cd3a45 439 val = of_get_property(dp, "ATY,MCLK", NULL);
1da177e4
LT		 440 if (val && *val)
441 rinfo->pll.mclk = (*val) / 10;
442
443 return 0;
444}
9f47df26 445#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 446
447/*
448 * Read PLL infos from chip registers
449 */
450static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
451{
452 unsigned char ppll_div_sel;
453 unsigned Ns, Nm, M;
454 unsigned sclk, mclk, tmp, ref_div;
455 int hTotal, vTotal, num, denom, m, n;
456 unsigned long long hz, vclk;
457 long xtal;
458 struct timeval start_tv, stop_tv;
459 long total_secs, total_usecs;
460 int i;
461
462 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
463 * here, so... --BenH
464 */
465
466 /* Flush PCI buffers ? */
017fb98e 467 tmp = INREG16(DEVICE_ID);
1da177e4
LT		 468
469 local_irq_disable();
470
471 for(i=0; i<1000000; i++)
472 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
473 break;
474
475 do_gettimeofday(&start_tv);
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
479 break;
480
481 for(i=0; i<1000000; i++)
482 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
483 break;
484
485 do_gettimeofday(&stop_tv);
486
487 local_irq_enable();
488
489 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
490 if (total_secs > 10)
491 return -1;
492 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
493 total_usecs += total_secs * 1000000;
494 if (total_usecs < 0)
495 total_usecs = -total_usecs;
496 hz = 1000000/total_usecs;
497
498 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
499 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
500 vclk = (long long)hTotal * (long long)vTotal * hz;
501
502 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
503 case 0:
504 default:
505 num = 1;
506 denom = 1;
507 break;
508 case 1:
509 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
510 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
511 num = 2*n;
512 denom = 2*m;
513 break;
514 case 2:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 }
521
522 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
523 radeon_pll_errata_after_index(rinfo);
524
525 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
526 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
527
528 num *= n;
529 denom *= m;
530
531 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
532 case 1:
533 denom *= 2;
534 break;
535 case 2:
536 denom *= 4;
537 break;
538 case 3:
539 denom *= 8;
540 break;
541 case 4:
542 denom *= 3;
543 break;
544 case 6:
545 denom *= 6;
546 break;
547 case 7:
548 denom *= 12;
549 break;
550 }
551
552 vclk *= denom;
553 do_div(vclk, 1000 * num);
554 xtal = vclk;
555
556 if ((xtal > 26900) && (xtal < 27100))
557 xtal = 2700;
558 else if ((xtal > 14200) && (xtal < 14400))
559 xtal = 1432;
560 else if ((xtal > 29400) && (xtal < 29600))
561 xtal = 2950;
562 else {
563 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
564 return -1;
565 }
566
567 tmp = INPLL(M_SPLL_REF_FB_DIV);
568 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
569
570 Ns = (tmp & 0xff0000) >> 16;
571 Nm = (tmp & 0xff00) >> 8;
572 M = (tmp & 0xff);
573 sclk = round_div((2 * Ns * xtal), (2 * M));
574 mclk = round_div((2 * Nm * xtal), (2 * M));
575
576 /* we're done, hopefully these are sane values */
577 rinfo->pll.ref_clk = xtal;
578 rinfo->pll.ref_div = ref_div;
579 rinfo->pll.sclk = sclk;
580 rinfo->pll.mclk = mclk;
581
582 return 0;
583}
584
585/*
4a4efbde 586 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
1da177e4
LT		 587 */
588static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
589{
590 /*
591 * In the case nothing works, these are defaults; they are mostly
592 * incomplete, however. It does provide ppll_max and _min values
593 * even for most other methods, however.
594 */
595 switch (rinfo->chipset) {
596 case PCI_DEVICE_ID_ATI_RADEON_QW:
597 case PCI_DEVICE_ID_ATI_RADEON_QX:
598 rinfo->pll.ppll_max = 35000;
599 rinfo->pll.ppll_min = 12000;
600 rinfo->pll.mclk = 23000;
601 rinfo->pll.sclk = 23000;
602 rinfo->pll.ref_clk = 2700;
603 break;
604 case PCI_DEVICE_ID_ATI_RADEON_QL:
605 case PCI_DEVICE_ID_ATI_RADEON_QN:
606 case PCI_DEVICE_ID_ATI_RADEON_QO:
607 case PCI_DEVICE_ID_ATI_RADEON_Ql:
608 case PCI_DEVICE_ID_ATI_RADEON_BB:
609 rinfo->pll.ppll_max = 35000;
610 rinfo->pll.ppll_min = 12000;
611 rinfo->pll.mclk = 27500;
612 rinfo->pll.sclk = 27500;
613 rinfo->pll.ref_clk = 2700;
614 break;
615 case PCI_DEVICE_ID_ATI_RADEON_Id:
616 case PCI_DEVICE_ID_ATI_RADEON_Ie:
617 case PCI_DEVICE_ID_ATI_RADEON_If:
618 case PCI_DEVICE_ID_ATI_RADEON_Ig:
619 rinfo->pll.ppll_max = 35000;
620 rinfo->pll.ppll_min = 12000;
621 rinfo->pll.mclk = 25000;
622 rinfo->pll.sclk = 25000;
623 rinfo->pll.ref_clk = 2700;
624 break;
625 case PCI_DEVICE_ID_ATI_RADEON_ND:
626 case PCI_DEVICE_ID_ATI_RADEON_NE:
627 case PCI_DEVICE_ID_ATI_RADEON_NF:
628 case PCI_DEVICE_ID_ATI_RADEON_NG:
629 rinfo->pll.ppll_max = 40000;
630 rinfo->pll.ppll_min = 20000;
631 rinfo->pll.mclk = 27000;
632 rinfo->pll.sclk = 27000;
633 rinfo->pll.ref_clk = 2700;
634 break;
635 case PCI_DEVICE_ID_ATI_RADEON_QD:
636 case PCI_DEVICE_ID_ATI_RADEON_QE:
637 case PCI_DEVICE_ID_ATI_RADEON_QF:
638 case PCI_DEVICE_ID_ATI_RADEON_QG:
639 default:
640 rinfo->pll.ppll_max = 35000;
641 rinfo->pll.ppll_min = 12000;
642 rinfo->pll.mclk = 16600;
643 rinfo->pll.sclk = 16600;
644 rinfo->pll.ref_clk = 2700;
645 break;
646 }
647 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
648
649
9f47df26 650#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4 651 /*
4a4efbde 652 * Retrieve PLL infos from Open Firmware first
1da177e4
LT		 653 */
654 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
4a4efbde 655 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
1da177e4
LT		 656 goto found;
657 }
9f47df26 658#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
1da177e4
LT		 659
660 /*
661 * Check out if we have an X86 which gave us some PLL informations
4a4efbde 662 * and if yes, retrieve them
1da177e4
LT		 663 */
664 if (!force_measure_pll && rinfo->bios_seg) {
665 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
666
667 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
668 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
669 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
670 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
671 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
672 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
673
4a4efbde 674 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
1da177e4
LT		 675 goto found;
676 }
677
678 /*
679 * We didn't get PLL parameters from either OF or BIOS, we try to
680 * probe them
681 */
682 if (radeon_probe_pll_params(rinfo) == 0) {
4a4efbde 683 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
1da177e4
LT		 684 goto found;
685 }
686
687 /*
688 * Fall back to already-set defaults...
689 */
690 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
691
692found:
693 /*
4a4efbde 694 * Some methods fail to retrieve SCLK and MCLK values, we apply default
1da177e4
LT		 695 * settings in this case (200Mhz). If that really happne often, we could
696 * fetch from registers instead...
697 */
698 if (rinfo->pll.mclk == 0)
699 rinfo->pll.mclk = 20000;
700 if (rinfo->pll.sclk == 0)
701 rinfo->pll.sclk = 20000;
702
703 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
704 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
705 rinfo->pll.ref_div,
706 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
707 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
708 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
709}
710
711static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
712{
713 struct radeonfb_info *rinfo = info->par;
714 struct fb_var_screeninfo v;
715 int nom, den;
716 unsigned int pitch;
717
718 if (radeon_match_mode(rinfo, &v, var))
719 return -EINVAL;
720
721 switch (v.bits_per_pixel) {
722 case 0 ... 8:
723 v.bits_per_pixel = 8;
724 break;
725 case 9 ... 16:
726 v.bits_per_pixel = 16;
727 break;
728 case 17 ... 24:
729#if 0 /* Doesn't seem to work */
730 v.bits_per_pixel = 24;
731 break;
732#endif
733 return -EINVAL;
734 case 25 ... 32:
735 v.bits_per_pixel = 32;
736 break;
737 default:
738 return -EINVAL;
739 }
740
741 switch (var_to_depth(&v)) {
742 case 8:
743 nom = den = 1;
744 v.red.offset = v.green.offset = v.blue.offset = 0;
745 v.red.length = v.green.length = v.blue.length = 8;
746 v.transp.offset = v.transp.length = 0;
747 break;
748 case 15:
749 nom = 2;
750 den = 1;
751 v.red.offset = 10;
752 v.green.offset = 5;
753 v.blue.offset = 0;
754 v.red.length = v.green.length = v.blue.length = 5;
755 v.transp.offset = v.transp.length = 0;
756 break;
757 case 16:
758 nom = 2;
759 den = 1;
760 v.red.offset = 11;
761 v.green.offset = 5;
762 v.blue.offset = 0;
763 v.red.length = 5;
764 v.green.length = 6;
765 v.blue.length = 5;
766 v.transp.offset = v.transp.length = 0;
767 break;
768 case 24:
769 nom = 4;
770 den = 1;
771 v.red.offset = 16;
772 v.green.offset = 8;
773 v.blue.offset = 0;
774 v.red.length = v.blue.length = v.green.length = 8;
775 v.transp.offset = v.transp.length = 0;
776 break;
777 case 32:
778 nom = 4;
779 den = 1;
780 v.red.offset = 16;
781 v.green.offset = 8;
782 v.blue.offset = 0;
783 v.red.length = v.blue.length = v.green.length = 8;
784 v.transp.offset = 24;
785 v.transp.length = 8;
786 break;
787 default:
788 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
789 var->xres, var->yres, var->bits_per_pixel);
790 return -EINVAL;
791 }
792
793 if (v.yres_virtual < v.yres)
794 v.yres_virtual = v.yres;
795 if (v.xres_virtual < v.xres)
796 v.xres_virtual = v.xres;
797
798
799 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
800 * with some panels, though I don't quite like this solution
801 */
802 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
803 v.xres_virtual = v.xres_virtual & ~7ul;
804 } else {
805 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
806 & ~(0x3f)) >> 6;
807 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
808 }
809
810 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
811 return -EINVAL;
812
813 if (v.xres_virtual < v.xres)
814 v.xres = v.xres_virtual;
815
816 if (v.xoffset < 0)
817 v.xoffset = 0;
818 if (v.yoffset < 0)
819 v.yoffset = 0;
820
821 if (v.xoffset > v.xres_virtual - v.xres)
822 v.xoffset = v.xres_virtual - v.xres - 1;
823
824 if (v.yoffset > v.yres_virtual - v.yres)
825 v.yoffset = v.yres_virtual - v.yres - 1;
826
827 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
828 v.transp.offset = v.transp.length =
829 v.transp.msb_right = 0;
830
831 memcpy(var, &v, sizeof(v));
832
833 return 0;
834}
835
836
837static int radeonfb_pan_display (struct fb_var_screeninfo *var,
838 struct fb_info *info)
839{
840 struct radeonfb_info *rinfo = info->par;
841
842 if ((var->xoffset + var->xres > var->xres_virtual)
843 || (var->yoffset + var->yres > var->yres_virtual))
844 return -EINVAL;
845
846 if (rinfo->asleep)
847 return 0;
848
849 radeon_fifo_wait(2);
850 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
851 * var->bits_per_pixel / 8) & ~7);
852 return 0;
853}
854
855
67a6680d
CH		 856static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
857 unsigned long arg)
1da177e4
LT		 858{
859 struct radeonfb_info *rinfo = info->par;
860 unsigned int tmp;
861 u32 value = 0;
862 int rc;
863
864 switch (cmd) {
865 /*
866 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
867 * and do something better using 2nd CRTC instead of just hackish
868 * routing to second output
869 */
870 case FBIO_RADEON_SET_MIRROR:
871 if (!rinfo->is_mobility)
872 return -EINVAL;
873
874 rc = get_user(value, (__u32 __user *)arg);
875
876 if (rc)
877 return rc;
878
879 radeon_fifo_wait(2);
880 if (value & 0x01) {
881 tmp = INREG(LVDS_GEN_CNTL);
882
883 tmp |= (LVDS_ON | LVDS_BLON);
884 } else {
885 tmp = INREG(LVDS_GEN_CNTL);
886
887 tmp &= ~(LVDS_ON | LVDS_BLON);
888 }
889
890 OUTREG(LVDS_GEN_CNTL, tmp);
891
892 if (value & 0x02) {
893 tmp = INREG(CRTC_EXT_CNTL);
894 tmp |= CRTC_CRT_ON;
895
896 mirror = 1;
897 } else {
898 tmp = INREG(CRTC_EXT_CNTL);
899 tmp &= ~CRTC_CRT_ON;
900
901 mirror = 0;
902 }
903
904 OUTREG(CRTC_EXT_CNTL, tmp);
905
906 return 0;
907 case FBIO_RADEON_GET_MIRROR:
908 if (!rinfo->is_mobility)
909 return -EINVAL;
910
911 tmp = INREG(LVDS_GEN_CNTL);
912 if ((LVDS_ON | LVDS_BLON) & tmp)
913 value |= 0x01;
914
915 tmp = INREG(CRTC_EXT_CNTL);
916 if (CRTC_CRT_ON & tmp)
917 value |= 0x02;
918
919 return put_user(value, (__u32 __user *)arg);
920 default:
921 return -EINVAL;
922 }
923
924 return -EINVAL;
925}
926
927
928int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
929{
930 u32 val;
931 u32 tmp_pix_clks;
932 int unblank = 0;
933
934 if (rinfo->lock_blank)
935 return 0;
936
937 radeon_engine_idle();
938
939 val = INREG(CRTC_EXT_CNTL);
940 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
941 CRTC_VSYNC_DIS);
942 switch (blank) {
943 case FB_BLANK_VSYNC_SUSPEND:
944 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
945 break;
946 case FB_BLANK_HSYNC_SUSPEND:
947 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
948 break;
949 case FB_BLANK_POWERDOWN:
950 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
951 CRTC_HSYNC_DIS);
952 break;
953 case FB_BLANK_NORMAL:
954 val |= CRTC_DISPLAY_DIS;
955 break;
956 case FB_BLANK_UNBLANK:
957 default:
958 unblank = 1;
959 }
960 OUTREG(CRTC_EXT_CNTL, val);
961
962
963 switch (rinfo->mon1_type) {
964 case MT_DFP:
965 if (unblank)
966 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
967 ~(FP_FPON | FP_TMDS_EN));
968 else {
969 if (mode_switch || blank == FB_BLANK_NORMAL)
970 break;
971 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
972 }
973 break;
974 case MT_LCD:
975 del_timer_sync(&rinfo->lvds_timer);
976 val = INREG(LVDS_GEN_CNTL);
977 if (unblank) {
978 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
979 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
980 & (LVDS_DIGON | LVDS_BL_MOD_EN));
981 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
982 OUTREG(LVDS_GEN_CNTL, target_val);
983 else if ((val ^ target_val) != 0) {
984 OUTREG(LVDS_GEN_CNTL, target_val
985 & ~(LVDS_ON | LVDS_BL_MOD_EN));
986 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
987 rinfo->init_state.lvds_gen_cntl |=
988 target_val & LVDS_STATE_MASK;
989 if (mode_switch) {
990 radeon_msleep(rinfo->panel_info.pwr_delay);
991 OUTREG(LVDS_GEN_CNTL, target_val);
992 }
993 else {
994 rinfo->pending_lvds_gen_cntl = target_val;
995 mod_timer(&rinfo->lvds_timer,
996 jiffies +
997 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
998 }
999 }
1000 } else {
1001 val |= LVDS_DISPLAY_DIS;
1002 OUTREG(LVDS_GEN_CNTL, val);
1003
1004 /* We don't do a full switch-off on a simple mode switch */
1005 if (mode_switch || blank == FB_BLANK_NORMAL)
1006 break;
1007
1008 /* Asic bug, when turning off LVDS_ON, we have to make sure
1009 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1010 */
1011 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1012 if (rinfo->is_mobility || rinfo->is_IGP)
1013 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1014 val &= ~(LVDS_BL_MOD_EN);
1015 OUTREG(LVDS_GEN_CNTL, val);
1016 udelay(100);
1017 val &= ~(LVDS_ON | LVDS_EN);
1018 OUTREG(LVDS_GEN_CNTL, val);
1019 val &= ~LVDS_DIGON;
1020 rinfo->pending_lvds_gen_cntl = val;
1021 mod_timer(&rinfo->lvds_timer,
1022 jiffies +
1023 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1024 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1025 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1026 if (rinfo->is_mobility || rinfo->is_IGP)
1027 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1028 }
1029 break;
1030 case MT_CRT:
1031 // todo: powerdown DAC
1032 default:
1033 break;
1034 }
1035
7ab87670 1036 return 0;
1da177e4
LT		 1037}
1038
1039static int radeonfb_blank (int blank, struct fb_info *info)
1040{
1041 struct radeonfb_info *rinfo = info->par;
1042
1043 if (rinfo->asleep)
1044 return 0;
1045
1046 return radeon_screen_blank(rinfo, blank, 0);
1047}
1048
71494376
BH		 1049static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1050 unsigned blue, unsigned transp,
1051 struct radeonfb_info *rinfo)
1da177e4 1052{
1da177e4
LT		 1053 u32 pindex;
1054 unsigned int i;
71494376
BH		 1055
1056
1da177e4 1057 if (regno > 255)
db77ec27 1058 return -EINVAL;
1da177e4
LT		 1059
1060 red >>= 8;
1061 green >>= 8;
1062 blue >>= 8;
1063 rinfo->palette[regno].red = red;
1064 rinfo->palette[regno].green = green;
1065 rinfo->palette[regno].blue = blue;
1066
1067 /* default */
1068 pindex = regno;
1069
1070 if (!rinfo->asleep) {
1da177e4 1071 radeon_fifo_wait(9);
1da177e4
LT		 1072
1073 if (rinfo->bpp == 16) {
1074 pindex = regno * 8;
1075
1076 if (rinfo->depth == 16 && regno > 63)
db77ec27 1077 return -EINVAL;
1da177e4 1078 if (rinfo->depth == 15 && regno > 31)
db77ec27 1079 return -EINVAL;
1da177e4 1080
71494376
BH		 1081 /* For 565, the green component is mixed one order
1082 * below
1083 */
1da177e4
LT		 1084 if (rinfo->depth == 16) {
1085 OUTREG(PALETTE_INDEX, pindex>>1);
71494376
BH		 1086 OUTREG(PALETTE_DATA,
1087 (rinfo->palette[regno>>1].red << 16) |
1088 (green << 8) |
1089 (rinfo->palette[regno>>1].blue));
1da177e4
LT		 1090 green = rinfo->palette[regno<<1].green;
1091 }
1092 }
1093
1094 if (rinfo->depth != 16 || regno < 32) {
1095 OUTREG(PALETTE_INDEX, pindex);
71494376
BH		 1096 OUTREG(PALETTE_DATA, (red << 16) |
1097 (green << 8) | blue);
1da177e4 1098 }
1da177e4
LT		 1099 }
1100 if (regno < 16) {
71494376 1101 u32 *pal = rinfo->info->pseudo_palette;
1da177e4
LT		 1102 switch (rinfo->depth) {
1103 case 15:
1104 pal[regno] = (regno << 10) | (regno << 5) | regno;
1105 break;
1106 case 16:
1107 pal[regno] = (regno << 11) | (regno << 5) | regno;
1108 break;
1109 case 24:
1110 pal[regno] = (regno << 16) | (regno << 8) | regno;
1111 break;
1112 case 32:
1113 i = (regno << 8) | regno;
1114 pal[regno] = (i << 16) | i;
1115 break;
1116 }
1117 }
1118 return 0;
1119}
1120
71494376
BH		 1121static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1122 unsigned blue, unsigned transp,
1123 struct fb_info *info)
1124{
1125 struct radeonfb_info *rinfo = info->par;
1126 u32 dac_cntl2, vclk_cntl = 0;
1127 int rc;
1128
1129 if (!rinfo->asleep) {
1130 if (rinfo->is_mobility) {
1131 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1132 OUTPLL(VCLK_ECP_CNTL,
1133 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1134 }
1135
1136 /* Make sure we are on first palette */
1137 if (rinfo->has_CRTC2) {
1138 dac_cntl2 = INREG(DAC_CNTL2);
1139 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1140 OUTREG(DAC_CNTL2, dac_cntl2);
1141 }
1142 }
1143
1144 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1145
1146 if (!rinfo->asleep && rinfo->is_mobility)
1147 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1148
1149 return rc;
1150}
1151
1152static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1153{
1154 struct radeonfb_info *rinfo = info->par;
1155 u16 *red, *green, *blue, *transp;
1156 u32 dac_cntl2, vclk_cntl = 0;
1157 int i, start, rc = 0;
1158
1159 if (!rinfo->asleep) {
1160 if (rinfo->is_mobility) {
1161 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1162 OUTPLL(VCLK_ECP_CNTL,
1163 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1164 }
1165
1166 /* Make sure we are on first palette */
1167 if (rinfo->has_CRTC2) {
1168 dac_cntl2 = INREG(DAC_CNTL2);
1169 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1170 OUTREG(DAC_CNTL2, dac_cntl2);
1171 }
1172 }
1173
1174 red = cmap->red;
1175 green = cmap->green;
1176 blue = cmap->blue;
1177 transp = cmap->transp;
1178 start = cmap->start;
1179
1180 for (i = 0; i < cmap->len; i++) {
1181 u_int hred, hgreen, hblue, htransp = 0xffff;
1182
1183 hred = *red++;
1184 hgreen = *green++;
1185 hblue = *blue++;
1186 if (transp)
1187 htransp = *transp++;
1188 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1189 rinfo);
1190 if (rc)
1191 break;
1192 }
1193
1194 if (!rinfo->asleep && rinfo->is_mobility)
1195 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1196
1197 return rc;
1198}
1da177e4
LT		 1199
1200static void radeon_save_state (struct radeonfb_info *rinfo,
1201 struct radeon_regs *save)
1202{
1203 /* CRTC regs */
1204 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1205 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1206 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1207 save->dac_cntl = INREG(DAC_CNTL);
1208 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1209 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1210 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1211 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1212 save->crtc_pitch = INREG(CRTC_PITCH);
1213 save->surface_cntl = INREG(SURFACE_CNTL);
1214
1215 /* FP regs */
1216 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1217 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1218 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1219 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1220 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1221 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1222 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1223 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1224 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1225 save->tmds_crc = INREG(TMDS_CRC);
1226 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1227 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1228
1229 /* PLL regs */
1230 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1231 radeon_pll_errata_after_index(rinfo);
1232 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1233 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1234}
1235
1236
1237static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1238{
1239 int i;
1240
1241 radeon_fifo_wait(20);
1242
1243 /* Workaround from XFree */
1244 if (rinfo->is_mobility) {
1245 /* A temporal workaround for the occational blanking on certain laptop
1246 * panels. This appears to related to the PLL divider registers
1247 * (fail to lock?). It occurs even when all dividers are the same
1248 * with their old settings. In this case we really don't need to
1249 * fiddle with PLL registers. By doing this we can avoid the blanking
1250 * problem with some panels.
1251 */
1252 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1253 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1254 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1255 /* We still have to force a switch to selected PPLL div thanks to
1256 * an XFree86 driver bug which will switch it away in some cases
1257 * even when using UseFDev */
1258 OUTREGP(CLOCK_CNTL_INDEX,
1259 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1260 ~PPLL_DIV_SEL_MASK);
1261 radeon_pll_errata_after_index(rinfo);
1262 radeon_pll_errata_after_data(rinfo);
1263 return;
1264 }
1265 }
1266
1267 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1268 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1269
1270 /* Reset PPLL & enable atomic update */
1271 OUTPLLP(PPLL_CNTL,
1272 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1273 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1274
1275 /* Switch to selected PPLL divider */
1276 OUTREGP(CLOCK_CNTL_INDEX,
1277 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1278 ~PPLL_DIV_SEL_MASK);
1279 radeon_pll_errata_after_index(rinfo);
1280 radeon_pll_errata_after_data(rinfo);
1281
1282 /* Set PPLL ref. div */
1283 if (rinfo->family == CHIP_FAMILY_R300 ||
1284 rinfo->family == CHIP_FAMILY_RS300 ||
1285 rinfo->family == CHIP_FAMILY_R350 ||
1286 rinfo->family == CHIP_FAMILY_RV350) {
1287 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1288 /* When restoring console mode, use saved PPLL_REF_DIV
1289 * setting.
1290 */
1291 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1292 } else {
1293 /* R300 uses ref_div_acc field as real ref divider */
1294 OUTPLLP(PPLL_REF_DIV,
1295 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1296 ~R300_PPLL_REF_DIV_ACC_MASK);
1297 }
1298 } else
1299 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1300
1301 /* Set PPLL divider 3 & post divider*/
1302 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1303 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1304
1305 /* Write update */
1306 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1307 ;
1308 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1309
1310 /* Wait read update complete */
1311 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1312 the cause yet, but this workaround will mask the problem for now.
1313 Other chips usually will pass at the very first test, so the
1314 workaround shouldn't have any effect on them. */
1315 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1316 ;
1317
1318 OUTPLL(HTOTAL_CNTL, 0);
1319
1320 /* Clear reset & atomic update */
1321 OUTPLLP(PPLL_CNTL, 0,
1322 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1323
1324 /* We may want some locking ... oh well */
1325 radeon_msleep(5);
1326
1327 /* Switch back VCLK source to PPLL */
1328 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1329}
1330
1331/*
1332 * Timer function for delayed LVDS panel power up/down
1333 */
1334static void radeon_lvds_timer_func(unsigned long data)
1335{
1336 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1337
1338 radeon_engine_idle();
1339
1340 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1341}
1342
1343/*
1344 * Apply a video mode. This will apply the whole register set, including
1345 * the PLL registers, to the card
1346 */
1347void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1348 int regs_only)
1349{
1350 int i;
1351 int primary_mon = PRIMARY_MONITOR(rinfo);
1352
1353 if (nomodeset)
1354 return;
1355
1356 if (!regs_only)
1357 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1358
1359 radeon_fifo_wait(31);
1360 for (i=0; i<10; i++)
1361 OUTREG(common_regs[i].reg, common_regs[i].val);
1362
1363 /* Apply surface registers */
1364 for (i=0; i<8; i++) {
1365 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1366 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1367 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1368 }
1369
1370 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1371 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1372 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1373 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1374 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1375 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1376 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1377 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1378 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1379 OUTREG(CRTC_OFFSET, 0);
1380 OUTREG(CRTC_OFFSET_CNTL, 0);
1381 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1382 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1383
1384 radeon_write_pll_regs(rinfo, mode);
1385
1386 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1387 radeon_fifo_wait(10);
1388 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1389 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1390 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1391 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1392 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1393 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1394 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1395 OUTREG(TMDS_CRC, mode->tmds_crc);
1396 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1397 }
1398
1399 if (!regs_only)
1400 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1401
1402 radeon_fifo_wait(2);
1403 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1404
1405 return;
1406}
1407
1408/*
1409 * Calculate the PLL values for a given mode
1410 */
1411static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1412 unsigned long freq)
1413{
1414 const struct {
1415 int divider;
1416 int bitvalue;
1417 } *post_div,
1418 post_divs[] = {
1419 { 1, 0 },
1420 { 2, 1 },
1421 { 4, 2 },
1422 { 8, 3 },
1423 { 3, 4 },
1424 { 16, 5 },
1425 { 6, 6 },
1426 { 12, 7 },
1427 { 0, 0 },
1428 };
1429 int fb_div, pll_output_freq = 0;
1430 int uses_dvo = 0;
1431
1432 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1433 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1434 * recent than an r(v)100...
1435 */
1436#if 1
1437 /* XXX I had reports of flicker happening with the cinema display
1438 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1439 * this case. This could just be a bandwidth calculation issue, I
1440 * haven't implemented the bandwidth code yet, but in the meantime,
1441 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1442 * I haven't seen a case were were absolutely needed an odd PLL
1443 * divider. I'll find a better fix once I have more infos on the
1444 * real cause of the problem.
1445 */
1446 while (rinfo->has_CRTC2) {
1447 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1448 u32 disp_output_cntl;
1449 int source;
1450
1451 /* FP2 path not enabled */
1452 if ((fp2_gen_cntl & FP2_ON) == 0)
1453 break;
1454 /* Not all chip revs have the same format for this register,
1455 * extract the source selection
1456 */
1457 if (rinfo->family == CHIP_FAMILY_R200 ||
1458 rinfo->family == CHIP_FAMILY_R300 ||
1459 rinfo->family == CHIP_FAMILY_R350 ||
1460 rinfo->family == CHIP_FAMILY_RV350) {
1461 source = (fp2_gen_cntl >> 10) & 0x3;
1462 /* sourced from transform unit, check for transform unit
1463 * own source
1464 */
1465 if (source == 3) {
1466 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1467 source = (disp_output_cntl >> 12) & 0x3;
1468 }
1469 } else
1470 source = (fp2_gen_cntl >> 13) & 0x1;
1471 /* sourced from CRTC2 -> exit */
1472 if (source == 1)
1473 break;
1474
1475 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1476 uses_dvo = 1;
1477 break;
1478 }
1479#else
1480 uses_dvo = 1;
1481#endif
1482 if (freq > rinfo->pll.ppll_max)
1483 freq = rinfo->pll.ppll_max;
1484 if (freq*12 < rinfo->pll.ppll_min)
1485 freq = rinfo->pll.ppll_min / 12;
1486 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1487 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1488
1489 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1490 pll_output_freq = post_div->divider * freq;
1491 /* If we output to the DVO port (external TMDS), we don't allow an
1492 * odd PLL divider as those aren't supported on this path
1493 */
1494 if (uses_dvo && (post_div->divider & 1))
1495 continue;
1496 if (pll_output_freq >= rinfo->pll.ppll_min &&
1497 pll_output_freq <= rinfo->pll.ppll_max)
1498 break;
1499 }
1500
1501 /* If we fall through the bottom, try the "default value"
1502 given by the terminal post_div->bitvalue */
1503 if ( !post_div->divider ) {
1504 post_div = &post_divs[post_div->bitvalue];
1505 pll_output_freq = post_div->divider * freq;
1506 }
1507 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1508 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1509 pll_output_freq);
1510
1511 /* If we fall through the bottom, try the "default value"
1512 given by the terminal post_div->bitvalue */
1513 if ( !post_div->divider ) {
1514 post_div = &post_divs[post_div->bitvalue];
1515 pll_output_freq = post_div->divider * freq;
1516 }
1517 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1518 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1519 pll_output_freq);
1520
1521 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1522 rinfo->pll.ref_clk);
1523 regs->ppll_ref_div = rinfo->pll.ref_div;
1524 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1525
1526 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1527 RTRACE("fb_div = 0x%x\n", fb_div);
1528 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1529}
1530
1531static int radeonfb_set_par(struct fb_info *info)
1532{
1533 struct radeonfb_info *rinfo = info->par;
1534 struct fb_var_screeninfo *mode = &info->var;
1535 struct radeon_regs *newmode;
1536 int hTotal, vTotal, hSyncStart, hSyncEnd,
1537 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1538 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1539 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1540 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1541 int i, freq;
1542 int format = 0;
1543 int nopllcalc = 0;
1544 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1545 int primary_mon = PRIMARY_MONITOR(rinfo);
1546 int depth = var_to_depth(mode);
1547 int use_rmx = 0;
1548
1549 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1550 if (!newmode)
1551 return -ENOMEM;
1552
1553 /* We always want engine to be idle on a mode switch, even
1554 * if we won't actually change the mode
1555 */
1556 radeon_engine_idle();
1557
1558 hSyncStart = mode->xres + mode->right_margin;
1559 hSyncEnd = hSyncStart + mode->hsync_len;
1560 hTotal = hSyncEnd + mode->left_margin;
1561
1562 vSyncStart = mode->yres + mode->lower_margin;
1563 vSyncEnd = vSyncStart + mode->vsync_len;
1564 vTotal = vSyncEnd + mode->upper_margin;
1565 pixClock = mode->pixclock;
1566
1567 sync = mode->sync;
1568 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1569 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1570
1571 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1572 if (rinfo->panel_info.xres < mode->xres)
1573 mode->xres = rinfo->panel_info.xres;
1574 if (rinfo->panel_info.yres < mode->yres)
1575 mode->yres = rinfo->panel_info.yres;
1576
1577 hTotal = mode->xres + rinfo->panel_info.hblank;
1578 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1579 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1580
1581 vTotal = mode->yres + rinfo->panel_info.vblank;
1582 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1583 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1584
1585 h_sync_pol = !rinfo->panel_info.hAct_high;
1586 v_sync_pol = !rinfo->panel_info.vAct_high;
1587
1588 pixClock = 100000000 / rinfo->panel_info.clock;
1589
1590 if (rinfo->panel_info.use_bios_dividers) {
1591 nopllcalc = 1;
1592 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1593 (rinfo->panel_info.post_divider << 16);
1594 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1595 }
1596 }
1597 dotClock = 1000000000 / pixClock;
1598 freq = dotClock / 10; /* x100 */
1599
1600 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1601 hSyncStart, hSyncEnd, hTotal);
1602 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1603 vSyncStart, vSyncEnd, vTotal);
1604
1605 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1606 vsync_wid = vSyncEnd - vSyncStart;
1607 if (hsync_wid == 0)
1608 hsync_wid = 1;
1609 else if (hsync_wid > 0x3f) /* max */
1610 hsync_wid = 0x3f;
1611
1612 if (vsync_wid == 0)
1613 vsync_wid = 1;
1614 else if (vsync_wid > 0x1f) /* max */
1615 vsync_wid = 0x1f;
1616
1617 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1618 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1619
1620 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1621
1622 format = radeon_get_dstbpp(depth);
1623 bytpp = mode->bits_per_pixel >> 3;
1624
1625 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1626 hsync_fudge = hsync_fudge_fp[format-1];
1627 else
1628 hsync_fudge = hsync_adj_tab[format-1];
1629
1630 hsync_start = hSyncStart - 8 + hsync_fudge;
1631
1632 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1633 (format << 8);
1634
1635 /* Clear auto-center etc... */
1636 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1637 newmode->crtc_more_cntl &= 0xfffffff0;
1638
1639 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1640 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1641 if (mirror)
1642 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1643
1644 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1645 CRTC_INTERLACE_EN);
1646 } else {
1647 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1648 CRTC_CRT_ON;
1649 }
1650
1651 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1652 DAC_8BIT_EN;
1653
1654 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1655 (((mode->xres / 8) - 1) << 16));
1656
1657 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1658 (hsync_wid << 16) | (h_sync_pol << 23));
1659
1660 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1661 ((mode->yres - 1) << 16);
1662
1663 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1664 (vsync_wid << 16) | (v_sync_pol << 23));
1665
1666 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1667 /* We first calculate the engine pitch */
1668 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1669 & ~(0x3f)) >> 6;
1670
1671 /* Then, re-multiply it to get the CRTC pitch */
1672 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1673 } else
1674 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1675
1676 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1677
1678 /*
1679 * It looks like recent chips have a problem with SURFACE_CNTL,
1680 * setting SURF_TRANSLATION_DIS completely disables the
1681 * swapper as well, so we leave it unset now.
1682 */
1683 newmode->surface_cntl = 0;
1684
1685#if defined(__BIG_ENDIAN)
1686
1687 /* Setup swapping on both apertures, though we currently
1688 * only use aperture 0, enabling swapper on aperture 1
1689 * won't harm
1690 */
1691 switch (mode->bits_per_pixel) {
1692 case 16:
1693 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1694 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1695 break;
1696 case 24:
1697 case 32:
1698 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1699 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1700 break;
1701 }
1702#endif
1703
1704 /* Clear surface registers */
1705 for (i=0; i<8; i++) {
1706 newmode->surf_lower_bound[i] = 0;
1707 newmode->surf_upper_bound[i] = 0x1f;
1708 newmode->surf_info[i] = 0;
1709 }
1710
1711 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1712 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1713 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1714 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1715
1716 rinfo->bpp = mode->bits_per_pixel;
1717 rinfo->depth = depth;
1718
1719 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1720 RTRACE("freq = %lu\n", (unsigned long)freq);
1721
1722 /* We use PPLL_DIV_3 */
1723 newmode->clk_cntl_index = 0x300;
1724
1725 /* Calculate PPLL value if necessary */
1726 if (!nopllcalc)
1727 radeon_calc_pll_regs(rinfo, newmode, freq);
1728
1729 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1730
1731 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1732 unsigned int hRatio, vRatio;
1733
1734 if (mode->xres > rinfo->panel_info.xres)
1735 mode->xres = rinfo->panel_info.xres;
1736 if (mode->yres > rinfo->panel_info.yres)
1737 mode->yres = rinfo->panel_info.yres;
1738
1739 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1740 << HORZ_PANEL_SHIFT);
1741 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1742 << VERT_PANEL_SHIFT);
1743
1744 if (mode->xres != rinfo->panel_info.xres) {
1745 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1746 rinfo->panel_info.xres);
1747 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1748 (newmode->fp_horz_stretch &
1749 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1750 HORZ_AUTO_RATIO_INC)));
1751 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1752 HORZ_STRETCH_ENABLE);
1753 use_rmx = 1;
1754 }
1755 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1756
1757 if (mode->yres != rinfo->panel_info.yres) {
1758 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1759 rinfo->panel_info.yres);
1760 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1761 (newmode->fp_vert_stretch &
1762 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1763 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1764 VERT_STRETCH_ENABLE);
1765 use_rmx = 1;
1766 }
1767 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1768
1769 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1770 ~(FP_SEL_CRTC2 |
1771 FP_RMX_HVSYNC_CONTROL_EN |
1772 FP_DFP_SYNC_SEL |
1773 FP_CRT_SYNC_SEL |
1774 FP_CRTC_LOCK_8DOT |
1775 FP_USE_SHADOW_EN |
1776 FP_CRTC_USE_SHADOW_VEND |
1777 FP_CRT_SYNC_ALT));
1778
1779 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1780 FP_CRTC_DONT_SHADOW_HEND |
1781 FP_PANEL_FORMAT);
1782
1783 if (IS_R300_VARIANT(rinfo) ||
1784 (rinfo->family == CHIP_FAMILY_R200)) {
1785 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1786 if (use_rmx)
1787 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1788 else
1789 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1790 } else
1791 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1792
1793 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1794 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1795 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1796 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1797
1798 if (primary_mon == MT_LCD) {
1799 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1800 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1801 } else {
1802 /* DFP */
1803 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1804 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1805 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1806 if (IS_R300_VARIANT(rinfo) ||
1807 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1808 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1809 else
1810 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1811 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1812 }
1813
1814 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1815 (((mode->xres / 8) - 1) << 16));
1816 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1817 ((mode->yres - 1) << 16);
1818 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1819 (hsync_wid << 16) | (h_sync_pol << 23));
1820 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1821 (vsync_wid << 16) | (v_sync_pol << 23));
1822 }
1823
1824 /* do it! */
1825 if (!rinfo->asleep) {
1826 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1827 radeon_write_mode (rinfo, newmode, 0);
1828 /* (re)initialize the engine */
1829 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1830 radeonfb_engine_init (rinfo);
1831 }
1832 /* Update fix */
1833 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1834 info->fix.line_length = rinfo->pitch*64;
1835 else
1836 info->fix.line_length = mode->xres_virtual
1837 * ((mode->bits_per_pixel + 1) / 8);
1838 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1839 : FB_VISUAL_DIRECTCOLOR;
1840
1841#ifdef CONFIG_BOOTX_TEXT
1842 /* Update debug text engine */
1843 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1844 rinfo->depth, info->fix.line_length);
1845#endif
1846
1847 kfree(newmode);
1848 return 0;
1849}
1850
1851
1852static struct fb_ops radeonfb_ops = {
1853 .owner = THIS_MODULE,
1854 .fb_check_var = radeonfb_check_var,
1855 .fb_set_par = radeonfb_set_par,
1856 .fb_setcolreg = radeonfb_setcolreg,
71494376 1857 .fb_setcmap = radeonfb_setcmap,
1da177e4
LT		 1858 .fb_pan_display = radeonfb_pan_display,
1859 .fb_blank = radeonfb_blank,
1860 .fb_ioctl = radeonfb_ioctl,
1861 .fb_sync = radeonfb_sync,
1862 .fb_fillrect = radeonfb_fillrect,
1863 .fb_copyarea = radeonfb_copyarea,
1864 .fb_imageblit = radeonfb_imageblit,
1da177e4
LT		 1865};
1866
1867
1868static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1869{
1870 struct fb_info *info = rinfo->info;
1871
1872 info->par = rinfo;
1873 info->pseudo_palette = rinfo->pseudo_palette;
1874 info->flags = FBINFO_DEFAULT
1875 | FBINFO_HWACCEL_COPYAREA
1876 | FBINFO_HWACCEL_FILLRECT
1877 | FBINFO_HWACCEL_XPAN
1878 | FBINFO_HWACCEL_YPAN;
1879 info->fbops = &radeonfb_ops;
1880 info->screen_base = rinfo->fb_base;
1881 info->screen_size = rinfo->mapped_vram;
1882 /* Fill fix common fields */
1883 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1884 info->fix.smem_start = rinfo->fb_base_phys;
1885 info->fix.smem_len = rinfo->video_ram;
1886 info->fix.type = FB_TYPE_PACKED_PIXELS;
1887 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1888 info->fix.xpanstep = 8;
1889 info->fix.ypanstep = 1;
1890 info->fix.ywrapstep = 0;
1891 info->fix.type_aux = 0;
1892 info->fix.mmio_start = rinfo->mmio_base_phys;
1893 info->fix.mmio_len = RADEON_REGSIZE;
1894 info->fix.accel = FB_ACCEL_ATI_RADEON;
1895
1896 fb_alloc_cmap(&info->cmap, 256, 0);
1897
1898 if (noaccel)
1899 info->flags |= FBINFO_HWACCEL_DISABLED;
1900
1901 return 0;
1902}
1903
1da177e4
LT		 1904/*
1905 * This reconfigure the card's internal memory map. In theory, we'd like
1906 * to setup the card's memory at the same address as it's PCI bus address,
1907 * and the AGP aperture right after that so that system RAM on 32 bits
1908 * machines at least, is directly accessible. However, doing so would
1909 * conflict with the current XFree drivers...
1910 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1911 * on the proper way to set this up and duplicate this here. In the meantime,
1912 * I put the card's memory at 0 in card space and AGP at some random high
1913 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1914 */
1915#ifdef CONFIG_PPC_OF
1916#undef SET_MC_FB_FROM_APERTURE
1917static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1918{
1919 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1920 u32 save_crtc_ext_cntl;
1921 u32 aper_base, aper_size;
1922 u32 agp_base;
1923
1924 /* First, we disable display to avoid interfering */
1925 if (rinfo->has_CRTC2) {
1926 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1927 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1928 }
1929 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1930 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1931
1932 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1933 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1934 mdelay(100);
1935
1936 aper_base = INREG(CONFIG_APER_0_BASE);
1937 aper_size = INREG(CONFIG_APER_SIZE);
1938
1939#ifdef SET_MC_FB_FROM_APERTURE
1940 /* Set framebuffer to be at the same address as set in PCI BAR */
1941 OUTREG(MC_FB_LOCATION,
1942 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1943 rinfo->fb_local_base = aper_base;
1944#else
1945 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1946 rinfo->fb_local_base = 0;
1947#endif
1948 agp_base = aper_base + aper_size;
1949 if (agp_base & 0xf0000000)
1950 agp_base = (aper_base | 0x0fffffff) + 1;
1951
1952 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1953 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1954 * always the case on PPCs afaik.
1955 */
1956#ifdef SET_MC_FB_FROM_APERTURE
1957 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1958#else
1959 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1960#endif
1961
1962 /* Fixup the display base addresses & engine offsets while we
1963 * are at it as well
1964 */
1965#ifdef SET_MC_FB_FROM_APERTURE
1966 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1967 if (rinfo->has_CRTC2)
1968 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1969 OUTREG(OV0_BASE_ADDR, aper_base);
1970#else
1971 OUTREG(DISPLAY_BASE_ADDR, 0);
1972 if (rinfo->has_CRTC2)
1973 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1974 OUTREG(OV0_BASE_ADDR, 0);
1975#endif
1976 mdelay(100);
1977
1978 /* Restore display settings */
1979 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1980 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1981 if (rinfo->has_CRTC2)
1982 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1983
1984 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1985 aper_base,
1986 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1987 0xffff0000 | (agp_base >> 16));
1988}
1989#endif /* CONFIG_PPC_OF */
1990
1991
1992static void radeon_identify_vram(struct radeonfb_info *rinfo)
1993{
1994 u32 tmp;
1995
1996 /* framebuffer size */
1997 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1998 (rinfo->family == CHIP_FAMILY_RS200) ||
dd144713 1999 (rinfo->family == CHIP_FAMILY_RS300) ||
2000 (rinfo->family == CHIP_FAMILY_RS480) ) {
1da177e4
LT		 2001 u32 tom = INREG(NB_TOM);
2002 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2003
2004 radeon_fifo_wait(6);
2005 OUTREG(MC_FB_LOCATION, tom);
2006 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2007 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2008 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2009
2010 /* This is supposed to fix the crtc2 noise problem. */
2011 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2012
2013 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2014 (rinfo->family == CHIP_FAMILY_RS200)) {
2015 /* This is to workaround the asic bug for RMX, some versions
2016 of BIOS dosen't have this register initialized correctly.
2017 */
2018 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2019 ~CRTC_H_CUTOFF_ACTIVE_EN);
2020 }
2021 } else {
2022 tmp = INREG(CONFIG_MEMSIZE);
2023 }
2024
2025 /* mem size is bits [28:0], mask off the rest */
2026 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2027
2028 /*
2029 * Hack to get around some busted production M6's
2030 * reporting no ram
2031 */
2032 if (rinfo->video_ram == 0) {
2033 switch (rinfo->pdev->device) {
2034 case PCI_CHIP_RADEON_LY:
2035 case PCI_CHIP_RADEON_LZ:
2036 rinfo->video_ram = 8192 * 1024;
2037 break;
2038 default:
2039 break;
2040 }
2041 }
2042
2043
2044 /*
2045 * Now try to identify VRAM type
2046 */
2047 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2048 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2049 rinfo->vram_ddr = 1;
2050 else
2051 rinfo->vram_ddr = 0;
2052
2053 tmp = INREG(MEM_CNTL);
2054 if (IS_R300_VARIANT(rinfo)) {
2055 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2056 switch (tmp) {
2057 case 0: rinfo->vram_width = 64; break;
2058 case 1: rinfo->vram_width = 128; break;
2059 case 2: rinfo->vram_width = 256; break;
2060 default: rinfo->vram_width = 128; break;
2061 }
2062 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2063 (rinfo->family == CHIP_FAMILY_RS100) ||
2064 (rinfo->family == CHIP_FAMILY_RS200)){
2065 if (tmp & RV100_MEM_HALF_MODE)
2066 rinfo->vram_width = 32;
2067 else
2068 rinfo->vram_width = 64;
2069 } else {
2070 if (tmp & MEM_NUM_CHANNELS_MASK)
2071 rinfo->vram_width = 128;
2072 else
2073 rinfo->vram_width = 64;
2074 }
2075
2076 /* This may not be correct, as some cards can have half of channel disabled
2077 * ToDo: identify these cases
2078 */
2079
2080 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2081 pci_name(rinfo->pdev),
2082 rinfo->video_ram / 1024,
2083 rinfo->vram_ddr ? "DDR" : "SDRAM",
2084 rinfo->vram_width);
2085}
2086
2087/*
2088 * Sysfs
2089 */
2090
2091static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2092{
2093 if (off > EDID_LENGTH)
2094 return 0;
2095
2096 if (off + count > EDID_LENGTH)
2097 count = EDID_LENGTH - off;
2098
2099 memcpy(buf, edid + off, count);
2100
2101 return count;
2102}
2103
2104
91a69029
ZR		 2105static ssize_t radeon_show_edid1(struct kobject *kobj,
2106 struct bin_attribute *bin_attr,
2107 char *buf, loff_t off, size_t count)
1da177e4
LT		 2108{
2109 struct device *dev = container_of(kobj, struct device, kobj);
2110 struct pci_dev *pdev = to_pci_dev(dev);
2111 struct fb_info *info = pci_get_drvdata(pdev);
2112 struct radeonfb_info *rinfo = info->par;
2113
2114 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2115}
2116
2117
91a69029
ZR		 2118static ssize_t radeon_show_edid2(struct kobject *kobj,
2119 struct bin_attribute *bin_attr,
2120 char *buf, loff_t off, size_t count)
1da177e4
LT		 2121{
2122 struct device *dev = container_of(kobj, struct device, kobj);
2123 struct pci_dev *pdev = to_pci_dev(dev);
2124 struct fb_info *info = pci_get_drvdata(pdev);
2125 struct radeonfb_info *rinfo = info->par;
2126
2127 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2128}
2129
2130static struct bin_attribute edid1_attr = {
2131 .attr = {
2132 .name = "edid1",
1da177e4
LT		 2133 .mode = 0444,
2134 },
2135 .size = EDID_LENGTH,
2136 .read = radeon_show_edid1,
2137};
2138
2139static struct bin_attribute edid2_attr = {
2140 .attr = {
2141 .name = "edid2",
1da177e4
LT		 2142 .mode = 0444,
2143 },
2144 .size = EDID_LENGTH,
2145 .read = radeon_show_edid2,
2146};
2147
2148
246846fc 2149static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
1da177e4
LT		 2150 const struct pci_device_id *ent)
2151{
2152 struct fb_info *info;
2153 struct radeonfb_info *rinfo;
2154 int ret;
2155
2156 RTRACE("radeonfb_pci_register BEGIN\n");
2157
2158 /* Enable device in PCI config */
2159 ret = pci_enable_device(pdev);
2160 if (ret < 0) {
2161 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2162 pci_name(pdev));
2163 goto err_out;
2164 }
2165
2166 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2167 if (!info) {
2168 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2169 pci_name(pdev));
2170 ret = -ENOMEM;
2171 goto err_disable;
2172 }
2173 rinfo = info->par;
2174 rinfo->info = info;
2175 rinfo->pdev = pdev;
2176
2177 spin_lock_init(&rinfo->reg_lock);
2178 init_timer(&rinfo->lvds_timer);
2179 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2180 rinfo->lvds_timer.data = (unsigned long)rinfo;
2181
2182 strcpy(rinfo->name, "ATI Radeon XX ");
2183 rinfo->name[11] = ent->device >> 8;
2184 rinfo->name[12] = ent->device & 0xFF;
2185 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2186 rinfo->chipset = pdev->device;
2187 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2188 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2189 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2190
2191 /* Set base addrs */
2192 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2193 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2194
2195 /* request the mem regions */
5251bffc 2196 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
1da177e4 2197 if (ret < 0) {
5251bffc
DB		 2198 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2199 pci_name(rinfo->pdev));
1da177e4
LT		 2200 goto err_release_fb;
2201 }
2202
5251bffc
DB		 2203 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2204 if (ret < 0) {
2205 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2206 pci_name(rinfo->pdev));
2207 goto err_release_pci0;
2208 }
2209
1da177e4
LT		 2210 /* map the regions */
2211 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2212 if (!rinfo->mmio_base) {
5251bffc
DB		 2213 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2214 pci_name(rinfo->pdev));
1da177e4 2215 ret = -EIO;
5251bffc 2216 goto err_release_pci2;
1da177e4
LT		 2217 }
2218
2219 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2220
2221 /*
2222 * Check for errata
2223 */
2224 rinfo->errata = 0;
2225 if (rinfo->family == CHIP_FAMILY_R300 &&
2226 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2227 == CFG_ATI_REV_A11)
2228 rinfo->errata |= CHIP_ERRATA_R300_CG;
2229
2230 if (rinfo->family == CHIP_FAMILY_RV200 ||
2231 rinfo->family == CHIP_FAMILY_RS200)
2232 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2233
2234 if (rinfo->family == CHIP_FAMILY_RV100 ||
2235 rinfo->family == CHIP_FAMILY_RS100 ||
2236 rinfo->family == CHIP_FAMILY_RS200)
2237 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2238
9f47df26 2239#if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
1da177e4
LT		 2240 /* On PPC, we obtain the OF device-node pointer to the firmware
2241 * data for this chip
2242 */
2243 rinfo->of_node = pci_device_to_OF_node(pdev);
2244 if (rinfo->of_node == NULL)
2245 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2246 pci_name(rinfo->pdev));
2247
9f47df26
DM		 2248#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2249#ifdef CONFIG_PPC_OF
1da177e4
LT		 2250 /* On PPC, the firmware sets up a memory mapping that tends
2251 * to cause lockups when enabling the engine. We reconfigure
2252 * the card internal memory mappings properly
2253 */
2254 fixup_memory_mappings(rinfo);
2255#endif /* CONFIG_PPC_OF */
2256
2257 /* Get VRAM size and type */
2258 radeon_identify_vram(rinfo);
2259
2260 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2261
2262 do {
2263 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2264 rinfo->mapped_vram);
2265 } while ( rinfo->fb_base == 0 &&
2266 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2267
8d5f7b43
BH		 2268 if (rinfo->fb_base == NULL) {
2269 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2270 pci_name(rinfo->pdev));
1da177e4
LT		 2271 ret = -EIO;
2272 goto err_unmap_rom;
2273 }
2274
2275 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2276 rinfo->mapped_vram/1024);
2277
2278 /*
4a4efbde 2279 * Map the BIOS ROM if any and retrieve PLL parameters from
1da177e4
LT		 2280 * the BIOS. We skip that on mobility chips as the real panel
2281 * values we need aren't in the ROM but in the BIOS image in
2282 * memory. This is definitely not the best meacnism though,
2283 * we really need the arch code to tell us which is the "primary"
2284 * video adapter to use the memory image (or better, the arch
2285 * should provide us a copy of the BIOS image to shield us from
2286 * archs who would store that elsewhere and/or could initialize
2287 * more than one adapter during boot).
2288 */
2289 if (!rinfo->is_mobility)
2290 radeon_map_ROM(rinfo, pdev);
2291
2292 /*
2293 * On x86, the primary display on laptop may have it's BIOS
2294 * ROM elsewhere, try to locate it at the legacy memory hole.
2295 * We probably need to make sure this is the primary display,
2296 * but that is difficult without some arch support.
2297 */
2298#ifdef CONFIG_X86
2299 if (rinfo->bios_seg == NULL)
2300 radeon_find_mem_vbios(rinfo);
2301#endif
2302
2303 /* If both above failed, try the BIOS ROM again for mobility
2304 * chips
2305 */
2306 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2307 radeon_map_ROM(rinfo, pdev);
2308
2309 /* Get informations about the board's PLL */
2310 radeon_get_pllinfo(rinfo);
2311
2312#ifdef CONFIG_FB_RADEON_I2C
2313 /* Register I2C bus */
2314 radeon_create_i2c_busses(rinfo);
2315#endif
2316
2317 /* set all the vital stuff */
2318 radeon_set_fbinfo (rinfo);
2319
2320 /* Probe screen types */
2321 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2322
2323 /* Build mode list, check out panel native model */
2324 radeon_check_modes(rinfo, mode_option);
2325
2326 /* Register some sysfs stuff (should be done better) */
2327 if (rinfo->mon1_EDID)
2328 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2329 if (rinfo->mon2_EDID)
2330 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2331
2332 /* save current mode regs before we switch into the new one
2333 * so we can restore this upon __exit
2334 */
2335 radeon_save_state (rinfo, &rinfo->init_state);
2336 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2337
2338 /* Setup Power Management capabilities */
2339 if (default_dynclk < -1) {
2340 /* -2 is special: means ON on mobility chips and do not
2341 * change on others
2342 */
994aad25 2343 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
1da177e4 2344 } else
994aad25 2345 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
1da177e4
LT		 2346
2347 pci_set_drvdata(pdev, info);
2348
2349 /* Register with fbdev layer */
2350 ret = register_framebuffer(info);
2351 if (ret < 0) {
2352 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2353 pci_name(rinfo->pdev));
2354 goto err_unmap_fb;
2355 }
2356
2357#ifdef CONFIG_MTRR
2358 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2359 rinfo->video_ram,
2360 MTRR_TYPE_WRCOMB, 1);
2361#endif
2362
202d4e60
RP		 2363 if (backlight)
2364 radeonfb_bl_init(rinfo);
1da177e4
LT		 2365
2366 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2367
2368 if (rinfo->bios_seg)
2369 radeon_unmap_ROM(rinfo, pdev);
2370 RTRACE("radeonfb_pci_register END\n");
2371
2372 return 0;
2373err_unmap_fb:
2374 iounmap(rinfo->fb_base);
2375err_unmap_rom:
2376 kfree(rinfo->mon1_EDID);
2377 kfree(rinfo->mon2_EDID);
2378 if (rinfo->mon1_modedb)
2379 fb_destroy_modedb(rinfo->mon1_modedb);
2380 fb_dealloc_cmap(&info->cmap);
2381#ifdef CONFIG_FB_RADEON_I2C
2382 radeon_delete_i2c_busses(rinfo);
2383#endif
2384 if (rinfo->bios_seg)
2385 radeon_unmap_ROM(rinfo, pdev);
2386 iounmap(rinfo->mmio_base);
5251bffc
DB		 2387err_release_pci2:
2388 pci_release_region(pdev, 2);
2389err_release_pci0:
2390 pci_release_region(pdev, 0);
1da177e4 2391err_release_fb:
5251bffc 2392 framebuffer_release(info);
1da177e4 2393err_disable:
1da177e4
LT		 2394err_out:
2395 return ret;
2396}
2397
2398
2399
2400static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2401{
2402 struct fb_info *info = pci_get_drvdata(pdev);
2403 struct radeonfb_info *rinfo = info->par;
2404
2405 if (!rinfo)
2406 return;
5474c120 2407
1da177e4
LT		 2408 radeonfb_pm_exit(rinfo);
2409
3ca34fcb
JS		 2410 if (rinfo->mon1_EDID)
2411 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2412 if (rinfo->mon2_EDID)
2413 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2414
1da177e4
LT		 2415#if 0
2416 /* restore original state
2417 *
2418 * Doesn't quite work yet, I suspect if we come from a legacy
2419 * VGA mode (or worse, text mode), we need to do some VGA black
2420 * magic here that I know nothing about. --BenH
2421 */
2422 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2423 #endif
2424
2425 del_timer_sync(&rinfo->lvds_timer);
2426
2427#ifdef CONFIG_MTRR
2428 if (rinfo->mtrr_hdl >= 0)
2429 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2430#endif
2431
2432 unregister_framebuffer(info);
2433
37ce69a5
RP		 2434 radeonfb_bl_exit(rinfo);
2435
1da177e4
LT		 2436 iounmap(rinfo->mmio_base);
2437 iounmap(rinfo->fb_base);
2438
5251bffc
DB		 2439 pci_release_region(pdev, 2);
2440 pci_release_region(pdev, 0);
1da177e4
LT		 2441
2442 kfree(rinfo->mon1_EDID);
2443 kfree(rinfo->mon2_EDID);
2444 if (rinfo->mon1_modedb)
2445 fb_destroy_modedb(rinfo->mon1_modedb);
2446#ifdef CONFIG_FB_RADEON_I2C
2447 radeon_delete_i2c_busses(rinfo);
2448#endif
2449 fb_dealloc_cmap(&info->cmap);
2450 framebuffer_release(info);
1da177e4
LT		 2451}
2452
2453
2454static struct pci_driver radeonfb_driver = {
2455 .name = "radeonfb",
2456 .id_table = radeonfb_pci_table,
2457 .probe = radeonfb_pci_register,
2458 .remove = __devexit_p(radeonfb_pci_unregister),
2459#ifdef CONFIG_PM
2460 .suspend = radeonfb_pci_suspend,
2461 .resume = radeonfb_pci_resume,
2462#endif /* CONFIG_PM */
2463};
2464
2465#ifndef MODULE
2466static int __init radeonfb_setup (char *options)
2467{
2468 char *this_opt;
2469
2470 if (!options || !*options)
2471 return 0;
2472
2473 while ((this_opt = strsep (&options, ",")) != NULL) {
2474 if (!*this_opt)
2475 continue;
2476
2477 if (!strncmp(this_opt, "noaccel", 7)) {
2478 noaccel = 1;
2479 } else if (!strncmp(this_opt, "mirror", 6)) {
2480 mirror = 1;
2481 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2482 force_dfp = 1;
2483 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2484 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
202d4e60
RP		 2485 } else if (!strncmp(this_opt, "backlight:", 10)) {
2486 backlight = simple_strtoul(this_opt+10, NULL, 0);
1da177e4
LT		 2487#ifdef CONFIG_MTRR
2488 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2489 nomtrr = 1;
2490#endif
2491 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2492 nomodeset = 1;
2493 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2494 force_measure_pll = 1;
2495 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2496 ignore_edid = 1;
994aad25
VB		 2497#if defined(CONFIG_PM) && defined(CONFIG_X86)
2498 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2499 force_sleep = 1;
2500 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2501 ignore_devlist = 1;
2502#endif
1da177e4
LT		 2503 } else
2504 mode_option = this_opt;
2505 }
2506 return 0;
2507}
2508#endif /* MODULE */
2509
2510static int __init radeonfb_init (void)
2511{
2512#ifndef MODULE
2513 char *option = NULL;
2514
2515 if (fb_get_options("radeonfb", &option))
2516 return -ENODEV;
2517 radeonfb_setup(option);
2518#endif
2519 return pci_register_driver (&radeonfb_driver);
2520}
2521
2522
2523static void __exit radeonfb_exit (void)
2524{
2525 pci_unregister_driver (&radeonfb_driver);
2526}
2527
2528module_init(radeonfb_init);
2529module_exit(radeonfb_exit);
2530
2531MODULE_AUTHOR("Ani Joshi");
2532MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2533MODULE_LICENSE("GPL");
2534module_param(noaccel, bool, 0);
2535module_param(default_dynclk, int, 0);
2536MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2537MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2538module_param(nomodeset, bool, 0);
2539MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2540module_param(mirror, bool, 0);
2541MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2542module_param(force_dfp, bool, 0);
2543MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2544module_param(ignore_edid, bool, 0);
2545MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2546module_param(monitor_layout, charp, 0);
2547MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2548module_param(force_measure_pll, bool, 0);
2549MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2550#ifdef CONFIG_MTRR
2551module_param(nomtrr, bool, 0);
2552MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2553#endif
2554module_param(panel_yres, int, 0);
2555MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2556module_param(mode_option, charp, 0);
2557MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
994aad25
VB		 2558#if defined(CONFIG_PM) && defined(CONFIG_X86)
2559module_param(force_sleep, bool, 0);
2560MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2561module_param(ignore_devlist, bool, 0);
2562MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2563#endif
Linux 6.x block layer and io_uring tree(s)