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[ARM] 3239/1: Add ARM optimised swab32
[linux-2.6-block.git] / drivers / video / amba-clcd.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/video/amba-clcd.c
3 *
4 * Copyright (C) 2001 ARM Limited, by David A Rusling
5 * Updated to 2.5, Deep Blue Solutions Ltd.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive
9 * for more details.
10 *
11 * ARM PrimeCell PL110 Color LCD Controller
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/mm.h>
20#include <linux/fb.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/list.h>
24
c6b8fdad 25#include <asm/sizes.h>
1da177e4
LT		 26#include <asm/hardware/amba.h>
27#include <asm/hardware/clock.h>
28
29#include <asm/hardware/amba_clcd.h>
30
31#define to_clcd(info) container_of(info, struct clcd_fb, fb)
32
33/* This is limited to 16 characters when displayed by X startup */
34static const char *clcd_name = "CLCD FB";
35
36/*
37 * Unfortunately, the enable/disable functions may be called either from
38 * process or IRQ context, and we _need_ to delay. This is _not_ good.
39 */
40static inline void clcdfb_sleep(unsigned int ms)
41{
42 if (in_atomic()) {
43 mdelay(ms);
44 } else {
45 msleep(ms);
46 }
47}
48
49static inline void clcdfb_set_start(struct clcd_fb *fb)
50{
51 unsigned long ustart = fb->fb.fix.smem_start;
52 unsigned long lstart;
53
54 ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
55 lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
56
57 writel(ustart, fb->regs + CLCD_UBAS);
58 writel(lstart, fb->regs + CLCD_LBAS);
59}
60
61static void clcdfb_disable(struct clcd_fb *fb)
62{
63 u32 val;
64
65 if (fb->board->disable)
66 fb->board->disable(fb);
67
68 val = readl(fb->regs + CLCD_CNTL);
69 if (val & CNTL_LCDPWR) {
70 val &= ~CNTL_LCDPWR;
71 writel(val, fb->regs + CLCD_CNTL);
72
73 clcdfb_sleep(20);
74 }
75 if (val & CNTL_LCDEN) {
76 val &= ~CNTL_LCDEN;
77 writel(val, fb->regs + CLCD_CNTL);
78 }
79
80 /*
81 * Disable CLCD clock source.
82 */
83 clk_disable(fb->clk);
84}
85
86static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
87{
88 /*
89 * Enable the CLCD clock source.
90 */
91 clk_enable(fb->clk);
92
93 /*
94 * Bring up by first enabling..
95 */
96 cntl |= CNTL_LCDEN;
97 writel(cntl, fb->regs + CLCD_CNTL);
98
99 clcdfb_sleep(20);
100
101 /*
102 * and now apply power.
103 */
104 cntl |= CNTL_LCDPWR;
105 writel(cntl, fb->regs + CLCD_CNTL);
106
107 /*
108 * finally, enable the interface.
109 */
110 if (fb->board->enable)
111 fb->board->enable(fb);
112}
113
114static int
115clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
116{
117 int ret = 0;
118
119 memset(&var->transp, 0, sizeof(var->transp));
120 memset(&var->red, 0, sizeof(var->red));
121 memset(&var->green, 0, sizeof(var->green));
122 memset(&var->blue, 0, sizeof(var->blue));
123
124 switch (var->bits_per_pixel) {
125 case 1:
126 case 2:
127 case 4:
128 case 8:
c4d12b98 129 var->red.length = var->bits_per_pixel;
1da177e4 130 var->red.offset = 0;
c4d12b98 131 var->green.length = var->bits_per_pixel;
1da177e4 132 var->green.offset = 0;
c4d12b98 133 var->blue.length = var->bits_per_pixel;
1da177e4
LT		 134 var->blue.offset = 0;
135 break;
136 case 16:
137 var->red.length = 5;
ed562ab1 138 var->green.length = 6;
1da177e4
LT		 139 var->blue.length = 5;
140 if (fb->panel->cntl & CNTL_BGR) {
ed562ab1 141 var->red.offset = 11;
1da177e4
LT		 142 var->green.offset = 5;
143 var->blue.offset = 0;
144 } else {
145 var->red.offset = 0;
146 var->green.offset = 5;
ed562ab1 147 var->blue.offset = 11;
1da177e4
LT		 148 }
149 break;
82235e91 150 case 32:
1da177e4
LT		 151 if (fb->panel->cntl & CNTL_LCDTFT) {
152 var->red.length = 8;
153 var->green.length = 8;
154 var->blue.length = 8;
155
156 if (fb->panel->cntl & CNTL_BGR) {
157 var->red.offset = 16;
158 var->green.offset = 8;
159 var->blue.offset = 0;
160 } else {
161 var->red.offset = 0;
162 var->green.offset = 8;
163 var->blue.offset = 16;
164 }
165 break;
166 }
167 default:
168 ret = -EINVAL;
169 break;
170 }
171
172 return ret;
173}
174
175static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
176{
177 struct clcd_fb *fb = to_clcd(info);
178 int ret = -EINVAL;
179
180 if (fb->board->check)
181 ret = fb->board->check(fb, var);
82235e91
RK		 182
183 if (ret == 0 &&
184 var->xres_virtual * var->bits_per_pixel / 8 *
185 var->yres_virtual > fb->fb.fix.smem_len)
186 ret = -EINVAL;
187
1da177e4
LT		 188 if (ret == 0)
189 ret = clcdfb_set_bitfields(fb, var);
190
191 return ret;
192}
193
194static int clcdfb_set_par(struct fb_info *info)
195{
196 struct clcd_fb *fb = to_clcd(info);
197 struct clcd_regs regs;
198
199 fb->fb.fix.line_length = fb->fb.var.xres_virtual *
200 fb->fb.var.bits_per_pixel / 8;
201
202 if (fb->fb.var.bits_per_pixel <= 8)
203 fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
204 else
205 fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
206
207 fb->board->decode(fb, &regs);
208
209 clcdfb_disable(fb);
210
211 writel(regs.tim0, fb->regs + CLCD_TIM0);
212 writel(regs.tim1, fb->regs + CLCD_TIM1);
213 writel(regs.tim2, fb->regs + CLCD_TIM2);
214 writel(regs.tim3, fb->regs + CLCD_TIM3);
215
216 clcdfb_set_start(fb);
217
218 clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
219
220 fb->clcd_cntl = regs.cntl;
221
222 clcdfb_enable(fb, regs.cntl);
223
224#ifdef DEBUG
225 printk(KERN_INFO "CLCD: Registers set to\n"
226 KERN_INFO " %08x %08x %08x %08x\n"
227 KERN_INFO " %08x %08x %08x %08x\n",
228 readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
229 readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
230 readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
231 readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
232#endif
233
234 return 0;
235}
236
237static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
238{
239 unsigned int mask = (1 << bf->length) - 1;
240
241 return (val >> (16 - bf->length) & mask) << bf->offset;
242}
243
244/*
245 * Set a single color register. The values supplied have a 16 bit
246 * magnitude. Return != 0 for invalid regno.
247 */
248static int
249clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
250 unsigned int blue, unsigned int transp, struct fb_info *info)
251{
252 struct clcd_fb *fb = to_clcd(info);
253
254 if (regno < 16)
255 fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
256 convert_bitfield(blue, &fb->fb.var.blue) |
257 convert_bitfield(green, &fb->fb.var.green) |
258 convert_bitfield(red, &fb->fb.var.red);
259
1ddb8a16 260 if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
1da177e4
LT		 261 int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
262 u32 val, mask, newval;
263
264 newval = (red >> 11) & 0x001f;
265 newval |= (green >> 6) & 0x03e0;
266 newval |= (blue >> 1) & 0x7c00;
267
268 /*
269 * 3.2.11: if we're configured for big endian
270 * byte order, the palette entries are swapped.
271 */
272 if (fb->clcd_cntl & CNTL_BEBO)
273 regno ^= 1;
274
275 if (regno & 1) {
276 newval <<= 16;
277 mask = 0x0000ffff;
278 } else {
279 mask = 0xffff0000;
280 }
281
282 val = readl(fb->regs + hw_reg) & mask;
283 writel(val | newval, fb->regs + hw_reg);
284 }
285
286 return regno > 255;
287}
288
289/*
290 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
291 * then the caller blanks by setting the CLUT (Color Look Up Table) to all
292 * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
293 * to e.g. a video mode which doesn't support it. Implements VESA suspend
294 * and powerdown modes on hardware that supports disabling hsync/vsync:
295 * blank_mode == 2: suspend vsync
296 * blank_mode == 3: suspend hsync
297 * blank_mode == 4: powerdown
298 */
299static int clcdfb_blank(int blank_mode, struct fb_info *info)
300{
301 struct clcd_fb *fb = to_clcd(info);
302
303 if (blank_mode != 0) {
304 clcdfb_disable(fb);
305 } else {
306 clcdfb_enable(fb, fb->clcd_cntl);
307 }
308 return 0;
309}
310
311static int clcdfb_mmap(struct fb_info *info, struct file *file,
312 struct vm_area_struct *vma)
313{
314 struct clcd_fb *fb = to_clcd(info);
315 unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
316 int ret = -EINVAL;
317
318 len = info->fix.smem_len;
319
320 if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
321 fb->board->mmap)
322 ret = fb->board->mmap(fb, vma);
323
324 return ret;
325}
326
327static struct fb_ops clcdfb_ops = {
328 .owner = THIS_MODULE,
329 .fb_check_var = clcdfb_check_var,
330 .fb_set_par = clcdfb_set_par,
331 .fb_setcolreg = clcdfb_setcolreg,
332 .fb_blank = clcdfb_blank,
333 .fb_fillrect = cfb_fillrect,
334 .fb_copyarea = cfb_copyarea,
335 .fb_imageblit = cfb_imageblit,
1da177e4
LT		 336 .fb_mmap = clcdfb_mmap,
337};
338
339static int clcdfb_register(struct clcd_fb *fb)
340{
341 int ret;
342
343 fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
344 if (IS_ERR(fb->clk)) {
345 ret = PTR_ERR(fb->clk);
346 goto out;
347 }
348
1da177e4
LT		 349 fb->fb.fix.mmio_start = fb->dev->res.start;
350 fb->fb.fix.mmio_len = SZ_4K;
351
352 fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
353 if (!fb->regs) {
354 printk(KERN_ERR "CLCD: unable to remap registers\n");
355 ret = -ENOMEM;
a8d3584a 356 goto free_clk;
1da177e4
LT		 357 }
358
359 fb->fb.fbops = &clcdfb_ops;
360 fb->fb.flags = FBINFO_FLAG_DEFAULT;
361 fb->fb.pseudo_palette = fb->cmap;
362
363 strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
364 fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
365 fb->fb.fix.type_aux = 0;
366 fb->fb.fix.xpanstep = 0;
367 fb->fb.fix.ypanstep = 0;
368 fb->fb.fix.ywrapstep = 0;
369 fb->fb.fix.accel = FB_ACCEL_NONE;
370
371 fb->fb.var.xres = fb->panel->mode.xres;
372 fb->fb.var.yres = fb->panel->mode.yres;
373 fb->fb.var.xres_virtual = fb->panel->mode.xres;
374 fb->fb.var.yres_virtual = fb->panel->mode.yres;
375 fb->fb.var.bits_per_pixel = fb->panel->bpp;
376 fb->fb.var.grayscale = fb->panel->grayscale;
377 fb->fb.var.pixclock = fb->panel->mode.pixclock;
378 fb->fb.var.left_margin = fb->panel->mode.left_margin;
379 fb->fb.var.right_margin = fb->panel->mode.right_margin;
380 fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
381 fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
382 fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
383 fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
384 fb->fb.var.sync = fb->panel->mode.sync;
385 fb->fb.var.vmode = fb->panel->mode.vmode;
386 fb->fb.var.activate = FB_ACTIVATE_NOW;
387 fb->fb.var.nonstd = 0;
388 fb->fb.var.height = fb->panel->height;
389 fb->fb.var.width = fb->panel->width;
390 fb->fb.var.accel_flags = 0;
391
392 fb->fb.monspecs.hfmin = 0;
393 fb->fb.monspecs.hfmax = 100000;
394 fb->fb.monspecs.vfmin = 0;
395 fb->fb.monspecs.vfmax = 400;
396 fb->fb.monspecs.dclkmin = 1000000;
397 fb->fb.monspecs.dclkmax = 100000000;
398
399 /*
400 * Make sure that the bitfields are set appropriately.
401 */
402 clcdfb_set_bitfields(fb, &fb->fb.var);
403
404 /*
405 * Allocate colourmap.
406 */
407 fb_alloc_cmap(&fb->fb.cmap, 256, 0);
408
409 /*
410 * Ensure interrupts are disabled.
411 */
412 writel(0, fb->regs + CLCD_IENB);
413
414 fb_set_var(&fb->fb, &fb->fb.var);
415
416 printk(KERN_INFO "CLCD: %s hardware, %s display\n",
417 fb->board->name, fb->panel->mode.name);
418
419 ret = register_framebuffer(&fb->fb);
420 if (ret == 0)
421 goto out;
422
423 printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
424
425 iounmap(fb->regs);
1da177e4
LT		 426 free_clk:
427 clk_put(fb->clk);
428 out:
429 return ret;
430}
431
432static int clcdfb_probe(struct amba_device *dev, void *id)
433{
434 struct clcd_board *board = dev->dev.platform_data;
435 struct clcd_fb *fb;
436 int ret;
437
438 if (!board)
439 return -EINVAL;
440
441 ret = amba_request_regions(dev, NULL);
442 if (ret) {
443 printk(KERN_ERR "CLCD: unable to reserve regs region\n");
444 goto out;
445 }
446
447 fb = (struct clcd_fb *) kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
448 if (!fb) {
449 printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
450 ret = -ENOMEM;
451 goto free_region;
452 }
453 memset(fb, 0, sizeof(struct clcd_fb));
454
455 fb->dev = dev;
456 fb->board = board;
457
458 ret = fb->board->setup(fb);
459 if (ret)
460 goto free_fb;
461
462 ret = clcdfb_register(fb);
463 if (ret == 0) {
464 amba_set_drvdata(dev, fb);
465 goto out;
466 }
467
468 fb->board->remove(fb);
469 free_fb:
470 kfree(fb);
471 free_region:
472 amba_release_regions(dev);
473 out:
474 return ret;
475}
476
477static int clcdfb_remove(struct amba_device *dev)
478{
479 struct clcd_fb *fb = amba_get_drvdata(dev);
480
481 amba_set_drvdata(dev, NULL);
482
483 clcdfb_disable(fb);
484 unregister_framebuffer(&fb->fb);
485 iounmap(fb->regs);
1da177e4
LT		 486 clk_put(fb->clk);
487
488 fb->board->remove(fb);
489
490 kfree(fb);
491
492 amba_release_regions(dev);
493
494 return 0;
495}
496
497static struct amba_id clcdfb_id_table[] = {
498 {
499 .id = 0x00041110,
e831556f 500 .mask = 0x000ffffe,
1da177e4
LT		 501 },
502 { 0, 0 },
503};
504
505static struct amba_driver clcd_driver = {
506 .drv = {
e831556f 507 .name = "clcd-pl11x",
1da177e4
LT		 508 },
509 .probe = clcdfb_probe,
510 .remove = clcdfb_remove,
511 .id_table = clcdfb_id_table,
512};
513
2c250134 514static int __init amba_clcdfb_init(void)
1da177e4
LT		 515{
516 if (fb_get_options("ambafb", NULL))
517 return -ENODEV;
518
519 return amba_driver_register(&clcd_driver);
520}
521
522module_init(amba_clcdfb_init);
523
524static void __exit amba_clcdfb_exit(void)
525{
526 amba_driver_unregister(&clcd_driver);
527}
528
529module_exit(amba_clcdfb_exit);
530
531MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
532MODULE_LICENSE("GPL");
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