[linux-2.6-block.git] / drivers / usb / typec / typec_wcove.c

// SPDX-License-Identifier: GPL-2.0
/**
 * typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
 *
 * Copyright (C) 2017 Intel Corporation
 * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
 */

#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/usb/tcpm.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/mfd/intel_soc_pmic.h>

/* Register offsets */
#define WCOVE_CHGRIRQ0		0x4e09

#define USBC_CONTROL1		0x7001
#define USBC_CONTROL2		0x7002
#define USBC_CONTROL3		0x7003
#define USBC_CC1_CTRL		0x7004
#define USBC_CC2_CTRL		0x7005
#define USBC_STATUS1		0x7007
#define USBC_STATUS2		0x7008
#define USBC_STATUS3		0x7009
#define USBC_CC1		0x700a
#define USBC_CC2		0x700b
#define USBC_CC1_STATUS		0x700c
#define USBC_CC2_STATUS		0x700d
#define USBC_IRQ1		0x7015
#define USBC_IRQ2		0x7016
#define USBC_IRQMASK1		0x7017
#define USBC_IRQMASK2		0x7018
#define USBC_PDCFG2		0x701a
#define USBC_PDCFG3		0x701b
#define USBC_PDSTATUS		0x701c
#define USBC_RXSTATUS		0x701d
#define USBC_RXINFO		0x701e
#define USBC_TXCMD		0x701f
#define USBC_TXINFO		0x7020
#define USBC_RX_DATA		0x7028
#define USBC_TX_DATA		0x7047

/* Register bits */

#define USBC_CONTROL1_MODE_MASK		0x3
#define   USBC_CONTROL1_MODE_SNK	0
#define   USBC_CONTROL1_MODE_SNKACC	1
#define   USBC_CONTROL1_MODE_SRC	2
#define   USBC_CONTROL1_MODE_SRCACC	3
#define   USBC_CONTROL1_MODE_DRP	4
#define   USBC_CONTROL1_MODE_DRPACC	5
#define   USBC_CONTROL1_MODE_TEST	7
#define USBC_CONTROL1_CURSRC_MASK	0xc
#define   USBC_CONTROL1_CURSRC_UA_0	(0 << 3)
#define   USBC_CONTROL1_CURSRC_UA_80	(1 << 3)
#define   USBC_CONTROL1_CURSRC_UA_180	(2 << 3)
#define   USBC_CONTROL1_CURSRC_UA_330	(3 << 3)
#define USBC_CONTROL1_DRPTOGGLE_RANDOM	0xe0

#define USBC_CONTROL2_UNATT_SNK		BIT(0)
#define USBC_CONTROL2_UNATT_SRC		BIT(1)
#define USBC_CONTROL2_DIS_ST		BIT(2)

#define USBC_CONTROL3_DET_DIS		BIT(0)
#define USBC_CONTROL3_PD_DIS		BIT(1)
#define USBC_CONTROL3_RESETPHY		BIT(2)

#define USBC_CC_CTRL_PU_EN		BIT(0)
#define USBC_CC_CTRL_VCONN_EN		BIT(1)
#define USBC_CC_CTRL_TX_EN		BIT(2)
#define USBC_CC_CTRL_PD_EN		BIT(3)
#define USBC_CC_CTRL_CDET_EN		BIT(4)
#define USBC_CC_CTRL_RDET_EN		BIT(5)
#define USBC_CC_CTRL_ADC_EN		BIT(6)
#define USBC_CC_CTRL_VBUSOK		BIT(7)

#define USBC_STATUS1_DET_ONGOING	BIT(6)
#define USBC_STATUS1_RSLT(r)		((r) & 0xf)
#define USBC_RSLT_NOTHING		0
#define USBC_RSLT_SRC_DEFAULT		1
#define USBC_RSLT_SRC_1_5A		2
#define USBC_RSLT_SRC_3_0A		3
#define USBC_RSLT_SNK			4
#define USBC_RSLT_DEBUG_ACC		5
#define USBC_RSLT_AUDIO_ACC		6
#define USBC_RSLT_UNDEF			15
#define USBC_STATUS1_ORIENT(r)		(((r) >> 4) & 0x3)
#define USBC_ORIENT_NORMAL		1
#define USBC_ORIENT_REVERSE		2

#define USBC_STATUS2_VBUS_REQ		BIT(5)

#define UCSC_CC_STATUS_SNK_RP		BIT(0)
#define UCSC_CC_STATUS_PWRDEFSNK	BIT(1)
#define UCSC_CC_STATUS_PWR_1P5A_SNK	BIT(2)
#define UCSC_CC_STATUS_PWR_3A_SNK	BIT(3)
#define UCSC_CC_STATUS_SRC_RP		BIT(4)
#define UCSC_CC_STATUS_RX(r)		(((r) >> 5) & 0x3)
#define   USBC_CC_STATUS_RD		1
#define   USBC_CC_STATUS_RA		2

#define USBC_IRQ1_ADCDONE1		BIT(2)
#define USBC_IRQ1_OVERTEMP		BIT(1)
#define USBC_IRQ1_SHORT			BIT(0)

#define USBC_IRQ2_CC_CHANGE		BIT(7)
#define USBC_IRQ2_RX_PD			BIT(6)
#define USBC_IRQ2_RX_HR			BIT(5)
#define USBC_IRQ2_RX_CR			BIT(4)
#define USBC_IRQ2_TX_SUCCESS		BIT(3)
#define USBC_IRQ2_TX_FAIL		BIT(2)

#define USBC_IRQMASK1_ALL	(USBC_IRQ1_ADCDONE1 | USBC_IRQ1_OVERTEMP | \
				 USBC_IRQ1_SHORT)

#define USBC_IRQMASK2_ALL	(USBC_IRQ2_CC_CHANGE | USBC_IRQ2_RX_PD | \
				 USBC_IRQ2_RX_HR | USBC_IRQ2_RX_CR | \
				 USBC_IRQ2_TX_SUCCESS | USBC_IRQ2_TX_FAIL)

#define USBC_PDCFG2_SOP			BIT(0)
#define USBC_PDCFG2_SOP_P		BIT(1)
#define USBC_PDCFG2_SOP_PP		BIT(2)
#define USBC_PDCFG2_SOP_P_DEBUG		BIT(3)
#define USBC_PDCFG2_SOP_PP_DEBUG	BIT(4)

#define USBC_PDCFG3_DATAROLE_SHIFT	1
#define USBC_PDCFG3_SOP_SHIFT		2

#define USBC_RXSTATUS_RXCLEAR		BIT(0)
#define USBC_RXSTATUS_RXDATA		BIT(7)

#define USBC_RXINFO_RXBYTES(i)		(((i) >> 3) & 0x1f)

#define USBC_TXCMD_BUF_RDY		BIT(0)
#define USBC_TXCMD_START		BIT(1)
#define USBC_TXCMD_NOP			(0 << 5)
#define USBC_TXCMD_MSG			(1 << 5)
#define USBC_TXCMD_CR			(2 << 5)
#define USBC_TXCMD_HR			(3 << 5)
#define USBC_TXCMD_BIST			(4 << 5)

#define USBC_TXINFO_RETRIES(d)		(d << 3)

struct wcove_typec {
	struct mutex lock; /* device lock */
	struct device *dev;
	struct regmap *regmap;
	guid_t guid;

	bool vbus;

	struct tcpc_dev tcpc;
	struct tcpm_port *tcpm;
};

#define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)

enum wcove_typec_func {
	WCOVE_FUNC_DRIVE_VBUS = 1,
	WCOVE_FUNC_ORIENTATION,
	WCOVE_FUNC_ROLE,
	WCOVE_FUNC_DRIVE_VCONN,
};

enum wcove_typec_orientation {
	WCOVE_ORIENTATION_NORMAL,
	WCOVE_ORIENTATION_REVERSE,
};

enum wcove_typec_role {
	WCOVE_ROLE_HOST,
	WCOVE_ROLE_DEVICE,
};

#define WCOVE_DSM_UUID		"482383f0-2876-4e49-8685-db66211af037"

static int wcove_typec_func(struct wcove_typec *wcove,
			    enum wcove_typec_func func, int param)
{
	union acpi_object *obj;
	union acpi_object tmp;
	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);

	tmp.type = ACPI_TYPE_INTEGER;
	tmp.integer.value = param;

	obj = acpi_evaluate_dsm(ACPI_HANDLE(wcove->dev), &wcove->guid, 1, func,
				&argv4);
	if (!obj) {
		dev_err(wcove->dev, "%s: failed to evaluate _DSM\n", __func__);
		return -EIO;
	}

	ACPI_FREE(obj);
	return 0;
}

static int wcove_init(struct tcpc_dev *tcpc)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	int ret;

	/* Unmask everything */
	ret = regmap_write(wcove->regmap, USBC_IRQMASK1, 0);
	if (ret)
		return ret;

	return regmap_write(wcove->regmap, USBC_IRQMASK2, 0);
}

static int wcove_get_vbus(struct tcpc_dev *tcpc)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	unsigned int cc1ctrl;
	int ret;

	ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
	if (ret)
		return ret;

	wcove->vbus = !!(cc1ctrl & USBC_CC_CTRL_VBUSOK);

	return wcove->vbus;
}

static int wcove_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);

	return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VBUS, on);
}

static int wcove_set_vconn(struct tcpc_dev *tcpc, bool on)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);

	return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, on);
}

static enum typec_cc_status wcove_to_typec_cc(unsigned int cc)
{
	if (cc & UCSC_CC_STATUS_SNK_RP) {
		if (cc & UCSC_CC_STATUS_PWRDEFSNK)
			return TYPEC_CC_RP_DEF;
		else if (cc & UCSC_CC_STATUS_PWR_1P5A_SNK)
			return TYPEC_CC_RP_1_5;
		else if (cc & UCSC_CC_STATUS_PWR_3A_SNK)
			return TYPEC_CC_RP_3_0;
	} else {
		switch (UCSC_CC_STATUS_RX(cc)) {
		case USBC_CC_STATUS_RD:
			return TYPEC_CC_RD;
		case USBC_CC_STATUS_RA:
			return TYPEC_CC_RA;
		default:
			break;
		}
	}
	return TYPEC_CC_OPEN;
}

static int wcove_get_cc(struct tcpc_dev *tcpc, enum typec_cc_status *cc1,
			enum typec_cc_status *cc2)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	unsigned int cc1_status;
	unsigned int cc2_status;
	int ret;

	ret = regmap_read(wcove->regmap, USBC_CC1_STATUS, &cc1_status);
	if (ret)
		return ret;

	ret = regmap_read(wcove->regmap, USBC_CC2_STATUS, &cc2_status);
	if (ret)
		return ret;

	*cc1 = wcove_to_typec_cc(cc1_status);
	*cc2 = wcove_to_typec_cc(cc2_status);

	return 0;
}

static int wcove_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
{
	/* XXX: Relying on the HW FSM to configure things correctly for now */
	return 0;
}

static int wcove_set_polarity(struct tcpc_dev *tcpc, enum typec_cc_polarity pol)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);

	return wcove_typec_func(wcove, WCOVE_FUNC_ORIENTATION, pol);
}

static int wcove_set_current_limit(struct tcpc_dev *tcpc, u32 max_ma, u32 mv)
{
	return 0;
}

static int wcove_set_roles(struct tcpc_dev *tcpc, bool attached,
			   enum typec_role role, enum typec_data_role data)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	unsigned int val;
	int ret;

	ret = wcove_typec_func(wcove, WCOVE_FUNC_ROLE, data == TYPEC_HOST ?
			       WCOVE_ROLE_HOST : WCOVE_ROLE_DEVICE);
	if (ret)
		return ret;

	val = role;
	val |= data << USBC_PDCFG3_DATAROLE_SHIFT;
	val |= PD_REV20 << USBC_PDCFG3_SOP_SHIFT;

	return regmap_write(wcove->regmap, USBC_PDCFG3, val);
}

static int wcove_set_pd_rx(struct tcpc_dev *tcpc, bool on)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);

	return regmap_write(wcove->regmap, USBC_PDCFG2,
			    on ? USBC_PDCFG2_SOP : 0);
}

static int wcove_pd_transmit(struct tcpc_dev *tcpc,
			     enum tcpm_transmit_type type,
			     const struct pd_message *msg)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	unsigned int info = 0;
	unsigned int cmd;
	int ret;

	ret = regmap_read(wcove->regmap, USBC_TXCMD, &cmd);
	if (ret)
		return ret;

	if (!(cmd & USBC_TXCMD_BUF_RDY)) {
		dev_warn(wcove->dev, "%s: Last transmission still ongoing!",
			 __func__);
		return -EBUSY;
	}

	if (msg) {
		const u8 *data = (void *)msg;
		int i;

		for (i = 0; i < pd_header_cnt(msg->header) * 4 + 2; i++) {
			ret = regmap_write(wcove->regmap, USBC_TX_DATA + i,
					   data[i]);
			if (ret)
				return ret;
		}
	}

	switch (type) {
	case TCPC_TX_SOP:
	case TCPC_TX_SOP_PRIME:
	case TCPC_TX_SOP_PRIME_PRIME:
	case TCPC_TX_SOP_DEBUG_PRIME:
	case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
		info = type + 1;
		cmd = USBC_TXCMD_MSG;
		break;
	case TCPC_TX_HARD_RESET:
		cmd = USBC_TXCMD_HR;
		break;
	case TCPC_TX_CABLE_RESET:
		cmd = USBC_TXCMD_CR;
		break;
	case TCPC_TX_BIST_MODE_2:
		cmd = USBC_TXCMD_BIST;
		break;
	default:
		return -EINVAL;
	}

	/* NOTE Setting maximum number of retries (7) */
	ret = regmap_write(wcove->regmap, USBC_TXINFO,
			   info | USBC_TXINFO_RETRIES(7));
	if (ret)
		return ret;

	return regmap_write(wcove->regmap, USBC_TXCMD, cmd | USBC_TXCMD_START);
}

static int wcove_start_drp_toggling(struct tcpc_dev *tcpc,
				    enum typec_cc_status cc)
{
	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	unsigned int usbc_ctrl;

	usbc_ctrl = USBC_CONTROL1_MODE_DRP | USBC_CONTROL1_DRPTOGGLE_RANDOM;

	switch (cc) {
	case TYPEC_CC_RP_1_5:
		usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_180;
		break;
	case TYPEC_CC_RP_3_0:
		usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_330;
		break;
	default:
		usbc_ctrl |= USBC_CONTROL1_CURSRC_UA_80;
		break;
	}

	return regmap_write(wcove->regmap, USBC_CONTROL1, usbc_ctrl);
}

static int wcove_read_rx_buffer(struct wcove_typec *wcove, void *msg)
{
	unsigned int info;
	int ret;
	int i;

	ret = regmap_read(wcove->regmap, USBC_RXINFO, &info);
	if (ret)
		return ret;

	/* FIXME: Check that USBC_RXINFO_RXBYTES(info) matches the header */

	for (i = 0; i < USBC_RXINFO_RXBYTES(info); i++) {
		ret = regmap_read(wcove->regmap, USBC_RX_DATA + i, msg + i);
		if (ret)
			return ret;
	}

	return regmap_write(wcove->regmap, USBC_RXSTATUS,
			    USBC_RXSTATUS_RXCLEAR);
}

static irqreturn_t wcove_typec_irq(int irq, void *data)
{
	struct wcove_typec *wcove = data;
	unsigned int usbc_irq1 = 0;
	unsigned int usbc_irq2 = 0;
	unsigned int cc1ctrl;
	int ret;

	mutex_lock(&wcove->lock);

	/* Read.. */
	ret = regmap_read(wcove->regmap, USBC_IRQ1, &usbc_irq1);
	if (ret)
		goto err;

	ret = regmap_read(wcove->regmap, USBC_IRQ2, &usbc_irq2);
	if (ret)
		goto err;

	ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
	if (ret)
		goto err;

	if (!wcove->tcpm)
		goto err;

	/* ..check.. */
	if (usbc_irq1 & USBC_IRQ1_OVERTEMP) {
		dev_err(wcove->dev, "VCONN Switch Over Temperature!\n");
		wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
		/* REVISIT: Report an error? */
	}

	if (usbc_irq1 & USBC_IRQ1_SHORT) {
		dev_err(wcove->dev, "VCONN Switch Short Circuit!\n");
		wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
		/* REVISIT: Report an error? */
	}

	if (wcove->vbus != !!(cc1ctrl & USBC_CC_CTRL_VBUSOK))
		tcpm_vbus_change(wcove->tcpm);

	/* REVISIT: See if tcpm code can be made to consider Type-C HW FSMs */
	if (usbc_irq2 & USBC_IRQ2_CC_CHANGE)
		tcpm_cc_change(wcove->tcpm);

	if (usbc_irq2 & USBC_IRQ2_RX_PD) {
		unsigned int status;

		/*
		 * FIXME: Need to check if TX is ongoing and report
		 * TX_DIREGARDED if needed?
		 */

		ret = regmap_read(wcove->regmap, USBC_RXSTATUS, &status);
		if (ret)
			goto err;

		/* Flush all buffers */
		while (status & USBC_RXSTATUS_RXDATA) {
			struct pd_message msg;

			ret = wcove_read_rx_buffer(wcove, &msg);
			if (ret) {
				dev_err(wcove->dev, "%s: RX read failed\n",
					__func__);
				goto err;
			}

			tcpm_pd_receive(wcove->tcpm, &msg);

			ret = regmap_read(wcove->regmap, USBC_RXSTATUS,
					  &status);
			if (ret)
				goto err;
		}
	}

	if (usbc_irq2 & USBC_IRQ2_RX_HR)
		tcpm_pd_hard_reset(wcove->tcpm);

	/* REVISIT: if (usbc_irq2 & USBC_IRQ2_RX_CR) */

	if (usbc_irq2 & USBC_IRQ2_TX_SUCCESS)
		tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_SUCCESS);

	if (usbc_irq2 & USBC_IRQ2_TX_FAIL)
		tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_FAILED);

err:
	/* ..and clear. */
	if (usbc_irq1) {
		ret = regmap_write(wcove->regmap, USBC_IRQ1, usbc_irq1);
		if (ret)
			dev_WARN(wcove->dev, "%s failed to clear IRQ1\n",
				 __func__);
	}

	if (usbc_irq2) {
		ret = regmap_write(wcove->regmap, USBC_IRQ2, usbc_irq2);
		if (ret)
			dev_WARN(wcove->dev, "%s failed to clear IRQ2\n",
				 __func__);
	}

	/* REVISIT: Clear WhiskeyCove CHGR Type-C interrupt */
	regmap_write(wcove->regmap, WCOVE_CHGRIRQ0, BIT(5));

	mutex_unlock(&wcove->lock);
	return IRQ_HANDLED;
}

/*
 * The following power levels should be safe to use with Joule board.
 */
static const u32 src_pdo[] = {
	PDO_FIXED(5000, 1500, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
		  PDO_FIXED_USB_COMM),
};

static const u32 snk_pdo[] = {
	PDO_FIXED(12000, 3000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |
		  PDO_FIXED_USB_COMM),
	PDO_BATT(4750, 12000, 15000),
	PDO_VAR(4750, 12000, 3000),
};

static struct tcpc_config wcove_typec_config = {
	.src_pdo = src_pdo,
	.nr_src_pdo = ARRAY_SIZE(src_pdo),
	.snk_pdo = snk_pdo,
	.nr_snk_pdo = ARRAY_SIZE(snk_pdo),

	.max_snk_mv = 12000,
	.max_snk_ma = 3000,
	.max_snk_mw = 36000,
	.operating_snk_mw = 15000,

	.type = TYPEC_PORT_DRP,
	.default_role = TYPEC_SINK,
};

static int wcove_typec_probe(struct platform_device *pdev)
{
	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
	struct wcove_typec *wcove;
	int irq;
	int ret;

	wcove = devm_kzalloc(&pdev->dev, sizeof(*wcove), GFP_KERNEL);
	if (!wcove)
		return -ENOMEM;

	mutex_init(&wcove->lock);
	wcove->dev = &pdev->dev;
	wcove->regmap = pmic->regmap;

	irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
				  platform_get_irq(pdev, 0));
	if (irq < 0)
		return irq;

	ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
	if (ret)
		return ret;

	if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &wcove->guid, 0, 0x1f)) {
		dev_err(&pdev->dev, "Missing _DSM functions\n");
		return -ENODEV;
	}

	wcove->tcpc.init = wcove_init;
	wcove->tcpc.get_vbus = wcove_get_vbus;
	wcove->tcpc.set_vbus = wcove_set_vbus;
	wcove->tcpc.set_cc = wcove_set_cc;
	wcove->tcpc.get_cc = wcove_get_cc;
	wcove->tcpc.set_polarity = wcove_set_polarity;
	wcove->tcpc.set_vconn = wcove_set_vconn;
	wcove->tcpc.set_current_limit = wcove_set_current_limit;
	wcove->tcpc.start_drp_toggling = wcove_start_drp_toggling;

	wcove->tcpc.set_pd_rx = wcove_set_pd_rx;
	wcove->tcpc.set_roles = wcove_set_roles;
	wcove->tcpc.pd_transmit = wcove_pd_transmit;

	wcove->tcpc.config = &wcove_typec_config;

	wcove->tcpm = tcpm_register_port(wcove->dev, &wcove->tcpc);
	if (IS_ERR(wcove->tcpm))
		return PTR_ERR(wcove->tcpm);

	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
					wcove_typec_irq, IRQF_ONESHOT,
					"wcove_typec", wcove);
	if (ret) {
		tcpm_unregister_port(wcove->tcpm);
		return ret;
	}

	platform_set_drvdata(pdev, wcove);
	return 0;
}

static int wcove_typec_remove(struct platform_device *pdev)
{
	struct wcove_typec *wcove = platform_get_drvdata(pdev);
	unsigned int val;

	/* Mask everything */
	regmap_read(wcove->regmap, USBC_IRQMASK1, &val);
	regmap_write(wcove->regmap, USBC_IRQMASK1, val | USBC_IRQMASK1_ALL);
	regmap_read(wcove->regmap, USBC_IRQMASK2, &val);
	regmap_write(wcove->regmap, USBC_IRQMASK2, val | USBC_IRQMASK2_ALL);

	tcpm_unregister_port(wcove->tcpm);

	return 0;
}

static struct platform_driver wcove_typec_driver = {
	.driver = {
		.name		= "bxt_wcove_usbc",
	},
	.probe			= wcove_typec_probe,
	.remove			= wcove_typec_remove,
};

module_platform_driver(wcove_typec_driver);

MODULE_AUTHOR("Intel Corporation");
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("WhiskeyCove PMIC USB Type-C PHY driver");
MODULE_ALIAS("platform:bxt_wcove_usbc");
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
d2061f9c HK	2	/**
	3	* typec_wcove.c - WhiskeyCove PMIC USB Type-C PHY driver
	4	*
	5	* Copyright (C) 2017 Intel Corporation
	6	* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
d2061f9c HK	7	*/
	8
	9	#include <linux/acpi.h>
	10	#include <linux/module.h>
3c4fb9f1	11	#include <linux/usb/tcpm.h>
d2061f9c	12	#include <linux/interrupt.h>
d2061f9c HK	13	#include <linux/platform_device.h>
	14	#include <linux/mfd/intel_soc_pmic.h>
	15
	16	/* Register offsets */
	17	#define WCOVE_CHGRIRQ0 0x4e09
d2061f9c HK	18
	19	#define USBC_CONTROL1 0x7001
	20	#define USBC_CONTROL2 0x7002
	21	#define USBC_CONTROL3 0x7003
	22	#define USBC_CC1_CTRL 0x7004
	23	#define USBC_CC2_CTRL 0x7005
	24	#define USBC_STATUS1 0x7007
	25	#define USBC_STATUS2 0x7008
	26	#define USBC_STATUS3 0x7009
3c4fb9f1 HK	27	#define USBC_CC1 0x700a
	28	#define USBC_CC2 0x700b
	29	#define USBC_CC1_STATUS 0x700c
	30	#define USBC_CC2_STATUS 0x700d
d2061f9c HK	31	#define USBC_IRQ1 0x7015
	32	#define USBC_IRQ2 0x7016
	33	#define USBC_IRQMASK1 0x7017
	34	#define USBC_IRQMASK2 0x7018
3c4fb9f1 HK	35	#define USBC_PDCFG2 0x701a
	36	#define USBC_PDCFG3 0x701b
	37	#define USBC_PDSTATUS 0x701c
	38	#define USBC_RXSTATUS 0x701d
	39	#define USBC_RXINFO 0x701e
	40	#define USBC_TXCMD 0x701f
	41	#define USBC_TXINFO 0x7020
	42	#define USBC_RX_DATA 0x7028
	43	#define USBC_TX_DATA 0x7047
d2061f9c HK	44
	45	/* Register bits */
	46
3c4fb9f1 HK	47	#define USBC_CONTROL1_MODE_MASK 0x3
	48	#define USBC_CONTROL1_MODE_SNK 0
	49	#define USBC_CONTROL1_MODE_SNKACC 1
	50	#define USBC_CONTROL1_MODE_SRC 2
	51	#define USBC_CONTROL1_MODE_SRCACC 3
	52	#define USBC_CONTROL1_MODE_DRP 4
	53	#define USBC_CONTROL1_MODE_DRPACC 5
	54	#define USBC_CONTROL1_MODE_TEST 7
	55	#define USBC_CONTROL1_CURSRC_MASK 0xc
	56	#define USBC_CONTROL1_CURSRC_UA_0 (0 << 3)
	57	#define USBC_CONTROL1_CURSRC_UA_80 (1 << 3)
	58	#define USBC_CONTROL1_CURSRC_UA_180 (2 << 3)
	59	#define USBC_CONTROL1_CURSRC_UA_330 (3 << 3)
	60	#define USBC_CONTROL1_DRPTOGGLE_RANDOM 0xe0
d2061f9c HK	61
	62	#define USBC_CONTROL2_UNATT_SNK BIT(0)
	63	#define USBC_CONTROL2_UNATT_SRC BIT(1)
	64	#define USBC_CONTROL2_DIS_ST BIT(2)
	65
3c4fb9f1	66	#define USBC_CONTROL3_DET_DIS BIT(0)
d2061f9c	67	#define USBC_CONTROL3_PD_DIS BIT(1)
3c4fb9f1	68	#define USBC_CONTROL3_RESETPHY BIT(2)
d2061f9c	69
3c4fb9f1	70	#define USBC_CC_CTRL_PU_EN BIT(0)
d2061f9c	71	#define USBC_CC_CTRL_VCONN_EN BIT(1)
3c4fb9f1 HK	72	#define USBC_CC_CTRL_TX_EN BIT(2)
	73	#define USBC_CC_CTRL_PD_EN BIT(3)
	74	#define USBC_CC_CTRL_CDET_EN BIT(4)
	75	#define USBC_CC_CTRL_RDET_EN BIT(5)
	76	#define USBC_CC_CTRL_ADC_EN BIT(6)
	77	#define USBC_CC_CTRL_VBUSOK BIT(7)
d2061f9c HK	78
	79	#define USBC_STATUS1_DET_ONGOING BIT(6)
	80	#define USBC_STATUS1_RSLT(r) ((r) & 0xf)
	81	#define USBC_RSLT_NOTHING 0
	82	#define USBC_RSLT_SRC_DEFAULT 1
	83	#define USBC_RSLT_SRC_1_5A 2
	84	#define USBC_RSLT_SRC_3_0A 3
	85	#define USBC_RSLT_SNK 4
	86	#define USBC_RSLT_DEBUG_ACC 5
	87	#define USBC_RSLT_AUDIO_ACC 6
	88	#define USBC_RSLT_UNDEF 15
	89	#define USBC_STATUS1_ORIENT(r) (((r) >> 4) & 0x3)
	90	#define USBC_ORIENT_NORMAL 1
	91	#define USBC_ORIENT_REVERSE 2
	92
	93	#define USBC_STATUS2_VBUS_REQ BIT(5)
	94
3c4fb9f1 HK	95	#define UCSC_CC_STATUS_SNK_RP BIT(0)
	96	#define UCSC_CC_STATUS_PWRDEFSNK BIT(1)
	97	#define UCSC_CC_STATUS_PWR_1P5A_SNK BIT(2)
	98	#define UCSC_CC_STATUS_PWR_3A_SNK BIT(3)
	99	#define UCSC_CC_STATUS_SRC_RP BIT(4)
	100	#define UCSC_CC_STATUS_RX(r) (((r) >> 5) & 0x3)
	101	#define USBC_CC_STATUS_RD 1
	102	#define USBC_CC_STATUS_RA 2
	103
d2061f9c HK	104	#define USBC_IRQ1_ADCDONE1 BIT(2)
	105	#define USBC_IRQ1_OVERTEMP BIT(1)
	106	#define USBC_IRQ1_SHORT BIT(0)
	107
	108	#define USBC_IRQ2_CC_CHANGE BIT(7)
	109	#define USBC_IRQ2_RX_PD BIT(6)
	110	#define USBC_IRQ2_RX_HR BIT(5)
	111	#define USBC_IRQ2_RX_CR BIT(4)
	112	#define USBC_IRQ2_TX_SUCCESS BIT(3)
	113	#define USBC_IRQ2_TX_FAIL BIT(2)
	114
	115	#define USBC_IRQMASK1_ALL (USBC_IRQ1_ADCDONE1 \| USBC_IRQ1_OVERTEMP \| \
	116	USBC_IRQ1_SHORT)
	117
	118	#define USBC_IRQMASK2_ALL (USBC_IRQ2_CC_CHANGE \| USBC_IRQ2_RX_PD \| \
	119	USBC_IRQ2_RX_HR \| USBC_IRQ2_RX_CR \| \
	120	USBC_IRQ2_TX_SUCCESS \| USBC_IRQ2_TX_FAIL)
	121
3c4fb9f1 HK	122	#define USBC_PDCFG2_SOP BIT(0)
	123	#define USBC_PDCFG2_SOP_P BIT(1)
	124	#define USBC_PDCFG2_SOP_PP BIT(2)
	125	#define USBC_PDCFG2_SOP_P_DEBUG BIT(3)
	126	#define USBC_PDCFG2_SOP_PP_DEBUG BIT(4)
	127
	128	#define USBC_PDCFG3_DATAROLE_SHIFT 1
	129	#define USBC_PDCFG3_SOP_SHIFT 2
	130
	131	#define USBC_RXSTATUS_RXCLEAR BIT(0)
	132	#define USBC_RXSTATUS_RXDATA BIT(7)
	133
	134	#define USBC_RXINFO_RXBYTES(i) (((i) >> 3) & 0x1f)
	135
	136	#define USBC_TXCMD_BUF_RDY BIT(0)
	137	#define USBC_TXCMD_START BIT(1)
	138	#define USBC_TXCMD_NOP (0 << 5)
	139	#define USBC_TXCMD_MSG (1 << 5)
	140	#define USBC_TXCMD_CR (2 << 5)
	141	#define USBC_TXCMD_HR (3 << 5)
	142	#define USBC_TXCMD_BIST (4 << 5)
	143
	144	#define USBC_TXINFO_RETRIES(d) (d << 3)
	145
d2061f9c HK	146	struct wcove_typec {
	147	struct mutex lock; /* device lock */
	148	struct device *dev;
	149	struct regmap *regmap;
3c4fb9f1 HK	150	guid_t guid;
	151
	152	bool vbus;
	153
	154	struct tcpc_dev tcpc;
	155	struct tcpm_port *tcpm;
d2061f9c HK	156	};
d2061f9c HK	157
3c4fb9f1 HK	158	#define tcpc_to_wcove(_tcpc_) container_of(_tcpc_, struct wcove_typec, tcpc)
3c4fb9f1 HK	159
d2061f9c HK	160	enum wcove_typec_func {
	161	WCOVE_FUNC_DRIVE_VBUS = 1,
	162	WCOVE_FUNC_ORIENTATION,
	163	WCOVE_FUNC_ROLE,
	164	WCOVE_FUNC_DRIVE_VCONN,
	165	};
	166
	167	enum wcove_typec_orientation {
	168	WCOVE_ORIENTATION_NORMAL,
	169	WCOVE_ORIENTATION_REVERSE,
	170	};
	171
	172	enum wcove_typec_role {
	173	WCOVE_ROLE_HOST,
	174	WCOVE_ROLE_DEVICE,
	175	};
	176
3c4fb9f1	177	#define WCOVE_DSM_UUID "482383f0-2876-4e49-8685-db66211af037"
d2061f9c HK	178
	179	static int wcove_typec_func(struct wcove_typec *wcove,
	180	enum wcove_typec_func func, int param)
	181	{
	182	union acpi_object *obj;
	183	union acpi_object tmp;
	184	union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
	185
	186	tmp.type = ACPI_TYPE_INTEGER;
	187	tmp.integer.value = param;
	188
3c4fb9f1	189	obj = acpi_evaluate_dsm(ACPI_HANDLE(wcove->dev), &wcove->guid, 1, func,
d2061f9c HK	190	&argv4);
	191	if (!obj) {
	192	dev_err(wcove->dev, "%s: failed to evaluate _DSM\n", __func__);
	193	return -EIO;
	194	}
	195
	196	ACPI_FREE(obj);
	197	return 0;
	198	}
	199
3c4fb9f1	200	static int wcove_init(struct tcpc_dev *tcpc)
d2061f9c	201	{
3c4fb9f1	202	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
d2061f9c HK	203	int ret;
d2061f9c HK	204
3c4fb9f1 HK	205	/* Unmask everything */
3c4fb9f1 HK	206	ret = regmap_write(wcove->regmap, USBC_IRQMASK1, 0);
d2061f9c	207	if (ret)
3c4fb9f1	208	return ret;
d2061f9c	209
3c4fb9f1 HK	210	return regmap_write(wcove->regmap, USBC_IRQMASK2, 0);
3c4fb9f1 HK	211	}
d2061f9c	212
3c4fb9f1 HK	213	static int wcove_get_vbus(struct tcpc_dev *tcpc)
	214	{
	215	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	216	unsigned int cc1ctrl;
	217	int ret;
d2061f9c	218
3c4fb9f1	219	ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
d2061f9c	220	if (ret)
3c4fb9f1	221	return ret;
d2061f9c	222
3c4fb9f1	223	wcove->vbus = !!(cc1ctrl & USBC_CC_CTRL_VBUSOK);
d2061f9c	224
3c4fb9f1 HK	225	return wcove->vbus;
3c4fb9f1 HK	226	}
d2061f9c	227
3c4fb9f1 HK	228	static int wcove_set_vbus(struct tcpc_dev *tcpc, bool on, bool sink)
	229	{
	230	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
d2061f9c	231
3c4fb9f1 HK	232	return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VBUS, on);
	233	}
	234
	235	static int wcove_set_vconn(struct tcpc_dev *tcpc, bool on)
	236	{
	237	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	238
	239	return wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, on);
	240	}
	241
	242	static enum typec_cc_status wcove_to_typec_cc(unsigned int cc)
	243	{
	244	if (cc & UCSC_CC_STATUS_SNK_RP) {
	245	if (cc & UCSC_CC_STATUS_PWRDEFSNK)
	246	return TYPEC_CC_RP_DEF;
	247	else if (cc & UCSC_CC_STATUS_PWR_1P5A_SNK)
	248	return TYPEC_CC_RP_1_5;
	249	else if (cc & UCSC_CC_STATUS_PWR_3A_SNK)
	250	return TYPEC_CC_RP_3_0;
	251	} else {
	252	switch (UCSC_CC_STATUS_RX(cc)) {
	253	case USBC_CC_STATUS_RD:
	254	return TYPEC_CC_RD;
	255	case USBC_CC_STATUS_RA:
	256	return TYPEC_CC_RA;
	257	default:
	258	break;
d2061f9c HK	259	}
d2061f9c HK	260	}
3c4fb9f1 HK	261	return TYPEC_CC_OPEN;
3c4fb9f1 HK	262	}
d2061f9c	263
3c4fb9f1 HK	264	static int wcove_get_cc(struct tcpc_dev tcpc, enum typec_cc_status cc1,
	265	enum typec_cc_status *cc2)
	266	{
	267	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	268	unsigned int cc1_status;
	269	unsigned int cc2_status;
	270	int ret;
d2061f9c	271
3c4fb9f1 HK	272	ret = regmap_read(wcove->regmap, USBC_CC1_STATUS, &cc1_status);
	273	if (ret)
	274	return ret;
d2061f9c	275
3c4fb9f1 HK	276	ret = regmap_read(wcove->regmap, USBC_CC2_STATUS, &cc2_status);
	277	if (ret)
	278	return ret;
d2061f9c	279
3c4fb9f1 HK	280	*cc1 = wcove_to_typec_cc(cc1_status);
3c4fb9f1 HK	281	*cc2 = wcove_to_typec_cc(cc2_status);
d2061f9c	282
3c4fb9f1 HK	283	return 0;
3c4fb9f1 HK	284	}
d2061f9c	285
3c4fb9f1 HK	286	static int wcove_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
	287	{
	288	/* XXX: Relying on the HW FSM to configure things correctly for now */
	289	return 0;
	290	}
d2061f9c	291
3c4fb9f1 HK	292	static int wcove_set_polarity(struct tcpc_dev *tcpc, enum typec_cc_polarity pol)
	293	{
	294	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
d2061f9c	295
3c4fb9f1 HK	296	return wcove_typec_func(wcove, WCOVE_FUNC_ORIENTATION, pol);
	297	}
	298
	299	static int wcove_set_current_limit(struct tcpc_dev *tcpc, u32 max_ma, u32 mv)
	300	{
	301	return 0;
	302	}
	303
	304	static int wcove_set_roles(struct tcpc_dev *tcpc, bool attached,
	305	enum typec_role role, enum typec_data_role data)
	306	{
	307	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	308	unsigned int val;
	309	int ret;
	310
	311	ret = wcove_typec_func(wcove, WCOVE_FUNC_ROLE, data == TYPEC_HOST ?
	312	WCOVE_ROLE_HOST : WCOVE_ROLE_DEVICE);
	313	if (ret)
	314	return ret;
	315
	316	val = role;
	317	val \|= data << USBC_PDCFG3_DATAROLE_SHIFT;
	318	val \|= PD_REV20 << USBC_PDCFG3_SOP_SHIFT;
	319
	320	return regmap_write(wcove->regmap, USBC_PDCFG3, val);
	321	}
	322
	323	static int wcove_set_pd_rx(struct tcpc_dev *tcpc, bool on)
	324	{
	325	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	326
	327	return regmap_write(wcove->regmap, USBC_PDCFG2,
	328	on ? USBC_PDCFG2_SOP : 0);
	329	}
	330
	331	static int wcove_pd_transmit(struct tcpc_dev *tcpc,
	332	enum tcpm_transmit_type type,
	333	const struct pd_message *msg)
	334	{
	335	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	336	unsigned int info = 0;
	337	unsigned int cmd;
	338	int ret;
	339
	340	ret = regmap_read(wcove->regmap, USBC_TXCMD, &cmd);
	341	if (ret)
	342	return ret;
	343
	344	if (!(cmd & USBC_TXCMD_BUF_RDY)) {
	345	dev_warn(wcove->dev, "%s: Last transmission still ongoing!",
	346	__func__);
	347	return -EBUSY;
d2061f9c HK	348	}
d2061f9c HK	349
3c4fb9f1 HK	350	if (msg) {
	351	const u8 data = (void )msg;
	352	int i;
	353
	354	for (i = 0; i < pd_header_cnt(msg->header) * 4 + 2; i++) {
	355	ret = regmap_write(wcove->regmap, USBC_TX_DATA + i,
	356	data[i]);
	357	if (ret)
	358	return ret;
	359	}
	360	}
d2061f9c	361
3c4fb9f1 HK	362	switch (type) {
	363	case TCPC_TX_SOP:
	364	case TCPC_TX_SOP_PRIME:
	365	case TCPC_TX_SOP_PRIME_PRIME:
	366	case TCPC_TX_SOP_DEBUG_PRIME:
	367	case TCPC_TX_SOP_DEBUG_PRIME_PRIME:
	368	info = type + 1;
	369	cmd = USBC_TXCMD_MSG;
d2061f9c	370	break;
3c4fb9f1 HK	371	case TCPC_TX_HARD_RESET:
3c4fb9f1 HK	372	cmd = USBC_TXCMD_HR;
d2061f9c	373	break;
3c4fb9f1 HK	374	case TCPC_TX_CABLE_RESET:
3c4fb9f1 HK	375	cmd = USBC_TXCMD_CR;
d2061f9c	376	break;
3c4fb9f1 HK	377	case TCPC_TX_BIST_MODE_2:
3c4fb9f1 HK	378	cmd = USBC_TXCMD_BIST;
d2061f9c	379	break;
3c4fb9f1 HK	380	default:
	381	return -EINVAL;
	382	}
	383
	384	/* NOTE Setting maximum number of retries (7) */
	385	ret = regmap_write(wcove->regmap, USBC_TXINFO,
	386	info \| USBC_TXINFO_RETRIES(7));
	387	if (ret)
	388	return ret;
	389
	390	return regmap_write(wcove->regmap, USBC_TXCMD, cmd \| USBC_TXCMD_START);
	391	}
	392
	393	static int wcove_start_drp_toggling(struct tcpc_dev *tcpc,
	394	enum typec_cc_status cc)
	395	{
	396	struct wcove_typec *wcove = tcpc_to_wcove(tcpc);
	397	unsigned int usbc_ctrl;
	398
	399	usbc_ctrl = USBC_CONTROL1_MODE_DRP \| USBC_CONTROL1_DRPTOGGLE_RANDOM;
	400
	401	switch (cc) {
	402	case TYPEC_CC_RP_1_5:
	403	usbc_ctrl \|= USBC_CONTROL1_CURSRC_UA_180;
d2061f9c	404	break;
3c4fb9f1 HK	405	case TYPEC_CC_RP_3_0:
3c4fb9f1 HK	406	usbc_ctrl \|= USBC_CONTROL1_CURSRC_UA_330;
d2061f9c HK	407	break;
d2061f9c HK	408	default:
3c4fb9f1 HK	409	usbc_ctrl \|= USBC_CONTROL1_CURSRC_UA_80;
3c4fb9f1 HK	410	break;
d2061f9c HK	411	}
d2061f9c HK	412
3c4fb9f1 HK	413	return regmap_write(wcove->regmap, USBC_CONTROL1, usbc_ctrl);
	414	}
	415
	416	static int wcove_read_rx_buffer(struct wcove_typec wcove, void msg)
	417	{
	418	unsigned int info;
	419	int ret;
	420	int i;
	421
	422	ret = regmap_read(wcove->regmap, USBC_RXINFO, &info);
	423	if (ret)
	424	return ret;
	425
	426	/* FIXME: Check that USBC_RXINFO_RXBYTES(info) matches the header */
	427
	428	for (i = 0; i < USBC_RXINFO_RXBYTES(info); i++) {
	429	ret = regmap_read(wcove->regmap, USBC_RX_DATA + i, msg + i);
	430	if (ret)
	431	return ret;
d2061f9c HK	432	}
d2061f9c HK	433
3c4fb9f1 HK	434	return regmap_write(wcove->regmap, USBC_RXSTATUS,
	435	USBC_RXSTATUS_RXCLEAR);
	436	}
	437
	438	static irqreturn_t wcove_typec_irq(int irq, void *data)
	439	{
	440	struct wcove_typec *wcove = data;
707a123d CIK	441	unsigned int usbc_irq1 = 0;
707a123d CIK	442	unsigned int usbc_irq2 = 0;
3c4fb9f1 HK	443	unsigned int cc1ctrl;
	444	int ret;
	445
	446	mutex_lock(&wcove->lock);
	447
	448	/* Read.. */
	449	ret = regmap_read(wcove->regmap, USBC_IRQ1, &usbc_irq1);
	450	if (ret)
	451	goto err;
	452
	453	ret = regmap_read(wcove->regmap, USBC_IRQ2, &usbc_irq2);
	454	if (ret)
	455	goto err;
	456
	457	ret = regmap_read(wcove->regmap, USBC_CC1_CTRL, &cc1ctrl);
	458	if (ret)
	459	goto err;
	460
	461	if (!wcove->tcpm)
	462	goto err;
	463
	464	/* ..check.. */
	465	if (usbc_irq1 & USBC_IRQ1_OVERTEMP) {
	466	dev_err(wcove->dev, "VCONN Switch Over Temperature!\n");
	467	wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
	468	/* REVISIT: Report an error? */
	469	}
	470
	471	if (usbc_irq1 & USBC_IRQ1_SHORT) {
	472	dev_err(wcove->dev, "VCONN Switch Short Circuit!\n");
d2061f9c	473	wcove_typec_func(wcove, WCOVE_FUNC_DRIVE_VCONN, false);
3c4fb9f1 HK	474	/* REVISIT: Report an error? */
	475	}
	476
	477	if (wcove->vbus != !!(cc1ctrl & USBC_CC_CTRL_VBUSOK))
	478	tcpm_vbus_change(wcove->tcpm);
	479
	480	/* REVISIT: See if tcpm code can be made to consider Type-C HW FSMs */
	481	if (usbc_irq2 & USBC_IRQ2_CC_CHANGE)
	482	tcpm_cc_change(wcove->tcpm);
	483
	484	if (usbc_irq2 & USBC_IRQ2_RX_PD) {
	485	unsigned int status;
	486
	487	/*
	488	* FIXME: Need to check if TX is ongoing and report
	489	* TX_DIREGARDED if needed?
	490	*/
	491
	492	ret = regmap_read(wcove->regmap, USBC_RXSTATUS, &status);
	493	if (ret)
	494	goto err;
	495
	496	/* Flush all buffers */
	497	while (status & USBC_RXSTATUS_RXDATA) {
	498	struct pd_message msg;
	499
	500	ret = wcove_read_rx_buffer(wcove, &msg);
	501	if (ret) {
	502	dev_err(wcove->dev, "%s: RX read failed\n",
	503	__func__);
	504	goto err;
	505	}
	506
	507	tcpm_pd_receive(wcove->tcpm, &msg);
	508
	509	ret = regmap_read(wcove->regmap, USBC_RXSTATUS,
	510	&status);
	511	if (ret)
	512	goto err;
	513	}
	514	}
	515
	516	if (usbc_irq2 & USBC_IRQ2_RX_HR)
	517	tcpm_pd_hard_reset(wcove->tcpm);
	518
	519	/* REVISIT: if (usbc_irq2 & USBC_IRQ2_RX_CR) */
	520
	521	if (usbc_irq2 & USBC_IRQ2_TX_SUCCESS)
	522	tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_SUCCESS);
	523
	524	if (usbc_irq2 & USBC_IRQ2_TX_FAIL)
	525	tcpm_pd_transmit_complete(wcove->tcpm, TCPC_TX_FAILED);
d2061f9c	526
d2061f9c	527	err:
3c4fb9f1 HK	528	/* ..and clear. */
	529	if (usbc_irq1) {
	530	ret = regmap_write(wcove->regmap, USBC_IRQ1, usbc_irq1);
	531	if (ret)
	532	dev_WARN(wcove->dev, "%s failed to clear IRQ1\n",
	533	__func__);
	534	}
	535
	536	if (usbc_irq2) {
	537	ret = regmap_write(wcove->regmap, USBC_IRQ2, usbc_irq2);
	538	if (ret)
	539	dev_WARN(wcove->dev, "%s failed to clear IRQ2\n",
	540	__func__);
	541	}
	542
d2061f9c HK	543	/* REVISIT: Clear WhiskeyCove CHGR Type-C interrupt */
	544	regmap_write(wcove->regmap, WCOVE_CHGRIRQ0, BIT(5));
	545
	546	mutex_unlock(&wcove->lock);
	547	return IRQ_HANDLED;
	548	}
	549
3c4fb9f1 HK	550	/*
	551	* The following power levels should be safe to use with Joule board.
	552	*/
	553	static const u32 src_pdo[] = {
	554	PDO_FIXED(5000, 1500, PDO_FIXED_DUAL_ROLE \| PDO_FIXED_DATA_SWAP \|
	555	PDO_FIXED_USB_COMM),
	556	};
	557
	558	static const u32 snk_pdo[] = {
	559	PDO_FIXED(12000, 3000, PDO_FIXED_DUAL_ROLE \| PDO_FIXED_DATA_SWAP \|
	560	PDO_FIXED_USB_COMM),
	561	PDO_BATT(4750, 12000, 15000),
	562	PDO_VAR(4750, 12000, 3000),
	563	};
	564
	565	static struct tcpc_config wcove_typec_config = {
	566	.src_pdo = src_pdo,
	567	.nr_src_pdo = ARRAY_SIZE(src_pdo),
	568	.snk_pdo = snk_pdo,
	569	.nr_snk_pdo = ARRAY_SIZE(snk_pdo),
	570
	571	.max_snk_mv = 12000,
	572	.max_snk_ma = 3000,
	573	.max_snk_mw = 36000,
	574	.operating_snk_mw = 15000,
	575
	576	.type = TYPEC_PORT_DRP,
	577	.default_role = TYPEC_SINK,
	578	};
	579
d2061f9c HK	580	static int wcove_typec_probe(struct platform_device *pdev)
	581	{
	582	struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
	583	struct wcove_typec *wcove;
3c4fb9f1	584	int irq;
d2061f9c HK	585	int ret;
	586
	587	wcove = devm_kzalloc(&pdev->dev, sizeof(*wcove), GFP_KERNEL);
	588	if (!wcove)
	589	return -ENOMEM;
	590
	591	mutex_init(&wcove->lock);
	592	wcove->dev = &pdev->dev;
	593	wcove->regmap = pmic->regmap;
	594
3c4fb9f1	595	irq = regmap_irq_get_virq(pmic->irq_chip_data_chgr,
d2061f9c	596	platform_get_irq(pdev, 0));
3c4fb9f1 HK	597	if (irq < 0)
3c4fb9f1 HK	598	return irq;
d2061f9c	599
3c4fb9f1	600	ret = guid_parse(WCOVE_DSM_UUID, &wcove->guid);
d2061f9c HK	601	if (ret)
	602	return ret;
	603
3c4fb9f1	604	if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &wcove->guid, 0, 0x1f)) {
d2061f9c HK	605	dev_err(&pdev->dev, "Missing _DSM functions\n");
	606	return -ENODEV;
	607	}
	608
3c4fb9f1 HK	609	wcove->tcpc.init = wcove_init;
	610	wcove->tcpc.get_vbus = wcove_get_vbus;
	611	wcove->tcpc.set_vbus = wcove_set_vbus;
	612	wcove->tcpc.set_cc = wcove_set_cc;
	613	wcove->tcpc.get_cc = wcove_get_cc;
	614	wcove->tcpc.set_polarity = wcove_set_polarity;
	615	wcove->tcpc.set_vconn = wcove_set_vconn;
	616	wcove->tcpc.set_current_limit = wcove_set_current_limit;
	617	wcove->tcpc.start_drp_toggling = wcove_start_drp_toggling;
d2061f9c	618
3c4fb9f1 HK	619	wcove->tcpc.set_pd_rx = wcove_set_pd_rx;
	620	wcove->tcpc.set_roles = wcove_set_roles;
	621	wcove->tcpc.pd_transmit = wcove_pd_transmit;
d2061f9c	622
3c4fb9f1	623	wcove->tcpc.config = &wcove_typec_config;
d2061f9c	624
3c4fb9f1 HK	625	wcove->tcpm = tcpm_register_port(wcove->dev, &wcove->tcpc);
	626	if (IS_ERR(wcove->tcpm))
	627	return PTR_ERR(wcove->tcpm);
d2061f9c	628
3c4fb9f1 HK	629	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	630	wcove_typec_irq, IRQF_ONESHOT,
	631	"wcove_typec", wcove);
	632	if (ret) {
	633	tcpm_unregister_port(wcove->tcpm);
	634	return ret;
	635	}
d2061f9c HK	636
	637	platform_set_drvdata(pdev, wcove);
	638	return 0;
	639	}
	640
	641	static int wcove_typec_remove(struct platform_device *pdev)
	642	{
	643	struct wcove_typec *wcove = platform_get_drvdata(pdev);
	644	unsigned int val;
	645
	646	/* Mask everything */
	647	regmap_read(wcove->regmap, USBC_IRQMASK1, &val);
	648	regmap_write(wcove->regmap, USBC_IRQMASK1, val \| USBC_IRQMASK1_ALL);
	649	regmap_read(wcove->regmap, USBC_IRQMASK2, &val);
	650	regmap_write(wcove->regmap, USBC_IRQMASK2, val \| USBC_IRQMASK2_ALL);
	651
3c4fb9f1 HK	652	tcpm_unregister_port(wcove->tcpm);
3c4fb9f1 HK	653
d2061f9c HK	654	return 0;
	655	}
	656
	657	static struct platform_driver wcove_typec_driver = {
	658	.driver = {
	659	.name = "bxt_wcove_usbc",
	660	},
	661	.probe = wcove_typec_probe,
	662	.remove = wcove_typec_remove,
	663	};
	664
	665	module_platform_driver(wcove_typec_driver);
	666
	667	MODULE_AUTHOR("Intel Corporation");
	668	MODULE_LICENSE("GPL v2");
	669	MODULE_DESCRIPTION("WhiskeyCove PMIC USB Type-C PHY driver");
	670	MODULE_ALIAS("platform:bxt_wcove_usbc");