Commit | Line | Data |
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788a4ee6 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
a3204711 | 2 | /***************************************************************************** |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 1997-2002 Inside Out Networks, Inc. | |
5 | * | |
1da177e4 LT |
6 | * Feb-16-2001 DMI Added I2C structure definitions |
7 | * May-29-2002 gkh Ported to Linux | |
8 | * | |
9 | * | |
10 | ******************************************************************************/ | |
11 | ||
12 | #ifndef _IO_TI_H_ | |
13 | #define _IO_TI_H_ | |
14 | ||
15 | /* Address Space */ | |
16 | #define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */ | |
17 | #define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */ | |
18 | #define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */ | |
19 | ||
a3204711 GKH |
20 | /* UART Defines */ |
21 | #define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */ | |
22 | #define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */ | |
23 | #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */ | |
1da177e4 LT |
24 | |
25 | /* Bits per character */ | |
26 | #define UMP_UART_CHAR5BITS 0x00 | |
27 | #define UMP_UART_CHAR6BITS 0x01 | |
28 | #define UMP_UART_CHAR7BITS 0x02 | |
29 | #define UMP_UART_CHAR8BITS 0x03 | |
30 | ||
31 | /* Parity */ | |
32 | #define UMP_UART_NOPARITY 0x00 | |
33 | #define UMP_UART_ODDPARITY 0x01 | |
34 | #define UMP_UART_EVENPARITY 0x02 | |
35 | #define UMP_UART_MARKPARITY 0x03 | |
36 | #define UMP_UART_SPACEPARITY 0x04 | |
37 | ||
38 | /* Stop bits */ | |
39 | #define UMP_UART_STOPBIT1 0x00 | |
40 | #define UMP_UART_STOPBIT15 0x01 | |
41 | #define UMP_UART_STOPBIT2 0x02 | |
42 | ||
43 | /* Line status register masks */ | |
44 | #define UMP_UART_LSR_OV_MASK 0x01 | |
45 | #define UMP_UART_LSR_PE_MASK 0x02 | |
46 | #define UMP_UART_LSR_FE_MASK 0x04 | |
47 | #define UMP_UART_LSR_BR_MASK 0x08 | |
48 | #define UMP_UART_LSR_ER_MASK 0x0F | |
49 | #define UMP_UART_LSR_RX_MASK 0x10 | |
50 | #define UMP_UART_LSR_TX_MASK 0x20 | |
51 | ||
a3204711 | 52 | #define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK) |
1da177e4 LT |
53 | |
54 | /* Port Settings Constants) */ | |
55 | #define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001 | |
56 | #define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002 | |
57 | #define UMP_MASK_UART_FLAGS_PARITY 0x0008 | |
58 | #define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010 | |
59 | #define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020 | |
60 | #define UMP_MASK_UART_FLAGS_OUT_X 0x0040 | |
61 | #define UMP_MASK_UART_FLAGS_OUT_XA 0x0080 | |
62 | #define UMP_MASK_UART_FLAGS_IN_X 0x0100 | |
63 | #define UMP_MASK_UART_FLAGS_DTR_FLOW 0x0800 | |
64 | #define UMP_MASK_UART_FLAGS_DTR_DISABLE 0x1000 | |
65 | #define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT 0x2000 | |
66 | #define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR 0x4000 | |
67 | ||
68 | #define UMP_DMA_MODE_CONTINOUS 0x01 | |
69 | #define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80 | |
70 | #define UMP_PIPE_TRANSFER_MODE_MASK 0x03 | |
71 | #define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C | |
72 | ||
73 | /* Purge port Direction Mask Bits */ | |
74 | #define UMP_PORT_DIR_OUT 0x01 | |
75 | #define UMP_PORT_DIR_IN 0x02 | |
76 | ||
a3204711 GKH |
77 | /* Address of Port 0 */ |
78 | #define UMPM_UART1_PORT 0x03 | |
79 | ||
80 | /* Commands */ | |
81 | #define UMPC_SET_CONFIG 0x05 | |
82 | #define UMPC_OPEN_PORT 0x06 | |
83 | #define UMPC_CLOSE_PORT 0x07 | |
84 | #define UMPC_START_PORT 0x08 | |
85 | #define UMPC_STOP_PORT 0x09 | |
86 | #define UMPC_TEST_PORT 0x0A | |
87 | #define UMPC_PURGE_PORT 0x0B | |
88 | ||
89 | /* Force the Firmware to complete the current Read */ | |
90 | #define UMPC_COMPLETE_READ 0x80 | |
91 | /* Force UMP back into BOOT Mode */ | |
92 | #define UMPC_HARDWARE_RESET 0x81 | |
93 | /* | |
94 | * Copy current download image to type 0xf2 record in 16k I2C | |
95 | * firmware will change 0xff record to type 2 record when complete | |
96 | */ | |
97 | #define UMPC_COPY_DNLD_TO_I2C 0x82 | |
1da177e4 | 98 | |
a3204711 GKH |
99 | /* |
100 | * Special function register commands | |
101 | * wIndex is register address | |
102 | * wValue is MSB/LSB mask/data | |
103 | */ | |
104 | #define UMPC_WRITE_SFR 0x83 /* Write SFR Register */ | |
1da177e4 | 105 | |
a3204711 GKH |
106 | /* wIndex is register address */ |
107 | #define UMPC_READ_SFR 0x84 /* Read SRF Register */ | |
1da177e4 | 108 | |
a3204711 | 109 | /* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ |
1da177e4 LT |
110 | #define UMPC_SET_CLR_DTR 0x85 |
111 | ||
a3204711 | 112 | /* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ |
1da177e4 LT |
113 | #define UMPC_SET_CLR_RTS 0x86 |
114 | ||
a3204711 | 115 | /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ |
1da177e4 LT |
116 | #define UMPC_SET_CLR_LOOPBACK 0x87 |
117 | ||
a3204711 | 118 | /* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */ |
1da177e4 LT |
119 | #define UMPC_SET_CLR_BREAK 0x88 |
120 | ||
a3204711 | 121 | /* Read MSR wIndex ModuleID (port) */ |
1da177e4 LT |
122 | #define UMPC_READ_MSR 0x89 |
123 | ||
a3204711 GKH |
124 | /* Toolkit commands */ |
125 | /* Read-write group */ | |
126 | #define UMPC_MEMORY_READ 0x92 | |
127 | #define UMPC_MEMORY_WRITE 0x93 | |
1da177e4 LT |
128 | |
129 | /* | |
130 | * UMP DMA Definitions | |
131 | */ | |
132 | #define UMPD_OEDB1_ADDRESS 0xFF08 | |
133 | #define UMPD_OEDB2_ADDRESS 0xFF10 | |
134 | ||
a3204711 | 135 | struct out_endpoint_desc_block { |
35aeb1b3 JH |
136 | u8 Configuration; |
137 | u8 XBufAddr; | |
138 | u8 XByteCount; | |
139 | u8 Unused1; | |
140 | u8 Unused2; | |
141 | u8 YBufAddr; | |
142 | u8 YByteCount; | |
143 | u8 BufferSize; | |
46388e86 | 144 | }; |
1da177e4 LT |
145 | |
146 | ||
147 | /* | |
148 | * TYPE DEFINITIONS | |
149 | * Structures for Firmware commands | |
150 | */ | |
a3204711 GKH |
151 | /* UART settings */ |
152 | struct ump_uart_config { | |
35aeb1b3 JH |
153 | u16 wBaudRate; /* Baud rate */ |
154 | u16 wFlags; /* Bitmap mask of flags */ | |
155 | u8 bDataBits; /* 5..8 - data bits per character */ | |
156 | u8 bParity; /* Parity settings */ | |
157 | u8 bStopBits; /* Stop bits settings */ | |
1da177e4 LT |
158 | char cXon; /* XON character */ |
159 | char cXoff; /* XOFF character */ | |
35aeb1b3 | 160 | u8 bUartMode; /* Will be updated when a user */ |
1da177e4 | 161 | /* interface is defined */ |
46388e86 | 162 | }; |
1da177e4 LT |
163 | |
164 | ||
165 | /* | |
166 | * TYPE DEFINITIONS | |
167 | * Structures for USB interrupts | |
168 | */ | |
a3204711 GKH |
169 | /* Interrupt packet structure */ |
170 | struct ump_interrupt { | |
35aeb1b3 JH |
171 | u8 bICode; /* Interrupt code (interrupt num) */ |
172 | u8 bIInfo; /* Interrupt information */ | |
46388e86 | 173 | }; |
1da177e4 LT |
174 | |
175 | ||
691a03cf | 176 | #define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 6) & 0x01) |
1da177e4 LT |
177 | #define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f) |
178 | #define TIUMP_INTERRUPT_CODE_LSR 0x03 | |
179 | #define TIUMP_INTERRUPT_CODE_MSR 0x04 | |
180 | ||
181 | #endif |