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91525d08 | 1 | /* |
91525d08 BG |
2 | * Copyright (C) 2010 Google, Inc. |
3 | * | |
4 | * Author: | |
5 | * Erik Gilling <konkers@google.com> | |
6 | * Benoit Goby <benoit@android.com> | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/resource.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/err.h> | |
4265cbfd | 23 | #include <linux/export.h> |
91525d08 BG |
24 | #include <linux/platform_device.h> |
25 | #include <linux/io.h> | |
26 | #include <linux/gpio.h> | |
3a55c6a8 | 27 | #include <linux/of.h> |
aa607ebf | 28 | #include <linux/of_gpio.h> |
91525d08 BG |
29 | #include <linux/usb/otg.h> |
30 | #include <linux/usb/ulpi.h> | |
31 | #include <asm/mach-types.h> | |
1ba8216f | 32 | #include <linux/usb/tegra_usb_phy.h> |
ffc7493d SW |
33 | |
34 | #define TEGRA_USB_BASE 0xC5000000 | |
35 | #define TEGRA_USB_SIZE SZ_16K | |
91525d08 BG |
36 | |
37 | #define ULPI_VIEWPORT 0x170 | |
38 | ||
39 | #define USB_PORTSC1 0x184 | |
40 | #define USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
41 | #define USB_PORTSC1_PSPD(x) (((x) & 0x3) << 26) | |
42 | #define USB_PORTSC1_PHCD (1 << 23) | |
43 | #define USB_PORTSC1_WKOC (1 << 22) | |
44 | #define USB_PORTSC1_WKDS (1 << 21) | |
45 | #define USB_PORTSC1_WKCN (1 << 20) | |
46 | #define USB_PORTSC1_PTC(x) (((x) & 0xf) << 16) | |
47 | #define USB_PORTSC1_PP (1 << 12) | |
48 | #define USB_PORTSC1_SUSP (1 << 7) | |
49 | #define USB_PORTSC1_PE (1 << 2) | |
50 | #define USB_PORTSC1_CCS (1 << 0) | |
51 | ||
52 | #define USB_SUSP_CTRL 0x400 | |
53 | #define USB_WAKE_ON_CNNT_EN_DEV (1 << 3) | |
54 | #define USB_WAKE_ON_DISCON_EN_DEV (1 << 4) | |
55 | #define USB_SUSP_CLR (1 << 5) | |
56 | #define USB_PHY_CLK_VALID (1 << 7) | |
57 | #define UTMIP_RESET (1 << 11) | |
58 | #define UHSIC_RESET (1 << 11) | |
59 | #define UTMIP_PHY_ENABLE (1 << 12) | |
60 | #define ULPI_PHY_ENABLE (1 << 13) | |
61 | #define USB_SUSP_SET (1 << 14) | |
62 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) | |
63 | ||
64 | #define USB1_LEGACY_CTRL 0x410 | |
65 | #define USB1_NO_LEGACY_MODE (1 << 0) | |
66 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) | |
67 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) | |
68 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ | |
69 | (1 << 1) | |
70 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) | |
71 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) | |
72 | ||
73 | #define ULPI_TIMING_CTRL_0 0x424 | |
74 | #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) | |
75 | #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) | |
76 | ||
77 | #define ULPI_TIMING_CTRL_1 0x428 | |
78 | #define ULPI_DATA_TRIMMER_LOAD (1 << 0) | |
79 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) | |
80 | #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) | |
81 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) | |
82 | #define ULPI_DIR_TRIMMER_LOAD (1 << 24) | |
83 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) | |
84 | ||
85 | #define UTMIP_PLL_CFG1 0x804 | |
86 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
87 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
88 | ||
89 | #define UTMIP_XCVR_CFG0 0x808 | |
90 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) | |
91 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) | |
92 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | |
93 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) | |
94 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) | |
95 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) | |
96 | #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) | |
97 | ||
98 | #define UTMIP_BIAS_CFG0 0x80c | |
99 | #define UTMIP_OTGPD (1 << 11) | |
100 | #define UTMIP_BIASPD (1 << 10) | |
101 | ||
102 | #define UTMIP_HSRX_CFG0 0x810 | |
103 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) | |
104 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) | |
105 | ||
106 | #define UTMIP_HSRX_CFG1 0x814 | |
107 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) | |
108 | ||
109 | #define UTMIP_TX_CFG0 0x820 | |
110 | #define UTMIP_FS_PREABMLE_J (1 << 19) | |
111 | #define UTMIP_HS_DISCON_DISABLE (1 << 8) | |
112 | ||
113 | #define UTMIP_MISC_CFG0 0x824 | |
114 | #define UTMIP_DPDM_OBSERVE (1 << 26) | |
115 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) | |
116 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) | |
117 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) | |
118 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) | |
119 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) | |
120 | #define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22) | |
121 | ||
122 | #define UTMIP_MISC_CFG1 0x828 | |
123 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) | |
124 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
125 | ||
126 | #define UTMIP_DEBOUNCE_CFG0 0x82c | |
127 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) | |
128 | ||
129 | #define UTMIP_BAT_CHRG_CFG0 0x830 | |
130 | #define UTMIP_PD_CHRG (1 << 0) | |
131 | ||
132 | #define UTMIP_SPARE_CFG0 0x834 | |
133 | #define FUSE_SETUP_SEL (1 << 3) | |
134 | ||
135 | #define UTMIP_XCVR_CFG1 0x838 | |
136 | #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) | |
137 | #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) | |
138 | #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) | |
139 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) | |
140 | ||
141 | #define UTMIP_BIAS_CFG1 0x83c | |
142 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) | |
143 | ||
144 | static DEFINE_SPINLOCK(utmip_pad_lock); | |
145 | static int utmip_pad_count; | |
146 | ||
147 | struct tegra_xtal_freq { | |
148 | int freq; | |
149 | u8 enable_delay; | |
150 | u8 stable_count; | |
151 | u8 active_delay; | |
152 | u8 xtal_freq_count; | |
153 | u16 debounce; | |
154 | }; | |
155 | ||
156 | static const struct tegra_xtal_freq tegra_freq_table[] = { | |
157 | { | |
158 | .freq = 12000000, | |
159 | .enable_delay = 0x02, | |
160 | .stable_count = 0x2F, | |
161 | .active_delay = 0x04, | |
162 | .xtal_freq_count = 0x76, | |
163 | .debounce = 0x7530, | |
164 | }, | |
165 | { | |
166 | .freq = 13000000, | |
167 | .enable_delay = 0x02, | |
168 | .stable_count = 0x33, | |
169 | .active_delay = 0x05, | |
170 | .xtal_freq_count = 0x7F, | |
171 | .debounce = 0x7EF4, | |
172 | }, | |
173 | { | |
174 | .freq = 19200000, | |
175 | .enable_delay = 0x03, | |
176 | .stable_count = 0x4B, | |
177 | .active_delay = 0x06, | |
178 | .xtal_freq_count = 0xBB, | |
179 | .debounce = 0xBB80, | |
180 | }, | |
181 | { | |
182 | .freq = 26000000, | |
183 | .enable_delay = 0x04, | |
184 | .stable_count = 0x66, | |
185 | .active_delay = 0x09, | |
186 | .xtal_freq_count = 0xFE, | |
187 | .debounce = 0xFDE8, | |
188 | }, | |
189 | }; | |
190 | ||
191 | static struct tegra_utmip_config utmip_default[] = { | |
192 | [0] = { | |
193 | .hssync_start_delay = 9, | |
194 | .idle_wait_delay = 17, | |
195 | .elastic_limit = 16, | |
196 | .term_range_adj = 6, | |
197 | .xcvr_setup = 9, | |
198 | .xcvr_lsfslew = 1, | |
199 | .xcvr_lsrslew = 1, | |
200 | }, | |
201 | [2] = { | |
202 | .hssync_start_delay = 9, | |
203 | .idle_wait_delay = 17, | |
204 | .elastic_limit = 16, | |
205 | .term_range_adj = 6, | |
206 | .xcvr_setup = 9, | |
207 | .xcvr_lsfslew = 2, | |
208 | .xcvr_lsrslew = 2, | |
209 | }, | |
210 | }; | |
211 | ||
91525d08 BG |
212 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
213 | { | |
214 | phy->pad_clk = clk_get_sys("utmip-pad", NULL); | |
215 | if (IS_ERR(phy->pad_clk)) { | |
216 | pr_err("%s: can't get utmip pad clock\n", __func__); | |
217 | return PTR_ERR(phy->pad_clk); | |
218 | } | |
219 | ||
3a55c6a8 | 220 | if (phy->is_legacy_phy) { |
91525d08 BG |
221 | phy->pad_regs = phy->regs; |
222 | } else { | |
223 | phy->pad_regs = ioremap(TEGRA_USB_BASE, TEGRA_USB_SIZE); | |
224 | if (!phy->pad_regs) { | |
225 | pr_err("%s: can't remap usb registers\n", __func__); | |
226 | clk_put(phy->pad_clk); | |
227 | return -ENOMEM; | |
228 | } | |
229 | } | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static void utmip_pad_close(struct tegra_usb_phy *phy) | |
234 | { | |
3a55c6a8 | 235 | if (!phy->is_legacy_phy) |
91525d08 BG |
236 | iounmap(phy->pad_regs); |
237 | clk_put(phy->pad_clk); | |
238 | } | |
239 | ||
240 | static void utmip_pad_power_on(struct tegra_usb_phy *phy) | |
241 | { | |
242 | unsigned long val, flags; | |
243 | void __iomem *base = phy->pad_regs; | |
244 | ||
6a5278d0 | 245 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
246 | |
247 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
248 | ||
249 | if (utmip_pad_count++ == 0) { | |
250 | val = readl(base + UTMIP_BIAS_CFG0); | |
251 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); | |
252 | writel(val, base + UTMIP_BIAS_CFG0); | |
253 | } | |
254 | ||
255 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
256 | ||
6a5278d0 | 257 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
258 | } |
259 | ||
260 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) | |
261 | { | |
262 | unsigned long val, flags; | |
263 | void __iomem *base = phy->pad_regs; | |
264 | ||
265 | if (!utmip_pad_count) { | |
266 | pr_err("%s: utmip pad already powered off\n", __func__); | |
267 | return -EINVAL; | |
268 | } | |
269 | ||
6a5278d0 | 270 | clk_prepare_enable(phy->pad_clk); |
91525d08 BG |
271 | |
272 | spin_lock_irqsave(&utmip_pad_lock, flags); | |
273 | ||
274 | if (--utmip_pad_count == 0) { | |
275 | val = readl(base + UTMIP_BIAS_CFG0); | |
276 | val |= UTMIP_OTGPD | UTMIP_BIASPD; | |
277 | writel(val, base + UTMIP_BIAS_CFG0); | |
278 | } | |
279 | ||
280 | spin_unlock_irqrestore(&utmip_pad_lock, flags); | |
281 | ||
6a5278d0 | 282 | clk_disable_unprepare(phy->pad_clk); |
91525d08 BG |
283 | |
284 | return 0; | |
285 | } | |
286 | ||
287 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) | |
288 | { | |
289 | unsigned long timeout = 2000; | |
290 | do { | |
291 | if ((readl(reg) & mask) == result) | |
292 | return 0; | |
293 | udelay(1); | |
294 | timeout--; | |
295 | } while (timeout); | |
296 | return -1; | |
297 | } | |
298 | ||
299 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) | |
300 | { | |
301 | unsigned long val; | |
302 | void __iomem *base = phy->regs; | |
303 | ||
3a55c6a8 | 304 | if (phy->is_legacy_phy) { |
91525d08 BG |
305 | val = readl(base + USB_SUSP_CTRL); |
306 | val |= USB_SUSP_SET; | |
307 | writel(val, base + USB_SUSP_CTRL); | |
308 | ||
309 | udelay(10); | |
310 | ||
311 | val = readl(base + USB_SUSP_CTRL); | |
312 | val &= ~USB_SUSP_SET; | |
313 | writel(val, base + USB_SUSP_CTRL); | |
3a55c6a8 | 314 | } else { |
91525d08 BG |
315 | val = readl(base + USB_PORTSC1); |
316 | val |= USB_PORTSC1_PHCD; | |
317 | writel(val, base + USB_PORTSC1); | |
318 | } | |
319 | ||
320 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) < 0) | |
321 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
322 | } | |
323 | ||
324 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) | |
325 | { | |
326 | unsigned long val; | |
327 | void __iomem *base = phy->regs; | |
328 | ||
3a55c6a8 | 329 | if (phy->is_legacy_phy) { |
91525d08 BG |
330 | val = readl(base + USB_SUSP_CTRL); |
331 | val |= USB_SUSP_CLR; | |
332 | writel(val, base + USB_SUSP_CTRL); | |
333 | ||
334 | udelay(10); | |
335 | ||
336 | val = readl(base + USB_SUSP_CTRL); | |
337 | val &= ~USB_SUSP_CLR; | |
338 | writel(val, base + USB_SUSP_CTRL); | |
3a55c6a8 | 339 | } else { |
91525d08 BG |
340 | val = readl(base + USB_PORTSC1); |
341 | val &= ~USB_PORTSC1_PHCD; | |
342 | writel(val, base + USB_PORTSC1); | |
343 | } | |
344 | ||
345 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
346 | USB_PHY_CLK_VALID)) | |
347 | pr_err("%s: timeout waiting for phy to stabilize\n", __func__); | |
348 | } | |
349 | ||
350 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |
351 | { | |
352 | unsigned long val; | |
353 | void __iomem *base = phy->regs; | |
354 | struct tegra_utmip_config *config = phy->config; | |
355 | ||
356 | val = readl(base + USB_SUSP_CTRL); | |
357 | val |= UTMIP_RESET; | |
358 | writel(val, base + USB_SUSP_CTRL); | |
359 | ||
3a55c6a8 | 360 | if (phy->is_legacy_phy) { |
91525d08 BG |
361 | val = readl(base + USB1_LEGACY_CTRL); |
362 | val |= USB1_NO_LEGACY_MODE; | |
363 | writel(val, base + USB1_LEGACY_CTRL); | |
364 | } | |
365 | ||
366 | val = readl(base + UTMIP_TX_CFG0); | |
367 | val &= ~UTMIP_FS_PREABMLE_J; | |
368 | writel(val, base + UTMIP_TX_CFG0); | |
369 | ||
370 | val = readl(base + UTMIP_HSRX_CFG0); | |
371 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); | |
372 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); | |
373 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); | |
374 | writel(val, base + UTMIP_HSRX_CFG0); | |
375 | ||
376 | val = readl(base + UTMIP_HSRX_CFG1); | |
377 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); | |
378 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); | |
379 | writel(val, base + UTMIP_HSRX_CFG1); | |
380 | ||
381 | val = readl(base + UTMIP_DEBOUNCE_CFG0); | |
382 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); | |
383 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); | |
384 | writel(val, base + UTMIP_DEBOUNCE_CFG0); | |
385 | ||
386 | val = readl(base + UTMIP_MISC_CFG0); | |
387 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; | |
388 | writel(val, base + UTMIP_MISC_CFG0); | |
389 | ||
390 | val = readl(base + UTMIP_MISC_CFG1); | |
391 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | UTMIP_PLLU_STABLE_COUNT(~0)); | |
392 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | | |
393 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); | |
394 | writel(val, base + UTMIP_MISC_CFG1); | |
395 | ||
396 | val = readl(base + UTMIP_PLL_CFG1); | |
397 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); | |
398 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | | |
399 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); | |
400 | writel(val, base + UTMIP_PLL_CFG1); | |
401 | ||
402 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
403 | val = readl(base + USB_SUSP_CTRL); | |
404 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); | |
405 | writel(val, base + USB_SUSP_CTRL); | |
406 | } | |
407 | ||
408 | utmip_pad_power_on(phy); | |
409 | ||
410 | val = readl(base + UTMIP_XCVR_CFG0); | |
411 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
412 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | | |
413 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | | |
414 | UTMIP_XCVR_HSSLEW_MSB(~0)); | |
415 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | |
416 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); | |
417 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | |
418 | writel(val, base + UTMIP_XCVR_CFG0); | |
419 | ||
420 | val = readl(base + UTMIP_XCVR_CFG1); | |
421 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
422 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); | |
423 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | |
424 | writel(val, base + UTMIP_XCVR_CFG1); | |
425 | ||
426 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
427 | val &= ~UTMIP_PD_CHRG; | |
428 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
429 | ||
430 | val = readl(base + UTMIP_BIAS_CFG1); | |
431 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); | |
432 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | |
433 | writel(val, base + UTMIP_BIAS_CFG1); | |
434 | ||
3a55c6a8 | 435 | if (phy->is_legacy_phy) { |
91525d08 BG |
436 | val = readl(base + UTMIP_SPARE_CFG0); |
437 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) | |
438 | val &= ~FUSE_SETUP_SEL; | |
439 | else | |
440 | val |= FUSE_SETUP_SEL; | |
441 | writel(val, base + UTMIP_SPARE_CFG0); | |
3a55c6a8 | 442 | } else { |
91525d08 BG |
443 | val = readl(base + USB_SUSP_CTRL); |
444 | val |= UTMIP_PHY_ENABLE; | |
445 | writel(val, base + USB_SUSP_CTRL); | |
446 | } | |
447 | ||
448 | val = readl(base + USB_SUSP_CTRL); | |
449 | val &= ~UTMIP_RESET; | |
450 | writel(val, base + USB_SUSP_CTRL); | |
451 | ||
3a55c6a8 | 452 | if (phy->is_legacy_phy) { |
91525d08 BG |
453 | val = readl(base + USB1_LEGACY_CTRL); |
454 | val &= ~USB1_VBUS_SENSE_CTL_MASK; | |
455 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; | |
456 | writel(val, base + USB1_LEGACY_CTRL); | |
457 | ||
458 | val = readl(base + USB_SUSP_CTRL); | |
459 | val &= ~USB_SUSP_SET; | |
460 | writel(val, base + USB_SUSP_CTRL); | |
461 | } | |
462 | ||
463 | utmi_phy_clk_enable(phy); | |
464 | ||
3a55c6a8 | 465 | if (!phy->is_legacy_phy) { |
91525d08 BG |
466 | val = readl(base + USB_PORTSC1); |
467 | val &= ~USB_PORTSC1_PTS(~0); | |
468 | writel(val, base + USB_PORTSC1); | |
469 | } | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
1ba8216f | 474 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 BG |
475 | { |
476 | unsigned long val; | |
477 | void __iomem *base = phy->regs; | |
478 | ||
479 | utmi_phy_clk_disable(phy); | |
480 | ||
481 | if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) { | |
482 | val = readl(base + USB_SUSP_CTRL); | |
483 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); | |
484 | val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5); | |
485 | writel(val, base + USB_SUSP_CTRL); | |
486 | } | |
487 | ||
488 | val = readl(base + USB_SUSP_CTRL); | |
489 | val |= UTMIP_RESET; | |
490 | writel(val, base + USB_SUSP_CTRL); | |
491 | ||
492 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | |
493 | val |= UTMIP_PD_CHRG; | |
494 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | |
495 | ||
496 | val = readl(base + UTMIP_XCVR_CFG0); | |
497 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
498 | UTMIP_FORCE_PDZI_POWERDOWN; | |
499 | writel(val, base + UTMIP_XCVR_CFG0); | |
500 | ||
501 | val = readl(base + UTMIP_XCVR_CFG1); | |
502 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | | |
503 | UTMIP_FORCE_PDDR_POWERDOWN; | |
504 | writel(val, base + UTMIP_XCVR_CFG1); | |
505 | ||
1ba8216f | 506 | return utmip_pad_power_off(phy); |
91525d08 BG |
507 | } |
508 | ||
509 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) | |
510 | { | |
511 | unsigned long val; | |
512 | void __iomem *base = phy->regs; | |
513 | ||
514 | val = readl(base + UTMIP_TX_CFG0); | |
515 | val |= UTMIP_HS_DISCON_DISABLE; | |
516 | writel(val, base + UTMIP_TX_CFG0); | |
517 | } | |
518 | ||
519 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) | |
520 | { | |
521 | unsigned long val; | |
522 | void __iomem *base = phy->regs; | |
523 | ||
524 | val = readl(base + UTMIP_TX_CFG0); | |
525 | val &= ~UTMIP_HS_DISCON_DISABLE; | |
526 | writel(val, base + UTMIP_TX_CFG0); | |
527 | } | |
528 | ||
529 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, | |
530 | enum tegra_usb_phy_port_speed port_speed) | |
531 | { | |
532 | unsigned long val; | |
533 | void __iomem *base = phy->regs; | |
534 | ||
535 | val = readl(base + UTMIP_MISC_CFG0); | |
536 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); | |
537 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
538 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; | |
539 | else | |
540 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; | |
541 | writel(val, base + UTMIP_MISC_CFG0); | |
542 | udelay(1); | |
543 | ||
544 | val = readl(base + UTMIP_MISC_CFG0); | |
545 | val |= UTMIP_DPDM_OBSERVE; | |
546 | writel(val, base + UTMIP_MISC_CFG0); | |
547 | udelay(10); | |
548 | } | |
549 | ||
550 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) | |
551 | { | |
552 | unsigned long val; | |
553 | void __iomem *base = phy->regs; | |
554 | ||
555 | val = readl(base + UTMIP_MISC_CFG0); | |
556 | val &= ~UTMIP_DPDM_OBSERVE; | |
557 | writel(val, base + UTMIP_MISC_CFG0); | |
558 | udelay(10); | |
559 | } | |
560 | ||
561 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) | |
562 | { | |
563 | int ret; | |
564 | unsigned long val; | |
565 | void __iomem *base = phy->regs; | |
566 | struct tegra_ulpi_config *config = phy->config; | |
567 | ||
568 | gpio_direction_output(config->reset_gpio, 0); | |
569 | msleep(5); | |
570 | gpio_direction_output(config->reset_gpio, 1); | |
571 | ||
6a5278d0 | 572 | clk_prepare_enable(phy->clk); |
91525d08 BG |
573 | msleep(1); |
574 | ||
575 | val = readl(base + USB_SUSP_CTRL); | |
576 | val |= UHSIC_RESET; | |
577 | writel(val, base + USB_SUSP_CTRL); | |
578 | ||
579 | val = readl(base + ULPI_TIMING_CTRL_0); | |
580 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; | |
581 | writel(val, base + ULPI_TIMING_CTRL_0); | |
582 | ||
583 | val = readl(base + USB_SUSP_CTRL); | |
584 | val |= ULPI_PHY_ENABLE; | |
585 | writel(val, base + USB_SUSP_CTRL); | |
586 | ||
587 | val = 0; | |
588 | writel(val, base + ULPI_TIMING_CTRL_1); | |
589 | ||
590 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
591 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
592 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
593 | writel(val, base + ULPI_TIMING_CTRL_1); | |
594 | udelay(10); | |
595 | ||
596 | val |= ULPI_DATA_TRIMMER_LOAD; | |
597 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
598 | val |= ULPI_DIR_TRIMMER_LOAD; | |
599 | writel(val, base + ULPI_TIMING_CTRL_1); | |
600 | ||
601 | /* Fix VbusInvalid due to floating VBUS */ | |
b96d3b08 | 602 | ret = usb_phy_io_write(phy->ulpi, 0x40, 0x08); |
91525d08 BG |
603 | if (ret) { |
604 | pr_err("%s: ulpi write failed\n", __func__); | |
605 | return ret; | |
606 | } | |
607 | ||
b96d3b08 | 608 | ret = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); |
91525d08 BG |
609 | if (ret) { |
610 | pr_err("%s: ulpi write failed\n", __func__); | |
611 | return ret; | |
612 | } | |
613 | ||
614 | val = readl(base + USB_PORTSC1); | |
615 | val |= USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN; | |
616 | writel(val, base + USB_PORTSC1); | |
617 | ||
618 | val = readl(base + USB_SUSP_CTRL); | |
619 | val |= USB_SUSP_CLR; | |
620 | writel(val, base + USB_SUSP_CTRL); | |
621 | udelay(100); | |
622 | ||
623 | val = readl(base + USB_SUSP_CTRL); | |
624 | val &= ~USB_SUSP_CLR; | |
625 | writel(val, base + USB_SUSP_CTRL); | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
1ba8216f | 630 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 BG |
631 | { |
632 | unsigned long val; | |
633 | void __iomem *base = phy->regs; | |
634 | struct tegra_ulpi_config *config = phy->config; | |
635 | ||
636 | /* Clear WKCN/WKDS/WKOC wake-on events that can cause the USB | |
637 | * Controller to immediately bring the ULPI PHY out of low power | |
638 | */ | |
639 | val = readl(base + USB_PORTSC1); | |
640 | val &= ~(USB_PORTSC1_WKOC | USB_PORTSC1_WKDS | USB_PORTSC1_WKCN); | |
641 | writel(val, base + USB_PORTSC1); | |
642 | ||
91525d08 | 643 | clk_disable(phy->clk); |
1ba8216f VB |
644 | return gpio_direction_output(config->reset_gpio, 0); |
645 | } | |
646 | ||
647 | static int tegra_phy_init(struct usb_phy *x) | |
648 | { | |
649 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
650 | struct tegra_ulpi_config *ulpi_config; | |
651 | int err; | |
652 | ||
3f9db1a1 | 653 | if (phy->is_ulpi_phy) { |
1ba8216f VB |
654 | ulpi_config = phy->config; |
655 | phy->clk = clk_get_sys(NULL, ulpi_config->clk); | |
656 | if (IS_ERR(phy->clk)) { | |
657 | pr_err("%s: can't get ulpi clock\n", __func__); | |
658 | err = -ENXIO; | |
659 | goto err1; | |
660 | } | |
661 | if (!gpio_is_valid(ulpi_config->reset_gpio)) | |
662 | ulpi_config->reset_gpio = | |
663 | of_get_named_gpio(phy->dev->of_node, | |
664 | "nvidia,phy-reset-gpio", 0); | |
665 | if (!gpio_is_valid(ulpi_config->reset_gpio)) { | |
666 | pr_err("%s: invalid reset gpio: %d\n", __func__, | |
667 | ulpi_config->reset_gpio); | |
668 | err = -EINVAL; | |
669 | goto err1; | |
670 | } | |
671 | gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b"); | |
672 | gpio_direction_output(ulpi_config->reset_gpio, 0); | |
673 | phy->ulpi = otg_ulpi_create(&ulpi_viewport_access_ops, 0); | |
674 | phy->ulpi->io_priv = phy->regs + ULPI_VIEWPORT; | |
675 | } else { | |
676 | err = utmip_pad_open(phy); | |
677 | if (err < 0) | |
678 | goto err1; | |
679 | } | |
680 | return 0; | |
681 | err1: | |
682 | clk_disable_unprepare(phy->pll_u); | |
683 | clk_put(phy->pll_u); | |
684 | return err; | |
685 | } | |
686 | ||
687 | static void tegra_usb_phy_close(struct usb_phy *x) | |
688 | { | |
689 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
690 | ||
3f9db1a1 | 691 | if (phy->is_ulpi_phy) |
1ba8216f VB |
692 | clk_put(phy->clk); |
693 | else | |
694 | utmip_pad_close(phy); | |
695 | clk_disable_unprepare(phy->pll_u); | |
696 | clk_put(phy->pll_u); | |
697 | kfree(phy); | |
698 | } | |
699 | ||
700 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) | |
701 | { | |
3f9db1a1 | 702 | if (phy->is_ulpi_phy) |
1ba8216f VB |
703 | return ulpi_phy_power_on(phy); |
704 | else | |
705 | return utmi_phy_power_on(phy); | |
706 | } | |
707 | ||
708 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) | |
709 | { | |
3f9db1a1 | 710 | if (phy->is_ulpi_phy) |
1ba8216f VB |
711 | return ulpi_phy_power_off(phy); |
712 | else | |
713 | return utmi_phy_power_off(phy); | |
714 | } | |
715 | ||
716 | static int tegra_usb_phy_suspend(struct usb_phy *x, int suspend) | |
717 | { | |
718 | struct tegra_usb_phy *phy = container_of(x, struct tegra_usb_phy, u_phy); | |
719 | if (suspend) | |
720 | return tegra_usb_phy_power_off(phy); | |
721 | else | |
722 | return tegra_usb_phy_power_on(phy); | |
91525d08 BG |
723 | } |
724 | ||
aa607ebf SW |
725 | struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance, |
726 | void __iomem *regs, void *config, enum tegra_usb_phy_mode phy_mode) | |
91525d08 BG |
727 | { |
728 | struct tegra_usb_phy *phy; | |
91525d08 BG |
729 | unsigned long parent_rate; |
730 | int i; | |
731 | int err; | |
3a55c6a8 | 732 | struct device_node *np = dev->of_node; |
91525d08 | 733 | |
5b26c94c | 734 | phy = kzalloc(sizeof(struct tegra_usb_phy), GFP_KERNEL); |
91525d08 BG |
735 | if (!phy) |
736 | return ERR_PTR(-ENOMEM); | |
737 | ||
738 | phy->instance = instance; | |
739 | phy->regs = regs; | |
740 | phy->config = config; | |
741 | phy->mode = phy_mode; | |
1ba8216f | 742 | phy->dev = dev; |
3a55c6a8 VB |
743 | phy->is_legacy_phy = |
744 | of_property_read_bool(np, "nvidia,has-legacy-mode"); | |
3f9db1a1 VB |
745 | err = of_property_match_string(np, "phy_type", "ulpi"); |
746 | if (err < 0) | |
747 | phy->is_ulpi_phy = false; | |
748 | else | |
749 | phy->is_ulpi_phy = true; | |
91525d08 BG |
750 | |
751 | if (!phy->config) { | |
3f9db1a1 | 752 | if (phy->is_ulpi_phy) { |
91525d08 BG |
753 | pr_err("%s: ulpi phy configuration missing", __func__); |
754 | err = -EINVAL; | |
755 | goto err0; | |
756 | } else { | |
757 | phy->config = &utmip_default[instance]; | |
758 | } | |
759 | } | |
760 | ||
761 | phy->pll_u = clk_get_sys(NULL, "pll_u"); | |
762 | if (IS_ERR(phy->pll_u)) { | |
763 | pr_err("Can't get pll_u clock\n"); | |
764 | err = PTR_ERR(phy->pll_u); | |
765 | goto err0; | |
766 | } | |
6a5278d0 | 767 | clk_prepare_enable(phy->pll_u); |
91525d08 BG |
768 | |
769 | parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); | |
770 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { | |
771 | if (tegra_freq_table[i].freq == parent_rate) { | |
772 | phy->freq = &tegra_freq_table[i]; | |
773 | break; | |
774 | } | |
775 | } | |
776 | if (!phy->freq) { | |
777 | pr_err("invalid pll_u parent rate %ld\n", parent_rate); | |
778 | err = -EINVAL; | |
779 | goto err1; | |
780 | } | |
781 | ||
1ba8216f VB |
782 | phy->u_phy.init = tegra_phy_init; |
783 | phy->u_phy.shutdown = tegra_usb_phy_close; | |
784 | phy->u_phy.set_suspend = tegra_usb_phy_suspend; | |
91525d08 BG |
785 | |
786 | return phy; | |
787 | ||
788 | err1: | |
6a5278d0 | 789 | clk_disable_unprepare(phy->pll_u); |
91525d08 BG |
790 | clk_put(phy->pll_u); |
791 | err0: | |
792 | kfree(phy); | |
793 | return ERR_PTR(err); | |
794 | } | |
4265cbfd | 795 | EXPORT_SYMBOL_GPL(tegra_usb_phy_open); |
91525d08 | 796 | |
91525d08 BG |
797 | void tegra_usb_phy_preresume(struct tegra_usb_phy *phy) |
798 | { | |
3f9db1a1 | 799 | if (!phy->is_ulpi_phy) |
91525d08 BG |
800 | utmi_phy_preresume(phy); |
801 | } | |
4265cbfd | 802 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
91525d08 BG |
803 | |
804 | void tegra_usb_phy_postresume(struct tegra_usb_phy *phy) | |
805 | { | |
3f9db1a1 | 806 | if (!phy->is_ulpi_phy) |
91525d08 BG |
807 | utmi_phy_postresume(phy); |
808 | } | |
4265cbfd | 809 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
91525d08 BG |
810 | |
811 | void tegra_ehci_phy_restore_start(struct tegra_usb_phy *phy, | |
812 | enum tegra_usb_phy_port_speed port_speed) | |
813 | { | |
3f9db1a1 | 814 | if (!phy->is_ulpi_phy) |
91525d08 BG |
815 | utmi_phy_restore_start(phy, port_speed); |
816 | } | |
4265cbfd | 817 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
91525d08 BG |
818 | |
819 | void tegra_ehci_phy_restore_end(struct tegra_usb_phy *phy) | |
820 | { | |
3f9db1a1 | 821 | if (!phy->is_ulpi_phy) |
91525d08 BG |
822 | utmi_phy_restore_end(phy); |
823 | } | |
4265cbfd | 824 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
91525d08 | 825 |