Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
91525d08 | 2 | /* |
91525d08 | 3 | * Copyright (C) 2010 Google, Inc. |
2d22b42d | 4 | * Copyright (C) 2013 NVIDIA Corporation |
91525d08 BG |
5 | * |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * Benoit Goby <benoit@android.com> | |
2d22b42d | 9 | * Venu Byravarasu <vbyravarasu@nvidia.com> |
91525d08 BG |
10 | */ |
11 | ||
91525d08 | 12 | #include <linux/delay.h> |
91525d08 | 13 | #include <linux/err.h> |
4265cbfd | 14 | #include <linux/export.h> |
9cb9322a | 15 | #include <linux/gpio/consumer.h> |
5bb69850 DO |
16 | #include <linux/iopoll.h> |
17 | #include <linux/module.h> | |
3a55c6a8 | 18 | #include <linux/of.h> |
3e635202 | 19 | #include <linux/of_device.h> |
5bb69850 DO |
20 | #include <linux/platform_device.h> |
21 | #include <linux/resource.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/spinlock.h> | |
24 | ||
25 | #include <linux/regulator/consumer.h> | |
26 | ||
91a687d8 | 27 | #include <linux/usb/ehci_def.h> |
5bb69850 | 28 | #include <linux/usb/of.h> |
1ba8216f | 29 | #include <linux/usb/tegra_usb_phy.h> |
5bb69850 | 30 | #include <linux/usb/ulpi.h> |
91525d08 | 31 | |
545592e8 | 32 | #define ULPI_VIEWPORT 0x170 |
91525d08 | 33 | |
3e635202 | 34 | /* PORTSC PTS/PHCD bits, Tegra20 only */ |
545592e8 DO |
35 | #define TEGRA_USB_PORTSC1 0x184 |
36 | #define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30) | |
37 | #define TEGRA_USB_PORTSC1_PHCD BIT(23) | |
91a687d8 | 38 | |
3e635202 | 39 | /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */ |
545592e8 DO |
40 | #define TEGRA_USB_HOSTPC1_DEVLC 0x1b4 |
41 | #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29) | |
42 | #define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22) | |
3e635202 | 43 | |
91a687d8 SW |
44 | /* Bits of PORTSC1, which will get cleared by writing 1 into them */ |
45 | #define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) | |
46 | ||
545592e8 | 47 | #define USB_SUSP_CTRL 0x400 |
35192007 | 48 | #define USB_WAKE_ON_RESUME_EN BIT(2) |
545592e8 DO |
49 | #define USB_WAKE_ON_CNNT_EN_DEV BIT(3) |
50 | #define USB_WAKE_ON_DISCON_EN_DEV BIT(4) | |
51 | #define USB_SUSP_CLR BIT(5) | |
52 | #define USB_PHY_CLK_VALID BIT(7) | |
53 | #define UTMIP_RESET BIT(11) | |
54 | #define UHSIC_RESET BIT(11) | |
55 | #define UTMIP_PHY_ENABLE BIT(12) | |
56 | #define ULPI_PHY_ENABLE BIT(13) | |
57 | #define USB_SUSP_SET BIT(14) | |
58 | #define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16) | |
59 | ||
35192007 | 60 | #define USB_PHY_VBUS_SENSORS 0x404 |
7917e906 | 61 | #define B_SESS_VLD_WAKEUP_EN BIT(14) |
35192007 DO |
62 | #define A_SESS_VLD_WAKEUP_EN BIT(22) |
63 | #define A_VBUS_VLD_WAKEUP_EN BIT(30) | |
64 | ||
65 | #define USB_PHY_VBUS_WAKEUP_ID 0x408 | |
c1baf6c5 DO |
66 | #define ID_INT_EN BIT(0) |
67 | #define ID_CHG_DET BIT(1) | |
68 | #define VBUS_WAKEUP_INT_EN BIT(8) | |
69 | #define VBUS_WAKEUP_CHG_DET BIT(9) | |
6f8d39a8 | 70 | #define VBUS_WAKEUP_STS BIT(10) |
35192007 DO |
71 | #define VBUS_WAKEUP_WAKEUP_EN BIT(30) |
72 | ||
545592e8 DO |
73 | #define USB1_LEGACY_CTRL 0x410 |
74 | #define USB1_NO_LEGACY_MODE BIT(0) | |
91525d08 BG |
75 | #define USB1_VBUS_SENSE_CTL_MASK (3 << 1) |
76 | #define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1) | |
77 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \ | |
78 | (1 << 1) | |
79 | #define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1) | |
80 | #define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1) | |
81 | ||
545592e8 DO |
82 | #define ULPI_TIMING_CTRL_0 0x424 |
83 | #define ULPI_OUTPUT_PINMUX_BYP BIT(10) | |
84 | #define ULPI_CLKOUT_PINMUX_BYP BIT(11) | |
91525d08 | 85 | |
545592e8 DO |
86 | #define ULPI_TIMING_CTRL_1 0x428 |
87 | #define ULPI_DATA_TRIMMER_LOAD BIT(0) | |
88 | #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) | |
89 | #define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16) | |
90 | #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) | |
91 | #define ULPI_DIR_TRIMMER_LOAD BIT(24) | |
92 | #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) | |
91525d08 | 93 | |
545592e8 | 94 | #define UTMIP_PLL_CFG1 0x804 |
91525d08 BG |
95 | #define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) |
96 | #define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
97 | ||
545592e8 | 98 | #define UTMIP_XCVR_CFG0 0x808 |
91525d08 | 99 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) |
f5833a0b | 100 | #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) |
91525d08 BG |
101 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) |
102 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | |
545592e8 DO |
103 | #define UTMIP_FORCE_PD_POWERDOWN BIT(14) |
104 | #define UTMIP_FORCE_PD2_POWERDOWN BIT(16) | |
105 | #define UTMIP_FORCE_PDZI_POWERDOWN BIT(18) | |
106 | #define UTMIP_XCVR_LSBIAS_SEL BIT(21) | |
e497a24d TT |
107 | #define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4) |
108 | #define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25) | |
91525d08 | 109 | |
545592e8 DO |
110 | #define UTMIP_BIAS_CFG0 0x80c |
111 | #define UTMIP_OTGPD BIT(11) | |
112 | #define UTMIP_BIASPD BIT(10) | |
113 | #define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0) | |
114 | #define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2) | |
115 | #define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24) | |
91525d08 | 116 | |
545592e8 DO |
117 | #define UTMIP_HSRX_CFG0 0x810 |
118 | #define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10) | |
119 | #define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15) | |
91525d08 | 120 | |
545592e8 DO |
121 | #define UTMIP_HSRX_CFG1 0x814 |
122 | #define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1) | |
91525d08 | 123 | |
545592e8 DO |
124 | #define UTMIP_TX_CFG0 0x820 |
125 | #define UTMIP_FS_PREABMLE_J BIT(19) | |
126 | #define UTMIP_HS_DISCON_DISABLE BIT(8) | |
91525d08 | 127 | |
545592e8 DO |
128 | #define UTMIP_MISC_CFG0 0x824 |
129 | #define UTMIP_DPDM_OBSERVE BIT(26) | |
130 | #define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27) | |
131 | #define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf) | |
132 | #define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe) | |
133 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd) | |
134 | #define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc) | |
135 | #define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22) | |
91525d08 | 136 | |
545592e8 DO |
137 | #define UTMIP_MISC_CFG1 0x828 |
138 | #define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18) | |
139 | #define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
91525d08 | 140 | |
545592e8 DO |
141 | #define UTMIP_DEBOUNCE_CFG0 0x82c |
142 | #define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0) | |
91525d08 | 143 | |
545592e8 DO |
144 | #define UTMIP_BAT_CHRG_CFG0 0x830 |
145 | #define UTMIP_PD_CHRG BIT(0) | |
91525d08 | 146 | |
545592e8 DO |
147 | #define UTMIP_SPARE_CFG0 0x834 |
148 | #define FUSE_SETUP_SEL BIT(3) | |
91525d08 | 149 | |
545592e8 DO |
150 | #define UTMIP_XCVR_CFG1 0x838 |
151 | #define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0) | |
152 | #define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2) | |
153 | #define UTMIP_FORCE_PDDR_POWERDOWN BIT(4) | |
154 | #define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18) | |
91525d08 | 155 | |
545592e8 DO |
156 | #define UTMIP_BIAS_CFG1 0x83c |
157 | #define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3) | |
91525d08 | 158 | |
3e635202 | 159 | /* For Tegra30 and above only, the address is different in Tegra20 */ |
545592e8 DO |
160 | #define USB_USBMODE 0x1f8 |
161 | #define USB_USBMODE_MASK (3 << 0) | |
162 | #define USB_USBMODE_HOST (3 << 0) | |
163 | #define USB_USBMODE_DEVICE (2 << 0) | |
3e635202 | 164 | |
c1baf6c5 DO |
165 | #define PMC_USB_AO 0xf0 |
166 | #define VBUS_WAKEUP_PD_P0 BIT(2) | |
167 | #define ID_PD_P0 BIT(3) | |
168 | ||
91525d08 | 169 | static DEFINE_SPINLOCK(utmip_pad_lock); |
545592e8 | 170 | static unsigned int utmip_pad_count; |
91525d08 BG |
171 | |
172 | struct tegra_xtal_freq { | |
545592e8 | 173 | unsigned int freq; |
91525d08 BG |
174 | u8 enable_delay; |
175 | u8 stable_count; | |
176 | u8 active_delay; | |
177 | u8 xtal_freq_count; | |
178 | u16 debounce; | |
179 | }; | |
180 | ||
181 | static const struct tegra_xtal_freq tegra_freq_table[] = { | |
182 | { | |
183 | .freq = 12000000, | |
184 | .enable_delay = 0x02, | |
185 | .stable_count = 0x2F, | |
186 | .active_delay = 0x04, | |
187 | .xtal_freq_count = 0x76, | |
188 | .debounce = 0x7530, | |
189 | }, | |
190 | { | |
191 | .freq = 13000000, | |
192 | .enable_delay = 0x02, | |
193 | .stable_count = 0x33, | |
194 | .active_delay = 0x05, | |
195 | .xtal_freq_count = 0x7F, | |
196 | .debounce = 0x7EF4, | |
197 | }, | |
198 | { | |
199 | .freq = 19200000, | |
200 | .enable_delay = 0x03, | |
201 | .stable_count = 0x4B, | |
202 | .active_delay = 0x06, | |
203 | .xtal_freq_count = 0xBB, | |
204 | .debounce = 0xBB80, | |
205 | }, | |
206 | { | |
207 | .freq = 26000000, | |
208 | .enable_delay = 0x04, | |
209 | .stable_count = 0x66, | |
210 | .active_delay = 0x09, | |
211 | .xtal_freq_count = 0xFE, | |
212 | .debounce = 0xFDE8, | |
213 | }, | |
214 | }; | |
215 | ||
545592e8 DO |
216 | static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy) |
217 | { | |
218 | return container_of(u_phy, struct tegra_usb_phy, u_phy); | |
219 | } | |
220 | ||
91a687d8 SW |
221 | static void set_pts(struct tegra_usb_phy *phy, u8 pts_val) |
222 | { | |
223 | void __iomem *base = phy->regs; | |
01d6ea31 | 224 | u32 val; |
91a687d8 | 225 | |
3e635202 | 226 | if (phy->soc_config->has_hostpc) { |
b07e5f86 | 227 | val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); |
3e635202 TT |
228 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0); |
229 | val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val); | |
b07e5f86 | 230 | writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); |
3e635202 | 231 | } else { |
b07e5f86 DO |
232 | val = readl_relaxed(base + TEGRA_USB_PORTSC1); |
233 | val &= ~TEGRA_PORTSC1_RWC_BITS; | |
3e635202 TT |
234 | val &= ~TEGRA_USB_PORTSC1_PTS(~0); |
235 | val |= TEGRA_USB_PORTSC1_PTS(pts_val); | |
b07e5f86 | 236 | writel_relaxed(val, base + TEGRA_USB_PORTSC1); |
3e635202 | 237 | } |
91a687d8 SW |
238 | } |
239 | ||
240 | static void set_phcd(struct tegra_usb_phy *phy, bool enable) | |
241 | { | |
242 | void __iomem *base = phy->regs; | |
01d6ea31 | 243 | u32 val; |
91a687d8 | 244 | |
3e635202 | 245 | if (phy->soc_config->has_hostpc) { |
b07e5f86 | 246 | val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC); |
3e635202 TT |
247 | if (enable) |
248 | val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD; | |
249 | else | |
250 | val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD; | |
b07e5f86 | 251 | writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC); |
3e635202 | 252 | } else { |
b07e5f86 | 253 | val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; |
3e635202 TT |
254 | if (enable) |
255 | val |= TEGRA_USB_PORTSC1_PHCD; | |
256 | else | |
257 | val &= ~TEGRA_USB_PORTSC1_PHCD; | |
b07e5f86 | 258 | writel_relaxed(val, base + TEGRA_USB_PORTSC1); |
3e635202 | 259 | } |
91a687d8 SW |
260 | } |
261 | ||
91525d08 BG |
262 | static int utmip_pad_open(struct tegra_usb_phy *phy) |
263 | { | |
14347036 | 264 | int ret; |
f59cd940 | 265 | |
14347036 DO |
266 | ret = clk_prepare_enable(phy->pad_clk); |
267 | if (ret) { | |
268 | dev_err(phy->u_phy.dev, | |
269 | "Failed to enable UTMI-pads clock: %d\n", ret); | |
270 | return ret; | |
271 | } | |
272 | ||
273 | spin_lock(&utmip_pad_lock); | |
274 | ||
275 | ret = reset_control_deassert(phy->pad_rst); | |
276 | if (ret) { | |
277 | dev_err(phy->u_phy.dev, | |
278 | "Failed to initialize UTMI-pads reset: %d\n", ret); | |
279 | goto unlock; | |
280 | } | |
281 | ||
282 | ret = reset_control_assert(phy->pad_rst); | |
283 | if (ret) { | |
284 | dev_err(phy->u_phy.dev, | |
285 | "Failed to assert UTMI-pads reset: %d\n", ret); | |
286 | goto unlock; | |
287 | } | |
288 | ||
289 | udelay(1); | |
290 | ||
291 | ret = reset_control_deassert(phy->pad_rst); | |
292 | if (ret) | |
293 | dev_err(phy->u_phy.dev, | |
294 | "Failed to deassert UTMI-pads reset: %d\n", ret); | |
295 | unlock: | |
296 | spin_unlock(&utmip_pad_lock); | |
297 | ||
298 | clk_disable_unprepare(phy->pad_clk); | |
299 | ||
300 | return ret; | |
301 | } | |
302 | ||
303 | static int utmip_pad_close(struct tegra_usb_phy *phy) | |
304 | { | |
305 | int ret; | |
306 | ||
307 | ret = clk_prepare_enable(phy->pad_clk); | |
308 | if (ret) { | |
309 | dev_err(phy->u_phy.dev, | |
310 | "Failed to enable UTMI-pads clock: %d\n", ret); | |
311 | return ret; | |
312 | } | |
313 | ||
314 | ret = reset_control_assert(phy->pad_rst); | |
315 | if (ret) | |
316 | dev_err(phy->u_phy.dev, | |
317 | "Failed to assert UTMI-pads reset: %d\n", ret); | |
318 | ||
319 | udelay(1); | |
320 | ||
321 | clk_disable_unprepare(phy->pad_clk); | |
322 | ||
323 | return ret; | |
91525d08 BG |
324 | } |
325 | ||
545592e8 | 326 | static int utmip_pad_power_on(struct tegra_usb_phy *phy) |
91525d08 | 327 | { |
e497a24d | 328 | struct tegra_utmip_config *config = phy->config; |
545592e8 | 329 | void __iomem *base = phy->pad_regs; |
01d6ea31 | 330 | u32 val; |
545592e8 | 331 | int err; |
91525d08 | 332 | |
545592e8 DO |
333 | err = clk_prepare_enable(phy->pad_clk); |
334 | if (err) | |
335 | return err; | |
91525d08 | 336 | |
f1f0c751 | 337 | spin_lock(&utmip_pad_lock); |
91525d08 BG |
338 | |
339 | if (utmip_pad_count++ == 0) { | |
b07e5f86 | 340 | val = readl_relaxed(base + UTMIP_BIAS_CFG0); |
91525d08 | 341 | val &= ~(UTMIP_OTGPD | UTMIP_BIASPD); |
e497a24d TT |
342 | |
343 | if (phy->soc_config->requires_extra_tuning_parameters) { | |
344 | val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) | | |
345 | UTMIP_HSDISCON_LEVEL(~0) | | |
346 | UTMIP_HSDISCON_LEVEL_MSB(~0)); | |
347 | ||
348 | val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level); | |
349 | val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level); | |
350 | val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level); | |
351 | } | |
b07e5f86 | 352 | writel_relaxed(val, base + UTMIP_BIAS_CFG0); |
91525d08 BG |
353 | } |
354 | ||
35192007 DO |
355 | if (phy->pad_wakeup) { |
356 | phy->pad_wakeup = false; | |
357 | utmip_pad_count--; | |
358 | } | |
359 | ||
f1f0c751 | 360 | spin_unlock(&utmip_pad_lock); |
91525d08 | 361 | |
6a5278d0 | 362 | clk_disable_unprepare(phy->pad_clk); |
545592e8 DO |
363 | |
364 | return 0; | |
91525d08 BG |
365 | } |
366 | ||
367 | static int utmip_pad_power_off(struct tegra_usb_phy *phy) | |
368 | { | |
91525d08 | 369 | void __iomem *base = phy->pad_regs; |
01d6ea31 | 370 | u32 val; |
92bd2ef2 DO |
371 | int ret; |
372 | ||
373 | ret = clk_prepare_enable(phy->pad_clk); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
f1f0c751 | 377 | spin_lock(&utmip_pad_lock); |
91525d08 BG |
378 | |
379 | if (!utmip_pad_count) { | |
f59cd940 | 380 | dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n"); |
92bd2ef2 DO |
381 | ret = -EINVAL; |
382 | goto ulock; | |
91525d08 BG |
383 | } |
384 | ||
35192007 DO |
385 | /* |
386 | * In accordance to TRM, OTG and Bias pad circuits could be turned off | |
387 | * to save power if wake is enabled, but the VBUS-change detection | |
388 | * method is board-specific and these circuits may need to be enabled | |
389 | * to generate wakeup event, hence we will just keep them both enabled. | |
390 | */ | |
391 | if (phy->wakeup_enabled) { | |
392 | phy->pad_wakeup = true; | |
393 | utmip_pad_count++; | |
394 | } | |
395 | ||
91525d08 | 396 | if (--utmip_pad_count == 0) { |
b07e5f86 | 397 | val = readl_relaxed(base + UTMIP_BIAS_CFG0); |
91525d08 | 398 | val |= UTMIP_OTGPD | UTMIP_BIASPD; |
b07e5f86 | 399 | writel_relaxed(val, base + UTMIP_BIAS_CFG0); |
91525d08 | 400 | } |
92bd2ef2 | 401 | ulock: |
f1f0c751 | 402 | spin_unlock(&utmip_pad_lock); |
91525d08 | 403 | |
6a5278d0 | 404 | clk_disable_unprepare(phy->pad_clk); |
91525d08 | 405 | |
92bd2ef2 | 406 | return ret; |
91525d08 BG |
407 | } |
408 | ||
409 | static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result) | |
410 | { | |
43bcf64e DO |
411 | u32 tmp; |
412 | ||
b07e5f86 DO |
413 | return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result, |
414 | 2000, 6000); | |
91525d08 BG |
415 | } |
416 | ||
417 | static void utmi_phy_clk_disable(struct tegra_usb_phy *phy) | |
418 | { | |
91525d08 | 419 | void __iomem *base = phy->regs; |
01d6ea31 | 420 | u32 val; |
91525d08 | 421 | |
203f44c4 JH |
422 | /* |
423 | * The USB driver may have already initiated the phy clock | |
424 | * disable so wait to see if the clock turns off and if not | |
425 | * then proceed with gating the clock. | |
426 | */ | |
427 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0) | |
428 | return; | |
429 | ||
3a55c6a8 | 430 | if (phy->is_legacy_phy) { |
b07e5f86 | 431 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 432 | val |= USB_SUSP_SET; |
b07e5f86 | 433 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 | 434 | |
545592e8 | 435 | usleep_range(10, 100); |
91525d08 | 436 | |
b07e5f86 | 437 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 438 | val &= ~USB_SUSP_SET; |
b07e5f86 | 439 | writel_relaxed(val, base + USB_SUSP_CTRL); |
545592e8 | 440 | } else { |
91a687d8 | 441 | set_phcd(phy, true); |
545592e8 | 442 | } |
91525d08 | 443 | |
545592e8 | 444 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0)) |
f59cd940 DO |
445 | dev_err(phy->u_phy.dev, |
446 | "Timeout waiting for PHY to stabilize on disable\n"); | |
91525d08 BG |
447 | } |
448 | ||
449 | static void utmi_phy_clk_enable(struct tegra_usb_phy *phy) | |
450 | { | |
91525d08 | 451 | void __iomem *base = phy->regs; |
01d6ea31 | 452 | u32 val; |
91525d08 | 453 | |
203f44c4 JH |
454 | /* |
455 | * The USB driver may have already initiated the phy clock | |
456 | * enable so wait to see if the clock turns on and if not | |
457 | * then proceed with ungating the clock. | |
458 | */ | |
459 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
460 | USB_PHY_CLK_VALID) == 0) | |
461 | return; | |
462 | ||
3a55c6a8 | 463 | if (phy->is_legacy_phy) { |
b07e5f86 | 464 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 465 | val |= USB_SUSP_CLR; |
b07e5f86 | 466 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 | 467 | |
545592e8 | 468 | usleep_range(10, 100); |
91525d08 | 469 | |
b07e5f86 | 470 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 471 | val &= ~USB_SUSP_CLR; |
b07e5f86 | 472 | writel_relaxed(val, base + USB_SUSP_CTRL); |
545592e8 | 473 | } else { |
91a687d8 | 474 | set_phcd(phy, false); |
545592e8 | 475 | } |
91525d08 BG |
476 | |
477 | if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, | |
545592e8 | 478 | USB_PHY_CLK_VALID)) |
f59cd940 DO |
479 | dev_err(phy->u_phy.dev, |
480 | "Timeout waiting for PHY to stabilize on enable\n"); | |
91525d08 BG |
481 | } |
482 | ||
483 | static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |
484 | { | |
91525d08 | 485 | struct tegra_utmip_config *config = phy->config; |
545592e8 | 486 | void __iomem *base = phy->regs; |
01d6ea31 | 487 | u32 val; |
545592e8 | 488 | int err; |
91525d08 | 489 | |
b07e5f86 | 490 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 491 | val |= UTMIP_RESET; |
b07e5f86 | 492 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 | 493 | |
3a55c6a8 | 494 | if (phy->is_legacy_phy) { |
b07e5f86 | 495 | val = readl_relaxed(base + USB1_LEGACY_CTRL); |
91525d08 | 496 | val |= USB1_NO_LEGACY_MODE; |
b07e5f86 | 497 | writel_relaxed(val, base + USB1_LEGACY_CTRL); |
91525d08 BG |
498 | } |
499 | ||
b07e5f86 | 500 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
f5833a0b | 501 | val |= UTMIP_FS_PREABMLE_J; |
b07e5f86 | 502 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
91525d08 | 503 | |
b07e5f86 | 504 | val = readl_relaxed(base + UTMIP_HSRX_CFG0); |
91525d08 BG |
505 | val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0)); |
506 | val |= UTMIP_IDLE_WAIT(config->idle_wait_delay); | |
507 | val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit); | |
b07e5f86 | 508 | writel_relaxed(val, base + UTMIP_HSRX_CFG0); |
91525d08 | 509 | |
b07e5f86 | 510 | val = readl_relaxed(base + UTMIP_HSRX_CFG1); |
91525d08 BG |
511 | val &= ~UTMIP_HS_SYNC_START_DLY(~0); |
512 | val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay); | |
b07e5f86 | 513 | writel_relaxed(val, base + UTMIP_HSRX_CFG1); |
91525d08 | 514 | |
b07e5f86 | 515 | val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0); |
91525d08 BG |
516 | val &= ~UTMIP_BIAS_DEBOUNCE_A(~0); |
517 | val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce); | |
b07e5f86 | 518 | writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0); |
91525d08 | 519 | |
b07e5f86 | 520 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
91525d08 | 521 | val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE; |
b07e5f86 | 522 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
91525d08 | 523 | |
3e635202 | 524 | if (!phy->soc_config->utmi_pll_config_in_car_module) { |
b07e5f86 | 525 | val = readl_relaxed(base + UTMIP_MISC_CFG1); |
3e635202 TT |
526 | val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) | |
527 | UTMIP_PLLU_STABLE_COUNT(~0)); | |
528 | val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) | | |
529 | UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count); | |
b07e5f86 | 530 | writel_relaxed(val, base + UTMIP_MISC_CFG1); |
3e635202 | 531 | |
b07e5f86 | 532 | val = readl_relaxed(base + UTMIP_PLL_CFG1); |
3e635202 TT |
533 | val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) | |
534 | UTMIP_PLLU_ENABLE_DLY_COUNT(~0)); | |
535 | val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) | | |
536 | UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay); | |
b07e5f86 | 537 | writel_relaxed(val, base + UTMIP_PLL_CFG1); |
3e635202 | 538 | } |
91525d08 | 539 | |
35192007 DO |
540 | val = readl_relaxed(base + USB_SUSP_CTRL); |
541 | val &= ~USB_WAKE_ON_RESUME_EN; | |
542 | writel_relaxed(val, base + USB_SUSP_CTRL); | |
543 | ||
c1baf6c5 | 544 | if (phy->mode != USB_DR_MODE_HOST) { |
b07e5f86 | 545 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 546 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); |
b07e5f86 | 547 | writel_relaxed(val, base + USB_SUSP_CTRL); |
f5833a0b | 548 | |
35192007 DO |
549 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
550 | val &= ~VBUS_WAKEUP_WAKEUP_EN; | |
c1baf6c5 | 551 | val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); |
35192007 DO |
552 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
553 | ||
554 | val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); | |
555 | val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN); | |
7917e906 | 556 | val &= ~(B_SESS_VLD_WAKEUP_EN); |
35192007 DO |
557 | writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); |
558 | ||
b07e5f86 | 559 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
f5833a0b | 560 | val &= ~UTMIP_PD_CHRG; |
b07e5f86 | 561 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
f5833a0b | 562 | } else { |
b07e5f86 | 563 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
f5833a0b | 564 | val |= UTMIP_PD_CHRG; |
b07e5f86 | 565 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
91525d08 BG |
566 | } |
567 | ||
545592e8 DO |
568 | err = utmip_pad_power_on(phy); |
569 | if (err) | |
570 | return err; | |
91525d08 | 571 | |
b07e5f86 | 572 | val = readl_relaxed(base + UTMIP_XCVR_CFG0); |
91525d08 | 573 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | |
f5833a0b TT |
574 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | |
575 | UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | | |
e497a24d TT |
576 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0)); |
577 | ||
578 | if (!config->xcvr_setup_use_fuses) { | |
579 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | |
580 | val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); | |
581 | } | |
91525d08 BG |
582 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); |
583 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | |
e497a24d TT |
584 | |
585 | if (phy->soc_config->requires_extra_tuning_parameters) { | |
586 | val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0)); | |
587 | val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew); | |
588 | val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew); | |
589 | } | |
b07e5f86 | 590 | writel_relaxed(val, base + UTMIP_XCVR_CFG0); |
91525d08 | 591 | |
b07e5f86 | 592 | val = readl_relaxed(base + UTMIP_XCVR_CFG1); |
91525d08 BG |
593 | val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | |
594 | UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0)); | |
595 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | |
b07e5f86 | 596 | writel_relaxed(val, base + UTMIP_XCVR_CFG1); |
91525d08 | 597 | |
b07e5f86 | 598 | val = readl_relaxed(base + UTMIP_BIAS_CFG1); |
91525d08 BG |
599 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); |
600 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | |
b07e5f86 | 601 | writel_relaxed(val, base + UTMIP_BIAS_CFG1); |
91525d08 | 602 | |
b07e5f86 | 603 | val = readl_relaxed(base + UTMIP_SPARE_CFG0); |
e497a24d TT |
604 | if (config->xcvr_setup_use_fuses) |
605 | val |= FUSE_SETUP_SEL; | |
606 | else | |
607 | val &= ~FUSE_SETUP_SEL; | |
b07e5f86 | 608 | writel_relaxed(val, base + UTMIP_SPARE_CFG0); |
e497a24d TT |
609 | |
610 | if (!phy->is_legacy_phy) { | |
b07e5f86 | 611 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 612 | val |= UTMIP_PHY_ENABLE; |
b07e5f86 | 613 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 BG |
614 | } |
615 | ||
b07e5f86 | 616 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 617 | val &= ~UTMIP_RESET; |
b07e5f86 | 618 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 | 619 | |
3a55c6a8 | 620 | if (phy->is_legacy_phy) { |
b07e5f86 | 621 | val = readl_relaxed(base + USB1_LEGACY_CTRL); |
91525d08 BG |
622 | val &= ~USB1_VBUS_SENSE_CTL_MASK; |
623 | val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD; | |
b07e5f86 | 624 | writel_relaxed(val, base + USB1_LEGACY_CTRL); |
91525d08 | 625 | |
b07e5f86 | 626 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 627 | val &= ~USB_SUSP_SET; |
b07e5f86 | 628 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 BG |
629 | } |
630 | ||
631 | utmi_phy_clk_enable(phy); | |
632 | ||
3e635202 | 633 | if (phy->soc_config->requires_usbmode_setup) { |
b07e5f86 | 634 | val = readl_relaxed(base + USB_USBMODE); |
3e635202 TT |
635 | val &= ~USB_USBMODE_MASK; |
636 | if (phy->mode == USB_DR_MODE_HOST) | |
637 | val |= USB_USBMODE_HOST; | |
638 | else | |
639 | val |= USB_USBMODE_DEVICE; | |
b07e5f86 | 640 | writel_relaxed(val, base + USB_USBMODE); |
3e635202 TT |
641 | } |
642 | ||
bbdabdb6 | 643 | if (!phy->is_legacy_phy) |
91a687d8 | 644 | set_pts(phy, 0); |
91525d08 BG |
645 | |
646 | return 0; | |
647 | } | |
648 | ||
1ba8216f | 649 | static int utmi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 | 650 | { |
91525d08 | 651 | void __iomem *base = phy->regs; |
01d6ea31 | 652 | u32 val; |
91525d08 | 653 | |
6f8d39a8 DO |
654 | /* |
655 | * Give hardware time to settle down after VBUS disconnection, | |
656 | * otherwise PHY will immediately wake up from suspend. | |
657 | */ | |
658 | if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST) | |
659 | readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID, | |
660 | val, !(val & VBUS_WAKEUP_STS), | |
661 | 5000, 100000); | |
662 | ||
91525d08 BG |
663 | utmi_phy_clk_disable(phy); |
664 | ||
35192007 DO |
665 | /* PHY won't resume if reset is asserted */ |
666 | if (!phy->wakeup_enabled) { | |
b07e5f86 | 667 | val = readl_relaxed(base + USB_SUSP_CTRL); |
35192007 | 668 | val |= UTMIP_RESET; |
b07e5f86 | 669 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 BG |
670 | } |
671 | ||
b07e5f86 | 672 | val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0); |
91525d08 | 673 | val |= UTMIP_PD_CHRG; |
b07e5f86 | 674 | writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0); |
91525d08 | 675 | |
35192007 DO |
676 | if (!phy->wakeup_enabled) { |
677 | val = readl_relaxed(base + UTMIP_XCVR_CFG0); | |
678 | val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | |
679 | UTMIP_FORCE_PDZI_POWERDOWN; | |
680 | writel_relaxed(val, base + UTMIP_XCVR_CFG0); | |
681 | } | |
91525d08 | 682 | |
b07e5f86 | 683 | val = readl_relaxed(base + UTMIP_XCVR_CFG1); |
91525d08 BG |
684 | val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | |
685 | UTMIP_FORCE_PDDR_POWERDOWN; | |
b07e5f86 | 686 | writel_relaxed(val, base + UTMIP_XCVR_CFG1); |
91525d08 | 687 | |
35192007 DO |
688 | if (phy->wakeup_enabled) { |
689 | val = readl_relaxed(base + USB_SUSP_CTRL); | |
690 | val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0); | |
691 | val |= USB_WAKEUP_DEBOUNCE_COUNT(5); | |
692 | val |= USB_WAKE_ON_RESUME_EN; | |
693 | writel_relaxed(val, base + USB_SUSP_CTRL); | |
694 | ||
695 | /* | |
696 | * Ask VBUS sensor to generate wake event once cable is | |
697 | * connected. | |
698 | */ | |
c1baf6c5 | 699 | if (phy->mode != USB_DR_MODE_HOST) { |
35192007 DO |
700 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); |
701 | val |= VBUS_WAKEUP_WAKEUP_EN; | |
c1baf6c5 | 702 | val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); |
35192007 DO |
703 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); |
704 | ||
705 | val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); | |
706 | val |= A_VBUS_VLD_WAKEUP_EN; | |
707 | writel_relaxed(val, base + USB_PHY_VBUS_SENSORS); | |
708 | } | |
709 | } | |
710 | ||
1ba8216f | 711 | return utmip_pad_power_off(phy); |
91525d08 BG |
712 | } |
713 | ||
714 | static void utmi_phy_preresume(struct tegra_usb_phy *phy) | |
715 | { | |
91525d08 | 716 | void __iomem *base = phy->regs; |
01d6ea31 | 717 | u32 val; |
91525d08 | 718 | |
b07e5f86 | 719 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
91525d08 | 720 | val |= UTMIP_HS_DISCON_DISABLE; |
b07e5f86 | 721 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
91525d08 BG |
722 | } |
723 | ||
724 | static void utmi_phy_postresume(struct tegra_usb_phy *phy) | |
725 | { | |
91525d08 | 726 | void __iomem *base = phy->regs; |
01d6ea31 | 727 | u32 val; |
91525d08 | 728 | |
b07e5f86 | 729 | val = readl_relaxed(base + UTMIP_TX_CFG0); |
91525d08 | 730 | val &= ~UTMIP_HS_DISCON_DISABLE; |
b07e5f86 | 731 | writel_relaxed(val, base + UTMIP_TX_CFG0); |
91525d08 BG |
732 | } |
733 | ||
734 | static void utmi_phy_restore_start(struct tegra_usb_phy *phy, | |
735 | enum tegra_usb_phy_port_speed port_speed) | |
736 | { | |
91525d08 | 737 | void __iomem *base = phy->regs; |
01d6ea31 | 738 | u32 val; |
91525d08 | 739 | |
b07e5f86 | 740 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
91525d08 BG |
741 | val &= ~UTMIP_DPDM_OBSERVE_SEL(~0); |
742 | if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW) | |
743 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_K; | |
744 | else | |
745 | val |= UTMIP_DPDM_OBSERVE_SEL_FS_J; | |
b07e5f86 | 746 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
545592e8 | 747 | usleep_range(1, 10); |
91525d08 | 748 | |
b07e5f86 | 749 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
91525d08 | 750 | val |= UTMIP_DPDM_OBSERVE; |
b07e5f86 | 751 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
545592e8 | 752 | usleep_range(10, 100); |
91525d08 BG |
753 | } |
754 | ||
755 | static void utmi_phy_restore_end(struct tegra_usb_phy *phy) | |
756 | { | |
91525d08 | 757 | void __iomem *base = phy->regs; |
01d6ea31 | 758 | u32 val; |
91525d08 | 759 | |
b07e5f86 | 760 | val = readl_relaxed(base + UTMIP_MISC_CFG0); |
91525d08 | 761 | val &= ~UTMIP_DPDM_OBSERVE; |
b07e5f86 | 762 | writel_relaxed(val, base + UTMIP_MISC_CFG0); |
545592e8 | 763 | usleep_range(10, 100); |
91525d08 BG |
764 | } |
765 | ||
766 | static int ulpi_phy_power_on(struct tegra_usb_phy *phy) | |
767 | { | |
91525d08 | 768 | void __iomem *base = phy->regs; |
01d6ea31 | 769 | u32 val; |
545592e8 | 770 | int err; |
91525d08 | 771 | |
06e60e50 | 772 | gpiod_set_value_cansleep(phy->reset_gpio, 1); |
545592e8 DO |
773 | |
774 | err = clk_prepare_enable(phy->clk); | |
775 | if (err) | |
776 | return err; | |
777 | ||
778 | usleep_range(5000, 6000); | |
779 | ||
06e60e50 | 780 | gpiod_set_value_cansleep(phy->reset_gpio, 0); |
91525d08 | 781 | |
545592e8 | 782 | usleep_range(1000, 2000); |
91525d08 | 783 | |
b07e5f86 | 784 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 785 | val |= UHSIC_RESET; |
b07e5f86 | 786 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 | 787 | |
b07e5f86 | 788 | val = readl_relaxed(base + ULPI_TIMING_CTRL_0); |
91525d08 | 789 | val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; |
b07e5f86 | 790 | writel_relaxed(val, base + ULPI_TIMING_CTRL_0); |
91525d08 | 791 | |
b07e5f86 | 792 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 793 | val |= ULPI_PHY_ENABLE; |
b07e5f86 | 794 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 BG |
795 | |
796 | val = 0; | |
b07e5f86 | 797 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
91525d08 BG |
798 | |
799 | val |= ULPI_DATA_TRIMMER_SEL(4); | |
800 | val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); | |
801 | val |= ULPI_DIR_TRIMMER_SEL(4); | |
b07e5f86 | 802 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
545592e8 | 803 | usleep_range(10, 100); |
91525d08 BG |
804 | |
805 | val |= ULPI_DATA_TRIMMER_LOAD; | |
806 | val |= ULPI_STPDIRNXT_TRIMMER_LOAD; | |
807 | val |= ULPI_DIR_TRIMMER_LOAD; | |
b07e5f86 | 808 | writel_relaxed(val, base + ULPI_TIMING_CTRL_1); |
91525d08 BG |
809 | |
810 | /* Fix VbusInvalid due to floating VBUS */ | |
545592e8 DO |
811 | err = usb_phy_io_write(phy->ulpi, 0x40, 0x08); |
812 | if (err) { | |
813 | dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err); | |
814 | goto disable_clk; | |
91525d08 BG |
815 | } |
816 | ||
545592e8 DO |
817 | err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B); |
818 | if (err) { | |
819 | dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err); | |
820 | goto disable_clk; | |
91525d08 BG |
821 | } |
822 | ||
b07e5f86 | 823 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 824 | val |= USB_SUSP_CLR; |
b07e5f86 | 825 | writel_relaxed(val, base + USB_SUSP_CTRL); |
545592e8 | 826 | usleep_range(100, 1000); |
91525d08 | 827 | |
b07e5f86 | 828 | val = readl_relaxed(base + USB_SUSP_CTRL); |
91525d08 | 829 | val &= ~USB_SUSP_CLR; |
b07e5f86 | 830 | writel_relaxed(val, base + USB_SUSP_CTRL); |
91525d08 BG |
831 | |
832 | return 0; | |
545592e8 DO |
833 | |
834 | disable_clk: | |
835 | clk_disable_unprepare(phy->clk); | |
836 | ||
837 | return err; | |
91525d08 BG |
838 | } |
839 | ||
1ba8216f | 840 | static int ulpi_phy_power_off(struct tegra_usb_phy *phy) |
91525d08 | 841 | { |
06e60e50 | 842 | gpiod_set_value_cansleep(phy->reset_gpio, 1); |
28d190ac | 843 | usleep_range(5000, 6000); |
28d190ac DO |
844 | clk_disable_unprepare(phy->clk); |
845 | ||
35192007 DO |
846 | /* |
847 | * Wakeup currently unimplemented for ULPI, thus PHY needs to be | |
848 | * force-resumed. | |
849 | */ | |
850 | if (WARN_ON_ONCE(phy->wakeup_enabled)) { | |
851 | ulpi_phy_power_on(phy); | |
852 | return -EOPNOTSUPP; | |
853 | } | |
854 | ||
28d190ac | 855 | return 0; |
1ba8216f VB |
856 | } |
857 | ||
1ba8216f VB |
858 | static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) |
859 | { | |
18bd8bff DO |
860 | int err; |
861 | ||
862 | if (phy->powered_on) | |
863 | return 0; | |
864 | ||
3f9db1a1 | 865 | if (phy->is_ulpi_phy) |
18bd8bff | 866 | err = ulpi_phy_power_on(phy); |
1ba8216f | 867 | else |
18bd8bff DO |
868 | err = utmi_phy_power_on(phy); |
869 | if (err) | |
870 | return err; | |
871 | ||
872 | phy->powered_on = true; | |
873 | ||
b100402e DO |
874 | /* Let PHY settle down */ |
875 | usleep_range(2000, 2500); | |
876 | ||
18bd8bff | 877 | return 0; |
1ba8216f VB |
878 | } |
879 | ||
880 | static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) | |
881 | { | |
18bd8bff DO |
882 | int err; |
883 | ||
884 | if (!phy->powered_on) | |
885 | return 0; | |
886 | ||
3f9db1a1 | 887 | if (phy->is_ulpi_phy) |
18bd8bff | 888 | err = ulpi_phy_power_off(phy); |
1ba8216f | 889 | else |
18bd8bff DO |
890 | err = utmi_phy_power_off(phy); |
891 | if (err) | |
892 | return err; | |
893 | ||
894 | phy->powered_on = false; | |
895 | ||
896 | return 0; | |
1ba8216f VB |
897 | } |
898 | ||
5dcdafdd DO |
899 | static void tegra_usb_phy_shutdown(struct usb_phy *u_phy) |
900 | { | |
545592e8 | 901 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
5dcdafdd DO |
902 | |
903 | if (WARN_ON(!phy->freq)) | |
904 | return; | |
905 | ||
c1baf6c5 | 906 | usb_phy_set_wakeup(u_phy, false); |
5dcdafdd DO |
907 | tegra_usb_phy_power_off(phy); |
908 | ||
909 | if (!phy->is_ulpi_phy) | |
910 | utmip_pad_close(phy); | |
911 | ||
9df3adca | 912 | regulator_disable(phy->vbus); |
5dcdafdd DO |
913 | clk_disable_unprepare(phy->pll_u); |
914 | ||
915 | phy->freq = NULL; | |
916 | } | |
917 | ||
c1baf6c5 DO |
918 | static irqreturn_t tegra_usb_phy_isr(int irq, void *data) |
919 | { | |
920 | u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET; | |
921 | struct tegra_usb_phy *phy = data; | |
922 | void __iomem *base = phy->regs; | |
923 | ||
924 | /* | |
925 | * The PHY interrupt also wakes the USB controller driver since | |
926 | * interrupt is shared. We don't do anything in the PHY driver, | |
927 | * so just clear the interrupt. | |
928 | */ | |
929 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); | |
930 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); | |
931 | ||
932 | return val & int_mask ? IRQ_HANDLED : IRQ_NONE; | |
933 | } | |
934 | ||
35192007 DO |
935 | static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable) |
936 | { | |
937 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); | |
c1baf6c5 DO |
938 | void __iomem *base = phy->regs; |
939 | int ret = 0; | |
940 | u32 val; | |
941 | ||
942 | if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST && | |
943 | phy->irq > 0) { | |
944 | disable_irq(phy->irq); | |
945 | ||
946 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); | |
947 | val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN); | |
948 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); | |
949 | ||
950 | enable_irq(phy->irq); | |
951 | ||
952 | free_irq(phy->irq, phy); | |
953 | ||
954 | phy->wakeup_enabled = false; | |
955 | } | |
956 | ||
957 | if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) { | |
958 | ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED, | |
959 | dev_name(phy->u_phy.dev), phy); | |
960 | if (!ret) { | |
961 | disable_irq(phy->irq); | |
962 | ||
963 | /* | |
964 | * USB clock will be resumed once wake event will be | |
965 | * generated. The ID-change event requires to have | |
966 | * interrupts enabled, otherwise it won't be generated. | |
967 | */ | |
968 | val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); | |
969 | val |= ID_INT_EN | VBUS_WAKEUP_INT_EN; | |
970 | writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); | |
971 | ||
972 | enable_irq(phy->irq); | |
973 | } else { | |
974 | dev_err(phy->u_phy.dev, | |
975 | "Failed to request interrupt: %d", ret); | |
976 | enable = false; | |
977 | } | |
978 | } | |
35192007 DO |
979 | |
980 | phy->wakeup_enabled = enable; | |
981 | ||
c1baf6c5 | 982 | return ret; |
35192007 DO |
983 | } |
984 | ||
545592e8 | 985 | static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend) |
1ba8216f | 986 | { |
545592e8 | 987 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
c1baf6c5 | 988 | int ret; |
5dcdafdd DO |
989 | |
990 | if (WARN_ON(!phy->freq)) | |
991 | return -EINVAL; | |
992 | ||
c1baf6c5 DO |
993 | /* |
994 | * PHY is sharing IRQ with the CI driver, hence here we either | |
995 | * disable interrupt for both PHY and CI or for CI only. The | |
996 | * interrupt needs to be disabled while hardware is reprogrammed | |
997 | * because interrupt touches the programmed registers, and thus, | |
998 | * there could be a race condition. | |
999 | */ | |
1000 | if (phy->irq > 0) | |
1001 | disable_irq(phy->irq); | |
1002 | ||
1ba8216f | 1003 | if (suspend) |
c1baf6c5 | 1004 | ret = tegra_usb_phy_power_off(phy); |
1ba8216f | 1005 | else |
c1baf6c5 DO |
1006 | ret = tegra_usb_phy_power_on(phy); |
1007 | ||
1008 | if (phy->irq > 0) | |
1009 | enable_irq(phy->irq); | |
1010 | ||
1011 | return ret; | |
1012 | } | |
1013 | ||
1014 | static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy) | |
1015 | { | |
1016 | int err, val = 0; | |
1017 | ||
1018 | /* older device-trees don't have PMC regmap */ | |
1019 | if (!phy->pmc_regmap) | |
1020 | return 0; | |
1021 | ||
1022 | /* | |
1023 | * Tegra20 has a different layout of PMC USB register bits and AO is | |
1024 | * enabled by default after system reset on Tegra20, so assume nothing | |
1025 | * to do on Tegra20. | |
1026 | */ | |
1027 | if (!phy->soc_config->requires_pmc_ao_power_up) | |
1028 | return 0; | |
1029 | ||
1030 | /* enable VBUS wake-up detector */ | |
1031 | if (phy->mode != USB_DR_MODE_HOST) | |
1032 | val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4; | |
1033 | ||
1034 | /* enable ID-pin ACC detector for OTG mode switching */ | |
1035 | if (phy->mode == USB_DR_MODE_OTG) | |
1036 | val |= ID_PD_P0 << phy->instance * 4; | |
1037 | ||
1038 | /* disable detectors to reset them */ | |
1039 | err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val); | |
1040 | if (err) { | |
1041 | dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err); | |
1042 | return err; | |
1043 | } | |
1044 | ||
1045 | usleep_range(10, 100); | |
1046 | ||
1047 | /* enable detectors */ | |
1048 | err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val); | |
1049 | if (err) { | |
1050 | dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err); | |
1051 | return err; | |
1052 | } | |
1053 | ||
1054 | /* detectors starts to work after 10ms */ | |
1055 | usleep_range(10000, 15000); | |
1056 | ||
1057 | return 0; | |
91525d08 BG |
1058 | } |
1059 | ||
5dcdafdd | 1060 | static int tegra_usb_phy_init(struct usb_phy *u_phy) |
2d22b42d | 1061 | { |
545592e8 | 1062 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
2d22b42d | 1063 | unsigned long parent_rate; |
545592e8 | 1064 | unsigned int i; |
2d22b42d VB |
1065 | int err; |
1066 | ||
5dcdafdd DO |
1067 | if (WARN_ON(phy->freq)) |
1068 | return 0; | |
2d22b42d VB |
1069 | |
1070 | err = clk_prepare_enable(phy->pll_u); | |
1071 | if (err) | |
1072 | return err; | |
91525d08 BG |
1073 | |
1074 | parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); | |
1075 | for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) { | |
1076 | if (tegra_freq_table[i].freq == parent_rate) { | |
1077 | phy->freq = &tegra_freq_table[i]; | |
1078 | break; | |
1079 | } | |
1080 | } | |
1081 | if (!phy->freq) { | |
f59cd940 DO |
1082 | dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n", |
1083 | parent_rate); | |
91525d08 | 1084 | err = -EINVAL; |
aecc5af3 | 1085 | goto disable_clk; |
91525d08 BG |
1086 | } |
1087 | ||
9df3adca DO |
1088 | err = regulator_enable(phy->vbus); |
1089 | if (err) { | |
1090 | dev_err(phy->u_phy.dev, | |
1091 | "Failed to enable USB VBUS regulator: %d\n", err); | |
aecc5af3 | 1092 | goto disable_clk; |
f5b8c8b6 MP |
1093 | } |
1094 | ||
06e60e50 | 1095 | if (!phy->is_ulpi_phy) { |
2d22b42d | 1096 | err = utmip_pad_open(phy); |
06e60e50 | 1097 | if (err) |
aecc5af3 | 1098 | goto disable_vbus; |
06e60e50 | 1099 | } |
91525d08 | 1100 | |
c1baf6c5 DO |
1101 | err = tegra_usb_phy_configure_pmc(phy); |
1102 | if (err) | |
1103 | goto close_phy; | |
1104 | ||
5dcdafdd DO |
1105 | err = tegra_usb_phy_power_on(phy); |
1106 | if (err) | |
1107 | goto close_phy; | |
1108 | ||
2d22b42d | 1109 | return 0; |
91525d08 | 1110 | |
5dcdafdd DO |
1111 | close_phy: |
1112 | if (!phy->is_ulpi_phy) | |
1113 | utmip_pad_close(phy); | |
aecc5af3 DO |
1114 | |
1115 | disable_vbus: | |
1116 | regulator_disable(phy->vbus); | |
1117 | ||
1118 | disable_clk: | |
6a5278d0 | 1119 | clk_disable_unprepare(phy->pll_u); |
5dcdafdd DO |
1120 | |
1121 | phy->freq = NULL; | |
1122 | ||
2d22b42d | 1123 | return err; |
91525d08 BG |
1124 | } |
1125 | ||
545592e8 | 1126 | void tegra_usb_phy_preresume(struct usb_phy *u_phy) |
91525d08 | 1127 | { |
545592e8 | 1128 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
ab137d04 | 1129 | |
3f9db1a1 | 1130 | if (!phy->is_ulpi_phy) |
91525d08 BG |
1131 | utmi_phy_preresume(phy); |
1132 | } | |
4265cbfd | 1133 | EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume); |
91525d08 | 1134 | |
545592e8 | 1135 | void tegra_usb_phy_postresume(struct usb_phy *u_phy) |
91525d08 | 1136 | { |
545592e8 | 1137 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
ab137d04 | 1138 | |
3f9db1a1 | 1139 | if (!phy->is_ulpi_phy) |
91525d08 BG |
1140 | utmi_phy_postresume(phy); |
1141 | } | |
4265cbfd | 1142 | EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume); |
91525d08 | 1143 | |
545592e8 DO |
1144 | void tegra_ehci_phy_restore_start(struct usb_phy *u_phy, |
1145 | enum tegra_usb_phy_port_speed port_speed) | |
91525d08 | 1146 | { |
545592e8 | 1147 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
ab137d04 | 1148 | |
3f9db1a1 | 1149 | if (!phy->is_ulpi_phy) |
91525d08 BG |
1150 | utmi_phy_restore_start(phy, port_speed); |
1151 | } | |
4265cbfd | 1152 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start); |
91525d08 | 1153 | |
545592e8 | 1154 | void tegra_ehci_phy_restore_end(struct usb_phy *u_phy) |
91525d08 | 1155 | { |
545592e8 | 1156 | struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); |
ab137d04 | 1157 | |
3f9db1a1 | 1158 | if (!phy->is_ulpi_phy) |
91525d08 BG |
1159 | utmi_phy_restore_end(phy); |
1160 | } | |
4265cbfd | 1161 | EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end); |
91525d08 | 1162 | |
81d5dfe6 MP |
1163 | static int read_utmi_param(struct platform_device *pdev, const char *param, |
1164 | u8 *dest) | |
1165 | { | |
1166 | u32 value; | |
545592e8 DO |
1167 | int err; |
1168 | ||
1169 | err = of_property_read_u32(pdev->dev.of_node, param, &value); | |
1170 | if (err) | |
f59cd940 DO |
1171 | dev_err(&pdev->dev, |
1172 | "Failed to read USB UTMI parameter %s: %d\n", | |
81d5dfe6 | 1173 | param, err); |
545592e8 DO |
1174 | else |
1175 | *dest = value; | |
1176 | ||
81d5dfe6 MP |
1177 | return err; |
1178 | } | |
1179 | ||
1180 | static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, | |
1181 | struct platform_device *pdev) | |
1182 | { | |
545592e8 | 1183 | struct tegra_utmip_config *config; |
81d5dfe6 MP |
1184 | struct resource *res; |
1185 | int err; | |
81d5dfe6 MP |
1186 | |
1187 | tegra_phy->is_ulpi_phy = false; | |
1188 | ||
1189 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1190 | if (!res) { | |
f59cd940 | 1191 | dev_err(&pdev->dev, "Failed to get UTMI pad regs\n"); |
81d5dfe6 MP |
1192 | return -ENXIO; |
1193 | } | |
1194 | ||
a4a60194 DO |
1195 | /* |
1196 | * Note that UTMI pad registers are shared by all PHYs, therefore | |
1197 | * devm_platform_ioremap_resource() can't be used here. | |
1198 | */ | |
81d5dfe6 | 1199 | tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start, |
545592e8 | 1200 | resource_size(res)); |
851dd02b | 1201 | if (!tegra_phy->pad_regs) { |
f59cd940 | 1202 | dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n"); |
81d5dfe6 MP |
1203 | return -ENOMEM; |
1204 | } | |
1205 | ||
9ce9ec95 TR |
1206 | tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config), |
1207 | GFP_KERNEL); | |
01ad32d5 | 1208 | if (!tegra_phy->config) |
81d5dfe6 | 1209 | return -ENOMEM; |
81d5dfe6 MP |
1210 | |
1211 | config = tegra_phy->config; | |
1212 | ||
1213 | err = read_utmi_param(pdev, "nvidia,hssync-start-delay", | |
545592e8 DO |
1214 | &config->hssync_start_delay); |
1215 | if (err) | |
81d5dfe6 MP |
1216 | return err; |
1217 | ||
1218 | err = read_utmi_param(pdev, "nvidia,elastic-limit", | |
545592e8 DO |
1219 | &config->elastic_limit); |
1220 | if (err) | |
81d5dfe6 MP |
1221 | return err; |
1222 | ||
1223 | err = read_utmi_param(pdev, "nvidia,idle-wait-delay", | |
545592e8 DO |
1224 | &config->idle_wait_delay); |
1225 | if (err) | |
81d5dfe6 MP |
1226 | return err; |
1227 | ||
1228 | err = read_utmi_param(pdev, "nvidia,term-range-adj", | |
545592e8 DO |
1229 | &config->term_range_adj); |
1230 | if (err) | |
81d5dfe6 MP |
1231 | return err; |
1232 | ||
81d5dfe6 | 1233 | err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew", |
545592e8 DO |
1234 | &config->xcvr_lsfslew); |
1235 | if (err) | |
81d5dfe6 MP |
1236 | return err; |
1237 | ||
1238 | err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew", | |
545592e8 DO |
1239 | &config->xcvr_lsrslew); |
1240 | if (err) | |
81d5dfe6 MP |
1241 | return err; |
1242 | ||
e497a24d TT |
1243 | if (tegra_phy->soc_config->requires_extra_tuning_parameters) { |
1244 | err = read_utmi_param(pdev, "nvidia,xcvr-hsslew", | |
545592e8 DO |
1245 | &config->xcvr_hsslew); |
1246 | if (err) | |
e497a24d TT |
1247 | return err; |
1248 | ||
1249 | err = read_utmi_param(pdev, "nvidia,hssquelch-level", | |
545592e8 DO |
1250 | &config->hssquelch_level); |
1251 | if (err) | |
e497a24d TT |
1252 | return err; |
1253 | ||
1254 | err = read_utmi_param(pdev, "nvidia,hsdiscon-level", | |
545592e8 DO |
1255 | &config->hsdiscon_level); |
1256 | if (err) | |
e497a24d TT |
1257 | return err; |
1258 | } | |
1259 | ||
1260 | config->xcvr_setup_use_fuses = of_property_read_bool( | |
1261 | pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses"); | |
1262 | ||
1263 | if (!config->xcvr_setup_use_fuses) { | |
1264 | err = read_utmi_param(pdev, "nvidia,xcvr-setup", | |
545592e8 DO |
1265 | &config->xcvr_setup); |
1266 | if (err) | |
e497a24d TT |
1267 | return err; |
1268 | } | |
1269 | ||
81d5dfe6 MP |
1270 | return 0; |
1271 | } | |
1272 | ||
c1baf6c5 DO |
1273 | static void tegra_usb_phy_put_pmc_device(void *dev) |
1274 | { | |
1275 | put_device(dev); | |
1276 | } | |
1277 | ||
1278 | static int tegra_usb_phy_parse_pmc(struct device *dev, | |
1279 | struct tegra_usb_phy *phy) | |
1280 | { | |
1281 | struct platform_device *pmc_pdev; | |
1282 | struct of_phandle_args args; | |
1283 | int err; | |
1284 | ||
1285 | err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc", | |
1286 | 1, 0, &args); | |
1287 | if (err) { | |
1288 | if (err != -ENOENT) | |
1289 | return err; | |
1290 | ||
1291 | dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n"); | |
1292 | return 0; | |
1293 | } | |
1294 | ||
1295 | pmc_pdev = of_find_device_by_node(args.np); | |
1296 | of_node_put(args.np); | |
1297 | if (!pmc_pdev) | |
1298 | return -ENODEV; | |
1299 | ||
1300 | err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device, | |
1301 | &pmc_pdev->dev); | |
1302 | if (err) | |
1303 | return err; | |
1304 | ||
1305 | if (!platform_get_drvdata(pmc_pdev)) | |
1306 | return -EPROBE_DEFER; | |
1307 | ||
1308 | phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk"); | |
1309 | if (!phy->pmc_regmap) | |
1310 | return -EINVAL; | |
1311 | ||
1312 | phy->instance = args.args[0]; | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
3e635202 TT |
1317 | static const struct tegra_phy_soc_config tegra20_soc_config = { |
1318 | .utmi_pll_config_in_car_module = false, | |
1319 | .has_hostpc = false, | |
1320 | .requires_usbmode_setup = false, | |
1321 | .requires_extra_tuning_parameters = false, | |
c1baf6c5 | 1322 | .requires_pmc_ao_power_up = false, |
3e635202 TT |
1323 | }; |
1324 | ||
1325 | static const struct tegra_phy_soc_config tegra30_soc_config = { | |
1326 | .utmi_pll_config_in_car_module = true, | |
1327 | .has_hostpc = true, | |
1328 | .requires_usbmode_setup = true, | |
1329 | .requires_extra_tuning_parameters = true, | |
c1baf6c5 | 1330 | .requires_pmc_ao_power_up = true, |
3e635202 TT |
1331 | }; |
1332 | ||
0f0520ba | 1333 | static const struct of_device_id tegra_usb_phy_id_table[] = { |
3e635202 TT |
1334 | { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config }, |
1335 | { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config }, | |
1336 | { }, | |
1337 | }; | |
1338 | MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table); | |
1339 | ||
2d22b42d VB |
1340 | static int tegra_usb_phy_probe(struct platform_device *pdev) |
1341 | { | |
2d22b42d | 1342 | struct device_node *np = pdev->dev.of_node; |
545592e8 | 1343 | struct tegra_usb_phy *tegra_phy; |
9fdb07f7 | 1344 | enum usb_phy_interface phy_type; |
545592e8 | 1345 | struct reset_control *reset; |
06e60e50 | 1346 | struct gpio_desc *gpiod; |
545592e8 | 1347 | struct resource *res; |
87541747 | 1348 | struct usb_phy *phy; |
2d22b42d VB |
1349 | int err; |
1350 | ||
1351 | tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL); | |
01ad32d5 | 1352 | if (!tegra_phy) |
2d22b42d | 1353 | return -ENOMEM; |
2d22b42d | 1354 | |
545592e8 | 1355 | tegra_phy->soc_config = of_device_get_match_data(&pdev->dev); |
c1baf6c5 | 1356 | tegra_phy->irq = platform_get_irq_optional(pdev, 0); |
3e635202 | 1357 | |
2d22b42d VB |
1358 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1359 | if (!res) { | |
1360 | dev_err(&pdev->dev, "Failed to get I/O memory\n"); | |
1361 | return -ENXIO; | |
1362 | } | |
1363 | ||
a4a60194 DO |
1364 | /* |
1365 | * Note that PHY and USB controller are using shared registers, | |
1366 | * therefore devm_platform_ioremap_resource() can't be used here. | |
1367 | */ | |
2d22b42d | 1368 | tegra_phy->regs = devm_ioremap(&pdev->dev, res->start, |
545592e8 | 1369 | resource_size(res)); |
2d22b42d VB |
1370 | if (!tegra_phy->regs) { |
1371 | dev_err(&pdev->dev, "Failed to remap I/O memory\n"); | |
1372 | return -ENOMEM; | |
1373 | } | |
1374 | ||
1375 | tegra_phy->is_legacy_phy = | |
1376 | of_property_read_bool(np, "nvidia,has-legacy-mode"); | |
1377 | ||
6558d7ed | 1378 | if (of_find_property(np, "dr_mode", NULL)) |
06e7114f | 1379 | tegra_phy->mode = usb_get_dr_mode(&pdev->dev); |
6558d7ed TT |
1380 | else |
1381 | tegra_phy->mode = USB_DR_MODE_HOST; | |
1382 | ||
1383 | if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) { | |
1384 | dev_err(&pdev->dev, "dr_mode is invalid\n"); | |
1385 | return -EINVAL; | |
1386 | } | |
2d22b42d | 1387 | |
f5b8c8b6 | 1388 | /* On some boards, the VBUS regulator doesn't need to be controlled */ |
9df3adca DO |
1389 | tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus"); |
1390 | if (IS_ERR(tegra_phy->vbus)) | |
1391 | return PTR_ERR(tegra_phy->vbus); | |
f5b8c8b6 | 1392 | |
5dcdafdd DO |
1393 | tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u"); |
1394 | err = PTR_ERR_OR_ZERO(tegra_phy->pll_u); | |
1395 | if (err) { | |
1396 | dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err); | |
2d22b42d | 1397 | return err; |
5dcdafdd DO |
1398 | } |
1399 | ||
c1baf6c5 DO |
1400 | err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy); |
1401 | if (err) { | |
1402 | dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n"); | |
1403 | return err; | |
1404 | } | |
1405 | ||
545592e8 DO |
1406 | phy_type = of_usb_get_phy_mode(np); |
1407 | switch (phy_type) { | |
1408 | case USBPHY_INTERFACE_MODE_UTMI: | |
1409 | err = utmi_phy_probe(tegra_phy, pdev); | |
1410 | if (err) | |
1411 | return err; | |
1412 | ||
1413 | tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads"); | |
1414 | err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk); | |
1415 | if (err) { | |
1416 | dev_err(&pdev->dev, | |
1417 | "Failed to get UTMIP pad clock: %d\n", err); | |
1418 | return err; | |
1419 | } | |
1420 | ||
1421 | reset = devm_reset_control_get_optional_shared(&pdev->dev, | |
1422 | "utmi-pads"); | |
1423 | err = PTR_ERR_OR_ZERO(reset); | |
1424 | if (err) { | |
1425 | dev_err(&pdev->dev, | |
1426 | "Failed to get UTMI-pads reset: %d\n", err); | |
1427 | return err; | |
1428 | } | |
1429 | tegra_phy->pad_rst = reset; | |
1430 | break; | |
1431 | ||
1432 | case USBPHY_INTERFACE_MODE_ULPI: | |
1433 | tegra_phy->is_ulpi_phy = true; | |
1434 | ||
5dcdafdd DO |
1435 | tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link"); |
1436 | err = PTR_ERR_OR_ZERO(tegra_phy->clk); | |
1437 | if (err) { | |
1438 | dev_err(&pdev->dev, | |
1439 | "Failed to get ULPI clock: %d\n", err); | |
1440 | return err; | |
1441 | } | |
2d22b42d | 1442 | |
06e60e50 DO |
1443 | gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np, |
1444 | "nvidia,phy-reset-gpio", | |
1445 | 0, GPIOD_OUT_HIGH, | |
1446 | "ulpi_phy_reset_b"); | |
1447 | err = PTR_ERR_OR_ZERO(gpiod); | |
545592e8 | 1448 | if (err) { |
06e60e50 DO |
1449 | dev_err(&pdev->dev, |
1450 | "Request failed for reset GPIO: %d\n", err); | |
5dcdafdd DO |
1451 | return err; |
1452 | } | |
06e60e50 | 1453 | tegra_phy->reset_gpio = gpiod; |
5dcdafdd | 1454 | |
87541747 DO |
1455 | phy = devm_otg_ulpi_create(&pdev->dev, |
1456 | &ulpi_viewport_access_ops, 0); | |
1457 | if (!phy) { | |
5dcdafdd | 1458 | dev_err(&pdev->dev, "Failed to create ULPI OTG\n"); |
545592e8 | 1459 | return -ENOMEM; |
5dcdafdd DO |
1460 | } |
1461 | ||
87541747 | 1462 | tegra_phy->ulpi = phy; |
5dcdafdd | 1463 | tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT; |
545592e8 | 1464 | break; |
5dcdafdd | 1465 | |
545592e8 DO |
1466 | default: |
1467 | dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n", | |
1468 | phy_type); | |
1469 | return -EINVAL; | |
5dcdafdd DO |
1470 | } |
1471 | ||
1472 | tegra_phy->u_phy.dev = &pdev->dev; | |
1473 | tegra_phy->u_phy.init = tegra_usb_phy_init; | |
1474 | tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown; | |
35192007 | 1475 | tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup; |
5dcdafdd | 1476 | tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend; |
2d22b42d | 1477 | |
72031b52 | 1478 | platform_set_drvdata(pdev, tegra_phy); |
0ee5b4ab | 1479 | |
d410912e | 1480 | return usb_add_phy_dev(&tegra_phy->u_phy); |
0ee5b4ab TT |
1481 | } |
1482 | ||
1483 | static int tegra_usb_phy_remove(struct platform_device *pdev) | |
1484 | { | |
1485 | struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev); | |
1486 | ||
1487 | usb_remove_phy(&tegra_phy->u_phy); | |
5dcdafdd | 1488 | |
2d22b42d VB |
1489 | return 0; |
1490 | } | |
1491 | ||
2d22b42d VB |
1492 | static struct platform_driver tegra_usb_phy_driver = { |
1493 | .probe = tegra_usb_phy_probe, | |
0ee5b4ab | 1494 | .remove = tegra_usb_phy_remove, |
2d22b42d VB |
1495 | .driver = { |
1496 | .name = "tegra-phy", | |
78723920 | 1497 | .of_match_table = tegra_usb_phy_id_table, |
2d22b42d VB |
1498 | }, |
1499 | }; | |
1500 | module_platform_driver(tegra_usb_phy_driver); | |
1501 | ||
587376a1 SW |
1502 | MODULE_DESCRIPTION("Tegra USB PHY driver"); |
1503 | MODULE_LICENSE("GPL v2"); |