[linux-block.git] / drivers / usb / phy / phy-mxs-usb.c

/*
 * Copyright 2012-2013 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
 * on behalf of DENX Software Engineering GmbH
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/usb/otg.h>
#include <linux/stmp_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#define DRIVER_NAME "mxs_phy"

#define HW_USBPHY_PWD				0x00
#define HW_USBPHY_CTRL				0x30
#define HW_USBPHY_CTRL_SET			0x34
#define HW_USBPHY_CTRL_CLR			0x38

#define BM_USBPHY_CTRL_SFTRST			BIT(31)
#define BM_USBPHY_CTRL_CLKGATE			BIT(30)
#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS	BIT(26)
#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE	BIT(25)
#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD	BIT(20)
#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE	BIT(19)
#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL		BIT(18)
#define BM_USBPHY_CTRL_ENUTMILEVEL3		BIT(15)
#define BM_USBPHY_CTRL_ENUTMILEVEL2		BIT(14)
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT	BIT(1)

#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)

/* Do disconnection between PHY and controller without vbus */
#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS	BIT(0)

/*
 * The PHY will be in messy if there is a wakeup after putting
 * bus to suspend (set portsc.suspendM) but before setting PHY to low
 * power mode (set portsc.phcd).
 */
#define MXS_PHY_ABNORMAL_IN_SUSPEND		BIT(1)

/*
 * The SOF sends too fast after resuming, it will cause disconnection
 * between host and high speed device.
 */
#define MXS_PHY_SENDING_SOF_TOO_FAST		BIT(2)

struct mxs_phy_data {
	unsigned int flags;
};

static const struct mxs_phy_data imx23_phy_data = {
	.flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
};

static const struct mxs_phy_data imx6q_phy_data = {
	.flags = MXS_PHY_SENDING_SOF_TOO_FAST |
		MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
};

static const struct mxs_phy_data imx6sl_phy_data = {
	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
};

static const struct of_device_id mxs_phy_dt_ids[] = {
	{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
	{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
	{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);

struct mxs_phy {
	struct usb_phy phy;
	struct clk *clk;
	const struct mxs_phy_data *data;
	struct regmap *regmap_anatop;
};

static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
{
	int ret;
	void __iomem *base = mxs_phy->phy.io_priv;

	ret = stmp_reset_block(base + HW_USBPHY_CTRL);
	if (ret)
		return ret;

	/* Power up the PHY */
	writel(0, base + HW_USBPHY_PWD);

	/*
	 * USB PHY Ctrl Setting
	 * - Auto clock/power on
	 * - Enable full/low speed support
	 */
	writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
		BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
		BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
		BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
		BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
		BM_USBPHY_CTRL_ENUTMILEVEL2 |
		BM_USBPHY_CTRL_ENUTMILEVEL3,
	       base + HW_USBPHY_CTRL_SET);

	return 0;
}

static int mxs_phy_init(struct usb_phy *phy)
{
	int ret;
	struct mxs_phy *mxs_phy = to_mxs_phy(phy);

	ret = clk_prepare_enable(mxs_phy->clk);
	if (ret)
		return ret;

	return mxs_phy_hw_init(mxs_phy);
}

static void mxs_phy_shutdown(struct usb_phy *phy)
{
	struct mxs_phy *mxs_phy = to_mxs_phy(phy);

	writel(BM_USBPHY_CTRL_CLKGATE,
	       phy->io_priv + HW_USBPHY_CTRL_SET);

	clk_disable_unprepare(mxs_phy->clk);
}

static int mxs_phy_suspend(struct usb_phy *x, int suspend)
{
	int ret;
	struct mxs_phy *mxs_phy = to_mxs_phy(x);

	if (suspend) {
		writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
		writel(BM_USBPHY_CTRL_CLKGATE,
		       x->io_priv + HW_USBPHY_CTRL_SET);
		clk_disable_unprepare(mxs_phy->clk);
	} else {
		ret = clk_prepare_enable(mxs_phy->clk);
		if (ret)
			return ret;
		writel(BM_USBPHY_CTRL_CLKGATE,
		       x->io_priv + HW_USBPHY_CTRL_CLR);
		writel(0, x->io_priv + HW_USBPHY_PWD);
	}

	return 0;
}

static int mxs_phy_on_connect(struct usb_phy *phy,
		enum usb_device_speed speed)
{
	dev_dbg(phy->dev, "%s device has connected\n",
		(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");

	if (speed == USB_SPEED_HIGH)
		writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
		       phy->io_priv + HW_USBPHY_CTRL_SET);

	return 0;
}

static int mxs_phy_on_disconnect(struct usb_phy *phy,
		enum usb_device_speed speed)
{
	dev_dbg(phy->dev, "%s device has disconnected\n",
		(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");

	if (speed == USB_SPEED_HIGH)
		writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
		       phy->io_priv + HW_USBPHY_CTRL_CLR);

	return 0;
}

static int mxs_phy_probe(struct platform_device *pdev)
{
	struct resource *res;
	void __iomem *base;
	struct clk *clk;
	struct mxs_phy *mxs_phy;
	int ret;
	const struct of_device_id *of_id =
			of_match_device(mxs_phy_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev,
			"can't get the clock, err=%ld", PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
	if (!mxs_phy) {
		dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
		return -ENOMEM;
	}

	/* Some SoCs don't have anatop registers */
	if (of_get_property(np, "fsl,anatop", NULL)) {
		mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
			(np, "fsl,anatop");
		if (IS_ERR(mxs_phy->regmap_anatop)) {
			dev_dbg(&pdev->dev,
				"failed to find regmap for anatop\n");
			return PTR_ERR(mxs_phy->regmap_anatop);
		}
	}

	mxs_phy->phy.io_priv		= base;
	mxs_phy->phy.dev		= &pdev->dev;
	mxs_phy->phy.label		= DRIVER_NAME;
	mxs_phy->phy.init		= mxs_phy_init;
	mxs_phy->phy.shutdown		= mxs_phy_shutdown;
	mxs_phy->phy.set_suspend	= mxs_phy_suspend;
	mxs_phy->phy.notify_connect	= mxs_phy_on_connect;
	mxs_phy->phy.notify_disconnect	= mxs_phy_on_disconnect;
	mxs_phy->phy.type		= USB_PHY_TYPE_USB2;

	mxs_phy->clk = clk;
	mxs_phy->data = of_id->data;

	platform_set_drvdata(pdev, mxs_phy);

	ret = usb_add_phy_dev(&mxs_phy->phy);
	if (ret)
		return ret;

	return 0;
}

static int mxs_phy_remove(struct platform_device *pdev)
{
	struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);

	usb_remove_phy(&mxs_phy->phy);

	return 0;
}

static struct platform_driver mxs_phy_driver = {
	.probe = mxs_phy_probe,
	.remove = mxs_phy_remove,
	.driver = {
		.name = DRIVER_NAME,
		.owner	= THIS_MODULE,
		.of_match_table = mxs_phy_dt_ids,
	 },
};

static int __init mxs_phy_module_init(void)
{
	return platform_driver_register(&mxs_phy_driver);
}
postcore_initcall(mxs_phy_module_init);

static void __exit mxs_phy_module_exit(void)
{
	platform_driver_unregister(&mxs_phy_driver);
}
module_exit(mxs_phy_module_exit);

MODULE_ALIAS("platform:mxs-usb-phy");
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b3d99681	1	/*
2400780e	2	* Copyright 2012-2013 Freescale Semiconductor, Inc.
b3d99681 RZ	3	* Copyright (C) 2012 Marek Vasut <marex@denx.de>
	4	* on behalf of DENX Software Engineering GmbH
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/clk.h>
	18	#include <linux/usb/otg.h>
	19	#include <linux/stmp_device.h>
	20	#include <linux/delay.h>
	21	#include <linux/err.h>
	22	#include <linux/io.h>
2400780e	23	#include <linux/of_device.h>
0d896538 PC	24	#include <linux/regmap.h>
0d896538 PC	25	#include <linux/mfd/syscon.h>
b3d99681 RZ	26
	27	#define DRIVER_NAME "mxs_phy"
	28
	29	#define HW_USBPHY_PWD 0x00
	30	#define HW_USBPHY_CTRL 0x30
	31	#define HW_USBPHY_CTRL_SET 0x34
	32	#define HW_USBPHY_CTRL_CLR 0x38
	33
	34	#define BM_USBPHY_CTRL_SFTRST BIT(31)
	35	#define BM_USBPHY_CTRL_CLKGATE BIT(30)
13644144 PC	36	#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
	37	#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
	38	#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
	39	#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
	40	#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
b3d99681 RZ	41	#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
	42	#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
	43	#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
	44
2400780e PC	45	#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
	46
	47	/* Do disconnection between PHY and controller without vbus */
	48	#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
	49
	50	/*
	51	* The PHY will be in messy if there is a wakeup after putting
	52	* bus to suspend (set portsc.suspendM) but before setting PHY to low
	53	* power mode (set portsc.phcd).
	54	*/
	55	#define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
	56
	57	/*
	58	* The SOF sends too fast after resuming, it will cause disconnection
	59	* between host and high speed device.
	60	*/
	61	#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
	62
	63	struct mxs_phy_data {
	64	unsigned int flags;
	65	};
	66
	67	static const struct mxs_phy_data imx23_phy_data = {
	68	.flags = MXS_PHY_ABNORMAL_IN_SUSPEND \| MXS_PHY_SENDING_SOF_TOO_FAST,
	69	};
	70
	71	static const struct mxs_phy_data imx6q_phy_data = {
	72	.flags = MXS_PHY_SENDING_SOF_TOO_FAST \|
	73	MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
	74	};
	75
	76	static const struct mxs_phy_data imx6sl_phy_data = {
	77	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
	78	};
	79
	80	static const struct of_device_id mxs_phy_dt_ids[] = {
	81	{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
	82	{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
	83	{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
	84	{ /* sentinel */ }
	85	};
	86	MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
	87
b3d99681 RZ	88	struct mxs_phy {
	89	struct usb_phy phy;
	90	struct clk *clk;
2400780e	91	const struct mxs_phy_data *data;
0d896538	92	struct regmap *regmap_anatop;
b3d99681 RZ	93	};
b3d99681 RZ	94
51e563e3	95	static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
b3d99681	96	{
51e563e3	97	int ret;
b3d99681 RZ	98	void __iomem *base = mxs_phy->phy.io_priv;
b3d99681 RZ	99
51e563e3 FE	100	ret = stmp_reset_block(base + HW_USBPHY_CTRL);
	101	if (ret)
	102	return ret;
b3d99681 RZ	103
b3d99681 RZ	104	/* Power up the PHY */
b5a726b3	105	writel(0, base + HW_USBPHY_PWD);
b3d99681	106
13644144 PC	107	/*
	108	* USB PHY Ctrl Setting
	109	* - Auto clock/power on
	110	* - Enable full/low speed support
	111	*/
	112	writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS \|
	113	BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE \|
	114	BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD \|
	115	BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE \|
	116	BM_USBPHY_CTRL_ENAUTO_PWRON_PLL \|
	117	BM_USBPHY_CTRL_ENUTMILEVEL2 \|
	118	BM_USBPHY_CTRL_ENUTMILEVEL3,
b5a726b3	119	base + HW_USBPHY_CTRL_SET);
51e563e3 FE	120
51e563e3 FE	121	return 0;
b3d99681 RZ	122	}
	123
	124	static int mxs_phy_init(struct usb_phy *phy)
	125	{
67c21fc8	126	int ret;
b3d99681 RZ	127	struct mxs_phy *mxs_phy = to_mxs_phy(phy);
b3d99681 RZ	128
67c21fc8 FE	129	ret = clk_prepare_enable(mxs_phy->clk);
	130	if (ret)
	131	return ret;
	132
51e563e3	133	return mxs_phy_hw_init(mxs_phy);
b3d99681 RZ	134	}
	135
	136	static void mxs_phy_shutdown(struct usb_phy *phy)
	137	{
	138	struct mxs_phy *mxs_phy = to_mxs_phy(phy);
	139
b5a726b3 MKB	140	writel(BM_USBPHY_CTRL_CLKGATE,
b5a726b3 MKB	141	phy->io_priv + HW_USBPHY_CTRL_SET);
b3d99681 RZ	142
	143	clk_disable_unprepare(mxs_phy->clk);
	144	}
	145
04a6221c PC	146	static int mxs_phy_suspend(struct usb_phy *x, int suspend)
04a6221c PC	147	{
67c21fc8	148	int ret;
04a6221c PC	149	struct mxs_phy *mxs_phy = to_mxs_phy(x);
	150
	151	if (suspend) {
b5a726b3 MKB	152	writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
	153	writel(BM_USBPHY_CTRL_CLKGATE,
	154	x->io_priv + HW_USBPHY_CTRL_SET);
04a6221c PC	155	clk_disable_unprepare(mxs_phy->clk);
04a6221c PC	156	} else {
67c21fc8 FE	157	ret = clk_prepare_enable(mxs_phy->clk);
	158	if (ret)
	159	return ret;
b5a726b3 MKB	160	writel(BM_USBPHY_CTRL_CLKGATE,
	161	x->io_priv + HW_USBPHY_CTRL_CLR);
	162	writel(0, x->io_priv + HW_USBPHY_PWD);
04a6221c PC	163	}
	164
	165	return 0;
	166	}
	167
ac96511b PC	168	static int mxs_phy_on_connect(struct usb_phy *phy,
ac96511b PC	169	enum usb_device_speed speed)
b3d99681	170	{
f6a15824 PC	171	dev_dbg(phy->dev, "%s device has connected\n",
f6a15824 PC	172	(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
b3d99681	173
ac96511b	174	if (speed == USB_SPEED_HIGH)
b5a726b3 MKB	175	writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
b5a726b3 MKB	176	phy->io_priv + HW_USBPHY_CTRL_SET);
b3d99681 RZ	177
	178	return 0;
	179	}
	180
ac96511b PC	181	static int mxs_phy_on_disconnect(struct usb_phy *phy,
ac96511b PC	182	enum usb_device_speed speed)
b3d99681	183	{
f6a15824 PC	184	dev_dbg(phy->dev, "%s device has disconnected\n",
f6a15824 PC	185	(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
b3d99681	186
ac96511b	187	if (speed == USB_SPEED_HIGH)
b5a726b3 MKB	188	writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
b5a726b3 MKB	189	phy->io_priv + HW_USBPHY_CTRL_CLR);
b3d99681 RZ	190
	191	return 0;
	192	}
	193
	194	static int mxs_phy_probe(struct platform_device *pdev)
	195	{
	196	struct resource *res;
	197	void __iomem *base;
	198	struct clk *clk;
	199	struct mxs_phy *mxs_phy;
25df6397	200	int ret;
2400780e PC	201	const struct of_device_id *of_id =
2400780e PC	202	of_match_device(mxs_phy_dt_ids, &pdev->dev);
0d896538	203	struct device_node *np = pdev->dev.of_node;
b3d99681 RZ	204
b3d99681 RZ	205	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
148e1134 TR	206	base = devm_ioremap_resource(&pdev->dev, res);
	207	if (IS_ERR(base))
	208	return PTR_ERR(base);
b3d99681 RZ	209
	210	clk = devm_clk_get(&pdev->dev, NULL);
	211	if (IS_ERR(clk)) {
	212	dev_err(&pdev->dev,
	213	"can't get the clock, err=%ld", PTR_ERR(clk));
	214	return PTR_ERR(clk);
	215	}
	216
	217	mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
	218	if (!mxs_phy) {
	219	dev_err(&pdev->dev, "Failed to allocate USB PHY structure!\n");
	220	return -ENOMEM;
	221	}
	222
0d896538 PC	223	/* Some SoCs don't have anatop registers */
	224	if (of_get_property(np, "fsl,anatop", NULL)) {
	225	mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
	226	(np, "fsl,anatop");
	227	if (IS_ERR(mxs_phy->regmap_anatop)) {
	228	dev_dbg(&pdev->dev,
	229	"failed to find regmap for anatop\n");
	230	return PTR_ERR(mxs_phy->regmap_anatop);
	231	}
	232	}
	233
b3d99681 RZ	234	mxs_phy->phy.io_priv = base;
	235	mxs_phy->phy.dev = &pdev->dev;
	236	mxs_phy->phy.label = DRIVER_NAME;
	237	mxs_phy->phy.init = mxs_phy_init;
	238	mxs_phy->phy.shutdown = mxs_phy_shutdown;
04a6221c	239	mxs_phy->phy.set_suspend = mxs_phy_suspend;
b3d99681 RZ	240	mxs_phy->phy.notify_connect = mxs_phy_on_connect;
b3d99681 RZ	241	mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
4e0aa635	242	mxs_phy->phy.type = USB_PHY_TYPE_USB2;
b3d99681	243
b3d99681	244	mxs_phy->clk = clk;
2400780e	245	mxs_phy->data = of_id->data;
b3d99681	246
97a27f73	247	platform_set_drvdata(pdev, mxs_phy);
b3d99681	248
25df6397 SH	249	ret = usb_add_phy_dev(&mxs_phy->phy);
	250	if (ret)
	251	return ret;
	252
b3d99681 RZ	253	return 0;
	254	}
	255
fb4e98ab	256	static int mxs_phy_remove(struct platform_device *pdev)
b3d99681	257	{
25df6397 SH	258	struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
	259
	260	usb_remove_phy(&mxs_phy->phy);
	261
b3d99681 RZ	262	return 0;
	263	}
	264
b3d99681 RZ	265	static struct platform_driver mxs_phy_driver = {
b3d99681 RZ	266	.probe = mxs_phy_probe,
7690417d	267	.remove = mxs_phy_remove,
b3d99681 RZ	268	.driver = {
	269	.name = DRIVER_NAME,
	270	.owner = THIS_MODULE,
	271	.of_match_table = mxs_phy_dt_ids,
	272	},
	273	};
	274
	275	static int __init mxs_phy_module_init(void)
	276	{
	277	return platform_driver_register(&mxs_phy_driver);
	278	}
	279	postcore_initcall(mxs_phy_module_init);
	280
	281	static void __exit mxs_phy_module_exit(void)
	282	{
	283	platform_driver_unregister(&mxs_phy_driver);
	284	}
	285	module_exit(mxs_phy_module_exit);
	286
	287	MODULE_ALIAS("platform:mxs-usb-phy");
	288	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	289	MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
	290	MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
	291	MODULE_LICENSE("GPL");