Commit | Line | Data |
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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0+ |
b3d99681 | 2 | /* |
43f3634f | 3 | * Copyright 2012-2014 Freescale Semiconductor, Inc. |
b3d99681 RZ |
4 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> |
5 | * on behalf of DENX Software Engineering GmbH | |
b3d99681 RZ |
6 | */ |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/clk.h> | |
12 | #include <linux/usb/otg.h> | |
13 | #include <linux/stmp_device.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/io.h> | |
2400780e | 17 | #include <linux/of_device.h> |
0d896538 PC |
18 | #include <linux/regmap.h> |
19 | #include <linux/mfd/syscon.h> | |
b3d99681 RZ |
20 | |
21 | #define DRIVER_NAME "mxs_phy" | |
22 | ||
23 | #define HW_USBPHY_PWD 0x00 | |
da605f5f | 24 | #define HW_USBPHY_TX 0x10 |
b3d99681 RZ |
25 | #define HW_USBPHY_CTRL 0x30 |
26 | #define HW_USBPHY_CTRL_SET 0x34 | |
27 | #define HW_USBPHY_CTRL_CLR 0x38 | |
28 | ||
3f126505 PC |
29 | #define HW_USBPHY_DEBUG_SET 0x54 |
30 | #define HW_USBPHY_DEBUG_CLR 0x58 | |
31 | ||
22db05ec PC |
32 | #define HW_USBPHY_IP 0x90 |
33 | #define HW_USBPHY_IP_SET 0x94 | |
34 | #define HW_USBPHY_IP_CLR 0x98 | |
35 | ||
da605f5f JC |
36 | #define GM_USBPHY_TX_TXCAL45DP(x) (((x) & 0xf) << 16) |
37 | #define GM_USBPHY_TX_TXCAL45DN(x) (((x) & 0xf) << 8) | |
38 | #define GM_USBPHY_TX_D_CAL(x) (((x) & 0xf) << 0) | |
39 | ||
b3d99681 RZ |
40 | #define BM_USBPHY_CTRL_SFTRST BIT(31) |
41 | #define BM_USBPHY_CTRL_CLKGATE BIT(30) | |
7b09e676 | 42 | #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27) |
13644144 PC |
43 | #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26) |
44 | #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25) | |
3f126505 PC |
45 | #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23) |
46 | #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22) | |
47 | #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21) | |
13644144 PC |
48 | #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20) |
49 | #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19) | |
50 | #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18) | |
b3d99681 RZ |
51 | #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15) |
52 | #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14) | |
53 | #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1) | |
54 | ||
22db05ec PC |
55 | #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18)) |
56 | ||
3f126505 PC |
57 | #define BM_USBPHY_DEBUG_CLKGATE BIT(30) |
58 | ||
59 | /* Anatop Registers */ | |
bf783438 PC |
60 | #define ANADIG_ANA_MISC0 0x150 |
61 | #define ANADIG_ANA_MISC0_SET 0x154 | |
62 | #define ANADIG_ANA_MISC0_CLR 0x158 | |
63 | ||
e9365099 LJ |
64 | #define ANADIG_USB1_CHRG_DETECT_SET 0x1b4 |
65 | #define ANADIG_USB1_CHRG_DETECT_CLR 0x1b8 | |
66 | #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20) | |
67 | #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19) | |
68 | #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18) | |
69 | ||
3f126505 | 70 | #define ANADIG_USB1_VBUS_DET_STAT 0x1c0 |
e9365099 LJ |
71 | #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) |
72 | ||
73 | #define ANADIG_USB1_CHRG_DET_STAT 0x1d0 | |
74 | #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2) | |
75 | #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1) | |
76 | #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0) | |
77 | ||
3f126505 PC |
78 | #define ANADIG_USB2_VBUS_DET_STAT 0x220 |
79 | ||
80 | #define ANADIG_USB1_LOOPBACK_SET 0x1e4 | |
81 | #define ANADIG_USB1_LOOPBACK_CLR 0x1e8 | |
e9365099 LJ |
82 | #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0) |
83 | ||
3f126505 PC |
84 | #define ANADIG_USB2_LOOPBACK_SET 0x244 |
85 | #define ANADIG_USB2_LOOPBACK_CLR 0x248 | |
86 | ||
efdbd3a5 PC |
87 | #define ANADIG_USB1_MISC 0x1f0 |
88 | #define ANADIG_USB2_MISC 0x250 | |
89 | ||
bf783438 PC |
90 | #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12) |
91 | #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11) | |
92 | ||
3f126505 PC |
93 | #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3) |
94 | #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3) | |
95 | ||
96 | #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2) | |
97 | #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5) | |
98 | #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2) | |
99 | #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5) | |
100 | ||
efdbd3a5 PC |
101 | #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29) |
102 | #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28) | |
103 | #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29) | |
104 | #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28) | |
105 | ||
2400780e PC |
106 | #define to_mxs_phy(p) container_of((p), struct mxs_phy, phy) |
107 | ||
108 | /* Do disconnection between PHY and controller without vbus */ | |
109 | #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0) | |
110 | ||
111 | /* | |
112 | * The PHY will be in messy if there is a wakeup after putting | |
113 | * bus to suspend (set portsc.suspendM) but before setting PHY to low | |
114 | * power mode (set portsc.phcd). | |
115 | */ | |
116 | #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1) | |
117 | ||
118 | /* | |
119 | * The SOF sends too fast after resuming, it will cause disconnection | |
120 | * between host and high speed device. | |
121 | */ | |
122 | #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2) | |
123 | ||
22db05ec PC |
124 | /* |
125 | * IC has bug fixes logic, they include | |
126 | * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST | |
127 | * which are described at above flags, the RTL will handle it | |
128 | * according to different versions. | |
129 | */ | |
130 | #define MXS_PHY_NEED_IP_FIX BIT(3) | |
131 | ||
da605f5f JC |
132 | /* Minimum and maximum values for device tree entries */ |
133 | #define MXS_PHY_TX_CAL45_MIN 30 | |
134 | #define MXS_PHY_TX_CAL45_MAX 55 | |
135 | #define MXS_PHY_TX_D_CAL_MIN 79 | |
136 | #define MXS_PHY_TX_D_CAL_MAX 119 | |
137 | ||
2400780e PC |
138 | struct mxs_phy_data { |
139 | unsigned int flags; | |
140 | }; | |
141 | ||
142 | static const struct mxs_phy_data imx23_phy_data = { | |
143 | .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST, | |
144 | }; | |
145 | ||
146 | static const struct mxs_phy_data imx6q_phy_data = { | |
147 | .flags = MXS_PHY_SENDING_SOF_TOO_FAST | | |
22db05ec PC |
148 | MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | |
149 | MXS_PHY_NEED_IP_FIX, | |
2400780e PC |
150 | }; |
151 | ||
152 | static const struct mxs_phy_data imx6sl_phy_data = { | |
22db05ec PC |
153 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | |
154 | MXS_PHY_NEED_IP_FIX, | |
2400780e PC |
155 | }; |
156 | ||
d0ee68b5 SA |
157 | static const struct mxs_phy_data vf610_phy_data = { |
158 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS | | |
159 | MXS_PHY_NEED_IP_FIX, | |
160 | }; | |
161 | ||
43f3634f | 162 | static const struct mxs_phy_data imx6sx_phy_data = { |
dd811ba7 | 163 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, |
43f3634f PC |
164 | }; |
165 | ||
5c256b68 PC |
166 | static const struct mxs_phy_data imx6ul_phy_data = { |
167 | .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS, | |
168 | }; | |
169 | ||
2400780e | 170 | static const struct of_device_id mxs_phy_dt_ids[] = { |
43f3634f | 171 | { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, |
2400780e PC |
172 | { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, |
173 | { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, | |
174 | { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, }, | |
d0ee68b5 | 175 | { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, }, |
5c256b68 | 176 | { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, }, |
2400780e PC |
177 | { /* sentinel */ } |
178 | }; | |
179 | MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids); | |
180 | ||
b3d99681 RZ |
181 | struct mxs_phy { |
182 | struct usb_phy phy; | |
183 | struct clk *clk; | |
2400780e | 184 | const struct mxs_phy_data *data; |
0d896538 | 185 | struct regmap *regmap_anatop; |
83be181b | 186 | int port_id; |
da605f5f JC |
187 | u32 tx_reg_set; |
188 | u32 tx_reg_mask; | |
b3d99681 RZ |
189 | }; |
190 | ||
bf783438 PC |
191 | static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy) |
192 | { | |
193 | return mxs_phy->data == &imx6q_phy_data; | |
194 | } | |
195 | ||
196 | static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy) | |
197 | { | |
198 | return mxs_phy->data == &imx6sl_phy_data; | |
199 | } | |
200 | ||
47d1845f PC |
201 | /* |
202 | * PHY needs some 32K cycles to switch from 32K clock to | |
203 | * bus (such as AHB/AXI, etc) clock. | |
204 | */ | |
205 | static void mxs_phy_clock_switch_delay(void) | |
206 | { | |
207 | usleep_range(300, 400); | |
208 | } | |
209 | ||
da605f5f JC |
210 | static void mxs_phy_tx_init(struct mxs_phy *mxs_phy) |
211 | { | |
212 | void __iomem *base = mxs_phy->phy.io_priv; | |
213 | u32 phytx; | |
214 | ||
215 | /* Update TX register if there is anything to write */ | |
216 | if (mxs_phy->tx_reg_mask) { | |
217 | phytx = readl(base + HW_USBPHY_TX); | |
218 | phytx &= ~mxs_phy->tx_reg_mask; | |
219 | phytx |= mxs_phy->tx_reg_set; | |
220 | writel(phytx, base + HW_USBPHY_TX); | |
221 | } | |
222 | } | |
223 | ||
51e563e3 | 224 | static int mxs_phy_hw_init(struct mxs_phy *mxs_phy) |
b3d99681 | 225 | { |
51e563e3 | 226 | int ret; |
b3d99681 RZ |
227 | void __iomem *base = mxs_phy->phy.io_priv; |
228 | ||
51e563e3 FE |
229 | ret = stmp_reset_block(base + HW_USBPHY_CTRL); |
230 | if (ret) | |
231 | return ret; | |
b3d99681 RZ |
232 | |
233 | /* Power up the PHY */ | |
b5a726b3 | 234 | writel(0, base + HW_USBPHY_PWD); |
b3d99681 | 235 | |
13644144 PC |
236 | /* |
237 | * USB PHY Ctrl Setting | |
238 | * - Auto clock/power on | |
239 | * - Enable full/low speed support | |
240 | */ | |
241 | writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | | |
242 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | | |
243 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | | |
244 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | | |
245 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL | | |
246 | BM_USBPHY_CTRL_ENUTMILEVEL2 | | |
247 | BM_USBPHY_CTRL_ENUTMILEVEL3, | |
b5a726b3 | 248 | base + HW_USBPHY_CTRL_SET); |
51e563e3 | 249 | |
22db05ec PC |
250 | if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) |
251 | writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET); | |
252 | ||
da605f5f JC |
253 | mxs_phy_tx_init(mxs_phy); |
254 | ||
51e563e3 | 255 | return 0; |
b3d99681 RZ |
256 | } |
257 | ||
3f126505 PC |
258 | /* Return true if the vbus is there */ |
259 | static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy) | |
260 | { | |
63b121e3 | 261 | unsigned int vbus_value = 0; |
3f126505 | 262 | |
543aa486 SW |
263 | if (!mxs_phy->regmap_anatop) |
264 | return false; | |
265 | ||
3f126505 PC |
266 | if (mxs_phy->port_id == 0) |
267 | regmap_read(mxs_phy->regmap_anatop, | |
268 | ANADIG_USB1_VBUS_DET_STAT, | |
269 | &vbus_value); | |
270 | else if (mxs_phy->port_id == 1) | |
271 | regmap_read(mxs_phy->regmap_anatop, | |
272 | ANADIG_USB2_VBUS_DET_STAT, | |
273 | &vbus_value); | |
274 | ||
275 | if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID) | |
276 | return true; | |
277 | else | |
278 | return false; | |
279 | } | |
280 | ||
281 | static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) | |
282 | { | |
283 | void __iomem *base = mxs_phy->phy.io_priv; | |
284 | u32 reg; | |
285 | ||
286 | if (disconnect) | |
287 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
288 | base + HW_USBPHY_DEBUG_CLR); | |
289 | ||
290 | if (mxs_phy->port_id == 0) { | |
291 | reg = disconnect ? ANADIG_USB1_LOOPBACK_SET | |
292 | : ANADIG_USB1_LOOPBACK_CLR; | |
293 | regmap_write(mxs_phy->regmap_anatop, reg, | |
294 | BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 | | |
295 | BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN); | |
296 | } else if (mxs_phy->port_id == 1) { | |
297 | reg = disconnect ? ANADIG_USB2_LOOPBACK_SET | |
298 | : ANADIG_USB2_LOOPBACK_CLR; | |
299 | regmap_write(mxs_phy->regmap_anatop, reg, | |
300 | BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 | | |
301 | BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN); | |
302 | } | |
303 | ||
304 | if (!disconnect) | |
305 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
306 | base + HW_USBPHY_DEBUG_SET); | |
307 | ||
308 | /* Delay some time, and let Linestate be SE0 for controller */ | |
309 | if (disconnect) | |
310 | usleep_range(500, 1000); | |
311 | } | |
312 | ||
7b09e676 LJ |
313 | static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) |
314 | { | |
315 | void __iomem *base = mxs_phy->phy.io_priv; | |
316 | u32 phyctrl = readl(base + HW_USBPHY_CTRL); | |
317 | ||
318 | if (IS_ENABLED(CONFIG_USB_OTG) && | |
319 | !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE)) | |
320 | return true; | |
321 | ||
322 | return false; | |
323 | } | |
324 | ||
3f126505 PC |
325 | static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) |
326 | { | |
327 | bool vbus_is_on = false; | |
328 | ||
329 | /* If the SoCs don't need to disconnect line without vbus, quit */ | |
330 | if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) | |
331 | return; | |
332 | ||
333 | /* If the SoCs don't have anatop, quit */ | |
334 | if (!mxs_phy->regmap_anatop) | |
335 | return; | |
336 | ||
337 | vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); | |
338 | ||
7b09e676 | 339 | if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy)) |
3f126505 PC |
340 | __mxs_phy_disconnect_line(mxs_phy, true); |
341 | else | |
342 | __mxs_phy_disconnect_line(mxs_phy, false); | |
343 | ||
344 | } | |
345 | ||
b3d99681 RZ |
346 | static int mxs_phy_init(struct usb_phy *phy) |
347 | { | |
67c21fc8 | 348 | int ret; |
b3d99681 RZ |
349 | struct mxs_phy *mxs_phy = to_mxs_phy(phy); |
350 | ||
47d1845f | 351 | mxs_phy_clock_switch_delay(); |
67c21fc8 FE |
352 | ret = clk_prepare_enable(mxs_phy->clk); |
353 | if (ret) | |
354 | return ret; | |
355 | ||
51e563e3 | 356 | return mxs_phy_hw_init(mxs_phy); |
b3d99681 RZ |
357 | } |
358 | ||
359 | static void mxs_phy_shutdown(struct usb_phy *phy) | |
360 | { | |
361 | struct mxs_phy *mxs_phy = to_mxs_phy(phy); | |
fdf80e78 PC |
362 | u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | |
363 | BM_USBPHY_CTRL_ENDPDMCHG_WKUP | | |
364 | BM_USBPHY_CTRL_ENIDCHG_WKUP | | |
365 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS | | |
366 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE | | |
367 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD | | |
368 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE | | |
369 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL; | |
370 | ||
371 | writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); | |
372 | writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); | |
b3d99681 | 373 | |
b5a726b3 MKB |
374 | writel(BM_USBPHY_CTRL_CLKGATE, |
375 | phy->io_priv + HW_USBPHY_CTRL_SET); | |
b3d99681 RZ |
376 | |
377 | clk_disable_unprepare(mxs_phy->clk); | |
378 | } | |
379 | ||
efdbd3a5 PC |
380 | static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy) |
381 | { | |
382 | unsigned int line_state; | |
383 | /* bit definition is the same for all controllers */ | |
384 | unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS, | |
385 | dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS; | |
386 | unsigned int reg = ANADIG_USB1_MISC; | |
387 | ||
388 | /* If the SoCs don't have anatop, quit */ | |
389 | if (!mxs_phy->regmap_anatop) | |
390 | return false; | |
391 | ||
392 | if (mxs_phy->port_id == 0) | |
393 | reg = ANADIG_USB1_MISC; | |
394 | else if (mxs_phy->port_id == 1) | |
395 | reg = ANADIG_USB2_MISC; | |
396 | ||
397 | regmap_read(mxs_phy->regmap_anatop, reg, &line_state); | |
398 | ||
399 | if ((line_state & (dp_bit | dm_bit)) == dm_bit) | |
400 | return true; | |
401 | else | |
402 | return false; | |
403 | } | |
404 | ||
04a6221c PC |
405 | static int mxs_phy_suspend(struct usb_phy *x, int suspend) |
406 | { | |
67c21fc8 | 407 | int ret; |
04a6221c | 408 | struct mxs_phy *mxs_phy = to_mxs_phy(x); |
efdbd3a5 PC |
409 | bool low_speed_connection, vbus_is_on; |
410 | ||
411 | low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy); | |
412 | vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); | |
04a6221c PC |
413 | |
414 | if (suspend) { | |
efdbd3a5 PC |
415 | /* |
416 | * FIXME: Do not power down RXPWD1PT1 bit for low speed | |
417 | * connect. The low speed connection will have problem at | |
418 | * very rare cases during usb suspend and resume process. | |
419 | */ | |
e235f7b8 PC |
420 | if (low_speed_connection & vbus_is_on) { |
421 | /* | |
422 | * If value to be set as pwd value is not 0xffffffff, | |
423 | * several 32Khz cycles are needed. | |
424 | */ | |
425 | mxs_phy_clock_switch_delay(); | |
426 | writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); | |
427 | } else { | |
efdbd3a5 | 428 | writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); |
e235f7b8 | 429 | } |
b5a726b3 MKB |
430 | writel(BM_USBPHY_CTRL_CLKGATE, |
431 | x->io_priv + HW_USBPHY_CTRL_SET); | |
04a6221c PC |
432 | clk_disable_unprepare(mxs_phy->clk); |
433 | } else { | |
47d1845f | 434 | mxs_phy_clock_switch_delay(); |
67c21fc8 FE |
435 | ret = clk_prepare_enable(mxs_phy->clk); |
436 | if (ret) | |
437 | return ret; | |
b5a726b3 MKB |
438 | writel(BM_USBPHY_CTRL_CLKGATE, |
439 | x->io_priv + HW_USBPHY_CTRL_CLR); | |
440 | writel(0, x->io_priv + HW_USBPHY_PWD); | |
04a6221c PC |
441 | } |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
3f126505 PC |
446 | static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled) |
447 | { | |
448 | struct mxs_phy *mxs_phy = to_mxs_phy(x); | |
449 | u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP | | |
450 | BM_USBPHY_CTRL_ENDPDMCHG_WKUP | | |
451 | BM_USBPHY_CTRL_ENIDCHG_WKUP; | |
452 | if (enabled) { | |
453 | mxs_phy_disconnect_line(mxs_phy, true); | |
454 | writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); | |
455 | } else { | |
456 | writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); | |
457 | mxs_phy_disconnect_line(mxs_phy, false); | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
ac96511b PC |
463 | static int mxs_phy_on_connect(struct usb_phy *phy, |
464 | enum usb_device_speed speed) | |
b3d99681 | 465 | { |
f6a15824 PC |
466 | dev_dbg(phy->dev, "%s device has connected\n", |
467 | (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); | |
b3d99681 | 468 | |
ac96511b | 469 | if (speed == USB_SPEED_HIGH) |
b5a726b3 MKB |
470 | writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, |
471 | phy->io_priv + HW_USBPHY_CTRL_SET); | |
b3d99681 RZ |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
ac96511b PC |
476 | static int mxs_phy_on_disconnect(struct usb_phy *phy, |
477 | enum usb_device_speed speed) | |
b3d99681 | 478 | { |
f6a15824 PC |
479 | dev_dbg(phy->dev, "%s device has disconnected\n", |
480 | (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS"); | |
b3d99681 | 481 | |
f78c0957 PC |
482 | /* Sometimes, the speed is not high speed when the error occurs */ |
483 | if (readl(phy->io_priv + HW_USBPHY_CTRL) & | |
484 | BM_USBPHY_CTRL_ENHOSTDISCONDETECT) | |
b5a726b3 MKB |
485 | writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT, |
486 | phy->io_priv + HW_USBPHY_CTRL_CLR); | |
b3d99681 RZ |
487 | |
488 | return 0; | |
489 | } | |
490 | ||
e9365099 LJ |
491 | #define MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT 100 |
492 | static int mxs_charger_data_contact_detect(struct mxs_phy *x) | |
493 | { | |
494 | struct regmap *regmap = x->regmap_anatop; | |
495 | int i, stable_contact_count = 0; | |
496 | u32 val; | |
497 | ||
498 | /* Check if vbus is valid */ | |
499 | regmap_read(regmap, ANADIG_USB1_VBUS_DET_STAT, &val); | |
500 | if (!(val & ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) { | |
501 | dev_err(x->phy.dev, "vbus is not valid\n"); | |
502 | return -EINVAL; | |
503 | } | |
504 | ||
505 | /* Enable charger detector */ | |
506 | regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, | |
507 | ANADIG_USB1_CHRG_DETECT_EN_B); | |
508 | /* | |
509 | * - Do not check whether a charger is connected to the USB port | |
510 | * - Check whether the USB plug has been in contact with each other | |
511 | */ | |
512 | regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, | |
513 | ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | | |
514 | ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); | |
515 | ||
516 | /* Check if plug is connected */ | |
517 | for (i = 0; i < MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT; i++) { | |
518 | regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); | |
519 | if (val & ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) { | |
520 | stable_contact_count++; | |
521 | if (stable_contact_count > 5) | |
522 | /* Data pin makes contact */ | |
523 | break; | |
524 | else | |
525 | usleep_range(5000, 10000); | |
526 | } else { | |
527 | stable_contact_count = 0; | |
528 | usleep_range(5000, 6000); | |
529 | } | |
530 | } | |
531 | ||
532 | if (i == MXS_USB_CHARGER_DATA_CONTACT_TIMEOUT) { | |
533 | dev_err(x->phy.dev, | |
534 | "Data pin can't make good contact.\n"); | |
535 | /* Disable charger detector */ | |
536 | regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, | |
537 | ANADIG_USB1_CHRG_DETECT_EN_B | | |
538 | ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); | |
539 | return -ENXIO; | |
540 | } | |
541 | ||
542 | return 0; | |
543 | } | |
544 | ||
545 | static enum usb_charger_type mxs_charger_primary_detection(struct mxs_phy *x) | |
546 | { | |
547 | struct regmap *regmap = x->regmap_anatop; | |
548 | enum usb_charger_type chgr_type = UNKNOWN_TYPE; | |
549 | u32 val; | |
550 | ||
551 | /* | |
552 | * - Do check whether a charger is connected to the USB port | |
553 | * - Do not Check whether the USB plug has been in contact with | |
554 | * each other | |
555 | */ | |
556 | regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_CLR, | |
557 | ANADIG_USB1_CHRG_DETECT_CHK_CONTACT | | |
558 | ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); | |
559 | ||
560 | msleep(100); | |
561 | ||
562 | /* Check if it is a charger */ | |
563 | regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); | |
564 | if (!(val & ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) { | |
565 | chgr_type = SDP_TYPE; | |
566 | dev_dbg(x->phy.dev, "It is a stardard downstream port\n"); | |
567 | } | |
568 | ||
569 | /* Disable charger detector */ | |
570 | regmap_write(regmap, ANADIG_USB1_CHRG_DETECT_SET, | |
571 | ANADIG_USB1_CHRG_DETECT_EN_B | | |
572 | ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B); | |
573 | ||
574 | return chgr_type; | |
575 | } | |
576 | ||
577 | /* | |
578 | * It must be called after DP is pulled up, which is used to | |
579 | * differentiate DCP and CDP. | |
580 | */ | |
581 | enum usb_charger_type mxs_charger_secondary_detection(struct mxs_phy *x) | |
582 | { | |
583 | struct regmap *regmap = x->regmap_anatop; | |
584 | int val; | |
585 | ||
586 | msleep(80); | |
587 | ||
588 | regmap_read(regmap, ANADIG_USB1_CHRG_DET_STAT, &val); | |
589 | if (val & ANADIG_USB1_CHRG_DET_STAT_DM_STATE) { | |
590 | dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); | |
591 | return DCP_TYPE; | |
592 | } else { | |
593 | dev_dbg(x->phy.dev, "It is a charging downstream port\n"); | |
594 | return CDP_TYPE; | |
595 | } | |
596 | } | |
597 | ||
598 | static enum usb_charger_type mxs_phy_charger_detect(struct usb_phy *phy) | |
599 | { | |
600 | struct mxs_phy *mxs_phy = to_mxs_phy(phy); | |
601 | struct regmap *regmap = mxs_phy->regmap_anatop; | |
602 | void __iomem *base = phy->io_priv; | |
603 | enum usb_charger_type chgr_type = UNKNOWN_TYPE; | |
604 | ||
49935086 FE |
605 | if (!regmap) |
606 | return UNKNOWN_TYPE; | |
607 | ||
e9365099 LJ |
608 | if (mxs_charger_data_contact_detect(mxs_phy)) |
609 | return chgr_type; | |
610 | ||
611 | chgr_type = mxs_charger_primary_detection(mxs_phy); | |
612 | ||
613 | if (chgr_type != SDP_TYPE) { | |
614 | /* Pull up DP via test */ | |
615 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
616 | base + HW_USBPHY_DEBUG_CLR); | |
617 | regmap_write(regmap, ANADIG_USB1_LOOPBACK_SET, | |
618 | ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); | |
619 | ||
620 | chgr_type = mxs_charger_secondary_detection(mxs_phy); | |
621 | ||
622 | /* Stop the test */ | |
623 | regmap_write(regmap, ANADIG_USB1_LOOPBACK_CLR, | |
624 | ANADIG_USB1_LOOPBACK_UTMI_TESTSTART); | |
625 | writel_relaxed(BM_USBPHY_DEBUG_CLKGATE, | |
626 | base + HW_USBPHY_DEBUG_SET); | |
627 | } | |
628 | ||
629 | return chgr_type; | |
630 | } | |
631 | ||
b3d99681 RZ |
632 | static int mxs_phy_probe(struct platform_device *pdev) |
633 | { | |
634 | struct resource *res; | |
635 | void __iomem *base; | |
636 | struct clk *clk; | |
637 | struct mxs_phy *mxs_phy; | |
25df6397 | 638 | int ret; |
89d99aea | 639 | const struct of_device_id *of_id; |
0d896538 | 640 | struct device_node *np = pdev->dev.of_node; |
da605f5f | 641 | u32 val; |
b3d99681 | 642 | |
89d99aea LC |
643 | of_id = of_match_device(mxs_phy_dt_ids, &pdev->dev); |
644 | if (!of_id) | |
645 | return -ENODEV; | |
646 | ||
b3d99681 | 647 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
148e1134 TR |
648 | base = devm_ioremap_resource(&pdev->dev, res); |
649 | if (IS_ERR(base)) | |
650 | return PTR_ERR(base); | |
b3d99681 RZ |
651 | |
652 | clk = devm_clk_get(&pdev->dev, NULL); | |
653 | if (IS_ERR(clk)) { | |
654 | dev_err(&pdev->dev, | |
655 | "can't get the clock, err=%ld", PTR_ERR(clk)); | |
656 | return PTR_ERR(clk); | |
657 | } | |
658 | ||
659 | mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); | |
c62fe556 | 660 | if (!mxs_phy) |
b3d99681 | 661 | return -ENOMEM; |
b3d99681 | 662 | |
0d896538 PC |
663 | /* Some SoCs don't have anatop registers */ |
664 | if (of_get_property(np, "fsl,anatop", NULL)) { | |
665 | mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle | |
666 | (np, "fsl,anatop"); | |
667 | if (IS_ERR(mxs_phy->regmap_anatop)) { | |
668 | dev_dbg(&pdev->dev, | |
669 | "failed to find regmap for anatop\n"); | |
670 | return PTR_ERR(mxs_phy->regmap_anatop); | |
671 | } | |
672 | } | |
673 | ||
da605f5f JC |
674 | /* Precompute which bits of the TX register are to be updated, if any */ |
675 | if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && | |
676 | val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { | |
677 | /* Scale to a 4-bit value */ | |
678 | val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF | |
679 | / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); | |
680 | mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); | |
681 | mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); | |
682 | } | |
683 | ||
684 | if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && | |
685 | val >= MXS_PHY_TX_CAL45_MIN && val <= MXS_PHY_TX_CAL45_MAX) { | |
686 | /* Scale to a 4-bit value. */ | |
687 | val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF | |
688 | / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); | |
689 | mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); | |
690 | mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); | |
691 | } | |
692 | ||
693 | if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && | |
694 | val >= MXS_PHY_TX_D_CAL_MIN && val <= MXS_PHY_TX_D_CAL_MAX) { | |
695 | /* Scale to a 4-bit value. Round up the values and heavily | |
696 | * weight the rounding by adding 2/3 of the denominator. | |
697 | */ | |
698 | val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF | |
699 | + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) | |
700 | / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); | |
701 | mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); | |
702 | mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); | |
703 | } | |
704 | ||
83be181b PC |
705 | ret = of_alias_get_id(np, "usbphy"); |
706 | if (ret < 0) | |
707 | dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
708 | mxs_phy->port_id = ret; | |
709 | ||
b3d99681 RZ |
710 | mxs_phy->phy.io_priv = base; |
711 | mxs_phy->phy.dev = &pdev->dev; | |
712 | mxs_phy->phy.label = DRIVER_NAME; | |
713 | mxs_phy->phy.init = mxs_phy_init; | |
714 | mxs_phy->phy.shutdown = mxs_phy_shutdown; | |
04a6221c | 715 | mxs_phy->phy.set_suspend = mxs_phy_suspend; |
b3d99681 RZ |
716 | mxs_phy->phy.notify_connect = mxs_phy_on_connect; |
717 | mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; | |
4e0aa635 | 718 | mxs_phy->phy.type = USB_PHY_TYPE_USB2; |
3f126505 | 719 | mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; |
e9365099 | 720 | mxs_phy->phy.charger_detect = mxs_phy_charger_detect; |
b3d99681 | 721 | |
b3d99681 | 722 | mxs_phy->clk = clk; |
2400780e | 723 | mxs_phy->data = of_id->data; |
b3d99681 | 724 | |
97a27f73 | 725 | platform_set_drvdata(pdev, mxs_phy); |
b3d99681 | 726 | |
bf783438 PC |
727 | device_set_wakeup_capable(&pdev->dev, true); |
728 | ||
082155ea | 729 | return usb_add_phy_dev(&mxs_phy->phy); |
b3d99681 RZ |
730 | } |
731 | ||
fb4e98ab | 732 | static int mxs_phy_remove(struct platform_device *pdev) |
b3d99681 | 733 | { |
25df6397 SH |
734 | struct mxs_phy *mxs_phy = platform_get_drvdata(pdev); |
735 | ||
736 | usb_remove_phy(&mxs_phy->phy); | |
737 | ||
b3d99681 RZ |
738 | return 0; |
739 | } | |
740 | ||
bf783438 PC |
741 | #ifdef CONFIG_PM_SLEEP |
742 | static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on) | |
743 | { | |
744 | unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR; | |
745 | ||
746 | /* If the SoCs don't have anatop, quit */ | |
747 | if (!mxs_phy->regmap_anatop) | |
748 | return; | |
749 | ||
750 | if (is_imx6q_phy(mxs_phy)) | |
751 | regmap_write(mxs_phy->regmap_anatop, reg, | |
752 | BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG); | |
753 | else if (is_imx6sl_phy(mxs_phy)) | |
754 | regmap_write(mxs_phy->regmap_anatop, | |
755 | reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL); | |
756 | } | |
757 | ||
758 | static int mxs_phy_system_suspend(struct device *dev) | |
759 | { | |
760 | struct mxs_phy *mxs_phy = dev_get_drvdata(dev); | |
761 | ||
762 | if (device_may_wakeup(dev)) | |
763 | mxs_phy_enable_ldo_in_suspend(mxs_phy, true); | |
764 | ||
765 | return 0; | |
766 | } | |
767 | ||
768 | static int mxs_phy_system_resume(struct device *dev) | |
769 | { | |
770 | struct mxs_phy *mxs_phy = dev_get_drvdata(dev); | |
771 | ||
772 | if (device_may_wakeup(dev)) | |
773 | mxs_phy_enable_ldo_in_suspend(mxs_phy, false); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | #endif /* CONFIG_PM_SLEEP */ | |
778 | ||
779 | static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend, | |
780 | mxs_phy_system_resume); | |
781 | ||
b3d99681 RZ |
782 | static struct platform_driver mxs_phy_driver = { |
783 | .probe = mxs_phy_probe, | |
7690417d | 784 | .remove = mxs_phy_remove, |
b3d99681 RZ |
785 | .driver = { |
786 | .name = DRIVER_NAME, | |
b3d99681 | 787 | .of_match_table = mxs_phy_dt_ids, |
bf783438 | 788 | .pm = &mxs_phy_pm, |
b3d99681 RZ |
789 | }, |
790 | }; | |
791 | ||
792 | static int __init mxs_phy_module_init(void) | |
793 | { | |
794 | return platform_driver_register(&mxs_phy_driver); | |
795 | } | |
796 | postcore_initcall(mxs_phy_module_init); | |
797 | ||
798 | static void __exit mxs_phy_module_exit(void) | |
799 | { | |
800 | platform_driver_unregister(&mxs_phy_driver); | |
801 | } | |
802 | module_exit(mxs_phy_module_exit); | |
803 | ||
804 | MODULE_ALIAS("platform:mxs-usb-phy"); | |
805 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
806 | MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>"); | |
807 | MODULE_DESCRIPTION("Freescale MXS USB PHY driver"); | |
808 | MODULE_LICENSE("GPL"); |