[linux-block.git] / drivers / usb / phy / phy-mxs-usb.c

/*
 * Copyright 2012-2014 Freescale Semiconductor, Inc.
 * Copyright (C) 2012 Marek Vasut <marex@denx.de>
 * on behalf of DENX Software Engineering GmbH
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/usb/otg.h>
#include <linux/stmp_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#define DRIVER_NAME "mxs_phy"

#define HW_USBPHY_PWD				0x00
#define HW_USBPHY_CTRL				0x30
#define HW_USBPHY_CTRL_SET			0x34
#define HW_USBPHY_CTRL_CLR			0x38

#define HW_USBPHY_DEBUG_SET			0x54
#define HW_USBPHY_DEBUG_CLR			0x58

#define HW_USBPHY_IP				0x90
#define HW_USBPHY_IP_SET			0x94
#define HW_USBPHY_IP_CLR			0x98

#define BM_USBPHY_CTRL_SFTRST			BIT(31)
#define BM_USBPHY_CTRL_CLKGATE			BIT(30)
#define BM_USBPHY_CTRL_OTG_ID_VALUE		BIT(27)
#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS	BIT(26)
#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE	BIT(25)
#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP		BIT(23)
#define BM_USBPHY_CTRL_ENIDCHG_WKUP		BIT(22)
#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP		BIT(21)
#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD	BIT(20)
#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE	BIT(19)
#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL		BIT(18)
#define BM_USBPHY_CTRL_ENUTMILEVEL3		BIT(15)
#define BM_USBPHY_CTRL_ENUTMILEVEL2		BIT(14)
#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT	BIT(1)

#define BM_USBPHY_IP_FIX                       (BIT(17) | BIT(18))

#define BM_USBPHY_DEBUG_CLKGATE			BIT(30)

/* Anatop Registers */
#define ANADIG_ANA_MISC0			0x150
#define ANADIG_ANA_MISC0_SET			0x154
#define ANADIG_ANA_MISC0_CLR			0x158

#define ANADIG_USB1_VBUS_DET_STAT		0x1c0
#define ANADIG_USB2_VBUS_DET_STAT		0x220

#define ANADIG_USB1_LOOPBACK_SET		0x1e4
#define ANADIG_USB1_LOOPBACK_CLR		0x1e8
#define ANADIG_USB2_LOOPBACK_SET		0x244
#define ANADIG_USB2_LOOPBACK_CLR		0x248

#define ANADIG_USB1_MISC			0x1f0
#define ANADIG_USB2_MISC			0x250

#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG	BIT(12)
#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)

#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID	BIT(3)
#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID	BIT(3)

#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1	BIT(2)
#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN	BIT(5)
#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1	BIT(2)
#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN	BIT(5)

#define BM_ANADIG_USB1_MISC_RX_VPIN_FS		BIT(29)
#define BM_ANADIG_USB1_MISC_RX_VMIN_FS		BIT(28)
#define BM_ANADIG_USB2_MISC_RX_VPIN_FS		BIT(29)
#define BM_ANADIG_USB2_MISC_RX_VMIN_FS		BIT(28)

#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)

/* Do disconnection between PHY and controller without vbus */
#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS	BIT(0)

/*
 * The PHY will be in messy if there is a wakeup after putting
 * bus to suspend (set portsc.suspendM) but before setting PHY to low
 * power mode (set portsc.phcd).
 */
#define MXS_PHY_ABNORMAL_IN_SUSPEND		BIT(1)

/*
 * The SOF sends too fast after resuming, it will cause disconnection
 * between host and high speed device.
 */
#define MXS_PHY_SENDING_SOF_TOO_FAST		BIT(2)

/*
 * IC has bug fixes logic, they include
 * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
 * which are described at above flags, the RTL will handle it
 * according to different versions.
 */
#define MXS_PHY_NEED_IP_FIX			BIT(3)

struct mxs_phy_data {
	unsigned int flags;
};

static const struct mxs_phy_data imx23_phy_data = {
	.flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
};

static const struct mxs_phy_data imx6q_phy_data = {
	.flags = MXS_PHY_SENDING_SOF_TOO_FAST |
		MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
		MXS_PHY_NEED_IP_FIX,
};

static const struct mxs_phy_data imx6sl_phy_data = {
	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
		MXS_PHY_NEED_IP_FIX,
};

static const struct mxs_phy_data vf610_phy_data = {
	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
		MXS_PHY_NEED_IP_FIX,
};

static const struct mxs_phy_data imx6sx_phy_data = {
	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
};

static const struct of_device_id mxs_phy_dt_ids[] = {
	{ .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
	{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
	{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
	{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
	{ .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);

struct mxs_phy {
	struct usb_phy phy;
	struct clk *clk;
	const struct mxs_phy_data *data;
	struct regmap *regmap_anatop;
	int port_id;
};

static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
{
	return mxs_phy->data == &imx6q_phy_data;
}

static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
{
	return mxs_phy->data == &imx6sl_phy_data;
}

/*
 * PHY needs some 32K cycles to switch from 32K clock to
 * bus (such as AHB/AXI, etc) clock.
 */
static void mxs_phy_clock_switch_delay(void)
{
	usleep_range(300, 400);
}

static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
{
	int ret;
	void __iomem *base = mxs_phy->phy.io_priv;

	ret = stmp_reset_block(base + HW_USBPHY_CTRL);
	if (ret)
		return ret;

	/* Power up the PHY */
	writel(0, base + HW_USBPHY_PWD);

	/*
	 * USB PHY Ctrl Setting
	 * - Auto clock/power on
	 * - Enable full/low speed support
	 */
	writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
		BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
		BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
		BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
		BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
		BM_USBPHY_CTRL_ENUTMILEVEL2 |
		BM_USBPHY_CTRL_ENUTMILEVEL3,
	       base + HW_USBPHY_CTRL_SET);

	if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
		writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);

	return 0;
}

/* Return true if the vbus is there */
static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
{
	unsigned int vbus_value;

	if (mxs_phy->port_id == 0)
		regmap_read(mxs_phy->regmap_anatop,
			ANADIG_USB1_VBUS_DET_STAT,
			&vbus_value);
	else if (mxs_phy->port_id == 1)
		regmap_read(mxs_phy->regmap_anatop,
			ANADIG_USB2_VBUS_DET_STAT,
			&vbus_value);

	if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
		return true;
	else
		return false;
}

static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
{
	void __iomem *base = mxs_phy->phy.io_priv;
	u32 reg;

	if (disconnect)
		writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
			base + HW_USBPHY_DEBUG_CLR);

	if (mxs_phy->port_id == 0) {
		reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
			: ANADIG_USB1_LOOPBACK_CLR;
		regmap_write(mxs_phy->regmap_anatop, reg,
			BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
			BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
	} else if (mxs_phy->port_id == 1) {
		reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
			: ANADIG_USB2_LOOPBACK_CLR;
		regmap_write(mxs_phy->regmap_anatop, reg,
			BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
			BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
	}

	if (!disconnect)
		writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
			base + HW_USBPHY_DEBUG_SET);

	/* Delay some time, and let Linestate be SE0 for controller */
	if (disconnect)
		usleep_range(500, 1000);
}

static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
{
	void __iomem *base = mxs_phy->phy.io_priv;
	u32 phyctrl = readl(base + HW_USBPHY_CTRL);

	if (IS_ENABLED(CONFIG_USB_OTG) &&
			!(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE))
		return true;

	return false;
}

static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
{
	bool vbus_is_on = false;

	/* If the SoCs don't need to disconnect line without vbus, quit */
	if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
		return;

	/* If the SoCs don't have anatop, quit */
	if (!mxs_phy->regmap_anatop)
		return;

	vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);

	if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
		__mxs_phy_disconnect_line(mxs_phy, true);
	else
		__mxs_phy_disconnect_line(mxs_phy, false);

}

static int mxs_phy_init(struct usb_phy *phy)
{
	int ret;
	struct mxs_phy *mxs_phy = to_mxs_phy(phy);

	mxs_phy_clock_switch_delay();
	ret = clk_prepare_enable(mxs_phy->clk);
	if (ret)
		return ret;

	return mxs_phy_hw_init(mxs_phy);
}

static void mxs_phy_shutdown(struct usb_phy *phy)
{
	struct mxs_phy *mxs_phy = to_mxs_phy(phy);
	u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
			BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
			BM_USBPHY_CTRL_ENIDCHG_WKUP |
			BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
			BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
			BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
			BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
			BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;

	writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
	writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);

	writel(BM_USBPHY_CTRL_CLKGATE,
	       phy->io_priv + HW_USBPHY_CTRL_SET);

	clk_disable_unprepare(mxs_phy->clk);
}

static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
{
	unsigned int line_state;
	/* bit definition is the same for all controllers */
	unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
		     dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
	unsigned int reg = ANADIG_USB1_MISC;

	/* If the SoCs don't have anatop, quit */
	if (!mxs_phy->regmap_anatop)
		return false;

	if (mxs_phy->port_id == 0)
		reg = ANADIG_USB1_MISC;
	else if (mxs_phy->port_id == 1)
		reg = ANADIG_USB2_MISC;

	regmap_read(mxs_phy->regmap_anatop, reg, &line_state);

	if ((line_state & (dp_bit | dm_bit)) ==  dm_bit)
		return true;
	else
		return false;
}

static int mxs_phy_suspend(struct usb_phy *x, int suspend)
{
	int ret;
	struct mxs_phy *mxs_phy = to_mxs_phy(x);
	bool low_speed_connection, vbus_is_on;

	low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
	vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);

	if (suspend) {
		/*
		 * FIXME: Do not power down RXPWD1PT1 bit for low speed
		 * connect. The low speed connection will have problem at
		 * very rare cases during usb suspend and resume process.
		 */
		if (low_speed_connection & vbus_is_on) {
			/*
			 * If value to be set as pwd value is not 0xffffffff,
			 * several 32Khz cycles are needed.
			 */
			mxs_phy_clock_switch_delay();
			writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
		} else {
			writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
		}
		writel(BM_USBPHY_CTRL_CLKGATE,
		       x->io_priv + HW_USBPHY_CTRL_SET);
		clk_disable_unprepare(mxs_phy->clk);
	} else {
		mxs_phy_clock_switch_delay();
		ret = clk_prepare_enable(mxs_phy->clk);
		if (ret)
			return ret;
		writel(BM_USBPHY_CTRL_CLKGATE,
		       x->io_priv + HW_USBPHY_CTRL_CLR);
		writel(0, x->io_priv + HW_USBPHY_PWD);
	}

	return 0;
}

static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
{
	struct mxs_phy *mxs_phy = to_mxs_phy(x);
	u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
			BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
				BM_USBPHY_CTRL_ENIDCHG_WKUP;
	if (enabled) {
		mxs_phy_disconnect_line(mxs_phy, true);
		writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
	} else {
		writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
		mxs_phy_disconnect_line(mxs_phy, false);
	}

	return 0;
}

static int mxs_phy_on_connect(struct usb_phy *phy,
		enum usb_device_speed speed)
{
	dev_dbg(phy->dev, "%s device has connected\n",
		(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");

	if (speed == USB_SPEED_HIGH)
		writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
		       phy->io_priv + HW_USBPHY_CTRL_SET);

	return 0;
}

static int mxs_phy_on_disconnect(struct usb_phy *phy,
		enum usb_device_speed speed)
{
	dev_dbg(phy->dev, "%s device has disconnected\n",
		(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");

	/* Sometimes, the speed is not high speed when the error occurs */
	if (readl(phy->io_priv + HW_USBPHY_CTRL) &
			BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
		writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
		       phy->io_priv + HW_USBPHY_CTRL_CLR);

	return 0;
}

static int mxs_phy_probe(struct platform_device *pdev)
{
	struct resource *res;
	void __iomem *base;
	struct clk *clk;
	struct mxs_phy *mxs_phy;
	int ret;
	const struct of_device_id *of_id =
			of_match_device(mxs_phy_dt_ids, &pdev->dev);
	struct device_node *np = pdev->dev.of_node;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev,
			"can't get the clock, err=%ld", PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
	if (!mxs_phy)
		return -ENOMEM;

	/* Some SoCs don't have anatop registers */
	if (of_get_property(np, "fsl,anatop", NULL)) {
		mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
			(np, "fsl,anatop");
		if (IS_ERR(mxs_phy->regmap_anatop)) {
			dev_dbg(&pdev->dev,
				"failed to find regmap for anatop\n");
			return PTR_ERR(mxs_phy->regmap_anatop);
		}
	}

	ret = of_alias_get_id(np, "usbphy");
	if (ret < 0)
		dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
	mxs_phy->port_id = ret;

	mxs_phy->phy.io_priv		= base;
	mxs_phy->phy.dev		= &pdev->dev;
	mxs_phy->phy.label		= DRIVER_NAME;
	mxs_phy->phy.init		= mxs_phy_init;
	mxs_phy->phy.shutdown		= mxs_phy_shutdown;
	mxs_phy->phy.set_suspend	= mxs_phy_suspend;
	mxs_phy->phy.notify_connect	= mxs_phy_on_connect;
	mxs_phy->phy.notify_disconnect	= mxs_phy_on_disconnect;
	mxs_phy->phy.type		= USB_PHY_TYPE_USB2;
	mxs_phy->phy.set_wakeup		= mxs_phy_set_wakeup;

	mxs_phy->clk = clk;
	mxs_phy->data = of_id->data;

	platform_set_drvdata(pdev, mxs_phy);

	device_set_wakeup_capable(&pdev->dev, true);

	ret = usb_add_phy_dev(&mxs_phy->phy);
	if (ret)
		return ret;

	return 0;
}

static int mxs_phy_remove(struct platform_device *pdev)
{
	struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);

	usb_remove_phy(&mxs_phy->phy);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
{
	unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;

	/* If the SoCs don't have anatop, quit */
	if (!mxs_phy->regmap_anatop)
		return;

	if (is_imx6q_phy(mxs_phy))
		regmap_write(mxs_phy->regmap_anatop, reg,
			BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
	else if (is_imx6sl_phy(mxs_phy))
		regmap_write(mxs_phy->regmap_anatop,
			reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
}

static int mxs_phy_system_suspend(struct device *dev)
{
	struct mxs_phy *mxs_phy = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		mxs_phy_enable_ldo_in_suspend(mxs_phy, true);

	return 0;
}

static int mxs_phy_system_resume(struct device *dev)
{
	struct mxs_phy *mxs_phy = dev_get_drvdata(dev);

	if (device_may_wakeup(dev))
		mxs_phy_enable_ldo_in_suspend(mxs_phy, false);

	return 0;
}
#endif /* CONFIG_PM_SLEEP */

static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
		mxs_phy_system_resume);

static struct platform_driver mxs_phy_driver = {
	.probe = mxs_phy_probe,
	.remove = mxs_phy_remove,
	.driver = {
		.name = DRIVER_NAME,
		.of_match_table = mxs_phy_dt_ids,
		.pm = &mxs_phy_pm,
	 },
};

static int __init mxs_phy_module_init(void)
{
	return platform_driver_register(&mxs_phy_driver);
}
postcore_initcall(mxs_phy_module_init);

static void __exit mxs_phy_module_exit(void)
{
	platform_driver_unregister(&mxs_phy_driver);
}
module_exit(mxs_phy_module_exit);

MODULE_ALIAS("platform:mxs-usb-phy");
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
b3d99681	1	/*
43f3634f	2	* Copyright 2012-2014 Freescale Semiconductor, Inc.
b3d99681 RZ	3	* Copyright (C) 2012 Marek Vasut <marex@denx.de>
	4	* on behalf of DENX Software Engineering GmbH
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/kernel.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/clk.h>
	18	#include <linux/usb/otg.h>
	19	#include <linux/stmp_device.h>
	20	#include <linux/delay.h>
	21	#include <linux/err.h>
	22	#include <linux/io.h>
2400780e	23	#include <linux/of_device.h>
0d896538 PC	24	#include <linux/regmap.h>
0d896538 PC	25	#include <linux/mfd/syscon.h>
b3d99681 RZ	26
	27	#define DRIVER_NAME "mxs_phy"
	28
	29	#define HW_USBPHY_PWD 0x00
	30	#define HW_USBPHY_CTRL 0x30
	31	#define HW_USBPHY_CTRL_SET 0x34
	32	#define HW_USBPHY_CTRL_CLR 0x38
	33
3f126505 PC	34	#define HW_USBPHY_DEBUG_SET 0x54
	35	#define HW_USBPHY_DEBUG_CLR 0x58
	36
22db05ec PC	37	#define HW_USBPHY_IP 0x90
	38	#define HW_USBPHY_IP_SET 0x94
	39	#define HW_USBPHY_IP_CLR 0x98
	40
b3d99681 RZ	41	#define BM_USBPHY_CTRL_SFTRST BIT(31)
b3d99681 RZ	42	#define BM_USBPHY_CTRL_CLKGATE BIT(30)
7b09e676	43	#define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
13644144 PC	44	#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
13644144 PC	45	#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
3f126505 PC	46	#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
	47	#define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
	48	#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
13644144 PC	49	#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
	50	#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
	51	#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
b3d99681 RZ	52	#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
	53	#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
	54	#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
	55
22db05ec PC	56	#define BM_USBPHY_IP_FIX (BIT(17) \| BIT(18))
22db05ec PC	57
3f126505 PC	58	#define BM_USBPHY_DEBUG_CLKGATE BIT(30)
	59
	60	/* Anatop Registers */
bf783438 PC	61	#define ANADIG_ANA_MISC0 0x150
	62	#define ANADIG_ANA_MISC0_SET 0x154
	63	#define ANADIG_ANA_MISC0_CLR 0x158
	64
3f126505 PC	65	#define ANADIG_USB1_VBUS_DET_STAT 0x1c0
	66	#define ANADIG_USB2_VBUS_DET_STAT 0x220
	67
	68	#define ANADIG_USB1_LOOPBACK_SET 0x1e4
	69	#define ANADIG_USB1_LOOPBACK_CLR 0x1e8
	70	#define ANADIG_USB2_LOOPBACK_SET 0x244
	71	#define ANADIG_USB2_LOOPBACK_CLR 0x248
	72
efdbd3a5 PC	73	#define ANADIG_USB1_MISC 0x1f0
	74	#define ANADIG_USB2_MISC 0x250
	75
bf783438 PC	76	#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
	77	#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
	78
3f126505 PC	79	#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
	80	#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
	81
	82	#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
	83	#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
	84	#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
	85	#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
	86
efdbd3a5 PC	87	#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
	88	#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
	89	#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
	90	#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
	91
2400780e PC	92	#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
	93
	94	/* Do disconnection between PHY and controller without vbus */
	95	#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
	96
	97	/*
	98	* The PHY will be in messy if there is a wakeup after putting
	99	* bus to suspend (set portsc.suspendM) but before setting PHY to low
	100	* power mode (set portsc.phcd).
	101	*/
	102	#define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
	103
	104	/*
	105	* The SOF sends too fast after resuming, it will cause disconnection
	106	* between host and high speed device.
	107	*/
	108	#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
	109
22db05ec PC	110	/*
	111	* IC has bug fixes logic, they include
	112	* MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
	113	* which are described at above flags, the RTL will handle it
	114	* according to different versions.
	115	*/
	116	#define MXS_PHY_NEED_IP_FIX BIT(3)
	117
2400780e PC	118	struct mxs_phy_data {
	119	unsigned int flags;
	120	};
	121
	122	static const struct mxs_phy_data imx23_phy_data = {
	123	.flags = MXS_PHY_ABNORMAL_IN_SUSPEND \| MXS_PHY_SENDING_SOF_TOO_FAST,
	124	};
	125
	126	static const struct mxs_phy_data imx6q_phy_data = {
	127	.flags = MXS_PHY_SENDING_SOF_TOO_FAST \|
22db05ec PC	128	MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS \|
22db05ec PC	129	MXS_PHY_NEED_IP_FIX,
2400780e PC	130	};
	131
	132	static const struct mxs_phy_data imx6sl_phy_data = {
22db05ec PC	133	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS \|
22db05ec PC	134	MXS_PHY_NEED_IP_FIX,
2400780e PC	135	};
2400780e PC	136
d0ee68b5 SA	137	static const struct mxs_phy_data vf610_phy_data = {
	138	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS \|
	139	MXS_PHY_NEED_IP_FIX,
	140	};
	141
43f3634f	142	static const struct mxs_phy_data imx6sx_phy_data = {
dd811ba7	143	.flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
43f3634f PC	144	};
43f3634f PC	145
2400780e	146	static const struct of_device_id mxs_phy_dt_ids[] = {
43f3634f	147	{ .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
2400780e PC	148	{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
	149	{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
	150	{ .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
d0ee68b5	151	{ .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
2400780e PC	152	{ /* sentinel */ }
	153	};
	154	MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
	155
b3d99681 RZ	156	struct mxs_phy {
	157	struct usb_phy phy;
	158	struct clk *clk;
2400780e	159	const struct mxs_phy_data *data;
0d896538	160	struct regmap *regmap_anatop;
83be181b	161	int port_id;
b3d99681 RZ	162	};
b3d99681 RZ	163
bf783438 PC	164	static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
	165	{
	166	return mxs_phy->data == &imx6q_phy_data;
	167	}
	168
	169	static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
	170	{
	171	return mxs_phy->data == &imx6sl_phy_data;
	172	}
	173
47d1845f PC	174	/*
	175	* PHY needs some 32K cycles to switch from 32K clock to
	176	* bus (such as AHB/AXI, etc) clock.
	177	*/
	178	static void mxs_phy_clock_switch_delay(void)
	179	{
	180	usleep_range(300, 400);
	181	}
	182
51e563e3	183	static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
b3d99681	184	{
51e563e3	185	int ret;
b3d99681 RZ	186	void __iomem *base = mxs_phy->phy.io_priv;
b3d99681 RZ	187
51e563e3 FE	188	ret = stmp_reset_block(base + HW_USBPHY_CTRL);
	189	if (ret)
	190	return ret;
b3d99681 RZ	191
b3d99681 RZ	192	/* Power up the PHY */
b5a726b3	193	writel(0, base + HW_USBPHY_PWD);
b3d99681	194
13644144 PC	195	/*
	196	* USB PHY Ctrl Setting
	197	* - Auto clock/power on
	198	* - Enable full/low speed support
	199	*/
	200	writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS \|
	201	BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE \|
	202	BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD \|
	203	BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE \|
	204	BM_USBPHY_CTRL_ENAUTO_PWRON_PLL \|
	205	BM_USBPHY_CTRL_ENUTMILEVEL2 \|
	206	BM_USBPHY_CTRL_ENUTMILEVEL3,
b5a726b3	207	base + HW_USBPHY_CTRL_SET);
51e563e3	208
22db05ec PC	209	if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
	210	writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
	211
51e563e3	212	return 0;
b3d99681 RZ	213	}
b3d99681 RZ	214
3f126505 PC	215	/* Return true if the vbus is there */
	216	static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
	217	{
	218	unsigned int vbus_value;
	219
	220	if (mxs_phy->port_id == 0)
	221	regmap_read(mxs_phy->regmap_anatop,
	222	ANADIG_USB1_VBUS_DET_STAT,
	223	&vbus_value);
	224	else if (mxs_phy->port_id == 1)
	225	regmap_read(mxs_phy->regmap_anatop,
	226	ANADIG_USB2_VBUS_DET_STAT,
	227	&vbus_value);
	228
	229	if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
	230	return true;
	231	else
	232	return false;
	233	}
	234
	235	static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
	236	{
	237	void __iomem *base = mxs_phy->phy.io_priv;
	238	u32 reg;
	239
	240	if (disconnect)
	241	writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
	242	base + HW_USBPHY_DEBUG_CLR);
	243
	244	if (mxs_phy->port_id == 0) {
	245	reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
	246	: ANADIG_USB1_LOOPBACK_CLR;
	247	regmap_write(mxs_phy->regmap_anatop, reg,
	248	BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 \|
	249	BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
	250	} else if (mxs_phy->port_id == 1) {
	251	reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
	252	: ANADIG_USB2_LOOPBACK_CLR;
	253	regmap_write(mxs_phy->regmap_anatop, reg,
	254	BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 \|
	255	BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
	256	}
	257
	258	if (!disconnect)
	259	writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
	260	base + HW_USBPHY_DEBUG_SET);
	261
	262	/* Delay some time, and let Linestate be SE0 for controller */
	263	if (disconnect)
	264	usleep_range(500, 1000);
	265	}
	266
7b09e676 LJ	267	static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
	268	{
	269	void __iomem *base = mxs_phy->phy.io_priv;
	270	u32 phyctrl = readl(base + HW_USBPHY_CTRL);
	271
	272	if (IS_ENABLED(CONFIG_USB_OTG) &&
	273	!(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE))
	274	return true;
	275
	276	return false;
	277	}
	278
3f126505 PC	279	static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
	280	{
	281	bool vbus_is_on = false;
	282
	283	/* If the SoCs don't need to disconnect line without vbus, quit */
	284	if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
	285	return;
	286
	287	/* If the SoCs don't have anatop, quit */
	288	if (!mxs_phy->regmap_anatop)
	289	return;
	290
	291	vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
	292
7b09e676	293	if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
3f126505 PC	294	__mxs_phy_disconnect_line(mxs_phy, true);
	295	else
	296	__mxs_phy_disconnect_line(mxs_phy, false);
	297
	298	}
	299
b3d99681 RZ	300	static int mxs_phy_init(struct usb_phy *phy)
b3d99681 RZ	301	{
67c21fc8	302	int ret;
b3d99681 RZ	303	struct mxs_phy *mxs_phy = to_mxs_phy(phy);
b3d99681 RZ	304
47d1845f	305	mxs_phy_clock_switch_delay();
67c21fc8 FE	306	ret = clk_prepare_enable(mxs_phy->clk);
	307	if (ret)
	308	return ret;
	309
51e563e3	310	return mxs_phy_hw_init(mxs_phy);
b3d99681 RZ	311	}
	312
	313	static void mxs_phy_shutdown(struct usb_phy *phy)
	314	{
	315	struct mxs_phy *mxs_phy = to_mxs_phy(phy);
fdf80e78 PC	316	u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP \|
	317	BM_USBPHY_CTRL_ENDPDMCHG_WKUP \|
	318	BM_USBPHY_CTRL_ENIDCHG_WKUP \|
	319	BM_USBPHY_CTRL_ENAUTOSET_USBCLKS \|
	320	BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE \|
	321	BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD \|
	322	BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE \|
	323	BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;
	324
	325	writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
	326	writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
b3d99681	327
b5a726b3 MKB	328	writel(BM_USBPHY_CTRL_CLKGATE,
b5a726b3 MKB	329	phy->io_priv + HW_USBPHY_CTRL_SET);
b3d99681 RZ	330
	331	clk_disable_unprepare(mxs_phy->clk);
	332	}
	333
efdbd3a5 PC	334	static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
	335	{
	336	unsigned int line_state;
	337	/* bit definition is the same for all controllers */
	338	unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
	339	dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
	340	unsigned int reg = ANADIG_USB1_MISC;
	341
	342	/* If the SoCs don't have anatop, quit */
	343	if (!mxs_phy->regmap_anatop)
	344	return false;
	345
	346	if (mxs_phy->port_id == 0)
	347	reg = ANADIG_USB1_MISC;
	348	else if (mxs_phy->port_id == 1)
	349	reg = ANADIG_USB2_MISC;
	350
	351	regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
	352
	353	if ((line_state & (dp_bit \| dm_bit)) == dm_bit)
	354	return true;
	355	else
	356	return false;
	357	}
	358
04a6221c PC	359	static int mxs_phy_suspend(struct usb_phy *x, int suspend)
04a6221c PC	360	{
67c21fc8	361	int ret;
04a6221c	362	struct mxs_phy *mxs_phy = to_mxs_phy(x);
efdbd3a5 PC	363	bool low_speed_connection, vbus_is_on;
	364
	365	low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
	366	vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
04a6221c PC	367
04a6221c PC	368	if (suspend) {
efdbd3a5 PC	369	/*
	370	* FIXME: Do not power down RXPWD1PT1 bit for low speed
	371	* connect. The low speed connection will have problem at
	372	* very rare cases during usb suspend and resume process.
	373	*/
e235f7b8 PC	374	if (low_speed_connection & vbus_is_on) {
	375	/*
	376	* If value to be set as pwd value is not 0xffffffff,
	377	* several 32Khz cycles are needed.
	378	*/
	379	mxs_phy_clock_switch_delay();
	380	writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
	381	} else {
efdbd3a5	382	writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
e235f7b8	383	}
b5a726b3 MKB	384	writel(BM_USBPHY_CTRL_CLKGATE,
b5a726b3 MKB	385	x->io_priv + HW_USBPHY_CTRL_SET);
04a6221c PC	386	clk_disable_unprepare(mxs_phy->clk);
04a6221c PC	387	} else {
47d1845f	388	mxs_phy_clock_switch_delay();
67c21fc8 FE	389	ret = clk_prepare_enable(mxs_phy->clk);
	390	if (ret)
	391	return ret;
b5a726b3 MKB	392	writel(BM_USBPHY_CTRL_CLKGATE,
	393	x->io_priv + HW_USBPHY_CTRL_CLR);
	394	writel(0, x->io_priv + HW_USBPHY_PWD);
04a6221c PC	395	}
	396
	397	return 0;
	398	}
	399
3f126505 PC	400	static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
	401	{
	402	struct mxs_phy *mxs_phy = to_mxs_phy(x);
	403	u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP \|
	404	BM_USBPHY_CTRL_ENDPDMCHG_WKUP \|
	405	BM_USBPHY_CTRL_ENIDCHG_WKUP;
	406	if (enabled) {
	407	mxs_phy_disconnect_line(mxs_phy, true);
	408	writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
	409	} else {
	410	writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
	411	mxs_phy_disconnect_line(mxs_phy, false);
	412	}
	413
	414	return 0;
	415	}
	416
ac96511b PC	417	static int mxs_phy_on_connect(struct usb_phy *phy,
ac96511b PC	418	enum usb_device_speed speed)
b3d99681	419	{
f6a15824 PC	420	dev_dbg(phy->dev, "%s device has connected\n",
f6a15824 PC	421	(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
b3d99681	422
ac96511b	423	if (speed == USB_SPEED_HIGH)
b5a726b3 MKB	424	writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
b5a726b3 MKB	425	phy->io_priv + HW_USBPHY_CTRL_SET);
b3d99681 RZ	426
	427	return 0;
	428	}
	429
ac96511b PC	430	static int mxs_phy_on_disconnect(struct usb_phy *phy,
ac96511b PC	431	enum usb_device_speed speed)
b3d99681	432	{
f6a15824 PC	433	dev_dbg(phy->dev, "%s device has disconnected\n",
f6a15824 PC	434	(speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
b3d99681	435
f78c0957 PC	436	/* Sometimes, the speed is not high speed when the error occurs */
	437	if (readl(phy->io_priv + HW_USBPHY_CTRL) &
	438	BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
b5a726b3 MKB	439	writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
b5a726b3 MKB	440	phy->io_priv + HW_USBPHY_CTRL_CLR);
b3d99681 RZ	441
	442	return 0;
	443	}
	444
	445	static int mxs_phy_probe(struct platform_device *pdev)
	446	{
	447	struct resource *res;
	448	void __iomem *base;
	449	struct clk *clk;
	450	struct mxs_phy *mxs_phy;
25df6397	451	int ret;
2400780e PC	452	const struct of_device_id *of_id =
2400780e PC	453	of_match_device(mxs_phy_dt_ids, &pdev->dev);
0d896538	454	struct device_node *np = pdev->dev.of_node;
b3d99681 RZ	455
b3d99681 RZ	456	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
148e1134 TR	457	base = devm_ioremap_resource(&pdev->dev, res);
	458	if (IS_ERR(base))
	459	return PTR_ERR(base);
b3d99681 RZ	460
	461	clk = devm_clk_get(&pdev->dev, NULL);
	462	if (IS_ERR(clk)) {
	463	dev_err(&pdev->dev,
	464	"can't get the clock, err=%ld", PTR_ERR(clk));
	465	return PTR_ERR(clk);
	466	}
	467
	468	mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL);
c62fe556	469	if (!mxs_phy)
b3d99681	470	return -ENOMEM;
b3d99681	471
0d896538 PC	472	/* Some SoCs don't have anatop registers */
	473	if (of_get_property(np, "fsl,anatop", NULL)) {
	474	mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
	475	(np, "fsl,anatop");
	476	if (IS_ERR(mxs_phy->regmap_anatop)) {
	477	dev_dbg(&pdev->dev,
	478	"failed to find regmap for anatop\n");
	479	return PTR_ERR(mxs_phy->regmap_anatop);
	480	}
	481	}
	482
83be181b PC	483	ret = of_alias_get_id(np, "usbphy");
	484	if (ret < 0)
	485	dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
	486	mxs_phy->port_id = ret;
	487
b3d99681 RZ	488	mxs_phy->phy.io_priv = base;
	489	mxs_phy->phy.dev = &pdev->dev;
	490	mxs_phy->phy.label = DRIVER_NAME;
	491	mxs_phy->phy.init = mxs_phy_init;
	492	mxs_phy->phy.shutdown = mxs_phy_shutdown;
04a6221c	493	mxs_phy->phy.set_suspend = mxs_phy_suspend;
b3d99681 RZ	494	mxs_phy->phy.notify_connect = mxs_phy_on_connect;
b3d99681 RZ	495	mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
4e0aa635	496	mxs_phy->phy.type = USB_PHY_TYPE_USB2;
3f126505	497	mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup;
b3d99681	498
b3d99681	499	mxs_phy->clk = clk;
2400780e	500	mxs_phy->data = of_id->data;
b3d99681	501
97a27f73	502	platform_set_drvdata(pdev, mxs_phy);
b3d99681	503
bf783438 PC	504	device_set_wakeup_capable(&pdev->dev, true);
bf783438 PC	505
25df6397 SH	506	ret = usb_add_phy_dev(&mxs_phy->phy);
	507	if (ret)
	508	return ret;
	509
b3d99681 RZ	510	return 0;
	511	}
	512
fb4e98ab	513	static int mxs_phy_remove(struct platform_device *pdev)
b3d99681	514	{
25df6397 SH	515	struct mxs_phy *mxs_phy = platform_get_drvdata(pdev);
	516
	517	usb_remove_phy(&mxs_phy->phy);
	518
b3d99681 RZ	519	return 0;
	520	}
	521
bf783438 PC	522	#ifdef CONFIG_PM_SLEEP
	523	static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
	524	{
	525	unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
	526
	527	/* If the SoCs don't have anatop, quit */
	528	if (!mxs_phy->regmap_anatop)
	529	return;
	530
	531	if (is_imx6q_phy(mxs_phy))
	532	regmap_write(mxs_phy->regmap_anatop, reg,
	533	BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
	534	else if (is_imx6sl_phy(mxs_phy))
	535	regmap_write(mxs_phy->regmap_anatop,
	536	reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
	537	}
	538
	539	static int mxs_phy_system_suspend(struct device *dev)
	540	{
	541	struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
	542
	543	if (device_may_wakeup(dev))
	544	mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
	545
	546	return 0;
	547	}
	548
	549	static int mxs_phy_system_resume(struct device *dev)
	550	{
	551	struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
	552
	553	if (device_may_wakeup(dev))
	554	mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
	555
	556	return 0;
	557	}
	558	#endif /* CONFIG_PM_SLEEP */
	559
	560	static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
	561	mxs_phy_system_resume);
	562
b3d99681 RZ	563	static struct platform_driver mxs_phy_driver = {
b3d99681 RZ	564	.probe = mxs_phy_probe,
7690417d	565	.remove = mxs_phy_remove,
b3d99681 RZ	566	.driver = {
b3d99681 RZ	567	.name = DRIVER_NAME,
b3d99681	568	.of_match_table = mxs_phy_dt_ids,
bf783438	569	.pm = &mxs_phy_pm,
b3d99681 RZ	570	},
	571	};
	572
	573	static int __init mxs_phy_module_init(void)
	574	{
	575	return platform_driver_register(&mxs_phy_driver);
	576	}
	577	postcore_initcall(mxs_phy_module_init);
	578
	579	static void __exit mxs_phy_module_exit(void)
	580	{
	581	platform_driver_unregister(&mxs_phy_driver);
	582	}
	583	module_exit(mxs_phy_module_exit);
	584
	585	MODULE_ALIAS("platform:mxs-usb-phy");
	586	MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
	587	MODULE_AUTHOR("Richard Zhao <richard.zhao@freescale.com>");
	588	MODULE_DESCRIPTION("Freescale MXS USB PHY driver");
	589	MODULE_LICENSE("GPL");