Commit | Line | Data |
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d860852e | 1 | /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. |
e0c201f3 PK |
2 | * |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | * | |
12 | * You should have received a copy of the GNU General Public License | |
13 | * along with this program; if not, write to the Free Software | |
14 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
15 | * 02110-1301, USA. | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
b9b09231 | 21 | #include <linux/extcon.h> |
6f98f545 | 22 | #include <linux/gpio/consumer.h> |
e0c201f3 PK |
23 | #include <linux/platform_device.h> |
24 | #include <linux/clk.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/err.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/ioport.h> | |
31 | #include <linux/uaccess.h> | |
32 | #include <linux/debugfs.h> | |
33 | #include <linux/seq_file.h> | |
87c0104a | 34 | #include <linux/pm_runtime.h> |
8364f9af II |
35 | #include <linux/of.h> |
36 | #include <linux/of_device.h> | |
6f98f545 | 37 | #include <linux/reboot.h> |
a2734543 | 38 | #include <linux/reset.h> |
b9b09231 AB |
39 | #include <linux/types.h> |
40 | #include <linux/usb/otg.h> | |
e0c201f3 PK |
41 | |
42 | #include <linux/usb.h> | |
43 | #include <linux/usb/otg.h> | |
8364f9af | 44 | #include <linux/usb/of.h> |
e0c201f3 PK |
45 | #include <linux/usb/ulpi.h> |
46 | #include <linux/usb/gadget.h> | |
47 | #include <linux/usb/hcd.h> | |
e0c201f3 | 48 | #include <linux/usb/msm_hsusb_hw.h> |
11aa5c47 | 49 | #include <linux/regulator/consumer.h> |
e0c201f3 | 50 | |
b9b09231 AB |
51 | /** |
52 | * OTG control | |
53 | * | |
54 | * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host | |
55 | * only configuration. | |
56 | * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY. | |
57 | * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware. | |
58 | * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs. | |
59 | * | |
60 | */ | |
61 | enum otg_control_type { | |
62 | OTG_NO_CONTROL = 0, | |
63 | OTG_PHY_CONTROL, | |
64 | OTG_PMIC_CONTROL, | |
65 | OTG_USER_CONTROL, | |
66 | }; | |
67 | ||
68 | /** | |
69 | * PHY used in | |
70 | * | |
71 | * INVALID_PHY Unsupported PHY | |
72 | * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY | |
73 | * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY | |
74 | * | |
75 | */ | |
76 | enum msm_usb_phy_type { | |
77 | INVALID_PHY = 0, | |
78 | CI_45NM_INTEGRATED_PHY, | |
79 | SNPS_28NM_INTEGRATED_PHY, | |
80 | }; | |
81 | ||
82 | #define IDEV_CHG_MAX 1500 | |
83 | #define IUNIT 100 | |
84 | ||
85 | /** | |
86 | * Different states involved in USB charger detection. | |
87 | * | |
88 | * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection | |
89 | * process is not yet started. | |
90 | * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact. | |
91 | * USB_CHG_STATE_DCD_DONE Data pin contact is detected. | |
92 | * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects | |
93 | * between SDP and DCP/CDP). | |
94 | * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects | |
95 | * between DCP and CDP). | |
96 | * USB_CHG_STATE_DETECTED USB charger type is determined. | |
97 | * | |
98 | */ | |
99 | enum usb_chg_state { | |
100 | USB_CHG_STATE_UNDEFINED = 0, | |
101 | USB_CHG_STATE_WAIT_FOR_DCD, | |
102 | USB_CHG_STATE_DCD_DONE, | |
103 | USB_CHG_STATE_PRIMARY_DONE, | |
104 | USB_CHG_STATE_SECONDARY_DONE, | |
105 | USB_CHG_STATE_DETECTED, | |
106 | }; | |
107 | ||
108 | /** | |
109 | * USB charger types | |
110 | * | |
111 | * USB_INVALID_CHARGER Invalid USB charger. | |
112 | * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port | |
113 | * on USB2.0 compliant host/hub. | |
114 | * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger). | |
115 | * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and | |
116 | * IDEV_CHG_MAX can be drawn irrespective of USB state. | |
117 | * | |
118 | */ | |
119 | enum usb_chg_type { | |
120 | USB_INVALID_CHARGER = 0, | |
121 | USB_SDP_CHARGER, | |
122 | USB_DCP_CHARGER, | |
123 | USB_CDP_CHARGER, | |
124 | }; | |
125 | ||
126 | /** | |
127 | * struct msm_otg_platform_data - platform device data | |
128 | * for msm_otg driver. | |
129 | * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as | |
130 | * "do not overwrite default vaule at this address". | |
131 | * @phy_init_sz: PHY configuration sequence size. | |
132 | * @vbus_power: VBUS power on/off routine. | |
133 | * @power_budget: VBUS power budget in mA (0 will be treated as 500mA). | |
134 | * @mode: Supported mode (OTG/peripheral/host). | |
135 | * @otg_control: OTG switch controlled by user/Id pin | |
136 | */ | |
137 | struct msm_otg_platform_data { | |
138 | int *phy_init_seq; | |
139 | int phy_init_sz; | |
140 | void (*vbus_power)(bool on); | |
141 | unsigned power_budget; | |
142 | enum usb_dr_mode mode; | |
143 | enum otg_control_type otg_control; | |
144 | enum msm_usb_phy_type phy_type; | |
145 | void (*setup_gpio)(enum usb_otg_state state); | |
146 | }; | |
147 | ||
148 | /** | |
149 | * struct msm_usb_cable - structure for exteternal connector cable | |
150 | * state tracking | |
151 | * @nb: hold event notification callback | |
152 | * @conn: used for notification registration | |
153 | */ | |
154 | struct msm_usb_cable { | |
155 | struct notifier_block nb; | |
156 | struct extcon_dev *extcon; | |
157 | }; | |
158 | ||
159 | /** | |
160 | * struct msm_otg: OTG driver data. Shared by HCD and DCD. | |
161 | * @otg: USB OTG Transceiver structure. | |
162 | * @pdata: otg device platform data. | |
163 | * @irq: IRQ number assigned for HSUSB controller. | |
164 | * @clk: clock struct of usb_hs_clk. | |
165 | * @pclk: clock struct of usb_hs_pclk. | |
166 | * @core_clk: clock struct of usb_hs_core_clk. | |
167 | * @regs: ioremapped register base address. | |
168 | * @inputs: OTG state machine inputs(Id, SessValid etc). | |
169 | * @sm_work: OTG state machine work. | |
170 | * @in_lpm: indicates low power mode (LPM) state. | |
171 | * @async_int: Async interrupt arrived. | |
172 | * @cur_power: The amount of mA available from downstream port. | |
173 | * @chg_work: Charger detection work. | |
174 | * @chg_state: The state of charger detection process. | |
175 | * @chg_type: The type of charger attached. | |
176 | * @dcd_retires: The retry count used to track Data contact | |
177 | * detection process. | |
178 | * @manual_pullup: true if VBUS is not routed to USB controller/phy | |
179 | * and controller driver therefore enables pull-up explicitly before | |
180 | * starting controller using usbcmd run/stop bit. | |
181 | * @vbus: VBUS signal state trakining, using extcon framework | |
182 | * @id: ID signal state trakining, using extcon framework | |
183 | * @switch_gpio: Descriptor for GPIO used to control external Dual | |
184 | * SPDT USB Switch. | |
185 | * @reboot: Used to inform the driver to route USB D+/D- line to Device | |
186 | * connector | |
187 | */ | |
188 | struct msm_otg { | |
189 | struct usb_phy phy; | |
190 | struct msm_otg_platform_data *pdata; | |
191 | int irq; | |
192 | struct clk *clk; | |
193 | struct clk *pclk; | |
194 | struct clk *core_clk; | |
195 | void __iomem *regs; | |
196 | #define ID 0 | |
197 | #define B_SESS_VLD 1 | |
198 | unsigned long inputs; | |
199 | struct work_struct sm_work; | |
200 | atomic_t in_lpm; | |
201 | int async_int; | |
202 | unsigned cur_power; | |
203 | int phy_number; | |
204 | struct delayed_work chg_work; | |
205 | enum usb_chg_state chg_state; | |
206 | enum usb_chg_type chg_type; | |
207 | u8 dcd_retries; | |
208 | struct regulator *v3p3; | |
209 | struct regulator *v1p8; | |
210 | struct regulator *vddcx; | |
211 | ||
212 | struct reset_control *phy_rst; | |
213 | struct reset_control *link_rst; | |
214 | int vdd_levels[3]; | |
215 | ||
216 | bool manual_pullup; | |
217 | ||
218 | struct msm_usb_cable vbus; | |
219 | struct msm_usb_cable id; | |
220 | ||
221 | struct gpio_desc *switch_gpio; | |
222 | struct notifier_block reboot; | |
223 | }; | |
224 | ||
e0c201f3 PK |
225 | #define MSM_USB_BASE (motg->regs) |
226 | #define DRIVER_NAME "msm_otg" | |
227 | ||
228 | #define ULPI_IO_TIMEOUT_USEC (10 * 1000) | |
d69c6f5d | 229 | #define LINK_RESET_TIMEOUT_USEC (250 * 1000) |
11aa5c47 A |
230 | |
231 | #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */ | |
232 | #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */ | |
233 | #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */ | |
234 | #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */ | |
235 | ||
236 | #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */ | |
237 | #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */ | |
238 | #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */ | |
239 | #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */ | |
240 | ||
241 | #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */ | |
242 | #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */ | |
01799b62 II |
243 | #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */ |
244 | ||
245 | enum vdd_levels { | |
246 | VDD_LEVEL_NONE = 0, | |
247 | VDD_LEVEL_MIN, | |
248 | VDD_LEVEL_MAX, | |
249 | }; | |
11aa5c47 | 250 | |
11aa5c47 A |
251 | static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init) |
252 | { | |
253 | int ret = 0; | |
254 | ||
255 | if (init) { | |
37cfdaf7 | 256 | ret = regulator_set_voltage(motg->vddcx, |
01799b62 II |
257 | motg->vdd_levels[VDD_LEVEL_MIN], |
258 | motg->vdd_levels[VDD_LEVEL_MAX]); | |
11aa5c47 | 259 | if (ret) { |
3aca0fa9 | 260 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
11aa5c47 A |
261 | return ret; |
262 | } | |
263 | ||
37cfdaf7 | 264 | ret = regulator_enable(motg->vddcx); |
6b99c68e | 265 | if (ret) |
1d4c9293 | 266 | dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n"); |
11aa5c47 | 267 | } else { |
37cfdaf7 | 268 | ret = regulator_set_voltage(motg->vddcx, 0, |
01799b62 | 269 | motg->vdd_levels[VDD_LEVEL_MAX]); |
e99c4309 | 270 | if (ret) |
3aca0fa9 | 271 | dev_err(motg->phy.dev, "Cannot set vddcx voltage\n"); |
37cfdaf7 | 272 | ret = regulator_disable(motg->vddcx); |
11aa5c47 | 273 | if (ret) |
1d4c9293 | 274 | dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n"); |
11aa5c47 A |
275 | } |
276 | ||
277 | return ret; | |
278 | } | |
279 | ||
280 | static int msm_hsusb_ldo_init(struct msm_otg *motg, int init) | |
281 | { | |
282 | int rc = 0; | |
283 | ||
284 | if (init) { | |
37cfdaf7 | 285 | rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN, |
11aa5c47 A |
286 | USB_PHY_3P3_VOL_MAX); |
287 | if (rc) { | |
3aca0fa9 | 288 | dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n"); |
6b99c68e | 289 | goto exit; |
11aa5c47 | 290 | } |
37cfdaf7 | 291 | rc = regulator_enable(motg->v3p3); |
11aa5c47 | 292 | if (rc) { |
1d4c9293 | 293 | dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n"); |
6b99c68e | 294 | goto exit; |
11aa5c47 | 295 | } |
37cfdaf7 | 296 | rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN, |
11aa5c47 A |
297 | USB_PHY_1P8_VOL_MAX); |
298 | if (rc) { | |
3aca0fa9 | 299 | dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n"); |
6b99c68e | 300 | goto disable_3p3; |
11aa5c47 | 301 | } |
37cfdaf7 | 302 | rc = regulator_enable(motg->v1p8); |
11aa5c47 | 303 | if (rc) { |
1d4c9293 | 304 | dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n"); |
6b99c68e | 305 | goto disable_3p3; |
11aa5c47 A |
306 | } |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
37cfdaf7 | 311 | regulator_disable(motg->v1p8); |
11aa5c47 | 312 | disable_3p3: |
37cfdaf7 | 313 | regulator_disable(motg->v3p3); |
6b99c68e | 314 | exit: |
11aa5c47 A |
315 | return rc; |
316 | } | |
317 | ||
37cfdaf7 | 318 | static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on) |
11aa5c47 A |
319 | { |
320 | int ret = 0; | |
321 | ||
11aa5c47 | 322 | if (on) { |
fa53e351 | 323 | ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD); |
11aa5c47 | 324 | if (ret < 0) { |
3aca0fa9 | 325 | pr_err("Could not set HPM for v1p8\n"); |
11aa5c47 A |
326 | return ret; |
327 | } | |
fa53e351 | 328 | ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD); |
11aa5c47 | 329 | if (ret < 0) { |
3aca0fa9 | 330 | pr_err("Could not set HPM for v3p3\n"); |
fa53e351 | 331 | regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD); |
11aa5c47 A |
332 | return ret; |
333 | } | |
334 | } else { | |
fa53e351 | 335 | ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD); |
11aa5c47 | 336 | if (ret < 0) |
3aca0fa9 | 337 | pr_err("Could not set LPM for v1p8\n"); |
fa53e351 | 338 | ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD); |
11aa5c47 | 339 | if (ret < 0) |
3aca0fa9 | 340 | pr_err("Could not set LPM for v3p3\n"); |
11aa5c47 A |
341 | } |
342 | ||
343 | pr_debug("reg (%s)\n", on ? "HPM" : "LPM"); | |
344 | return ret < 0 ? ret : 0; | |
345 | } | |
346 | ||
1d4c9293 | 347 | static int ulpi_read(struct usb_phy *phy, u32 reg) |
e0c201f3 | 348 | { |
1d4c9293 | 349 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
350 | int cnt = 0; |
351 | ||
352 | /* initiate read operation */ | |
353 | writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg), | |
354 | USB_ULPI_VIEWPORT); | |
355 | ||
356 | /* wait for completion */ | |
357 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
358 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
359 | break; | |
360 | udelay(1); | |
361 | cnt++; | |
362 | } | |
363 | ||
364 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 365 | dev_err(phy->dev, "ulpi_read: timeout %08x\n", |
e0c201f3 PK |
366 | readl(USB_ULPI_VIEWPORT)); |
367 | return -ETIMEDOUT; | |
368 | } | |
369 | return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT)); | |
370 | } | |
371 | ||
1d4c9293 | 372 | static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
e0c201f3 | 373 | { |
1d4c9293 | 374 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
375 | int cnt = 0; |
376 | ||
377 | /* initiate write operation */ | |
378 | writel(ULPI_RUN | ULPI_WRITE | | |
379 | ULPI_ADDR(reg) | ULPI_DATA(val), | |
380 | USB_ULPI_VIEWPORT); | |
381 | ||
382 | /* wait for completion */ | |
383 | while (cnt < ULPI_IO_TIMEOUT_USEC) { | |
384 | if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN)) | |
385 | break; | |
386 | udelay(1); | |
387 | cnt++; | |
388 | } | |
389 | ||
390 | if (cnt >= ULPI_IO_TIMEOUT_USEC) { | |
1d4c9293 | 391 | dev_err(phy->dev, "ulpi_write: timeout\n"); |
e0c201f3 PK |
392 | return -ETIMEDOUT; |
393 | } | |
394 | return 0; | |
395 | } | |
396 | ||
1d4c9293 | 397 | static struct usb_phy_io_ops msm_otg_io_ops = { |
e0c201f3 PK |
398 | .read = ulpi_read, |
399 | .write = ulpi_write, | |
400 | }; | |
401 | ||
402 | static void ulpi_init(struct msm_otg *motg) | |
403 | { | |
404 | struct msm_otg_platform_data *pdata = motg->pdata; | |
8364f9af II |
405 | int *seq = pdata->phy_init_seq, idx; |
406 | u32 addr = ULPI_EXT_VENDOR_SPECIFIC; | |
e0c201f3 | 407 | |
8364f9af II |
408 | for (idx = 0; idx < pdata->phy_init_sz; idx++) { |
409 | if (seq[idx] == -1) | |
410 | continue; | |
e0c201f3 | 411 | |
1d4c9293 | 412 | dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n", |
8364f9af II |
413 | seq[idx], addr + idx); |
414 | ulpi_write(&motg->phy, seq[idx], addr + idx); | |
e0c201f3 PK |
415 | } |
416 | } | |
417 | ||
349907c2 II |
418 | static int msm_phy_notify_disconnect(struct usb_phy *phy, |
419 | enum usb_device_speed speed) | |
420 | { | |
44e42ae3 | 421 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
349907c2 II |
422 | int val; |
423 | ||
44e42ae3 II |
424 | if (motg->manual_pullup) { |
425 | val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL; | |
426 | usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A)); | |
427 | } | |
428 | ||
349907c2 II |
429 | /* |
430 | * Put the transceiver in non-driving mode. Otherwise host | |
431 | * may not detect soft-disconnection. | |
432 | */ | |
433 | val = ulpi_read(phy, ULPI_FUNC_CTRL); | |
434 | val &= ~ULPI_FUNC_CTRL_OPMODE_MASK; | |
435 | val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
436 | ulpi_write(phy, val, ULPI_FUNC_CTRL); | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
e0c201f3 PK |
441 | static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert) |
442 | { | |
a2734543 | 443 | int ret; |
5146d771 | 444 | |
32fc9eb5 | 445 | if (assert) |
a2734543 II |
446 | ret = reset_control_assert(motg->link_rst); |
447 | else | |
448 | ret = reset_control_deassert(motg->link_rst); | |
5146d771 | 449 | |
5146d771 II |
450 | if (ret) |
451 | dev_err(motg->phy.dev, "usb link clk reset %s failed\n", | |
452 | assert ? "assert" : "deassert"); | |
e0c201f3 | 453 | |
e0c201f3 PK |
454 | return ret; |
455 | } | |
456 | ||
457 | static int msm_otg_phy_clk_reset(struct msm_otg *motg) | |
458 | { | |
e44f1f4c | 459 | int ret = 0; |
e0c201f3 | 460 | |
32fc9eb5 | 461 | if (motg->phy_rst) |
a2734543 | 462 | ret = reset_control_reset(motg->phy_rst); |
5146d771 | 463 | |
e0c201f3 | 464 | if (ret) |
5146d771 II |
465 | dev_err(motg->phy.dev, "usb phy clk reset failed\n"); |
466 | ||
e0c201f3 PK |
467 | return ret; |
468 | } | |
469 | ||
d69c6f5d | 470 | static int msm_link_reset(struct msm_otg *motg) |
e0c201f3 PK |
471 | { |
472 | u32 val; | |
473 | int ret; | |
e0c201f3 PK |
474 | |
475 | ret = msm_otg_link_clk_reset(motg, 1); | |
e0c201f3 PK |
476 | if (ret) |
477 | return ret; | |
478 | ||
d69c6f5d II |
479 | /* wait for 1ms delay as suggested in HPG. */ |
480 | usleep_range(1000, 1200); | |
e0c201f3 | 481 | |
d69c6f5d | 482 | ret = msm_otg_link_clk_reset(motg, 0); |
e0c201f3 PK |
483 | if (ret) |
484 | return ret; | |
485 | ||
cfa3ff5d II |
486 | if (motg->phy_number) |
487 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
488 | ||
9f27984b | 489 | /* put transceiver in serial mode as part of reset */ |
d69c6f5d | 490 | val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK; |
9f27984b | 491 | writel(val | PORTSC_PTS_SERIAL, USB_PORTSC); |
d69c6f5d | 492 | |
e0c201f3 PK |
493 | return 0; |
494 | } | |
495 | ||
1d4c9293 | 496 | static int msm_otg_reset(struct usb_phy *phy) |
e0c201f3 | 497 | { |
1d4c9293 | 498 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 | 499 | int cnt = 0; |
e0c201f3 PK |
500 | |
501 | writel(USBCMD_RESET, USB_USBCMD); | |
502 | while (cnt < LINK_RESET_TIMEOUT_USEC) { | |
503 | if (!(readl(USB_USBCMD) & USBCMD_RESET)) | |
504 | break; | |
505 | udelay(1); | |
506 | cnt++; | |
507 | } | |
508 | if (cnt >= LINK_RESET_TIMEOUT_USEC) | |
509 | return -ETIMEDOUT; | |
510 | ||
9f27984b TB |
511 | /* select ULPI phy and clear other status/control bits in PORTSC */ |
512 | writel(PORTSC_PTS_ULPI, USB_PORTSC); | |
513 | ||
d69c6f5d II |
514 | writel(0x0, USB_AHBBURST); |
515 | writel(0x08, USB_AHBMODE); | |
516 | ||
517 | if (motg->phy_number) | |
518 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static void msm_phy_reset(struct msm_otg *motg) | |
523 | { | |
524 | void __iomem *addr; | |
525 | ||
526 | if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) { | |
527 | msm_otg_phy_clk_reset(motg); | |
528 | return; | |
529 | } | |
530 | ||
531 | addr = USB_PHY_CTRL; | |
532 | if (motg->phy_number) | |
533 | addr = USB_PHY_CTRL2; | |
534 | ||
535 | /* Assert USB PHY_POR */ | |
536 | writel(readl(addr) | PHY_POR_ASSERT, addr); | |
537 | ||
538 | /* | |
539 | * wait for minimum 10 microseconds as suggested in HPG. | |
540 | * Use a slightly larger value since the exact value didn't | |
541 | * work 100% of the time. | |
542 | */ | |
543 | udelay(12); | |
544 | ||
545 | /* Deassert USB PHY_POR */ | |
546 | writel(readl(addr) & ~PHY_POR_ASSERT, addr); | |
547 | } | |
548 | ||
549 | static int msm_usb_reset(struct usb_phy *phy) | |
550 | { | |
551 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
552 | int ret; | |
553 | ||
554 | if (!IS_ERR(motg->core_clk)) | |
555 | clk_prepare_enable(motg->core_clk); | |
556 | ||
557 | ret = msm_link_reset(motg); | |
558 | if (ret) { | |
559 | dev_err(phy->dev, "phy_reset failed\n"); | |
560 | return ret; | |
561 | } | |
562 | ||
563 | ret = msm_otg_reset(&motg->phy); | |
564 | if (ret) { | |
565 | dev_err(phy->dev, "link reset failed\n"); | |
566 | return ret; | |
567 | } | |
e0c201f3 PK |
568 | |
569 | msleep(100); | |
570 | ||
d69c6f5d II |
571 | /* Reset USB PHY after performing USB Link RESET */ |
572 | msm_phy_reset(motg); | |
573 | ||
574 | if (!IS_ERR(motg->core_clk)) | |
575 | clk_disable_unprepare(motg->core_clk); | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | static int msm_phy_init(struct usb_phy *phy) | |
581 | { | |
582 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); | |
583 | struct msm_otg_platform_data *pdata = motg->pdata; | |
584 | u32 val, ulpi_val = 0; | |
585 | ||
586 | /* Program USB PHY Override registers. */ | |
587 | ulpi_init(motg); | |
588 | ||
589 | /* | |
590 | * It is recommended in HPG to reset USB PHY after programming | |
591 | * USB PHY Override registers. | |
592 | */ | |
593 | msm_phy_reset(motg); | |
e0c201f3 PK |
594 | |
595 | if (pdata->otg_control == OTG_PHY_CONTROL) { | |
596 | val = readl(USB_OTGSC); | |
971232cf | 597 | if (pdata->mode == USB_DR_MODE_OTG) { |
e0c201f3 PK |
598 | ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID; |
599 | val |= OTGSC_IDIE | OTGSC_BSVIE; | |
971232cf | 600 | } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) { |
e0c201f3 PK |
601 | ulpi_val = ULPI_INT_SESS_VALID; |
602 | val |= OTGSC_BSVIE; | |
603 | } | |
604 | writel(val, USB_OTGSC); | |
1d4c9293 HK |
605 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE); |
606 | ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL); | |
e0c201f3 PK |
607 | } |
608 | ||
44e42ae3 II |
609 | if (motg->manual_pullup) { |
610 | val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT; | |
611 | ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A)); | |
612 | ||
613 | val = readl(USB_GENCONFIG_2); | |
614 | val |= GENCONFIG_2_SESS_VLD_CTRL_EN; | |
615 | writel(val, USB_GENCONFIG_2); | |
616 | ||
617 | val = readl(USB_USBCMD); | |
618 | val |= USBCMD_SESS_VLD_CTRL; | |
619 | writel(val, USB_USBCMD); | |
620 | ||
621 | val = ulpi_read(phy, ULPI_FUNC_CTRL); | |
622 | val &= ~ULPI_FUNC_CTRL_OPMODE_MASK; | |
623 | val |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
624 | ulpi_write(phy, val, ULPI_FUNC_CTRL); | |
625 | } | |
626 | ||
cfa3ff5d II |
627 | if (motg->phy_number) |
628 | writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2); | |
629 | ||
e0c201f3 PK |
630 | return 0; |
631 | } | |
632 | ||
87c0104a | 633 | #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000) |
7018773a PK |
634 | #define PHY_RESUME_TIMEOUT_USEC (100 * 1000) |
635 | ||
e7d613d1 JC |
636 | #ifdef CONFIG_PM |
637 | ||
37cfdaf7 | 638 | static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high) |
e7d613d1 | 639 | { |
01799b62 | 640 | int max_vol = motg->vdd_levels[VDD_LEVEL_MAX]; |
e7d613d1 JC |
641 | int min_vol; |
642 | int ret; | |
643 | ||
644 | if (high) | |
01799b62 | 645 | min_vol = motg->vdd_levels[VDD_LEVEL_MIN]; |
e7d613d1 | 646 | else |
01799b62 | 647 | min_vol = motg->vdd_levels[VDD_LEVEL_NONE]; |
e7d613d1 | 648 | |
37cfdaf7 | 649 | ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol); |
e7d613d1 | 650 | if (ret) { |
3aca0fa9 | 651 | pr_err("Cannot set vddcx voltage\n"); |
e7d613d1 JC |
652 | return ret; |
653 | } | |
654 | ||
655 | pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol); | |
656 | ||
657 | return ret; | |
658 | } | |
659 | ||
87c0104a PK |
660 | static int msm_otg_suspend(struct msm_otg *motg) |
661 | { | |
1d4c9293 HK |
662 | struct usb_phy *phy = &motg->phy; |
663 | struct usb_bus *bus = phy->otg->host; | |
87c0104a | 664 | struct msm_otg_platform_data *pdata = motg->pdata; |
cfa3ff5d | 665 | void __iomem *addr; |
87c0104a PK |
666 | int cnt = 0; |
667 | ||
668 | if (atomic_read(&motg->in_lpm)) | |
669 | return 0; | |
670 | ||
671 | disable_irq(motg->irq); | |
672 | /* | |
04aebcbb PK |
673 | * Chipidea 45-nm PHY suspend sequence: |
674 | * | |
87c0104a PK |
675 | * Interrupt Latch Register auto-clear feature is not present |
676 | * in all PHY versions. Latch register is clear on read type. | |
677 | * Clear latch register to avoid spurious wakeup from | |
678 | * low power mode (LPM). | |
04aebcbb | 679 | * |
87c0104a PK |
680 | * PHY comparators are disabled when PHY enters into low power |
681 | * mode (LPM). Keep PHY comparators ON in LPM only when we expect | |
682 | * VBUS/Id notifications from USB PHY. Otherwise turn off USB | |
683 | * PHY comparators. This save significant amount of power. | |
04aebcbb | 684 | * |
87c0104a PK |
685 | * PLL is not turned off when PHY enters into low power mode (LPM). |
686 | * Disable PLL for maximum power savings. | |
687 | */ | |
04aebcbb PK |
688 | |
689 | if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) { | |
1d4c9293 | 690 | ulpi_read(phy, 0x14); |
04aebcbb | 691 | if (pdata->otg_control == OTG_PHY_CONTROL) |
1d4c9293 HK |
692 | ulpi_write(phy, 0x01, 0x30); |
693 | ulpi_write(phy, 0x08, 0x09); | |
04aebcbb | 694 | } |
87c0104a PK |
695 | |
696 | /* | |
697 | * PHY may take some time or even fail to enter into low power | |
698 | * mode (LPM). Hence poll for 500 msec and reset the PHY and link | |
699 | * in failure case. | |
700 | */ | |
701 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
702 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
703 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
704 | break; | |
705 | udelay(1); | |
706 | cnt++; | |
707 | } | |
708 | ||
709 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) { | |
1d4c9293 HK |
710 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
711 | msm_otg_reset(phy); | |
87c0104a PK |
712 | enable_irq(motg->irq); |
713 | return -ETIMEDOUT; | |
714 | } | |
715 | ||
716 | /* | |
717 | * PHY has capability to generate interrupt asynchronously in low | |
718 | * power mode (LPM). This interrupt is level triggered. So USB IRQ | |
719 | * line must be disabled till async interrupt enable bit is cleared | |
720 | * in USBCMD register. Assert STP (ULPI interface STOP signal) to | |
721 | * block data communication from PHY. | |
722 | */ | |
723 | writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD); | |
724 | ||
cfa3ff5d II |
725 | addr = USB_PHY_CTRL; |
726 | if (motg->phy_number) | |
727 | addr = USB_PHY_CTRL2; | |
728 | ||
04aebcbb PK |
729 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
730 | motg->pdata->otg_control == OTG_PMIC_CONTROL) | |
cfa3ff5d | 731 | writel(readl(addr) | PHY_RETEN, addr); |
04aebcbb | 732 | |
b99a8f62 SB |
733 | clk_disable_unprepare(motg->pclk); |
734 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 735 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 736 | clk_disable_unprepare(motg->core_clk); |
87c0104a | 737 | |
04aebcbb PK |
738 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
739 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
37cfdaf7 II |
740 | msm_hsusb_ldo_set_mode(motg, 0); |
741 | msm_hsusb_config_vddcx(motg, 0); | |
04aebcbb PK |
742 | } |
743 | ||
1d4c9293 | 744 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
745 | enable_irq_wake(motg->irq); |
746 | if (bus) | |
747 | clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
748 | ||
749 | atomic_set(&motg->in_lpm, 1); | |
750 | enable_irq(motg->irq); | |
751 | ||
1d4c9293 | 752 | dev_info(phy->dev, "USB in low power mode\n"); |
87c0104a PK |
753 | |
754 | return 0; | |
755 | } | |
756 | ||
87c0104a PK |
757 | static int msm_otg_resume(struct msm_otg *motg) |
758 | { | |
1d4c9293 HK |
759 | struct usb_phy *phy = &motg->phy; |
760 | struct usb_bus *bus = phy->otg->host; | |
cfa3ff5d | 761 | void __iomem *addr; |
87c0104a PK |
762 | int cnt = 0; |
763 | unsigned temp; | |
764 | ||
765 | if (!atomic_read(&motg->in_lpm)) | |
766 | return 0; | |
767 | ||
b99a8f62 SB |
768 | clk_prepare_enable(motg->pclk); |
769 | clk_prepare_enable(motg->clk); | |
6b99c68e | 770 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 771 | clk_prepare_enable(motg->core_clk); |
87c0104a | 772 | |
04aebcbb PK |
773 | if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY && |
774 | motg->pdata->otg_control == OTG_PMIC_CONTROL) { | |
cfa3ff5d II |
775 | |
776 | addr = USB_PHY_CTRL; | |
777 | if (motg->phy_number) | |
778 | addr = USB_PHY_CTRL2; | |
779 | ||
37cfdaf7 II |
780 | msm_hsusb_ldo_set_mode(motg, 1); |
781 | msm_hsusb_config_vddcx(motg, 1); | |
cfa3ff5d | 782 | writel(readl(addr) & ~PHY_RETEN, addr); |
04aebcbb PK |
783 | } |
784 | ||
87c0104a PK |
785 | temp = readl(USB_USBCMD); |
786 | temp &= ~ASYNC_INTR_CTRL; | |
787 | temp &= ~ULPI_STP_CTRL; | |
788 | writel(temp, USB_USBCMD); | |
789 | ||
790 | /* | |
791 | * PHY comes out of low power mode (LPM) in case of wakeup | |
792 | * from asynchronous interrupt. | |
793 | */ | |
794 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
795 | goto skip_phy_resume; | |
796 | ||
797 | writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC); | |
798 | while (cnt < PHY_RESUME_TIMEOUT_USEC) { | |
799 | if (!(readl(USB_PORTSC) & PORTSC_PHCD)) | |
800 | break; | |
801 | udelay(1); | |
802 | cnt++; | |
803 | } | |
804 | ||
805 | if (cnt >= PHY_RESUME_TIMEOUT_USEC) { | |
806 | /* | |
807 | * This is a fatal error. Reset the link and | |
808 | * PHY. USB state can not be restored. Re-insertion | |
809 | * of USB cable is the only way to get USB working. | |
810 | */ | |
3aca0fa9 | 811 | dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n"); |
1d4c9293 | 812 | msm_otg_reset(phy); |
87c0104a PK |
813 | } |
814 | ||
815 | skip_phy_resume: | |
1d4c9293 | 816 | if (device_may_wakeup(phy->dev)) |
87c0104a PK |
817 | disable_irq_wake(motg->irq); |
818 | if (bus) | |
819 | set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags); | |
820 | ||
2ce2c3ac PK |
821 | atomic_set(&motg->in_lpm, 0); |
822 | ||
87c0104a PK |
823 | if (motg->async_int) { |
824 | motg->async_int = 0; | |
1d4c9293 | 825 | pm_runtime_put(phy->dev); |
87c0104a PK |
826 | enable_irq(motg->irq); |
827 | } | |
828 | ||
1d4c9293 | 829 | dev_info(phy->dev, "USB exited from low power mode\n"); |
87c0104a PK |
830 | |
831 | return 0; | |
832 | } | |
7018773a | 833 | #endif |
87c0104a | 834 | |
d860852e PK |
835 | static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA) |
836 | { | |
837 | if (motg->cur_power == mA) | |
838 | return; | |
839 | ||
840 | /* TODO: Notify PMIC about available current */ | |
1d4c9293 | 841 | dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA); |
d860852e PK |
842 | motg->cur_power = mA; |
843 | } | |
844 | ||
1d4c9293 | 845 | static int msm_otg_set_power(struct usb_phy *phy, unsigned mA) |
d860852e | 846 | { |
1d4c9293 | 847 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
d860852e PK |
848 | |
849 | /* | |
850 | * Gadget driver uses set_power method to notify about the | |
851 | * available current based on suspend/configured states. | |
852 | * | |
853 | * IDEV_CHG can be drawn irrespective of suspend/un-configured | |
854 | * states when CDP/ACA is connected. | |
855 | */ | |
856 | if (motg->chg_type == USB_SDP_CHARGER) | |
857 | msm_otg_notify_charger(motg, mA); | |
858 | ||
859 | return 0; | |
860 | } | |
861 | ||
1d4c9293 | 862 | static void msm_otg_start_host(struct usb_phy *phy, int on) |
e0c201f3 | 863 | { |
1d4c9293 | 864 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
865 | struct msm_otg_platform_data *pdata = motg->pdata; |
866 | struct usb_hcd *hcd; | |
867 | ||
1d4c9293 | 868 | if (!phy->otg->host) |
e0c201f3 PK |
869 | return; |
870 | ||
1d4c9293 | 871 | hcd = bus_to_hcd(phy->otg->host); |
e0c201f3 PK |
872 | |
873 | if (on) { | |
1d4c9293 | 874 | dev_dbg(phy->dev, "host on\n"); |
e0c201f3 PK |
875 | |
876 | if (pdata->vbus_power) | |
877 | pdata->vbus_power(1); | |
878 | /* | |
879 | * Some boards have a switch cotrolled by gpio | |
880 | * to enable/disable internal HUB. Enable internal | |
881 | * HUB before kicking the host. | |
882 | */ | |
883 | if (pdata->setup_gpio) | |
884 | pdata->setup_gpio(OTG_STATE_A_HOST); | |
885 | #ifdef CONFIG_USB | |
886 | usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); | |
3c9740a1 | 887 | device_wakeup_enable(hcd->self.controller); |
e0c201f3 PK |
888 | #endif |
889 | } else { | |
1d4c9293 | 890 | dev_dbg(phy->dev, "host off\n"); |
e0c201f3 PK |
891 | |
892 | #ifdef CONFIG_USB | |
893 | usb_remove_hcd(hcd); | |
894 | #endif | |
895 | if (pdata->setup_gpio) | |
896 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
897 | if (pdata->vbus_power) | |
898 | pdata->vbus_power(0); | |
899 | } | |
900 | } | |
901 | ||
1d4c9293 | 902 | static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host) |
e0c201f3 | 903 | { |
19c1eac2 | 904 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
e0c201f3 PK |
905 | struct usb_hcd *hcd; |
906 | ||
907 | /* | |
908 | * Fail host registration if this board can support | |
909 | * only peripheral configuration. | |
910 | */ | |
971232cf | 911 | if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) { |
19c1eac2 | 912 | dev_info(otg->usb_phy->dev, "Host mode is not supported\n"); |
e0c201f3 PK |
913 | return -ENODEV; |
914 | } | |
915 | ||
916 | if (!host) { | |
e47d9254 | 917 | if (otg->state == OTG_STATE_A_HOST) { |
19c1eac2 AT |
918 | pm_runtime_get_sync(otg->usb_phy->dev); |
919 | msm_otg_start_host(otg->usb_phy, 0); | |
e0c201f3 | 920 | otg->host = NULL; |
e47d9254 | 921 | otg->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
922 | schedule_work(&motg->sm_work); |
923 | } else { | |
924 | otg->host = NULL; | |
925 | } | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
930 | hcd = bus_to_hcd(host); | |
931 | hcd->power_budget = motg->pdata->power_budget; | |
932 | ||
933 | otg->host = host; | |
19c1eac2 | 934 | dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n"); |
e0c201f3 | 935 | |
8de4b3a3 II |
936 | pm_runtime_get_sync(otg->usb_phy->dev); |
937 | schedule_work(&motg->sm_work); | |
e0c201f3 PK |
938 | |
939 | return 0; | |
940 | } | |
941 | ||
1d4c9293 | 942 | static void msm_otg_start_peripheral(struct usb_phy *phy, int on) |
e0c201f3 | 943 | { |
1d4c9293 | 944 | struct msm_otg *motg = container_of(phy, struct msm_otg, phy); |
e0c201f3 PK |
945 | struct msm_otg_platform_data *pdata = motg->pdata; |
946 | ||
1d4c9293 | 947 | if (!phy->otg->gadget) |
e0c201f3 PK |
948 | return; |
949 | ||
950 | if (on) { | |
1d4c9293 | 951 | dev_dbg(phy->dev, "gadget on\n"); |
e0c201f3 PK |
952 | /* |
953 | * Some boards have a switch cotrolled by gpio | |
954 | * to enable/disable internal HUB. Disable internal | |
955 | * HUB before kicking the gadget. | |
956 | */ | |
957 | if (pdata->setup_gpio) | |
958 | pdata->setup_gpio(OTG_STATE_B_PERIPHERAL); | |
1d4c9293 | 959 | usb_gadget_vbus_connect(phy->otg->gadget); |
e0c201f3 | 960 | } else { |
1d4c9293 HK |
961 | dev_dbg(phy->dev, "gadget off\n"); |
962 | usb_gadget_vbus_disconnect(phy->otg->gadget); | |
e0c201f3 PK |
963 | if (pdata->setup_gpio) |
964 | pdata->setup_gpio(OTG_STATE_UNDEFINED); | |
965 | } | |
966 | ||
967 | } | |
968 | ||
1d4c9293 HK |
969 | static int msm_otg_set_peripheral(struct usb_otg *otg, |
970 | struct usb_gadget *gadget) | |
e0c201f3 | 971 | { |
19c1eac2 | 972 | struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy); |
e0c201f3 PK |
973 | |
974 | /* | |
975 | * Fail peripheral registration if this board can support | |
976 | * only host configuration. | |
977 | */ | |
971232cf | 978 | if (motg->pdata->mode == USB_DR_MODE_HOST) { |
19c1eac2 | 979 | dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n"); |
e0c201f3 PK |
980 | return -ENODEV; |
981 | } | |
982 | ||
983 | if (!gadget) { | |
e47d9254 | 984 | if (otg->state == OTG_STATE_B_PERIPHERAL) { |
19c1eac2 AT |
985 | pm_runtime_get_sync(otg->usb_phy->dev); |
986 | msm_otg_start_peripheral(otg->usb_phy, 0); | |
e0c201f3 | 987 | otg->gadget = NULL; |
e47d9254 | 988 | otg->state = OTG_STATE_UNDEFINED; |
e0c201f3 PK |
989 | schedule_work(&motg->sm_work); |
990 | } else { | |
991 | otg->gadget = NULL; | |
992 | } | |
993 | ||
994 | return 0; | |
995 | } | |
996 | otg->gadget = gadget; | |
19c1eac2 AT |
997 | dev_dbg(otg->usb_phy->dev, |
998 | "peripheral driver registered w/ tranceiver\n"); | |
e0c201f3 | 999 | |
8de4b3a3 II |
1000 | pm_runtime_get_sync(otg->usb_phy->dev); |
1001 | schedule_work(&motg->sm_work); | |
e0c201f3 PK |
1002 | |
1003 | return 0; | |
1004 | } | |
1005 | ||
d860852e PK |
1006 | static bool msm_chg_check_secondary_det(struct msm_otg *motg) |
1007 | { | |
1d4c9293 | 1008 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1009 | u32 chg_det; |
1010 | bool ret = false; | |
1011 | ||
1012 | switch (motg->pdata->phy_type) { | |
1013 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1014 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1015 | ret = chg_det & (1 << 4); |
1016 | break; | |
1017 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 1018 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
1019 | ret = chg_det & 1; |
1020 | break; | |
1021 | default: | |
1022 | break; | |
1023 | } | |
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | static void msm_chg_enable_secondary_det(struct msm_otg *motg) | |
1028 | { | |
1d4c9293 | 1029 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1030 | u32 chg_det; |
1031 | ||
1032 | switch (motg->pdata->phy_type) { | |
1033 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1034 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1035 | /* Turn off charger block */ |
1036 | chg_det |= ~(1 << 1); | |
1d4c9293 | 1037 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1038 | udelay(20); |
1039 | /* control chg block via ULPI */ | |
1040 | chg_det &= ~(1 << 3); | |
1d4c9293 | 1041 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1042 | /* put it in host mode for enabling D- source */ |
1043 | chg_det &= ~(1 << 2); | |
1d4c9293 | 1044 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1045 | /* Turn on chg detect block */ |
1046 | chg_det &= ~(1 << 1); | |
1d4c9293 | 1047 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1048 | udelay(20); |
1049 | /* enable chg detection */ | |
1050 | chg_det &= ~(1 << 0); | |
1d4c9293 | 1051 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1052 | break; |
1053 | case SNPS_28NM_INTEGRATED_PHY: | |
1054 | /* | |
1055 | * Configure DM as current source, DP as current sink | |
1056 | * and enable battery charging comparators. | |
1057 | */ | |
1d4c9293 HK |
1058 | ulpi_write(phy, 0x8, 0x85); |
1059 | ulpi_write(phy, 0x2, 0x85); | |
1060 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
1061 | break; |
1062 | default: | |
1063 | break; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | static bool msm_chg_check_primary_det(struct msm_otg *motg) | |
1068 | { | |
1d4c9293 | 1069 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1070 | u32 chg_det; |
1071 | bool ret = false; | |
1072 | ||
1073 | switch (motg->pdata->phy_type) { | |
1074 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1075 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1076 | ret = chg_det & (1 << 4); |
1077 | break; | |
1078 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 1079 | chg_det = ulpi_read(phy, 0x87); |
d860852e PK |
1080 | ret = chg_det & 1; |
1081 | break; | |
1082 | default: | |
1083 | break; | |
1084 | } | |
1085 | return ret; | |
1086 | } | |
1087 | ||
1088 | static void msm_chg_enable_primary_det(struct msm_otg *motg) | |
1089 | { | |
1d4c9293 | 1090 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1091 | u32 chg_det; |
1092 | ||
1093 | switch (motg->pdata->phy_type) { | |
1094 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1095 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1096 | /* enable chg detection */ |
1097 | chg_det &= ~(1 << 0); | |
1d4c9293 | 1098 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1099 | break; |
1100 | case SNPS_28NM_INTEGRATED_PHY: | |
1101 | /* | |
1102 | * Configure DP as current source, DM as current sink | |
1103 | * and enable battery charging comparators. | |
1104 | */ | |
1d4c9293 HK |
1105 | ulpi_write(phy, 0x2, 0x85); |
1106 | ulpi_write(phy, 0x1, 0x85); | |
d860852e PK |
1107 | break; |
1108 | default: | |
1109 | break; | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | static bool msm_chg_check_dcd(struct msm_otg *motg) | |
1114 | { | |
1d4c9293 | 1115 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1116 | u32 line_state; |
1117 | bool ret = false; | |
1118 | ||
1119 | switch (motg->pdata->phy_type) { | |
1120 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1121 | line_state = ulpi_read(phy, 0x15); |
d860852e PK |
1122 | ret = !(line_state & 1); |
1123 | break; | |
1124 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 1125 | line_state = ulpi_read(phy, 0x87); |
d860852e PK |
1126 | ret = line_state & 2; |
1127 | break; | |
1128 | default: | |
1129 | break; | |
1130 | } | |
1131 | return ret; | |
1132 | } | |
1133 | ||
1134 | static void msm_chg_disable_dcd(struct msm_otg *motg) | |
1135 | { | |
1d4c9293 | 1136 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1137 | u32 chg_det; |
1138 | ||
1139 | switch (motg->pdata->phy_type) { | |
1140 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1141 | chg_det = ulpi_read(phy, 0x34); |
d860852e | 1142 | chg_det &= ~(1 << 5); |
1d4c9293 | 1143 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1144 | break; |
1145 | case SNPS_28NM_INTEGRATED_PHY: | |
1d4c9293 | 1146 | ulpi_write(phy, 0x10, 0x86); |
d860852e PK |
1147 | break; |
1148 | default: | |
1149 | break; | |
1150 | } | |
1151 | } | |
1152 | ||
1153 | static void msm_chg_enable_dcd(struct msm_otg *motg) | |
1154 | { | |
1d4c9293 | 1155 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1156 | u32 chg_det; |
1157 | ||
1158 | switch (motg->pdata->phy_type) { | |
1159 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1160 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1161 | /* Turn on D+ current source */ |
1162 | chg_det |= (1 << 5); | |
1d4c9293 | 1163 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1164 | break; |
1165 | case SNPS_28NM_INTEGRATED_PHY: | |
1166 | /* Data contact detection enable */ | |
1d4c9293 | 1167 | ulpi_write(phy, 0x10, 0x85); |
d860852e PK |
1168 | break; |
1169 | default: | |
1170 | break; | |
1171 | } | |
1172 | } | |
1173 | ||
1174 | static void msm_chg_block_on(struct msm_otg *motg) | |
1175 | { | |
1d4c9293 | 1176 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1177 | u32 func_ctrl, chg_det; |
1178 | ||
1179 | /* put the controller in non-driving mode */ | |
1d4c9293 | 1180 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
1181 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
1182 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING; | |
1d4c9293 | 1183 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
1184 | |
1185 | switch (motg->pdata->phy_type) { | |
1186 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1187 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1188 | /* control chg block via ULPI */ |
1189 | chg_det &= ~(1 << 3); | |
1d4c9293 | 1190 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1191 | /* Turn on chg detect block */ |
1192 | chg_det &= ~(1 << 1); | |
1d4c9293 | 1193 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1194 | udelay(20); |
1195 | break; | |
1196 | case SNPS_28NM_INTEGRATED_PHY: | |
1197 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1198 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1199 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1200 | ulpi_write(phy, 0x1F, 0x92); |
1201 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1202 | udelay(100); |
1203 | break; | |
1204 | default: | |
1205 | break; | |
1206 | } | |
1207 | } | |
1208 | ||
1209 | static void msm_chg_block_off(struct msm_otg *motg) | |
1210 | { | |
1d4c9293 | 1211 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1212 | u32 func_ctrl, chg_det; |
1213 | ||
1214 | switch (motg->pdata->phy_type) { | |
1215 | case CI_45NM_INTEGRATED_PHY: | |
1d4c9293 | 1216 | chg_det = ulpi_read(phy, 0x34); |
d860852e PK |
1217 | /* Turn off charger block */ |
1218 | chg_det |= ~(1 << 1); | |
1d4c9293 | 1219 | ulpi_write(phy, chg_det, 0x34); |
d860852e PK |
1220 | break; |
1221 | case SNPS_28NM_INTEGRATED_PHY: | |
1222 | /* Clear charger detecting control bits */ | |
1d4c9293 | 1223 | ulpi_write(phy, 0x3F, 0x86); |
d860852e | 1224 | /* Clear alt interrupt latch and enable bits */ |
1d4c9293 HK |
1225 | ulpi_write(phy, 0x1F, 0x92); |
1226 | ulpi_write(phy, 0x1F, 0x95); | |
d860852e PK |
1227 | break; |
1228 | default: | |
1229 | break; | |
1230 | } | |
1231 | ||
1232 | /* put the controller in normal mode */ | |
1d4c9293 | 1233 | func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL); |
d860852e PK |
1234 | func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK; |
1235 | func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL; | |
1d4c9293 | 1236 | ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL); |
d860852e PK |
1237 | } |
1238 | ||
1239 | #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */ | |
1240 | #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */ | |
1241 | #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */ | |
1242 | #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */ | |
1243 | static void msm_chg_detect_work(struct work_struct *w) | |
1244 | { | |
1245 | struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work); | |
1d4c9293 | 1246 | struct usb_phy *phy = &motg->phy; |
d860852e PK |
1247 | bool is_dcd, tmout, vout; |
1248 | unsigned long delay; | |
1249 | ||
1d4c9293 | 1250 | dev_dbg(phy->dev, "chg detection work\n"); |
d860852e PK |
1251 | switch (motg->chg_state) { |
1252 | case USB_CHG_STATE_UNDEFINED: | |
1d4c9293 | 1253 | pm_runtime_get_sync(phy->dev); |
d860852e PK |
1254 | msm_chg_block_on(motg); |
1255 | msm_chg_enable_dcd(motg); | |
1256 | motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; | |
1257 | motg->dcd_retries = 0; | |
1258 | delay = MSM_CHG_DCD_POLL_TIME; | |
1259 | break; | |
1260 | case USB_CHG_STATE_WAIT_FOR_DCD: | |
1261 | is_dcd = msm_chg_check_dcd(motg); | |
1262 | tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES; | |
1263 | if (is_dcd || tmout) { | |
1264 | msm_chg_disable_dcd(motg); | |
1265 | msm_chg_enable_primary_det(motg); | |
1266 | delay = MSM_CHG_PRIMARY_DET_TIME; | |
1267 | motg->chg_state = USB_CHG_STATE_DCD_DONE; | |
1268 | } else { | |
1269 | delay = MSM_CHG_DCD_POLL_TIME; | |
1270 | } | |
1271 | break; | |
1272 | case USB_CHG_STATE_DCD_DONE: | |
1273 | vout = msm_chg_check_primary_det(motg); | |
1274 | if (vout) { | |
1275 | msm_chg_enable_secondary_det(motg); | |
1276 | delay = MSM_CHG_SECONDARY_DET_TIME; | |
1277 | motg->chg_state = USB_CHG_STATE_PRIMARY_DONE; | |
1278 | } else { | |
1279 | motg->chg_type = USB_SDP_CHARGER; | |
1280 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1281 | delay = 0; | |
1282 | } | |
1283 | break; | |
1284 | case USB_CHG_STATE_PRIMARY_DONE: | |
1285 | vout = msm_chg_check_secondary_det(motg); | |
1286 | if (vout) | |
1287 | motg->chg_type = USB_DCP_CHARGER; | |
1288 | else | |
1289 | motg->chg_type = USB_CDP_CHARGER; | |
1290 | motg->chg_state = USB_CHG_STATE_SECONDARY_DONE; | |
1291 | /* fall through */ | |
1292 | case USB_CHG_STATE_SECONDARY_DONE: | |
1293 | motg->chg_state = USB_CHG_STATE_DETECTED; | |
1294 | case USB_CHG_STATE_DETECTED: | |
1295 | msm_chg_block_off(motg); | |
1d4c9293 | 1296 | dev_dbg(phy->dev, "charger = %d\n", motg->chg_type); |
d860852e PK |
1297 | schedule_work(&motg->sm_work); |
1298 | return; | |
1299 | default: | |
1300 | return; | |
1301 | } | |
1302 | ||
1303 | schedule_delayed_work(&motg->chg_work, delay); | |
1304 | } | |
1305 | ||
e0c201f3 PK |
1306 | /* |
1307 | * We support OTG, Peripheral only and Host only configurations. In case | |
1308 | * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen | |
1309 | * via Id pin status or user request (debugfs). Id/BSV interrupts are not | |
1310 | * enabled when switch is controlled by user and default mode is supplied | |
1311 | * by board file, which can be changed by userspace later. | |
1312 | */ | |
1313 | static void msm_otg_init_sm(struct msm_otg *motg) | |
1314 | { | |
1315 | struct msm_otg_platform_data *pdata = motg->pdata; | |
1316 | u32 otgsc = readl(USB_OTGSC); | |
1317 | ||
1318 | switch (pdata->mode) { | |
971232cf | 1319 | case USB_DR_MODE_OTG: |
e0c201f3 PK |
1320 | if (pdata->otg_control == OTG_PHY_CONTROL) { |
1321 | if (otgsc & OTGSC_ID) | |
1322 | set_bit(ID, &motg->inputs); | |
1323 | else | |
1324 | clear_bit(ID, &motg->inputs); | |
1325 | ||
1326 | if (otgsc & OTGSC_BSV) | |
1327 | set_bit(B_SESS_VLD, &motg->inputs); | |
1328 | else | |
1329 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1330 | } else if (pdata->otg_control == OTG_USER_CONTROL) { | |
e0c201f3 PK |
1331 | set_bit(ID, &motg->inputs); |
1332 | clear_bit(B_SESS_VLD, &motg->inputs); | |
e0c201f3 PK |
1333 | } |
1334 | break; | |
971232cf | 1335 | case USB_DR_MODE_HOST: |
e0c201f3 PK |
1336 | clear_bit(ID, &motg->inputs); |
1337 | break; | |
971232cf | 1338 | case USB_DR_MODE_PERIPHERAL: |
e0c201f3 PK |
1339 | set_bit(ID, &motg->inputs); |
1340 | if (otgsc & OTGSC_BSV) | |
1341 | set_bit(B_SESS_VLD, &motg->inputs); | |
1342 | else | |
1343 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1344 | break; | |
1345 | default: | |
1346 | break; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | static void msm_otg_sm_work(struct work_struct *w) | |
1351 | { | |
1352 | struct msm_otg *motg = container_of(w, struct msm_otg, sm_work); | |
1d4c9293 | 1353 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1354 | |
e47d9254 | 1355 | switch (otg->state) { |
e0c201f3 | 1356 | case OTG_STATE_UNDEFINED: |
19c1eac2 AT |
1357 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n"); |
1358 | msm_otg_reset(otg->usb_phy); | |
e0c201f3 | 1359 | msm_otg_init_sm(motg); |
e47d9254 | 1360 | otg->state = OTG_STATE_B_IDLE; |
e0c201f3 PK |
1361 | /* FALL THROUGH */ |
1362 | case OTG_STATE_B_IDLE: | |
19c1eac2 | 1363 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n"); |
e0c201f3 PK |
1364 | if (!test_bit(ID, &motg->inputs) && otg->host) { |
1365 | /* disable BSV bit */ | |
1366 | writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC); | |
19c1eac2 | 1367 | msm_otg_start_host(otg->usb_phy, 1); |
e47d9254 | 1368 | otg->state = OTG_STATE_A_HOST; |
d860852e PK |
1369 | } else if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1370 | switch (motg->chg_state) { | |
1371 | case USB_CHG_STATE_UNDEFINED: | |
1372 | msm_chg_detect_work(&motg->chg_work.work); | |
1373 | break; | |
1374 | case USB_CHG_STATE_DETECTED: | |
1375 | switch (motg->chg_type) { | |
1376 | case USB_DCP_CHARGER: | |
1377 | msm_otg_notify_charger(motg, | |
1378 | IDEV_CHG_MAX); | |
1379 | break; | |
1380 | case USB_CDP_CHARGER: | |
1381 | msm_otg_notify_charger(motg, | |
1382 | IDEV_CHG_MAX); | |
19c1eac2 AT |
1383 | msm_otg_start_peripheral(otg->usb_phy, |
1384 | 1); | |
e47d9254 | 1385 | otg->state |
1d4c9293 | 1386 | = OTG_STATE_B_PERIPHERAL; |
d860852e PK |
1387 | break; |
1388 | case USB_SDP_CHARGER: | |
1389 | msm_otg_notify_charger(motg, IUNIT); | |
19c1eac2 AT |
1390 | msm_otg_start_peripheral(otg->usb_phy, |
1391 | 1); | |
e47d9254 | 1392 | otg->state |
1d4c9293 | 1393 | = OTG_STATE_B_PERIPHERAL; |
d860852e PK |
1394 | break; |
1395 | default: | |
1396 | break; | |
1397 | } | |
1398 | break; | |
1399 | default: | |
1400 | break; | |
1401 | } | |
1402 | } else { | |
1403 | /* | |
1404 | * If charger detection work is pending, decrement | |
1405 | * the pm usage counter to balance with the one that | |
1406 | * is incremented in charger detection work. | |
1407 | */ | |
1408 | if (cancel_delayed_work_sync(&motg->chg_work)) { | |
19c1eac2 AT |
1409 | pm_runtime_put_sync(otg->usb_phy->dev); |
1410 | msm_otg_reset(otg->usb_phy); | |
d860852e PK |
1411 | } |
1412 | msm_otg_notify_charger(motg, 0); | |
1413 | motg->chg_state = USB_CHG_STATE_UNDEFINED; | |
1414 | motg->chg_type = USB_INVALID_CHARGER; | |
e0c201f3 | 1415 | } |
508ccea1 | 1416 | |
e47d9254 | 1417 | if (otg->state == OTG_STATE_B_IDLE) |
19c1eac2 | 1418 | pm_runtime_put_sync(otg->usb_phy->dev); |
e0c201f3 PK |
1419 | break; |
1420 | case OTG_STATE_B_PERIPHERAL: | |
19c1eac2 | 1421 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n"); |
e0c201f3 PK |
1422 | if (!test_bit(B_SESS_VLD, &motg->inputs) || |
1423 | !test_bit(ID, &motg->inputs)) { | |
d860852e | 1424 | msm_otg_notify_charger(motg, 0); |
19c1eac2 | 1425 | msm_otg_start_peripheral(otg->usb_phy, 0); |
d860852e PK |
1426 | motg->chg_state = USB_CHG_STATE_UNDEFINED; |
1427 | motg->chg_type = USB_INVALID_CHARGER; | |
e47d9254 | 1428 | otg->state = OTG_STATE_B_IDLE; |
19c1eac2 | 1429 | msm_otg_reset(otg->usb_phy); |
e0c201f3 PK |
1430 | schedule_work(w); |
1431 | } | |
1432 | break; | |
1433 | case OTG_STATE_A_HOST: | |
19c1eac2 | 1434 | dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n"); |
e0c201f3 | 1435 | if (test_bit(ID, &motg->inputs)) { |
19c1eac2 | 1436 | msm_otg_start_host(otg->usb_phy, 0); |
e47d9254 | 1437 | otg->state = OTG_STATE_B_IDLE; |
19c1eac2 | 1438 | msm_otg_reset(otg->usb_phy); |
e0c201f3 PK |
1439 | schedule_work(w); |
1440 | } | |
1441 | break; | |
1442 | default: | |
1443 | break; | |
1444 | } | |
1445 | } | |
1446 | ||
1447 | static irqreturn_t msm_otg_irq(int irq, void *data) | |
1448 | { | |
1449 | struct msm_otg *motg = data; | |
1d4c9293 | 1450 | struct usb_phy *phy = &motg->phy; |
e0c201f3 PK |
1451 | u32 otgsc = 0; |
1452 | ||
87c0104a PK |
1453 | if (atomic_read(&motg->in_lpm)) { |
1454 | disable_irq_nosync(irq); | |
1455 | motg->async_int = 1; | |
1d4c9293 | 1456 | pm_runtime_get(phy->dev); |
87c0104a PK |
1457 | return IRQ_HANDLED; |
1458 | } | |
1459 | ||
e0c201f3 PK |
1460 | otgsc = readl(USB_OTGSC); |
1461 | if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS))) | |
1462 | return IRQ_NONE; | |
1463 | ||
1464 | if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) { | |
1465 | if (otgsc & OTGSC_ID) | |
1466 | set_bit(ID, &motg->inputs); | |
1467 | else | |
1468 | clear_bit(ID, &motg->inputs); | |
1d4c9293 HK |
1469 | dev_dbg(phy->dev, "ID set/clear\n"); |
1470 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1471 | } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) { |
1472 | if (otgsc & OTGSC_BSV) | |
1473 | set_bit(B_SESS_VLD, &motg->inputs); | |
1474 | else | |
1475 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1d4c9293 HK |
1476 | dev_dbg(phy->dev, "BSV set/clear\n"); |
1477 | pm_runtime_get_noresume(phy->dev); | |
e0c201f3 PK |
1478 | } |
1479 | ||
1480 | writel(otgsc, USB_OTGSC); | |
1481 | schedule_work(&motg->sm_work); | |
1482 | return IRQ_HANDLED; | |
1483 | } | |
1484 | ||
1485 | static int msm_otg_mode_show(struct seq_file *s, void *unused) | |
1486 | { | |
1487 | struct msm_otg *motg = s->private; | |
1d4c9293 | 1488 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1489 | |
e47d9254 | 1490 | switch (otg->state) { |
e0c201f3 | 1491 | case OTG_STATE_A_HOST: |
3aca0fa9 | 1492 | seq_puts(s, "host\n"); |
e0c201f3 PK |
1493 | break; |
1494 | case OTG_STATE_B_PERIPHERAL: | |
3aca0fa9 | 1495 | seq_puts(s, "peripheral\n"); |
e0c201f3 PK |
1496 | break; |
1497 | default: | |
3aca0fa9 | 1498 | seq_puts(s, "none\n"); |
e0c201f3 PK |
1499 | break; |
1500 | } | |
1501 | ||
1502 | return 0; | |
1503 | } | |
1504 | ||
1505 | static int msm_otg_mode_open(struct inode *inode, struct file *file) | |
1506 | { | |
1507 | return single_open(file, msm_otg_mode_show, inode->i_private); | |
1508 | } | |
1509 | ||
1510 | static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf, | |
1511 | size_t count, loff_t *ppos) | |
1512 | { | |
e2904ee4 PK |
1513 | struct seq_file *s = file->private_data; |
1514 | struct msm_otg *motg = s->private; | |
e0c201f3 | 1515 | char buf[16]; |
1d4c9293 | 1516 | struct usb_otg *otg = motg->phy.otg; |
e0c201f3 | 1517 | int status = count; |
971232cf | 1518 | enum usb_dr_mode req_mode; |
e0c201f3 PK |
1519 | |
1520 | memset(buf, 0x00, sizeof(buf)); | |
1521 | ||
1522 | if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) { | |
1523 | status = -EFAULT; | |
1524 | goto out; | |
1525 | } | |
1526 | ||
1527 | if (!strncmp(buf, "host", 4)) { | |
971232cf | 1528 | req_mode = USB_DR_MODE_HOST; |
e0c201f3 | 1529 | } else if (!strncmp(buf, "peripheral", 10)) { |
971232cf | 1530 | req_mode = USB_DR_MODE_PERIPHERAL; |
e0c201f3 | 1531 | } else if (!strncmp(buf, "none", 4)) { |
971232cf | 1532 | req_mode = USB_DR_MODE_UNKNOWN; |
e0c201f3 PK |
1533 | } else { |
1534 | status = -EINVAL; | |
1535 | goto out; | |
1536 | } | |
1537 | ||
1538 | switch (req_mode) { | |
971232cf | 1539 | case USB_DR_MODE_UNKNOWN: |
e47d9254 | 1540 | switch (otg->state) { |
e0c201f3 PK |
1541 | case OTG_STATE_A_HOST: |
1542 | case OTG_STATE_B_PERIPHERAL: | |
1543 | set_bit(ID, &motg->inputs); | |
1544 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1545 | break; | |
1546 | default: | |
1547 | goto out; | |
1548 | } | |
1549 | break; | |
971232cf | 1550 | case USB_DR_MODE_PERIPHERAL: |
e47d9254 | 1551 | switch (otg->state) { |
e0c201f3 PK |
1552 | case OTG_STATE_B_IDLE: |
1553 | case OTG_STATE_A_HOST: | |
1554 | set_bit(ID, &motg->inputs); | |
1555 | set_bit(B_SESS_VLD, &motg->inputs); | |
1556 | break; | |
1557 | default: | |
1558 | goto out; | |
1559 | } | |
1560 | break; | |
971232cf | 1561 | case USB_DR_MODE_HOST: |
e47d9254 | 1562 | switch (otg->state) { |
e0c201f3 PK |
1563 | case OTG_STATE_B_IDLE: |
1564 | case OTG_STATE_B_PERIPHERAL: | |
1565 | clear_bit(ID, &motg->inputs); | |
1566 | break; | |
1567 | default: | |
1568 | goto out; | |
1569 | } | |
1570 | break; | |
1571 | default: | |
1572 | goto out; | |
1573 | } | |
1574 | ||
19c1eac2 | 1575 | pm_runtime_get_sync(otg->usb_phy->dev); |
e0c201f3 PK |
1576 | schedule_work(&motg->sm_work); |
1577 | out: | |
1578 | return status; | |
1579 | } | |
1580 | ||
8f90afd9 | 1581 | static const struct file_operations msm_otg_mode_fops = { |
e0c201f3 PK |
1582 | .open = msm_otg_mode_open, |
1583 | .read = seq_read, | |
1584 | .write = msm_otg_mode_write, | |
1585 | .llseek = seq_lseek, | |
1586 | .release = single_release, | |
1587 | }; | |
1588 | ||
1589 | static struct dentry *msm_otg_dbg_root; | |
1590 | static struct dentry *msm_otg_dbg_mode; | |
1591 | ||
1592 | static int msm_otg_debugfs_init(struct msm_otg *motg) | |
1593 | { | |
1594 | msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL); | |
1595 | ||
1596 | if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root)) | |
1597 | return -ENODEV; | |
1598 | ||
1599 | msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR, | |
1600 | msm_otg_dbg_root, motg, &msm_otg_mode_fops); | |
1601 | if (!msm_otg_dbg_mode) { | |
1602 | debugfs_remove(msm_otg_dbg_root); | |
1603 | msm_otg_dbg_root = NULL; | |
1604 | return -ENODEV; | |
1605 | } | |
1606 | ||
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | static void msm_otg_debugfs_cleanup(void) | |
1611 | { | |
1612 | debugfs_remove(msm_otg_dbg_mode); | |
1613 | debugfs_remove(msm_otg_dbg_root); | |
1614 | } | |
1615 | ||
492240b0 | 1616 | static const struct of_device_id msm_otg_dt_match[] = { |
8364f9af II |
1617 | { |
1618 | .compatible = "qcom,usb-otg-ci", | |
1619 | .data = (void *) CI_45NM_INTEGRATED_PHY | |
1620 | }, | |
1621 | { | |
1622 | .compatible = "qcom,usb-otg-snps", | |
1623 | .data = (void *) SNPS_28NM_INTEGRATED_PHY | |
1624 | }, | |
1625 | { } | |
1626 | }; | |
1627 | MODULE_DEVICE_TABLE(of, msm_otg_dt_match); | |
1628 | ||
591fc116 II |
1629 | static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event, |
1630 | void *ptr) | |
1631 | { | |
1632 | struct msm_usb_cable *vbus = container_of(nb, struct msm_usb_cable, nb); | |
1633 | struct msm_otg *motg = container_of(vbus, struct msm_otg, vbus); | |
1634 | ||
1635 | if (event) | |
1636 | set_bit(B_SESS_VLD, &motg->inputs); | |
1637 | else | |
1638 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1639 | ||
6f98f545 II |
1640 | if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1641 | /* Switch D+/D- lines to Device connector */ | |
1642 | gpiod_set_value_cansleep(motg->switch_gpio, 0); | |
1643 | } else { | |
1644 | /* Switch D+/D- lines to Hub */ | |
1645 | gpiod_set_value_cansleep(motg->switch_gpio, 1); | |
1646 | } | |
1647 | ||
591fc116 II |
1648 | schedule_work(&motg->sm_work); |
1649 | ||
1650 | return NOTIFY_DONE; | |
1651 | } | |
1652 | ||
1653 | static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event, | |
1654 | void *ptr) | |
1655 | { | |
1656 | struct msm_usb_cable *id = container_of(nb, struct msm_usb_cable, nb); | |
1657 | struct msm_otg *motg = container_of(id, struct msm_otg, id); | |
1658 | ||
1659 | if (event) | |
1660 | clear_bit(ID, &motg->inputs); | |
1661 | else | |
1662 | set_bit(ID, &motg->inputs); | |
1663 | ||
1664 | schedule_work(&motg->sm_work); | |
1665 | ||
1666 | return NOTIFY_DONE; | |
1667 | } | |
1668 | ||
8364f9af II |
1669 | static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) |
1670 | { | |
1671 | struct msm_otg_platform_data *pdata; | |
591fc116 | 1672 | struct extcon_dev *ext_id, *ext_vbus; |
8364f9af II |
1673 | struct device_node *node = pdev->dev.of_node; |
1674 | struct property *prop; | |
1675 | int len, ret, words; | |
01799b62 | 1676 | u32 val, tmp[3]; |
8364f9af II |
1677 | |
1678 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1679 | if (!pdata) | |
1680 | return -ENOMEM; | |
1681 | ||
1682 | motg->pdata = pdata; | |
1683 | ||
928c75fb LC |
1684 | pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev); |
1685 | if (!pdata->phy_type) | |
1686 | return 1; | |
8364f9af | 1687 | |
a2734543 II |
1688 | motg->link_rst = devm_reset_control_get(&pdev->dev, "link"); |
1689 | if (IS_ERR(motg->link_rst)) | |
1690 | return PTR_ERR(motg->link_rst); | |
1691 | ||
1692 | motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy"); | |
1693 | if (IS_ERR(motg->phy_rst)) | |
e44f1f4c | 1694 | motg->phy_rst = NULL; |
a2734543 | 1695 | |
06e7114f | 1696 | pdata->mode = usb_get_dr_mode(&pdev->dev); |
8364f9af II |
1697 | if (pdata->mode == USB_DR_MODE_UNKNOWN) |
1698 | pdata->mode = USB_DR_MODE_OTG; | |
1699 | ||
1700 | pdata->otg_control = OTG_PHY_CONTROL; | |
1701 | if (!of_property_read_u32(node, "qcom,otg-control", &val)) | |
1702 | if (val == OTG_PMIC_CONTROL) | |
1703 | pdata->otg_control = val; | |
1704 | ||
cfa3ff5d II |
1705 | if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2) |
1706 | motg->phy_number = val; | |
1707 | ||
01799b62 II |
1708 | motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL; |
1709 | motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN; | |
1710 | motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX; | |
1711 | ||
1712 | if (of_get_property(node, "qcom,vdd-levels", &len) && | |
1713 | len == sizeof(tmp)) { | |
1714 | of_property_read_u32_array(node, "qcom,vdd-levels", | |
1715 | tmp, len / sizeof(*tmp)); | |
1716 | motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE]; | |
1717 | motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN]; | |
1718 | motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; | |
1719 | } | |
1720 | ||
44e42ae3 II |
1721 | motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup"); |
1722 | ||
6f98f545 II |
1723 | motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch", |
1724 | GPIOD_OUT_LOW); | |
1725 | if (IS_ERR(motg->switch_gpio)) | |
1726 | return PTR_ERR(motg->switch_gpio); | |
1727 | ||
591fc116 II |
1728 | ext_id = ERR_PTR(-ENODEV); |
1729 | ext_vbus = ERR_PTR(-ENODEV); | |
1730 | if (of_property_read_bool(node, "extcon")) { | |
1731 | ||
1732 | /* Each one of them is not mandatory */ | |
1733 | ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0); | |
1734 | if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) | |
1735 | return PTR_ERR(ext_vbus); | |
1736 | ||
1737 | ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1); | |
1738 | if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) | |
1739 | return PTR_ERR(ext_id); | |
1740 | } | |
1741 | ||
1742 | if (!IS_ERR(ext_vbus)) { | |
83b7b67c | 1743 | motg->vbus.extcon = ext_vbus; |
591fc116 | 1744 | motg->vbus.nb.notifier_call = msm_otg_vbus_notifier; |
83b7b67c CC |
1745 | ret = extcon_register_notifier(ext_vbus, EXTCON_USB, |
1746 | &motg->vbus.nb); | |
591fc116 II |
1747 | if (ret < 0) { |
1748 | dev_err(&pdev->dev, "register VBUS notifier failed\n"); | |
1749 | return ret; | |
1750 | } | |
1751 | ||
83b7b67c | 1752 | ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB); |
591fc116 II |
1753 | if (ret) |
1754 | set_bit(B_SESS_VLD, &motg->inputs); | |
1755 | else | |
1756 | clear_bit(B_SESS_VLD, &motg->inputs); | |
1757 | } | |
1758 | ||
1759 | if (!IS_ERR(ext_id)) { | |
83b7b67c | 1760 | motg->id.extcon = ext_id; |
591fc116 | 1761 | motg->id.nb.notifier_call = msm_otg_id_notifier; |
83b7b67c CC |
1762 | ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST, |
1763 | &motg->id.nb); | |
591fc116 II |
1764 | if (ret < 0) { |
1765 | dev_err(&pdev->dev, "register ID notifier failed\n"); | |
a38a08df SK |
1766 | extcon_unregister_notifier(motg->vbus.extcon, |
1767 | EXTCON_USB, &motg->vbus.nb); | |
591fc116 II |
1768 | return ret; |
1769 | } | |
1770 | ||
83b7b67c | 1771 | ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST); |
591fc116 II |
1772 | if (ret) |
1773 | clear_bit(ID, &motg->inputs); | |
1774 | else | |
1775 | set_bit(ID, &motg->inputs); | |
1776 | } | |
1777 | ||
8364f9af II |
1778 | prop = of_find_property(node, "qcom,phy-init-sequence", &len); |
1779 | if (!prop || !len) | |
1780 | return 0; | |
1781 | ||
1782 | words = len / sizeof(u32); | |
1783 | ||
1784 | if (words >= ULPI_EXT_VENDOR_SPECIFIC) { | |
1785 | dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); | |
1786 | return 0; | |
1787 | } | |
1788 | ||
1789 | pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); | |
9da22206 | 1790 | if (!pdata->phy_init_seq) |
8364f9af | 1791 | return 0; |
8364f9af II |
1792 | |
1793 | ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", | |
1794 | pdata->phy_init_seq, words); | |
1795 | if (!ret) | |
1796 | pdata->phy_init_sz = words; | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | ||
6f98f545 II |
1801 | static int msm_otg_reboot_notify(struct notifier_block *this, |
1802 | unsigned long code, void *unused) | |
1803 | { | |
1804 | struct msm_otg *motg = container_of(this, struct msm_otg, reboot); | |
1805 | ||
1806 | /* | |
1807 | * Ensure that D+/D- lines are routed to uB connector, so | |
1808 | * we could load bootloader/kernel at next reboot | |
1809 | */ | |
1810 | gpiod_set_value_cansleep(motg->switch_gpio, 0); | |
1811 | return NOTIFY_DONE; | |
1812 | } | |
1813 | ||
06a6ec44 | 1814 | static int msm_otg_probe(struct platform_device *pdev) |
e0c201f3 | 1815 | { |
6b99c68e | 1816 | struct regulator_bulk_data regs[3]; |
e0c201f3 | 1817 | int ret = 0; |
8364f9af II |
1818 | struct device_node *np = pdev->dev.of_node; |
1819 | struct msm_otg_platform_data *pdata; | |
e0c201f3 PK |
1820 | struct resource *res; |
1821 | struct msm_otg *motg; | |
1d4c9293 | 1822 | struct usb_phy *phy; |
30bf8667 | 1823 | void __iomem *phy_select; |
e0c201f3 | 1824 | |
6b99c68e | 1825 | motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL); |
9da22206 | 1826 | if (!motg) |
e0c201f3 | 1827 | return -ENOMEM; |
e0c201f3 | 1828 | |
6b99c68e II |
1829 | motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg), |
1830 | GFP_KERNEL); | |
9da22206 | 1831 | if (!motg->phy.otg) |
6b99c68e | 1832 | return -ENOMEM; |
1d4c9293 | 1833 | |
1d4c9293 HK |
1834 | phy = &motg->phy; |
1835 | phy->dev = &pdev->dev; | |
e0c201f3 | 1836 | |
8364f9af | 1837 | motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk"); |
e0c201f3 PK |
1838 | if (IS_ERR(motg->clk)) { |
1839 | dev_err(&pdev->dev, "failed to get usb_hs_clk\n"); | |
6b99c68e | 1840 | return PTR_ERR(motg->clk); |
e0c201f3 | 1841 | } |
0f73cac8 A |
1842 | |
1843 | /* | |
1844 | * If USB Core is running its protocol engine based on CORE CLK, | |
1845 | * CORE CLK must be running at >55Mhz for correct HSUSB | |
1846 | * operation and USB core cannot tolerate frequency changes on | |
ff0e4a68 | 1847 | * CORE CLK. |
0f73cac8 | 1848 | */ |
8364f9af | 1849 | motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk"); |
e0c201f3 PK |
1850 | if (IS_ERR(motg->pclk)) { |
1851 | dev_err(&pdev->dev, "failed to get usb_hs_pclk\n"); | |
6b99c68e | 1852 | return PTR_ERR(motg->pclk); |
e0c201f3 PK |
1853 | } |
1854 | ||
1855 | /* | |
1856 | * USB core clock is not present on all MSM chips. This | |
1857 | * clock is introduced to remove the dependency on AXI | |
1858 | * bus frequency. | |
1859 | */ | |
8364f9af II |
1860 | motg->core_clk = devm_clk_get(&pdev->dev, |
1861 | np ? "alt_core" : "usb_hs_core_clk"); | |
e0c201f3 PK |
1862 | |
1863 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2ea7b148 DC |
1864 | if (!res) |
1865 | return -EINVAL; | |
1866 | motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | |
1867 | if (!motg->regs) | |
1868 | return -ENOMEM; | |
e0c201f3 | 1869 | |
a38a08df SK |
1870 | pdata = dev_get_platdata(&pdev->dev); |
1871 | if (!pdata) { | |
1872 | if (!np) | |
1873 | return -ENXIO; | |
1874 | ret = msm_otg_read_dt(pdev, motg); | |
1875 | if (ret) | |
1876 | return ret; | |
1877 | } | |
1878 | ||
30bf8667 TB |
1879 | /* |
1880 | * NOTE: The PHYs can be multiplexed between the chipidea controller | |
1881 | * and the dwc3 controller, using a single bit. It is important that | |
1882 | * the dwc3 driver does not set this bit in an incompatible way. | |
1883 | */ | |
1884 | if (motg->phy_number) { | |
1885 | phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4); | |
a38a08df SK |
1886 | if (!phy_select) { |
1887 | ret = -ENOMEM; | |
1888 | goto unregister_extcon; | |
1889 | } | |
30bf8667 | 1890 | /* Enable second PHY with the OTG port */ |
24597490 | 1891 | writel(0x1, phy_select); |
30bf8667 TB |
1892 | } |
1893 | ||
e0c201f3 PK |
1894 | dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs); |
1895 | ||
1896 | motg->irq = platform_get_irq(pdev, 0); | |
f60c114a | 1897 | if (motg->irq < 0) { |
e0c201f3 | 1898 | dev_err(&pdev->dev, "platform_get_irq failed\n"); |
a38a08df SK |
1899 | ret = motg->irq; |
1900 | goto unregister_extcon; | |
6b99c68e II |
1901 | } |
1902 | ||
f5ef2372 II |
1903 | regs[0].supply = "vddcx"; |
1904 | regs[1].supply = "v3p3"; | |
1905 | regs[2].supply = "v1p8"; | |
6b99c68e II |
1906 | |
1907 | ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs); | |
1908 | if (ret) | |
a38a08df | 1909 | goto unregister_extcon; |
6b99c68e II |
1910 | |
1911 | motg->vddcx = regs[0].consumer; | |
1912 | motg->v3p3 = regs[1].consumer; | |
1913 | motg->v1p8 = regs[2].consumer; | |
1914 | ||
1915 | clk_set_rate(motg->clk, 60000000); | |
e0c201f3 | 1916 | |
b99a8f62 SB |
1917 | clk_prepare_enable(motg->clk); |
1918 | clk_prepare_enable(motg->pclk); | |
11aa5c47 | 1919 | |
6b99c68e II |
1920 | if (!IS_ERR(motg->core_clk)) |
1921 | clk_prepare_enable(motg->core_clk); | |
1922 | ||
11aa5c47 A |
1923 | ret = msm_hsusb_init_vddcx(motg, 1); |
1924 | if (ret) { | |
1925 | dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); | |
6b99c68e | 1926 | goto disable_clks; |
11aa5c47 A |
1927 | } |
1928 | ||
1929 | ret = msm_hsusb_ldo_init(motg, 1); | |
1930 | if (ret) { | |
1931 | dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); | |
6b99c68e | 1932 | goto disable_vddcx; |
11aa5c47 | 1933 | } |
37cfdaf7 | 1934 | ret = msm_hsusb_ldo_set_mode(motg, 1); |
11aa5c47 A |
1935 | if (ret) { |
1936 | dev_err(&pdev->dev, "hsusb vreg enable failed\n"); | |
6b99c68e | 1937 | goto disable_ldo; |
11aa5c47 A |
1938 | } |
1939 | ||
e0c201f3 PK |
1940 | writel(0, USB_USBINTR); |
1941 | writel(0, USB_OTGSC); | |
1942 | ||
1943 | INIT_WORK(&motg->sm_work, msm_otg_sm_work); | |
d860852e | 1944 | INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work); |
6b99c68e | 1945 | ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED, |
e0c201f3 PK |
1946 | "msm_otg", motg); |
1947 | if (ret) { | |
1948 | dev_err(&pdev->dev, "request irq failed\n"); | |
6b99c68e | 1949 | goto disable_ldo; |
e0c201f3 PK |
1950 | } |
1951 | ||
d69c6f5d | 1952 | phy->init = msm_phy_init; |
1d4c9293 | 1953 | phy->set_power = msm_otg_set_power; |
349907c2 | 1954 | phy->notify_disconnect = msm_phy_notify_disconnect; |
e695abb3 | 1955 | phy->type = USB_PHY_TYPE_USB2; |
1d4c9293 HK |
1956 | |
1957 | phy->io_ops = &msm_otg_io_ops; | |
e0c201f3 | 1958 | |
19c1eac2 | 1959 | phy->otg->usb_phy = &motg->phy; |
1d4c9293 HK |
1960 | phy->otg->set_host = msm_otg_set_host; |
1961 | phy->otg->set_peripheral = msm_otg_set_peripheral; | |
e0c201f3 | 1962 | |
d69c6f5d II |
1963 | msm_usb_reset(phy); |
1964 | ||
e695abb3 | 1965 | ret = usb_add_phy_dev(&motg->phy); |
e0c201f3 | 1966 | if (ret) { |
721002ec | 1967 | dev_err(&pdev->dev, "usb_add_phy failed\n"); |
6b99c68e | 1968 | goto disable_ldo; |
e0c201f3 PK |
1969 | } |
1970 | ||
1971 | platform_set_drvdata(pdev, motg); | |
1972 | device_init_wakeup(&pdev->dev, 1); | |
1973 | ||
971232cf | 1974 | if (motg->pdata->mode == USB_DR_MODE_OTG && |
8364f9af | 1975 | motg->pdata->otg_control == OTG_USER_CONTROL) { |
e0c201f3 PK |
1976 | ret = msm_otg_debugfs_init(motg); |
1977 | if (ret) | |
3aca0fa9 | 1978 | dev_dbg(&pdev->dev, "Can not create mode change file\n"); |
e0c201f3 PK |
1979 | } |
1980 | ||
6f98f545 II |
1981 | if (test_bit(B_SESS_VLD, &motg->inputs)) { |
1982 | /* Switch D+/D- lines to Device connector */ | |
1983 | gpiod_set_value_cansleep(motg->switch_gpio, 0); | |
1984 | } else { | |
1985 | /* Switch D+/D- lines to Hub */ | |
1986 | gpiod_set_value_cansleep(motg->switch_gpio, 1); | |
1987 | } | |
1988 | ||
1989 | motg->reboot.notifier_call = msm_otg_reboot_notify; | |
1990 | register_reboot_notifier(&motg->reboot); | |
1991 | ||
87c0104a PK |
1992 | pm_runtime_set_active(&pdev->dev); |
1993 | pm_runtime_enable(&pdev->dev); | |
e0c201f3 | 1994 | |
87c0104a | 1995 | return 0; |
6b99c68e II |
1996 | |
1997 | disable_ldo: | |
1998 | msm_hsusb_ldo_init(motg, 0); | |
1999 | disable_vddcx: | |
2000 | msm_hsusb_init_vddcx(motg, 0); | |
e0c201f3 | 2001 | disable_clks: |
b99a8f62 SB |
2002 | clk_disable_unprepare(motg->pclk); |
2003 | clk_disable_unprepare(motg->clk); | |
6b99c68e II |
2004 | if (!IS_ERR(motg->core_clk)) |
2005 | clk_disable_unprepare(motg->core_clk); | |
a38a08df SK |
2006 | unregister_extcon: |
2007 | extcon_unregister_notifier(motg->id.extcon, | |
2008 | EXTCON_USB_HOST, &motg->id.nb); | |
2009 | extcon_unregister_notifier(motg->vbus.extcon, | |
2010 | EXTCON_USB, &motg->vbus.nb); | |
2011 | ||
e0c201f3 PK |
2012 | return ret; |
2013 | } | |
2014 | ||
fb4e98ab | 2015 | static int msm_otg_remove(struct platform_device *pdev) |
e0c201f3 PK |
2016 | { |
2017 | struct msm_otg *motg = platform_get_drvdata(pdev); | |
1d4c9293 | 2018 | struct usb_phy *phy = &motg->phy; |
87c0104a | 2019 | int cnt = 0; |
e0c201f3 | 2020 | |
1d4c9293 | 2021 | if (phy->otg->host || phy->otg->gadget) |
e0c201f3 PK |
2022 | return -EBUSY; |
2023 | ||
6f98f545 II |
2024 | unregister_reboot_notifier(&motg->reboot); |
2025 | ||
2026 | /* | |
2027 | * Ensure that D+/D- lines are routed to uB connector, so | |
2028 | * we could load bootloader/kernel at next reboot | |
2029 | */ | |
2030 | gpiod_set_value_cansleep(motg->switch_gpio, 0); | |
2031 | ||
83b7b67c CC |
2032 | extcon_unregister_notifier(motg->id.extcon, EXTCON_USB_HOST, &motg->id.nb); |
2033 | extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb); | |
591fc116 | 2034 | |
e0c201f3 | 2035 | msm_otg_debugfs_cleanup(); |
d860852e | 2036 | cancel_delayed_work_sync(&motg->chg_work); |
e0c201f3 | 2037 | cancel_work_sync(&motg->sm_work); |
87c0104a | 2038 | |
7018773a | 2039 | pm_runtime_resume(&pdev->dev); |
87c0104a | 2040 | |
e0c201f3 | 2041 | device_init_wakeup(&pdev->dev, 0); |
87c0104a | 2042 | pm_runtime_disable(&pdev->dev); |
e0c201f3 | 2043 | |
662dca54 | 2044 | usb_remove_phy(phy); |
6b99c68e | 2045 | disable_irq(motg->irq); |
e0c201f3 | 2046 | |
87c0104a PK |
2047 | /* |
2048 | * Put PHY in low power mode. | |
2049 | */ | |
1d4c9293 HK |
2050 | ulpi_read(phy, 0x14); |
2051 | ulpi_write(phy, 0x08, 0x09); | |
87c0104a PK |
2052 | |
2053 | writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC); | |
2054 | while (cnt < PHY_SUSPEND_TIMEOUT_USEC) { | |
2055 | if (readl(USB_PORTSC) & PORTSC_PHCD) | |
2056 | break; | |
2057 | udelay(1); | |
2058 | cnt++; | |
2059 | } | |
2060 | if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) | |
1d4c9293 | 2061 | dev_err(phy->dev, "Unable to suspend PHY\n"); |
87c0104a | 2062 | |
b99a8f62 SB |
2063 | clk_disable_unprepare(motg->pclk); |
2064 | clk_disable_unprepare(motg->clk); | |
6b99c68e | 2065 | if (!IS_ERR(motg->core_clk)) |
b99a8f62 | 2066 | clk_disable_unprepare(motg->core_clk); |
11aa5c47 | 2067 | msm_hsusb_ldo_init(motg, 0); |
e0c201f3 | 2068 | |
87c0104a | 2069 | pm_runtime_set_suspended(&pdev->dev); |
e0c201f3 | 2070 | |
e0c201f3 PK |
2071 | return 0; |
2072 | } | |
2073 | ||
ceb6c9c8 | 2074 | #ifdef CONFIG_PM |
87c0104a PK |
2075 | static int msm_otg_runtime_idle(struct device *dev) |
2076 | { | |
2077 | struct msm_otg *motg = dev_get_drvdata(dev); | |
1d4c9293 | 2078 | struct usb_otg *otg = motg->phy.otg; |
87c0104a PK |
2079 | |
2080 | dev_dbg(dev, "OTG runtime idle\n"); | |
2081 | ||
2082 | /* | |
2083 | * It is observed some times that a spurious interrupt | |
2084 | * comes when PHY is put into LPM immediately after PHY reset. | |
2085 | * This 1 sec delay also prevents entering into LPM immediately | |
2086 | * after asynchronous interrupt. | |
2087 | */ | |
e47d9254 | 2088 | if (otg->state != OTG_STATE_UNDEFINED) |
87c0104a PK |
2089 | pm_schedule_suspend(dev, 1000); |
2090 | ||
2091 | return -EAGAIN; | |
2092 | } | |
2093 | ||
2094 | static int msm_otg_runtime_suspend(struct device *dev) | |
2095 | { | |
2096 | struct msm_otg *motg = dev_get_drvdata(dev); | |
2097 | ||
2098 | dev_dbg(dev, "OTG runtime suspend\n"); | |
2099 | return msm_otg_suspend(motg); | |
2100 | } | |
2101 | ||
2102 | static int msm_otg_runtime_resume(struct device *dev) | |
2103 | { | |
2104 | struct msm_otg *motg = dev_get_drvdata(dev); | |
2105 | ||
2106 | dev_dbg(dev, "OTG runtime resume\n"); | |
2107 | return msm_otg_resume(motg); | |
2108 | } | |
87c0104a PK |
2109 | #endif |
2110 | ||
7018773a | 2111 | #ifdef CONFIG_PM_SLEEP |
87c0104a PK |
2112 | static int msm_otg_pm_suspend(struct device *dev) |
2113 | { | |
2114 | struct msm_otg *motg = dev_get_drvdata(dev); | |
2115 | ||
2116 | dev_dbg(dev, "OTG PM suspend\n"); | |
2117 | return msm_otg_suspend(motg); | |
2118 | } | |
2119 | ||
2120 | static int msm_otg_pm_resume(struct device *dev) | |
2121 | { | |
2122 | struct msm_otg *motg = dev_get_drvdata(dev); | |
2123 | int ret; | |
2124 | ||
2125 | dev_dbg(dev, "OTG PM resume\n"); | |
2126 | ||
2127 | ret = msm_otg_resume(motg); | |
2128 | if (ret) | |
2129 | return ret; | |
2130 | ||
2131 | /* | |
2132 | * Runtime PM Documentation recommends bringing the | |
2133 | * device to full powered state upon resume. | |
2134 | */ | |
2135 | pm_runtime_disable(dev); | |
2136 | pm_runtime_set_active(dev); | |
2137 | pm_runtime_enable(dev); | |
2138 | ||
2139 | return 0; | |
2140 | } | |
87c0104a PK |
2141 | #endif |
2142 | ||
2143 | static const struct dev_pm_ops msm_otg_dev_pm_ops = { | |
7018773a PK |
2144 | SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume) |
2145 | SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume, | |
2146 | msm_otg_runtime_idle) | |
87c0104a PK |
2147 | }; |
2148 | ||
e0c201f3 | 2149 | static struct platform_driver msm_otg_driver = { |
06a6ec44 | 2150 | .probe = msm_otg_probe, |
7690417d | 2151 | .remove = msm_otg_remove, |
e0c201f3 PK |
2152 | .driver = { |
2153 | .name = DRIVER_NAME, | |
87c0104a | 2154 | .pm = &msm_otg_dev_pm_ops, |
8364f9af | 2155 | .of_match_table = msm_otg_dt_match, |
e0c201f3 PK |
2156 | }, |
2157 | }; | |
2158 | ||
06a6ec44 | 2159 | module_platform_driver(msm_otg_driver); |
e0c201f3 PK |
2160 | |
2161 | MODULE_LICENSE("GPL v2"); | |
2162 | MODULE_DESCRIPTION("MSM USB transceiver driver"); |