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usbnet: add a mutex around phy register access
[linux-block.git] / drivers / usb / net / asix.c
CommitLineData
2e55cc72
DB		 1/*
2 * ASIX AX8817X based USB 2.0 Ethernet Devices
933a27d3 3 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
2e55cc72 4 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
933a27d3 5 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
2e55cc72
DB		 6 * Copyright (c) 2002-2003 TiVo Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23// #define DEBUG // error path messages, extra info
24// #define VERBOSE // more; success messages
25
2e55cc72
DB		 26#include <linux/module.h>
27#include <linux/kmod.h>
28#include <linux/sched.h>
29#include <linux/init.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/workqueue.h>
34#include <linux/mii.h>
35#include <linux/usb.h>
36#include <linux/crc32.h>
37
38#include "usbnet.h"
39
933a27d3
DH		 40#define DRIVER_VERSION "14-Jun-2006"
41static const char driver_name [] = "asix";
42
2e55cc72
DB		 43/* ASIX AX8817X based USB 2.0 Ethernet Devices */
44
45#define AX_CMD_SET_SW_MII 0x06
46#define AX_CMD_READ_MII_REG 0x07
47#define AX_CMD_WRITE_MII_REG 0x08
48#define AX_CMD_SET_HW_MII 0x0a
49#define AX_CMD_READ_EEPROM 0x0b
50#define AX_CMD_WRITE_EEPROM 0x0c
51#define AX_CMD_WRITE_ENABLE 0x0d
52#define AX_CMD_WRITE_DISABLE 0x0e
933a27d3 53#define AX_CMD_READ_RX_CTL 0x0f
2e55cc72
DB		 54#define AX_CMD_WRITE_RX_CTL 0x10
55#define AX_CMD_READ_IPG012 0x11
56#define AX_CMD_WRITE_IPG0 0x12
57#define AX_CMD_WRITE_IPG1 0x13
933a27d3 58#define AX_CMD_READ_NODE_ID 0x13
2e55cc72
DB		 59#define AX_CMD_WRITE_IPG2 0x14
60#define AX_CMD_WRITE_MULTI_FILTER 0x16
933a27d3 61#define AX88172_CMD_READ_NODE_ID 0x17
2e55cc72
DB		 62#define AX_CMD_READ_PHY_ID 0x19
63#define AX_CMD_READ_MEDIUM_STATUS 0x1a
64#define AX_CMD_WRITE_MEDIUM_MODE 0x1b
65#define AX_CMD_READ_MONITOR_MODE 0x1c
66#define AX_CMD_WRITE_MONITOR_MODE 0x1d
933a27d3 67#define AX_CMD_READ_GPIOS 0x1e
2e55cc72
DB		 68#define AX_CMD_WRITE_GPIOS 0x1f
69#define AX_CMD_SW_RESET 0x20
70#define AX_CMD_SW_PHY_STATUS 0x21
71#define AX_CMD_SW_PHY_SELECT 0x22
2e55cc72
DB		 72
73#define AX_MONITOR_MODE 0x01
74#define AX_MONITOR_LINK 0x02
75#define AX_MONITOR_MAGIC 0x04
76#define AX_MONITOR_HSFS 0x10
77
78/* AX88172 Medium Status Register values */
933a27d3
DH		 79#define AX88172_MEDIUM_FD 0x02
80#define AX88172_MEDIUM_TX 0x04
81#define AX88172_MEDIUM_FC 0x10
82#define AX88172_MEDIUM_DEFAULT \
83 ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
2e55cc72
DB		 84
85#define AX_MCAST_FILTER_SIZE 8
86#define AX_MAX_MCAST 64
87
2e55cc72
DB		 88#define AX_SWRESET_CLEAR 0x00
89#define AX_SWRESET_RR 0x01
90#define AX_SWRESET_RT 0x02
91#define AX_SWRESET_PRTE 0x04
92#define AX_SWRESET_PRL 0x08
93#define AX_SWRESET_BZ 0x10
94#define AX_SWRESET_IPRL 0x20
95#define AX_SWRESET_IPPD 0x40
96
97#define AX88772_IPG0_DEFAULT 0x15
98#define AX88772_IPG1_DEFAULT 0x0c
99#define AX88772_IPG2_DEFAULT 0x12
100
933a27d3
DH		 101/* AX88772 & AX88178 Medium Mode Register */
102#define AX_MEDIUM_PF 0x0080
103#define AX_MEDIUM_JFE 0x0040
104#define AX_MEDIUM_TFC 0x0020
105#define AX_MEDIUM_RFC 0x0010
106#define AX_MEDIUM_ENCK 0x0008
107#define AX_MEDIUM_AC 0x0004
108#define AX_MEDIUM_FD 0x0002
109#define AX_MEDIUM_GM 0x0001
110#define AX_MEDIUM_SM 0x1000
111#define AX_MEDIUM_SBP 0x0800
112#define AX_MEDIUM_PS 0x0200
113#define AX_MEDIUM_RE 0x0100
114
115#define AX88178_MEDIUM_DEFAULT \
116 (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
117 AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
118 AX_MEDIUM_RE )
2e55cc72 119
933a27d3
DH		 120#define AX88772_MEDIUM_DEFAULT \
121 (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
122 AX_MEDIUM_TFC | AX_MEDIUM_PS | \
123 AX_MEDIUM_AC | AX_MEDIUM_RE )
124
125/* AX88772 & AX88178 RX_CTL values */
126#define AX_RX_CTL_SO 0x0080
127#define AX_RX_CTL_AP 0x0020
128#define AX_RX_CTL_AM 0x0010
129#define AX_RX_CTL_AB 0x0008
130#define AX_RX_CTL_SEP 0x0004
131#define AX_RX_CTL_AMALL 0x0002
132#define AX_RX_CTL_PRO 0x0001
133#define AX_RX_CTL_MFB_2048 0x0000
134#define AX_RX_CTL_MFB_4096 0x0100
135#define AX_RX_CTL_MFB_8192 0x0200
136#define AX_RX_CTL_MFB_16384 0x0300
137
138#define AX_DEFAULT_RX_CTL \
139 (AX_RX_CTL_SO | AX_RX_CTL_AB )
140
141/* GPIO 0 .. 2 toggles */
142#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */
143#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */
144#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */
145#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */
146#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
147#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
148#define AX_GPIO_RESERVED 0x40 /* Reserved */
149#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
150
151#define AX_EEPROM_MAGIC 0xdeadbeef
152#define AX88172_EEPROM_LEN 0x40
153#define AX88772_EEPROM_LEN 0xff
154
155#define PHY_MODE_MARVELL 0x0000
156#define MII_MARVELL_LED_CTRL 0x0018
157#define MII_MARVELL_STATUS 0x001b
158#define MII_MARVELL_CTRL 0x0014
159
160#define MARVELL_LED_MANUAL 0x0019
161
162#define MARVELL_STATUS_HWCFG 0x0004
163
164#define MARVELL_CTRL_TXDELAY 0x0002
165#define MARVELL_CTRL_RXDELAY 0x0080
2e55cc72
DB		 166
167/* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
48b1be6a 168struct asix_data {
2e55cc72 169 u8 multi_filter[AX_MCAST_FILTER_SIZE];
933a27d3
DH		 170 u8 phymode;
171 u8 ledmode;
172 u8 eeprom_len;
2e55cc72
DB		 173};
174
175struct ax88172_int_data {
176 u16 res1;
177 u8 link;
178 u16 res2;
179 u8 status;
180 u16 res3;
181} __attribute__ ((packed));
182
48b1be6a 183static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
2e55cc72
DB		 184 u16 size, void *data)
185{
933a27d3
DH		 186 devdbg(dev,"asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
187 cmd, value, index, size);
2e55cc72
DB		 188 return usb_control_msg(
189 dev->udev,
190 usb_rcvctrlpipe(dev->udev, 0),
191 cmd,
192 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
193 value,
194 index,
195 data,
196 size,
197 USB_CTRL_GET_TIMEOUT);
198}
199
48b1be6a 200static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
2e55cc72
DB		 201 u16 size, void *data)
202{
933a27d3
DH		 203 devdbg(dev,"asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
204 cmd, value, index, size);
2e55cc72
DB		 205 return usb_control_msg(
206 dev->udev,
207 usb_sndctrlpipe(dev->udev, 0),
208 cmd,
209 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
210 value,
211 index,
212 data,
213 size,
214 USB_CTRL_SET_TIMEOUT);
215}
216
7d12e780 217static void asix_async_cmd_callback(struct urb *urb)
2e55cc72
DB		 218{
219 struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context;
220
221 if (urb->status < 0)
48b1be6a 222 printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d",
2e55cc72
DB		 223 urb->status);
224
225 kfree(req);
226 usb_free_urb(urb);
227}
228
933a27d3
DH		 229static void
230asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index,
231 u16 size, void *data)
232{
233 struct usb_ctrlrequest *req;
234 int status;
235 struct urb *urb;
236
237 devdbg(dev,"asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d",
238 cmd, value, index, size);
239 if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) {
240 deverr(dev, "Error allocating URB in write_cmd_async!");
241 return;
242 }
243
244 if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) {
245 deverr(dev, "Failed to allocate memory for control request");
246 usb_free_urb(urb);
247 return;
248 }
249
250 req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
251 req->bRequest = cmd;
252 req->wValue = value;
253 req->wIndex = index;
254 req->wLength = size;
255
256 usb_fill_control_urb(urb, dev->udev,
257 usb_sndctrlpipe(dev->udev, 0),
258 (void *)req, data, size,
259 asix_async_cmd_callback, req);
260
261 if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) {
262 deverr(dev, "Error submitting the control message: status=%d",
263 status);
264 kfree(req);
265 usb_free_urb(urb);
266 }
267}
268
269static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
270{
271 u8 *head;
272 u32 header;
273 char *packet;
274 struct sk_buff *ax_skb;
275 u16 size;
276
277 head = (u8 *) skb->data;
278 memcpy(&header, head, sizeof(header));
279 le32_to_cpus(&header);
280 packet = head + sizeof(header);
281
282 skb_pull(skb, 4);
283
284 while (skb->len > 0) {
285 if ((short)(header & 0x0000ffff) !=
286 ~((short)((header & 0xffff0000) >> 16))) {
287 deverr(dev,"asix_rx_fixup() Bad Header Length");
288 }
289 /* get the packet length */
290 size = (u16) (header & 0x0000ffff);
291
292 if ((skb->len) - ((size + 1) & 0xfffe) == 0)
293 return 2;
294 if (size > ETH_FRAME_LEN) {
295 deverr(dev,"asix_rx_fixup() Bad RX Length %d", size);
296 return 0;
297 }
298 ax_skb = skb_clone(skb, GFP_ATOMIC);
299 if (ax_skb) {
300 ax_skb->len = size;
301 ax_skb->data = packet;
302 ax_skb->tail = packet + size;
303 usbnet_skb_return(dev, ax_skb);
304 } else {
305 return 0;
306 }
307
308 skb_pull(skb, (size + 1) & 0xfffe);
309
310 if (skb->len == 0)
311 break;
312
313 head = (u8 *) skb->data;
314 memcpy(&header, head, sizeof(header));
315 le32_to_cpus(&header);
316 packet = head + sizeof(header);
317 skb_pull(skb, 4);
318 }
319
320 if (skb->len < 0) {
321 deverr(dev,"asix_rx_fixup() Bad SKB Length %d", skb->len);
322 return 0;
323 }
324 return 1;
325}
326
327static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
328 gfp_t flags)
329{
330 int padlen;
331 int headroom = skb_headroom(skb);
332 int tailroom = skb_tailroom(skb);
333 u32 packet_len;
334 u32 padbytes = 0xffff0000;
335
336 padlen = ((skb->len + 4) % 512) ? 0 : 4;
337
338 if ((!skb_cloned(skb))
339 && ((headroom + tailroom) >= (4 + padlen))) {
340 if ((headroom < 4) || (tailroom < padlen)) {
341 skb->data = memmove(skb->head + 4, skb->data, skb->len);
342 skb->tail = skb->data + skb->len;
343 }
344 } else {
345 struct sk_buff *skb2;
346 skb2 = skb_copy_expand(skb, 4, padlen, flags);
347 dev_kfree_skb_any(skb);
348 skb = skb2;
349 if (!skb)
350 return NULL;
351 }
352
353 skb_push(skb, 4);
354 packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4);
355 memcpy(skb->data, &packet_len, sizeof(packet_len));
356
357 if ((skb->len % 512) == 0) {
358 memcpy( skb->tail, &padbytes, sizeof(padbytes));
359 skb_put(skb, sizeof(padbytes));
360 }
361 return skb;
362}
363
364static void asix_status(struct usbnet *dev, struct urb *urb)
365{
366 struct ax88172_int_data *event;
367 int link;
368
369 if (urb->actual_length < 8)
370 return;
371
372 event = urb->transfer_buffer;
373 link = event->link & 0x01;
374 if (netif_carrier_ok(dev->net) != link) {
375 if (link) {
376 netif_carrier_on(dev->net);
377 usbnet_defer_kevent (dev, EVENT_LINK_RESET );
378 } else
379 netif_carrier_off(dev->net);
380 devdbg(dev, "Link Status is: %d", link);
381 }
382}
383
48b1be6a
DH		 384static inline int asix_set_sw_mii(struct usbnet *dev)
385{
386 int ret;
387 ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
388 if (ret < 0)
933a27d3 389 deverr(dev, "Failed to enable software MII access");
48b1be6a
DH		 390 return ret;
391}
392
393static inline int asix_set_hw_mii(struct usbnet *dev)
394{
395 int ret;
396 ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
397 if (ret < 0)
933a27d3 398 deverr(dev, "Failed to enable hardware MII access");
48b1be6a
DH		 399 return ret;
400}
401
933a27d3 402static inline int asix_get_phy_addr(struct usbnet *dev)
48b1be6a
DH		 403{
404 int ret = 0;
405 void *buf;
406
933a27d3
DH		 407 devdbg(dev, "asix_get_phy_addr()");
408
48b1be6a
DH		 409 buf = kmalloc(2, GFP_KERNEL);
410 if (!buf)
411 goto out1;
412
413 if ((ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID,
414 0, 0, 2, buf)) < 2) {
933a27d3 415 deverr(dev, "Error reading PHYID register: %02x", ret);
48b1be6a
DH		 416 goto out2;
417 }
933a27d3 418 devdbg(dev, "asix_get_phy_addr() returning 0x%04x", *((u16 *)buf));
48b1be6a
DH		 419 ret = *((u8 *)buf + 1);
420out2:
421 kfree(buf);
422out1:
423 return ret;
424}
425
426static int asix_sw_reset(struct usbnet *dev, u8 flags)
427{
428 int ret;
429
430 ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
431 if (ret < 0)
933a27d3
DH		 432 deverr(dev,"Failed to send software reset: %02x", ret);
433
434 return ret;
435}
48b1be6a 436
933a27d3
DH		 437static u16 asix_read_rx_ctl(struct usbnet *dev)
438{
439 u16 ret = 0;
440 void *buf;
441
442 buf = kmalloc(2, GFP_KERNEL);
443 if (!buf)
444 goto out1;
445
446 if ((ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL,
447 0, 0, 2, buf)) < 2) {
448 deverr(dev, "Error reading RX_CTL register: %02x", ret);
449 goto out2;
450 }
451 ret = le16_to_cpu(*((u16 *)buf));
452out2:
453 kfree(buf);
454out1:
48b1be6a
DH		 455 return ret;
456}
457
458static int asix_write_rx_ctl(struct usbnet *dev, u16 mode)
459{
460 int ret;
461
933a27d3 462 devdbg(dev,"asix_write_rx_ctl() - mode = 0x%04x", mode);
48b1be6a
DH		 463 ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
464 if (ret < 0)
933a27d3
DH		 465 deverr(dev, "Failed to write RX_CTL mode to 0x%04x: %02x",
466 mode, ret);
48b1be6a
DH		 467
468 return ret;
469}
470
933a27d3 471static u16 asix_read_medium_status(struct usbnet *dev)
2e55cc72 472{
933a27d3
DH		 473 u16 ret = 0;
474 void *buf;
2e55cc72 475
933a27d3
DH		 476 buf = kmalloc(2, GFP_KERNEL);
477 if (!buf)
478 goto out1;
2e55cc72 479
933a27d3
DH		 480 if ((ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS,
481 0, 0, 2, buf)) < 2) {
482 deverr(dev, "Error reading Medium Status register: %02x", ret);
483 goto out2;
2e55cc72 484 }
933a27d3
DH		 485 ret = le16_to_cpu(*((u16 *)buf));
486out2:
487 kfree(buf);
488out1:
489 return ret;
2e55cc72
DB		 490}
491
933a27d3 492static int asix_write_medium_mode(struct usbnet *dev, u16 mode)
2e55cc72 493{
933a27d3 494 int ret;
2e55cc72 495
933a27d3
DH		 496 devdbg(dev,"asix_write_medium_mode() - mode = 0x%04x", mode);
497 ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL);
498 if (ret < 0)
499 deverr(dev, "Failed to write Medium Mode mode to 0x%04x: %02x",
500 mode, ret);
2e55cc72 501
933a27d3
DH		 502 return ret;
503}
2e55cc72 504
933a27d3
DH		 505static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep)
506{
507 int ret;
2e55cc72 508
933a27d3
DH		 509 devdbg(dev,"asix_write_gpio() - value = 0x%04x", value);
510 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
511 if (ret < 0)
512 deverr(dev, "Failed to write GPIO value 0x%04x: %02x",
513 value, ret);
2e55cc72 514
933a27d3
DH		 515 if (sleep)
516 msleep(sleep);
517
518 return ret;
2e55cc72
DB		 519}
520
933a27d3
DH		 521/*
522 * AX88772 & AX88178 have a 16-bit RX_CTL value
523 */
48b1be6a 524static void asix_set_multicast(struct net_device *net)
2e55cc72
DB		 525{
526 struct usbnet *dev = netdev_priv(net);
48b1be6a 527 struct asix_data *data = (struct asix_data *)&dev->data;
933a27d3 528 u16 rx_ctl = AX_DEFAULT_RX_CTL;
2e55cc72
DB		 529
530 if (net->flags & IFF_PROMISC) {
933a27d3 531 rx_ctl |= AX_RX_CTL_PRO;
2e55cc72
DB		 532 } else if (net->flags & IFF_ALLMULTI
533 || net->mc_count > AX_MAX_MCAST) {
933a27d3 534 rx_ctl |= AX_RX_CTL_AMALL;
2e55cc72
DB		 535 } else if (net->mc_count == 0) {
536 /* just broadcast and directed */
537 } else {
538 /* We use the 20 byte dev->data
539 * for our 8 byte filter buffer
540 * to avoid allocating memory that
541 * is tricky to free later */
542 struct dev_mc_list *mc_list = net->mc_list;
543 u32 crc_bits;
544 int i;
545
546 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
547
548 /* Build the multicast hash filter. */
549 for (i = 0; i < net->mc_count; i++) {
550 crc_bits =
551 ether_crc(ETH_ALEN,
552 mc_list->dmi_addr) >> 26;
553 data->multi_filter[crc_bits >> 3] |=
554 1 << (crc_bits & 7);
555 mc_list = mc_list->next;
556 }
557
48b1be6a 558 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
2e55cc72
DB		 559 AX_MCAST_FILTER_SIZE, data->multi_filter);
560
933a27d3 561 rx_ctl |= AX_RX_CTL_AM;
2e55cc72
DB		 562 }
563
48b1be6a 564 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
2e55cc72
DB		 565}
566
48b1be6a 567static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc)
2e55cc72
DB		 568{
569 struct usbnet *dev = netdev_priv(netdev);
570 u16 res;
2e55cc72 571
a9fc6338 572 mutex_lock(&dev->phy_mutex);
48b1be6a
DH		 573 asix_set_sw_mii(dev);
574 asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id,
2e55cc72 575 (__u16)loc, 2, (u16 *)&res);
48b1be6a 576 asix_set_hw_mii(dev);
a9fc6338 577 mutex_unlock(&dev->phy_mutex);
2e55cc72 578
933a27d3 579 devdbg(dev, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x", phy_id, loc, le16_to_cpu(res & 0xffff));
2e55cc72 580
933a27d3 581 return le16_to_cpu(res & 0xffff);
2e55cc72
DB		 582}
583
584static void
48b1be6a 585asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val)
2e55cc72
DB		 586{
587 struct usbnet *dev = netdev_priv(netdev);
933a27d3 588 u16 res = cpu_to_le16(val);
2e55cc72 589
933a27d3 590 devdbg(dev, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x", phy_id, loc, val);
a9fc6338 591 mutex_lock(&dev->phy_mutex);
48b1be6a
DH		 592 asix_set_sw_mii(dev);
593 asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id,
2e55cc72 594 (__u16)loc, 2, (u16 *)&res);
48b1be6a 595 asix_set_hw_mii(dev);
a9fc6338 596 mutex_unlock(&dev->phy_mutex);
2e55cc72
DB		 597}
598
933a27d3
DH		 599/* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
600static u32 asix_get_phyid(struct usbnet *dev)
2e55cc72 601{
933a27d3
DH		 602 int phy_reg;
603 u32 phy_id;
2e55cc72 604
933a27d3
DH		 605 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
606 if (phy_reg < 0)
607 return 0;
2e55cc72 608
933a27d3 609 phy_id = (phy_reg & 0xffff) << 16;
2e55cc72 610
933a27d3
DH		 611 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
612 if (phy_reg < 0)
613 return 0;
614
615 phy_id |= (phy_reg & 0xffff);
616
617 return phy_id;
2e55cc72
DB		 618}
619
620static void
48b1be6a 621asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
2e55cc72
DB		 622{
623 struct usbnet *dev = netdev_priv(net);
624 u8 opt;
625
48b1be6a 626 if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) {
2e55cc72
DB		 627 wolinfo->supported = 0;
628 wolinfo->wolopts = 0;
629 return;
630 }
631 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
632 wolinfo->wolopts = 0;
633 if (opt & AX_MONITOR_MODE) {
634 if (opt & AX_MONITOR_LINK)
635 wolinfo->wolopts |= WAKE_PHY;
636 if (opt & AX_MONITOR_MAGIC)
637 wolinfo->wolopts |= WAKE_MAGIC;
638 }
639}
640
641static int
48b1be6a 642asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
2e55cc72
DB		 643{
644 struct usbnet *dev = netdev_priv(net);
645 u8 opt = 0;
646 u8 buf[1];
647
648 if (wolinfo->wolopts & WAKE_PHY)
649 opt |= AX_MONITOR_LINK;
650 if (wolinfo->wolopts & WAKE_MAGIC)
651 opt |= AX_MONITOR_MAGIC;
652 if (opt != 0)
653 opt |= AX_MONITOR_MODE;
654
48b1be6a 655 if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE,
2e55cc72
DB		 656 opt, 0, 0, &buf) < 0)
657 return -EINVAL;
658
659 return 0;
660}
661
48b1be6a 662static int asix_get_eeprom_len(struct net_device *net)
2e55cc72 663{
933a27d3
DH		 664 struct usbnet *dev = netdev_priv(net);
665 struct asix_data *data = (struct asix_data *)&dev->data;
666
667 return data->eeprom_len;
2e55cc72
DB		 668}
669
48b1be6a 670static int asix_get_eeprom(struct net_device *net,
2e55cc72
DB		 671 struct ethtool_eeprom *eeprom, u8 *data)
672{
673 struct usbnet *dev = netdev_priv(net);
674 u16 *ebuf = (u16 *)data;
675 int i;
676
677 /* Crude hack to ensure that we don't overwrite memory
678 * if an odd length is supplied
679 */
680 if (eeprom->len % 2)
681 return -EINVAL;
682
683 eeprom->magic = AX_EEPROM_MAGIC;
684
685 /* ax8817x returns 2 bytes from eeprom on read */
686 for (i=0; i < eeprom->len / 2; i++) {
48b1be6a 687 if (asix_read_cmd(dev, AX_CMD_READ_EEPROM,
2e55cc72
DB		 688 eeprom->offset + i, 0, 2, &ebuf[i]) < 0)
689 return -EINVAL;
690 }
691 return 0;
692}
693
48b1be6a 694static void asix_get_drvinfo (struct net_device *net,
2e55cc72
DB		 695 struct ethtool_drvinfo *info)
696{
933a27d3
DH		 697 struct usbnet *dev = netdev_priv(net);
698 struct asix_data *data = (struct asix_data *)&dev->data;
699
2e55cc72
DB		 700 /* Inherit standard device info */
701 usbnet_get_drvinfo(net, info);
933a27d3
DH		 702 strncpy (info->driver, driver_name, sizeof info->driver);
703 strncpy (info->version, DRIVER_VERSION, sizeof info->version);
704 info->eedump_len = data->eeprom_len;
2e55cc72
DB		 705}
706
933a27d3
DH		 707static u32 asix_get_link(struct net_device *net)
708{
709 struct usbnet *dev = netdev_priv(net);
710
711 return mii_link_ok(&dev->mii);
712}
713
714static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
715{
716 struct usbnet *dev = netdev_priv(net);
717
718 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
719}
720
721/* We need to override some ethtool_ops so we require our
722 own structure so we don't interfere with other usbnet
723 devices that may be connected at the same time. */
724static struct ethtool_ops ax88172_ethtool_ops = {
725 .get_drvinfo = asix_get_drvinfo,
726 .get_link = asix_get_link,
933a27d3 727 .get_msglevel = usbnet_get_msglevel,
2e55cc72 728 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 729 .get_wol = asix_get_wol,
730 .set_wol = asix_set_wol,
731 .get_eeprom_len = asix_get_eeprom_len,
732 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 733 .get_settings = usbnet_get_settings,
734 .set_settings = usbnet_set_settings,
735 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 736};
737
933a27d3 738static void ax88172_set_multicast(struct net_device *net)
2e55cc72
DB		 739{
740 struct usbnet *dev = netdev_priv(net);
933a27d3
DH		 741 struct asix_data *data = (struct asix_data *)&dev->data;
742 u8 rx_ctl = 0x8c;
2e55cc72 743
933a27d3
DH		 744 if (net->flags & IFF_PROMISC) {
745 rx_ctl |= 0x01;
746 } else if (net->flags & IFF_ALLMULTI
747 || net->mc_count > AX_MAX_MCAST) {
748 rx_ctl |= 0x02;
749 } else if (net->mc_count == 0) {
750 /* just broadcast and directed */
751 } else {
752 /* We use the 20 byte dev->data
753 * for our 8 byte filter buffer
754 * to avoid allocating memory that
755 * is tricky to free later */
756 struct dev_mc_list *mc_list = net->mc_list;
757 u32 crc_bits;
758 int i;
759
760 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
761
762 /* Build the multicast hash filter. */
763 for (i = 0; i < net->mc_count; i++) {
764 crc_bits =
765 ether_crc(ETH_ALEN,
766 mc_list->dmi_addr) >> 26;
767 data->multi_filter[crc_bits >> 3] |=
768 1 << (crc_bits & 7);
769 mc_list = mc_list->next;
770 }
771
772 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
773 AX_MCAST_FILTER_SIZE, data->multi_filter);
774
775 rx_ctl |= 0x10;
776 }
777
778 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
779}
780
781static int ax88172_link_reset(struct usbnet *dev)
782{
783 u8 mode;
784 struct ethtool_cmd ecmd;
785
786 mii_check_media(&dev->mii, 1, 1);
787 mii_ethtool_gset(&dev->mii, &ecmd);
788 mode = AX88172_MEDIUM_DEFAULT;
789
790 if (ecmd.duplex != DUPLEX_FULL)
791 mode |= ~AX88172_MEDIUM_FD;
792
793 devdbg(dev, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
794
795 asix_write_medium_mode(dev, mode);
796
797 return 0;
2e55cc72
DB		 798}
799
48b1be6a 800static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
2e55cc72
DB		 801{
802 int ret = 0;
803 void *buf;
804 int i;
805 unsigned long gpio_bits = dev->driver_info->data;
933a27d3
DH		 806 struct asix_data *data = (struct asix_data *)&dev->data;
807
808 data->eeprom_len = AX88172_EEPROM_LEN;
2e55cc72
DB		 809
810 usbnet_get_endpoints(dev,intf);
811
812 buf = kmalloc(ETH_ALEN, GFP_KERNEL);
813 if(!buf) {
814 ret = -ENOMEM;
815 goto out1;
816 }
817
818 /* Toggle the GPIOs in a manufacturer/model specific way */
819 for (i = 2; i >= 0; i--) {
48b1be6a 820 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
2e55cc72
DB		 821 (gpio_bits >> (i * 8)) & 0xff, 0, 0,
822 buf)) < 0)
823 goto out2;
824 msleep(5);
825 }
826
933a27d3 827 if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0)
2e55cc72 828 goto out2;
2e55cc72
DB		 829
830 /* Get the MAC address */
831 memset(buf, 0, ETH_ALEN);
933a27d3 832 if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
2e55cc72
DB		 833 0, 0, 6, buf)) < 0) {
834 dbg("read AX_CMD_READ_NODE_ID failed: %d", ret);
835 goto out2;
836 }
837 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
838
2e55cc72
DB		 839 /* Initialize MII structure */
840 dev->mii.dev = dev->net;
48b1be6a
DH		 841 dev->mii.mdio_read = asix_mdio_read;
842 dev->mii.mdio_write = asix_mdio_write;
2e55cc72
DB		 843 dev->mii.phy_id_mask = 0x3f;
844 dev->mii.reg_num_mask = 0x1f;
933a27d3 845 dev->mii.phy_id = asix_get_phy_addr(dev);
48b1be6a 846 dev->net->do_ioctl = asix_ioctl;
2e55cc72 847
933a27d3 848 dev->net->set_multicast_list = ax88172_set_multicast;
48b1be6a 849 dev->net->ethtool_ops = &ax88172_ethtool_ops;
2e55cc72 850
933a27d3
DH		 851 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
852 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 853 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
854 mii_nway_restart(&dev->mii);
855
856 return 0;
857out2:
858 kfree(buf);
859out1:
860 return ret;
861}
862
863static struct ethtool_ops ax88772_ethtool_ops = {
48b1be6a 864 .get_drvinfo = asix_get_drvinfo,
933a27d3 865 .get_link = asix_get_link,
2e55cc72
DB		 866 .get_msglevel = usbnet_get_msglevel,
867 .set_msglevel = usbnet_set_msglevel,
48b1be6a
DH		 868 .get_wol = asix_get_wol,
869 .set_wol = asix_set_wol,
870 .get_eeprom_len = asix_get_eeprom_len,
871 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 872 .get_settings = usbnet_get_settings,
873 .set_settings = usbnet_set_settings,
874 .nway_reset = usbnet_nway_reset,
2e55cc72
DB		 875};
876
933a27d3
DH		 877static int ax88772_link_reset(struct usbnet *dev)
878{
879 u16 mode;
880 struct ethtool_cmd ecmd;
881
882 mii_check_media(&dev->mii, 1, 1);
883 mii_ethtool_gset(&dev->mii, &ecmd);
884 mode = AX88772_MEDIUM_DEFAULT;
885
886 if (ecmd.speed != SPEED_100)
887 mode &= ~AX_MEDIUM_PS;
888
889 if (ecmd.duplex != DUPLEX_FULL)
890 mode &= ~AX_MEDIUM_FD;
891
892 devdbg(dev, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
893
894 asix_write_medium_mode(dev, mode);
895
896 return 0;
897}
898
2e55cc72
DB		 899static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
900{
901 int ret;
902 void *buf;
933a27d3
DH		 903 u16 rx_ctl;
904 struct asix_data *data = (struct asix_data *)&dev->data;
905 u32 phyid;
906
907 data->eeprom_len = AX88772_EEPROM_LEN;
2e55cc72
DB		 908
909 usbnet_get_endpoints(dev,intf);
910
911 buf = kmalloc(6, GFP_KERNEL);
912 if(!buf) {
913 dbg ("Cannot allocate memory for buffer");
914 ret = -ENOMEM;
915 goto out1;
916 }
917
933a27d3
DH		 918 if ((ret = asix_write_gpio(dev,
919 AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0)
2e55cc72
DB		 920 goto out2;
921
48b1be6a 922 if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
933a27d3 923 0x0000, 0, 0, buf)) < 0) {
2e55cc72
DB		 924 dbg("Select PHY #1 failed: %d", ret);
925 goto out2;
926 }
927
48b1be6a 928 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD)) < 0)
2e55cc72 929 goto out2;
2e55cc72
DB		 930
931 msleep(150);
48b1be6a 932 if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0)
2e55cc72 933 goto out2;
2e55cc72
DB		 934
935 msleep(150);
48b1be6a 936 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
2e55cc72 937 goto out2;
2e55cc72
DB		 938
939 msleep(150);
933a27d3
DH		 940 rx_ctl = asix_read_rx_ctl(dev);
941 dbg("RX_CTL is 0x%04x after software reset", rx_ctl);
942 if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0)
2e55cc72 943 goto out2;
2e55cc72 944
933a27d3
DH		 945 rx_ctl = asix_read_rx_ctl(dev);
946 dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl);
947
2e55cc72
DB		 948 /* Get the MAC address */
949 memset(buf, 0, ETH_ALEN);
933a27d3 950 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
2e55cc72
DB		 951 0, 0, ETH_ALEN, buf)) < 0) {
952 dbg("Failed to read MAC address: %d", ret);
953 goto out2;
954 }
955 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
956
2e55cc72
DB		 957 /* Initialize MII structure */
958 dev->mii.dev = dev->net;
48b1be6a
DH		 959 dev->mii.mdio_read = asix_mdio_read;
960 dev->mii.mdio_write = asix_mdio_write;
933a27d3
DH		 961 dev->mii.phy_id_mask = 0x1f;
962 dev->mii.reg_num_mask = 0x1f;
48b1be6a 963 dev->net->do_ioctl = asix_ioctl;
933a27d3
DH		 964 dev->mii.phy_id = asix_get_phy_addr(dev);
965
966 phyid = asix_get_phyid(dev);
967 dbg("PHYID=0x%08x", phyid);
2e55cc72 968
48b1be6a 969 if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0)
2e55cc72 970 goto out2;
2e55cc72 971
2e55cc72 972 msleep(150);
48b1be6a
DH		 973
974 if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0)
2e55cc72 975 goto out2;
2e55cc72 976
48b1be6a 977 msleep(150);
2e55cc72 978
48b1be6a 979 dev->net->set_multicast_list = asix_set_multicast;
2e55cc72
DB		 980 dev->net->ethtool_ops = &ax88772_ethtool_ops;
981
933a27d3
DH		 982 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
983 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
2e55cc72
DB		 984 ADVERTISE_ALL | ADVERTISE_CSMA);
985 mii_nway_restart(&dev->mii);
986
933a27d3 987 if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0)
2e55cc72 988 goto out2;
2e55cc72 989
48b1be6a 990 if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
2e55cc72
DB		 991 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
992 AX88772_IPG2_DEFAULT, 0, buf)) < 0) {
993 dbg("Write IPG,IPG1,IPG2 failed: %d", ret);
994 goto out2;
995 }
2e55cc72
DB		 996
997 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
933a27d3 998 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
2e55cc72 999 goto out2;
2e55cc72 1000
933a27d3
DH		 1001 rx_ctl = asix_read_rx_ctl(dev);
1002 dbg("RX_CTL is 0x%04x after all initializations", rx_ctl);
1003
1004 rx_ctl = asix_read_medium_status(dev);
1005 dbg("Medium Status is 0x%04x after all initializations", rx_ctl);
1006
2e55cc72
DB		 1007 kfree(buf);
1008
1009 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1010 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1011 /* hard_mtu is still the default - the device does not support
1012 jumbo eth frames */
1013 dev->rx_urb_size = 2048;
1014 }
1015
1016 return 0;
1017
1018out2:
1019 kfree(buf);
1020out1:
1021 return ret;
1022}
1023
933a27d3
DH		 1024static struct ethtool_ops ax88178_ethtool_ops = {
1025 .get_drvinfo = asix_get_drvinfo,
1026 .get_link = asix_get_link,
933a27d3
DH		 1027 .get_msglevel = usbnet_get_msglevel,
1028 .set_msglevel = usbnet_set_msglevel,
1029 .get_wol = asix_get_wol,
1030 .set_wol = asix_set_wol,
1031 .get_eeprom_len = asix_get_eeprom_len,
1032 .get_eeprom = asix_get_eeprom,
c41286fd
AB		 1033 .get_settings = usbnet_get_settings,
1034 .set_settings = usbnet_set_settings,
1035 .nway_reset = usbnet_nway_reset,
933a27d3
DH		 1036};
1037
1038static int marvell_phy_init(struct usbnet *dev)
2e55cc72 1039{
933a27d3
DH		 1040 struct asix_data *data = (struct asix_data *)&dev->data;
1041 u16 reg;
2e55cc72 1042
933a27d3 1043 devdbg(dev,"marvell_phy_init()");
2e55cc72 1044
933a27d3
DH		 1045 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
1046 devdbg(dev,"MII_MARVELL_STATUS = 0x%04x", reg);
2e55cc72 1047
933a27d3
DH		 1048 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
1049 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
2e55cc72 1050
933a27d3
DH		 1051 if (data->ledmode) {
1052 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1053 MII_MARVELL_LED_CTRL);
1054 devdbg(dev,"MII_MARVELL_LED_CTRL (1) = 0x%04x", reg);
2e55cc72 1055
933a27d3
DH		 1056 reg &= 0xf8ff;
1057 reg |= (1 + 0x0100);
1058 asix_mdio_write(dev->net, dev->mii.phy_id,
1059 MII_MARVELL_LED_CTRL, reg);
2e55cc72 1060
933a27d3
DH		 1061 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
1062 MII_MARVELL_LED_CTRL);
1063 devdbg(dev,"MII_MARVELL_LED_CTRL (2) = 0x%04x", reg);
1064 reg &= 0xfc0f;
1065 }
2e55cc72 1066
933a27d3
DH		 1067 return 0;
1068}
1069
1070static int marvell_led_status(struct usbnet *dev, u16 speed)
1071{
1072 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1073
1074 devdbg(dev, "marvell_led_status() read 0x%04x", reg);
1075
1076 /* Clear out the center LED bits - 0x03F0 */
1077 reg &= 0xfc0f;
1078
1079 switch (speed) {
1080 case SPEED_1000:
1081 reg |= 0x03e0;
1082 break;
1083 case SPEED_100:
1084 reg |= 0x03b0;
1085 break;
1086 default:
1087 reg |= 0x02f0;
2e55cc72
DB		 1088 }
1089
933a27d3
DH		 1090 devdbg(dev, "marvell_led_status() writing 0x%04x", reg);
1091 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1092
1093 return 0;
1094}
1095
1096static int ax88178_link_reset(struct usbnet *dev)
1097{
1098 u16 mode;
1099 struct ethtool_cmd ecmd;
1100 struct asix_data *data = (struct asix_data *)&dev->data;
1101
1102 devdbg(dev,"ax88178_link_reset()");
1103
1104 mii_check_media(&dev->mii, 1, 1);
1105 mii_ethtool_gset(&dev->mii, &ecmd);
1106 mode = AX88178_MEDIUM_DEFAULT;
1107
1108 if (ecmd.speed == SPEED_1000)
1109 mode |= AX_MEDIUM_GM | AX_MEDIUM_ENCK;
1110 else if (ecmd.speed == SPEED_100)
1111 mode |= AX_MEDIUM_PS;
1112 else
1113 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1114
1115 if (ecmd.duplex == DUPLEX_FULL)
1116 mode |= AX_MEDIUM_FD;
1117 else
1118 mode &= ~AX_MEDIUM_FD;
1119
1120 devdbg(dev, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode);
1121
1122 asix_write_medium_mode(dev, mode);
1123
1124 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1125 marvell_led_status(dev, ecmd.speed);
1126
1127 return 0;
1128}
1129
1130static void ax88178_set_mfb(struct usbnet *dev)
1131{
1132 u16 mfb = AX_RX_CTL_MFB_16384;
1133 u16 rxctl;
1134 u16 medium;
1135 int old_rx_urb_size = dev->rx_urb_size;
1136
1137 if (dev->hard_mtu < 2048) {
1138 dev->rx_urb_size = 2048;
1139 mfb = AX_RX_CTL_MFB_2048;
1140 } else if (dev->hard_mtu < 4096) {
1141 dev->rx_urb_size = 4096;
1142 mfb = AX_RX_CTL_MFB_4096;
1143 } else if (dev->hard_mtu < 8192) {
1144 dev->rx_urb_size = 8192;
1145 mfb = AX_RX_CTL_MFB_8192;
1146 } else if (dev->hard_mtu < 16384) {
1147 dev->rx_urb_size = 16384;
1148 mfb = AX_RX_CTL_MFB_16384;
2e55cc72 1149 }
933a27d3
DH		 1150
1151 rxctl = asix_read_rx_ctl(dev);
1152 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
1153
1154 medium = asix_read_medium_status(dev);
1155 if (dev->net->mtu > 1500)
1156 medium |= AX_MEDIUM_JFE;
1157 else
1158 medium &= ~AX_MEDIUM_JFE;
1159 asix_write_medium_mode(dev, medium);
1160
1161 if (dev->rx_urb_size > old_rx_urb_size)
1162 usbnet_unlink_rx_urbs(dev);
2e55cc72
DB		 1163}
1164
933a27d3 1165static int ax88178_change_mtu(struct net_device *net, int new_mtu)
2e55cc72 1166{
933a27d3
DH		 1167 struct usbnet *dev = netdev_priv(net);
1168 int ll_mtu = new_mtu + net->hard_header_len + 4;
2e55cc72 1169
933a27d3 1170 devdbg(dev, "ax88178_change_mtu() new_mtu=%d", new_mtu);
2e55cc72 1171
933a27d3
DH		 1172 if (new_mtu <= 0 || ll_mtu > 16384)
1173 return -EINVAL;
1174
1175 if ((ll_mtu % dev->maxpacket) == 0)
1176 return -EDOM;
1177
1178 net->mtu = new_mtu;
1179 dev->hard_mtu = net->mtu + net->hard_header_len;
1180 ax88178_set_mfb(dev);
1181
1182 return 0;
1183}
1184
1185static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1186{
1187 struct asix_data *data = (struct asix_data *)&dev->data;
1188 int ret;
1189 void *buf;
1190 u16 eeprom;
1191 int gpio0 = 0;
1192 u32 phyid;
1193
1194 usbnet_get_endpoints(dev,intf);
1195
1196 buf = kmalloc(6, GFP_KERNEL);
1197 if(!buf) {
1198 dbg ("Cannot allocate memory for buffer");
1199 ret = -ENOMEM;
1200 goto out1;
1201 }
1202
1203 eeprom = 0;
1204 asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &eeprom);
1205 dbg("GPIO Status: 0x%04x", eeprom);
1206
1207 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
1208 asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
1209 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
1210
1211 dbg("EEPROM index 0x17 is 0x%04x", eeprom);
1212
1213 if (eeprom == 0xffff) {
1214 data->phymode = PHY_MODE_MARVELL;
1215 data->ledmode = 0;
1216 gpio0 = 1;
2e55cc72 1217 } else {
933a27d3
DH		 1218 data->phymode = eeprom & 7;
1219 data->ledmode = eeprom >> 8;
1220 gpio0 = (eeprom & 0x80) ? 0 : 1;
2e55cc72 1221 }
933a27d3 1222 dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode);
2e55cc72 1223
933a27d3
DH		 1224 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
1225 if ((eeprom >> 8) != 1) {
1226 asix_write_gpio(dev, 0x003c, 30);
1227 asix_write_gpio(dev, 0x001c, 300);
1228 asix_write_gpio(dev, 0x003c, 30);
1229 } else {
1230 dbg("gpio phymode == 1 path");
1231 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
1232 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
1233 }
2e55cc72 1234
933a27d3
DH		 1235 asix_sw_reset(dev, 0);
1236 msleep(150);
1237
1238 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
1239 msleep(150);
1240
1241 asix_write_rx_ctl(dev, 0);
1242
1243 /* Get the MAC address */
1244 memset(buf, 0, ETH_ALEN);
1245 if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
1246 0, 0, ETH_ALEN, buf)) < 0) {
1247 dbg("Failed to read MAC address: %d", ret);
1248 goto out2;
2e55cc72 1249 }
933a27d3 1250 memcpy(dev->net->dev_addr, buf, ETH_ALEN);
2e55cc72 1251
933a27d3
DH		 1252 /* Initialize MII structure */
1253 dev->mii.dev = dev->net;
1254 dev->mii.mdio_read = asix_mdio_read;
1255 dev->mii.mdio_write = asix_mdio_write;
1256 dev->mii.phy_id_mask = 0x1f;
1257 dev->mii.reg_num_mask = 0xff;
1258 dev->mii.supports_gmii = 1;
1259 dev->net->do_ioctl = asix_ioctl;
1260 dev->mii.phy_id = asix_get_phy_addr(dev);
1261 dev->net->set_multicast_list = asix_set_multicast;
1262 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1263 dev->net->change_mtu = &ax88178_change_mtu;
2e55cc72 1264
933a27d3
DH		 1265 phyid = asix_get_phyid(dev);
1266 dbg("PHYID=0x%08x", phyid);
2e55cc72 1267
933a27d3
DH		 1268 if (data->phymode == PHY_MODE_MARVELL) {
1269 marvell_phy_init(dev);
1270 msleep(60);
1271 }
1272
1273 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
1274 BMCR_RESET | BMCR_ANENABLE);
1275 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1276 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1277 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1278 ADVERTISE_1000FULL);
1279
1280 mii_nway_restart(&dev->mii);
1281
1282 if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0)
1283 goto out2;
1284
1285 if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0)
1286 goto out2;
1287
1288 kfree(buf);
1289
1290 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1291 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1292 /* hard_mtu is still the default - the device does not support
1293 jumbo eth frames */
1294 dev->rx_urb_size = 2048;
1295 }
2e55cc72
DB		 1296
1297 return 0;
933a27d3
DH		 1298
1299out2:
1300 kfree(buf);
1301out1:
1302 return ret;
2e55cc72
DB		 1303}
1304
1305static const struct driver_info ax8817x_info = {
1306 .description = "ASIX AX8817x USB 2.0 Ethernet",
48b1be6a
DH		 1307 .bind = ax88172_bind,
1308 .status = asix_status,
2e55cc72
DB		 1309 .link_reset = ax88172_link_reset,
1310 .reset = ax88172_link_reset,
1311 .flags = FLAG_ETHER,
1312 .data = 0x00130103,
1313};
1314
1315static const struct driver_info dlink_dub_e100_info = {
1316 .description = "DLink DUB-E100 USB Ethernet",
48b1be6a
DH		 1317 .bind = ax88172_bind,
1318 .status = asix_status,
2e55cc72
DB		 1319 .link_reset = ax88172_link_reset,
1320 .reset = ax88172_link_reset,
1321 .flags = FLAG_ETHER,
1322 .data = 0x009f9d9f,
1323};
1324
1325static const struct driver_info netgear_fa120_info = {
1326 .description = "Netgear FA-120 USB Ethernet",
48b1be6a
DH		 1327 .bind = ax88172_bind,
1328 .status = asix_status,
2e55cc72
DB		 1329 .link_reset = ax88172_link_reset,
1330 .reset = ax88172_link_reset,
1331 .flags = FLAG_ETHER,
1332 .data = 0x00130103,
1333};
1334
1335static const struct driver_info hawking_uf200_info = {
1336 .description = "Hawking UF200 USB Ethernet",
48b1be6a
DH		 1337 .bind = ax88172_bind,
1338 .status = asix_status,
2e55cc72
DB		 1339 .link_reset = ax88172_link_reset,
1340 .reset = ax88172_link_reset,
1341 .flags = FLAG_ETHER,
1342 .data = 0x001f1d1f,
1343};
1344
1345static const struct driver_info ax88772_info = {
1346 .description = "ASIX AX88772 USB 2.0 Ethernet",
1347 .bind = ax88772_bind,
48b1be6a 1348 .status = asix_status,
2e55cc72
DB		 1349 .link_reset = ax88772_link_reset,
1350 .reset = ax88772_link_reset,
1351 .flags = FLAG_ETHER | FLAG_FRAMING_AX,
933a27d3
DH		 1352 .rx_fixup = asix_rx_fixup,
1353 .tx_fixup = asix_tx_fixup,
1354};
1355
1356static const struct driver_info ax88178_info = {
1357 .description = "ASIX AX88178 USB 2.0 Ethernet",
1358 .bind = ax88178_bind,
1359 .status = asix_status,
1360 .link_reset = ax88178_link_reset,
1361 .reset = ax88178_link_reset,
1362 .flags = FLAG_ETHER | FLAG_FRAMING_AX,
1363 .rx_fixup = asix_rx_fixup,
1364 .tx_fixup = asix_tx_fixup,
2e55cc72
DB		 1365};
1366
1367static const struct usb_device_id products [] = {
1368{
1369 // Linksys USB200M
1370 USB_DEVICE (0x077b, 0x2226),
1371 .driver_info = (unsigned long) &ax8817x_info,
1372}, {
1373 // Netgear FA120
1374 USB_DEVICE (0x0846, 0x1040),
1375 .driver_info = (unsigned long) &netgear_fa120_info,
1376}, {
1377 // DLink DUB-E100
1378 USB_DEVICE (0x2001, 0x1a00),
1379 .driver_info = (unsigned long) &dlink_dub_e100_info,
1380}, {
1381 // Intellinet, ST Lab USB Ethernet
1382 USB_DEVICE (0x0b95, 0x1720),
1383 .driver_info = (unsigned long) &ax8817x_info,
1384}, {
1385 // Hawking UF200, TrendNet TU2-ET100
1386 USB_DEVICE (0x07b8, 0x420a),
1387 .driver_info = (unsigned long) &hawking_uf200_info,
1388}, {
1389 // Billionton Systems, USB2AR
1390 USB_DEVICE (0x08dd, 0x90ff),
1391 .driver_info = (unsigned long) &ax8817x_info,
1392}, {
1393 // ATEN UC210T
1394 USB_DEVICE (0x0557, 0x2009),
1395 .driver_info = (unsigned long) &ax8817x_info,
1396}, {
1397 // Buffalo LUA-U2-KTX
1398 USB_DEVICE (0x0411, 0x003d),
1399 .driver_info = (unsigned long) &ax8817x_info,
1400}, {
1401 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1402 USB_DEVICE (0x6189, 0x182d),
1403 .driver_info = (unsigned long) &ax8817x_info,
1404}, {
1405 // corega FEther USB2-TX
1406 USB_DEVICE (0x07aa, 0x0017),
1407 .driver_info = (unsigned long) &ax8817x_info,
1408}, {
1409 // Surecom EP-1427X-2
1410 USB_DEVICE (0x1189, 0x0893),
1411 .driver_info = (unsigned long) &ax8817x_info,
1412}, {
1413 // goodway corp usb gwusb2e
1414 USB_DEVICE (0x1631, 0x6200),
1415 .driver_info = (unsigned long) &ax8817x_info,
1416}, {
1417 // ASIX AX88772 10/100
1418 USB_DEVICE (0x0b95, 0x7720),
1419 .driver_info = (unsigned long) &ax88772_info,
7327413c
EW		 1420}, {
1421 // ASIX AX88178 10/100/1000
1422 USB_DEVICE (0x0b95, 0x1780),
933a27d3 1423 .driver_info = (unsigned long) &ax88178_info,
5e0f76c6
DH		 1424}, {
1425 // Linksys USB200M Rev 2
1426 USB_DEVICE (0x13b1, 0x0018),
1427 .driver_info = (unsigned long) &ax88772_info,
5732ce84
DH		 1428}, {
1429 // 0Q0 cable ethernet
1430 USB_DEVICE (0x1557, 0x7720),
1431 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1432}, {
1433 // DLink DUB-E100 H/W Ver B1
1434 USB_DEVICE (0x07d1, 0x3c05),
1435 .driver_info = (unsigned long) &ax88772_info,
b923e7fc
DH		 1436}, {
1437 // DLink DUB-E100 H/W Ver B1 Alternate
1438 USB_DEVICE (0x2001, 0x3c05),
1439 .driver_info = (unsigned long) &ax88772_info,
933a27d3
DH		 1440}, {
1441 // Linksys USB1000
1442 USB_DEVICE (0x1737, 0x0039),
1443 .driver_info = (unsigned long) &ax88178_info,
2e55cc72
DB		 1444},
1445 { }, // END
1446};
1447MODULE_DEVICE_TABLE(usb, products);
1448
1449static struct usb_driver asix_driver = {
2e55cc72
DB		 1450 .name = "asix",
1451 .id_table = products,
1452 .probe = usbnet_probe,
1453 .suspend = usbnet_suspend,
1454 .resume = usbnet_resume,
1455 .disconnect = usbnet_disconnect,
1456};
1457
1458static int __init asix_init(void)
1459{
1460 return usb_register(&asix_driver);
1461}
1462module_init(asix_init);
1463
1464static void __exit asix_exit(void)
1465{
1466 usb_deregister(&asix_driver);
1467}
1468module_exit(asix_exit);
1469
1470MODULE_AUTHOR("David Hollis");
1471MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1472MODULE_LICENSE("GPL");
1473
Linux 6.x block layer and io_uring tree(s)