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2e55cc72 DB |
1 | /* |
2 | * ASIX AX8817X based USB 2.0 Ethernet Devices | |
933a27d3 | 3 | * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com> |
2e55cc72 | 4 | * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net> |
933a27d3 | 5 | * Copyright (C) 2006 James Painter <jamie.painter@iname.com> |
2e55cc72 DB |
6 | * Copyright (c) 2002-2003 TiVo Inc. |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | // #define DEBUG // error path messages, extra info | |
24 | // #define VERBOSE // more; success messages | |
25 | ||
2e55cc72 DB |
26 | #include <linux/module.h> |
27 | #include <linux/kmod.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/workqueue.h> | |
34 | #include <linux/mii.h> | |
35 | #include <linux/usb.h> | |
36 | #include <linux/crc32.h> | |
37 | ||
38 | #include "usbnet.h" | |
39 | ||
933a27d3 DH |
40 | #define DRIVER_VERSION "14-Jun-2006" |
41 | static const char driver_name [] = "asix"; | |
42 | ||
2e55cc72 DB |
43 | /* ASIX AX8817X based USB 2.0 Ethernet Devices */ |
44 | ||
45 | #define AX_CMD_SET_SW_MII 0x06 | |
46 | #define AX_CMD_READ_MII_REG 0x07 | |
47 | #define AX_CMD_WRITE_MII_REG 0x08 | |
48 | #define AX_CMD_SET_HW_MII 0x0a | |
49 | #define AX_CMD_READ_EEPROM 0x0b | |
50 | #define AX_CMD_WRITE_EEPROM 0x0c | |
51 | #define AX_CMD_WRITE_ENABLE 0x0d | |
52 | #define AX_CMD_WRITE_DISABLE 0x0e | |
933a27d3 | 53 | #define AX_CMD_READ_RX_CTL 0x0f |
2e55cc72 DB |
54 | #define AX_CMD_WRITE_RX_CTL 0x10 |
55 | #define AX_CMD_READ_IPG012 0x11 | |
56 | #define AX_CMD_WRITE_IPG0 0x12 | |
57 | #define AX_CMD_WRITE_IPG1 0x13 | |
933a27d3 | 58 | #define AX_CMD_READ_NODE_ID 0x13 |
2e55cc72 DB |
59 | #define AX_CMD_WRITE_IPG2 0x14 |
60 | #define AX_CMD_WRITE_MULTI_FILTER 0x16 | |
933a27d3 | 61 | #define AX88172_CMD_READ_NODE_ID 0x17 |
2e55cc72 DB |
62 | #define AX_CMD_READ_PHY_ID 0x19 |
63 | #define AX_CMD_READ_MEDIUM_STATUS 0x1a | |
64 | #define AX_CMD_WRITE_MEDIUM_MODE 0x1b | |
65 | #define AX_CMD_READ_MONITOR_MODE 0x1c | |
66 | #define AX_CMD_WRITE_MONITOR_MODE 0x1d | |
933a27d3 | 67 | #define AX_CMD_READ_GPIOS 0x1e |
2e55cc72 DB |
68 | #define AX_CMD_WRITE_GPIOS 0x1f |
69 | #define AX_CMD_SW_RESET 0x20 | |
70 | #define AX_CMD_SW_PHY_STATUS 0x21 | |
71 | #define AX_CMD_SW_PHY_SELECT 0x22 | |
2e55cc72 DB |
72 | |
73 | #define AX_MONITOR_MODE 0x01 | |
74 | #define AX_MONITOR_LINK 0x02 | |
75 | #define AX_MONITOR_MAGIC 0x04 | |
76 | #define AX_MONITOR_HSFS 0x10 | |
77 | ||
78 | /* AX88172 Medium Status Register values */ | |
933a27d3 DH |
79 | #define AX88172_MEDIUM_FD 0x02 |
80 | #define AX88172_MEDIUM_TX 0x04 | |
81 | #define AX88172_MEDIUM_FC 0x10 | |
82 | #define AX88172_MEDIUM_DEFAULT \ | |
83 | ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC ) | |
2e55cc72 DB |
84 | |
85 | #define AX_MCAST_FILTER_SIZE 8 | |
86 | #define AX_MAX_MCAST 64 | |
87 | ||
2e55cc72 DB |
88 | #define AX_SWRESET_CLEAR 0x00 |
89 | #define AX_SWRESET_RR 0x01 | |
90 | #define AX_SWRESET_RT 0x02 | |
91 | #define AX_SWRESET_PRTE 0x04 | |
92 | #define AX_SWRESET_PRL 0x08 | |
93 | #define AX_SWRESET_BZ 0x10 | |
94 | #define AX_SWRESET_IPRL 0x20 | |
95 | #define AX_SWRESET_IPPD 0x40 | |
96 | ||
97 | #define AX88772_IPG0_DEFAULT 0x15 | |
98 | #define AX88772_IPG1_DEFAULT 0x0c | |
99 | #define AX88772_IPG2_DEFAULT 0x12 | |
100 | ||
933a27d3 DH |
101 | /* AX88772 & AX88178 Medium Mode Register */ |
102 | #define AX_MEDIUM_PF 0x0080 | |
103 | #define AX_MEDIUM_JFE 0x0040 | |
104 | #define AX_MEDIUM_TFC 0x0020 | |
105 | #define AX_MEDIUM_RFC 0x0010 | |
106 | #define AX_MEDIUM_ENCK 0x0008 | |
107 | #define AX_MEDIUM_AC 0x0004 | |
108 | #define AX_MEDIUM_FD 0x0002 | |
109 | #define AX_MEDIUM_GM 0x0001 | |
110 | #define AX_MEDIUM_SM 0x1000 | |
111 | #define AX_MEDIUM_SBP 0x0800 | |
112 | #define AX_MEDIUM_PS 0x0200 | |
113 | #define AX_MEDIUM_RE 0x0100 | |
114 | ||
115 | #define AX88178_MEDIUM_DEFAULT \ | |
116 | (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ | |
117 | AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ | |
118 | AX_MEDIUM_RE ) | |
2e55cc72 | 119 | |
933a27d3 DH |
120 | #define AX88772_MEDIUM_DEFAULT \ |
121 | (AX_MEDIUM_FD | AX_MEDIUM_RFC | \ | |
122 | AX_MEDIUM_TFC | AX_MEDIUM_PS | \ | |
123 | AX_MEDIUM_AC | AX_MEDIUM_RE ) | |
124 | ||
125 | /* AX88772 & AX88178 RX_CTL values */ | |
126 | #define AX_RX_CTL_SO 0x0080 | |
127 | #define AX_RX_CTL_AP 0x0020 | |
128 | #define AX_RX_CTL_AM 0x0010 | |
129 | #define AX_RX_CTL_AB 0x0008 | |
130 | #define AX_RX_CTL_SEP 0x0004 | |
131 | #define AX_RX_CTL_AMALL 0x0002 | |
132 | #define AX_RX_CTL_PRO 0x0001 | |
133 | #define AX_RX_CTL_MFB_2048 0x0000 | |
134 | #define AX_RX_CTL_MFB_4096 0x0100 | |
135 | #define AX_RX_CTL_MFB_8192 0x0200 | |
136 | #define AX_RX_CTL_MFB_16384 0x0300 | |
137 | ||
138 | #define AX_DEFAULT_RX_CTL \ | |
139 | (AX_RX_CTL_SO | AX_RX_CTL_AB ) | |
140 | ||
141 | /* GPIO 0 .. 2 toggles */ | |
142 | #define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ | |
143 | #define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ | |
144 | #define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ | |
145 | #define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ | |
146 | #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ | |
147 | #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ | |
148 | #define AX_GPIO_RESERVED 0x40 /* Reserved */ | |
149 | #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ | |
150 | ||
151 | #define AX_EEPROM_MAGIC 0xdeadbeef | |
152 | #define AX88172_EEPROM_LEN 0x40 | |
153 | #define AX88772_EEPROM_LEN 0xff | |
154 | ||
155 | #define PHY_MODE_MARVELL 0x0000 | |
156 | #define MII_MARVELL_LED_CTRL 0x0018 | |
157 | #define MII_MARVELL_STATUS 0x001b | |
158 | #define MII_MARVELL_CTRL 0x0014 | |
159 | ||
160 | #define MARVELL_LED_MANUAL 0x0019 | |
161 | ||
162 | #define MARVELL_STATUS_HWCFG 0x0004 | |
163 | ||
164 | #define MARVELL_CTRL_TXDELAY 0x0002 | |
165 | #define MARVELL_CTRL_RXDELAY 0x0080 | |
2e55cc72 DB |
166 | |
167 | /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */ | |
48b1be6a | 168 | struct asix_data { |
2e55cc72 | 169 | u8 multi_filter[AX_MCAST_FILTER_SIZE]; |
933a27d3 DH |
170 | u8 phymode; |
171 | u8 ledmode; | |
172 | u8 eeprom_len; | |
2e55cc72 DB |
173 | }; |
174 | ||
175 | struct ax88172_int_data { | |
176 | u16 res1; | |
177 | u8 link; | |
178 | u16 res2; | |
179 | u8 status; | |
180 | u16 res3; | |
181 | } __attribute__ ((packed)); | |
182 | ||
48b1be6a | 183 | static int asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
184 | u16 size, void *data) |
185 | { | |
933a27d3 DH |
186 | devdbg(dev,"asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d", |
187 | cmd, value, index, size); | |
2e55cc72 DB |
188 | return usb_control_msg( |
189 | dev->udev, | |
190 | usb_rcvctrlpipe(dev->udev, 0), | |
191 | cmd, | |
192 | USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
193 | value, | |
194 | index, | |
195 | data, | |
196 | size, | |
197 | USB_CTRL_GET_TIMEOUT); | |
198 | } | |
199 | ||
48b1be6a | 200 | static int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, |
2e55cc72 DB |
201 | u16 size, void *data) |
202 | { | |
933a27d3 DH |
203 | devdbg(dev,"asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d", |
204 | cmd, value, index, size); | |
2e55cc72 DB |
205 | return usb_control_msg( |
206 | dev->udev, | |
207 | usb_sndctrlpipe(dev->udev, 0), | |
208 | cmd, | |
209 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, | |
210 | value, | |
211 | index, | |
212 | data, | |
213 | size, | |
214 | USB_CTRL_SET_TIMEOUT); | |
215 | } | |
216 | ||
7d12e780 | 217 | static void asix_async_cmd_callback(struct urb *urb) |
2e55cc72 DB |
218 | { |
219 | struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)urb->context; | |
220 | ||
221 | if (urb->status < 0) | |
48b1be6a | 222 | printk(KERN_DEBUG "asix_async_cmd_callback() failed with %d", |
2e55cc72 DB |
223 | urb->status); |
224 | ||
225 | kfree(req); | |
226 | usb_free_urb(urb); | |
227 | } | |
228 | ||
933a27d3 DH |
229 | static void |
230 | asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, | |
231 | u16 size, void *data) | |
232 | { | |
233 | struct usb_ctrlrequest *req; | |
234 | int status; | |
235 | struct urb *urb; | |
236 | ||
237 | devdbg(dev,"asix_write_cmd_async() cmd=0x%02x value=0x%04x index=0x%04x size=%d", | |
238 | cmd, value, index, size); | |
239 | if ((urb = usb_alloc_urb(0, GFP_ATOMIC)) == NULL) { | |
240 | deverr(dev, "Error allocating URB in write_cmd_async!"); | |
241 | return; | |
242 | } | |
243 | ||
244 | if ((req = kmalloc(sizeof(struct usb_ctrlrequest), GFP_ATOMIC)) == NULL) { | |
245 | deverr(dev, "Failed to allocate memory for control request"); | |
246 | usb_free_urb(urb); | |
247 | return; | |
248 | } | |
249 | ||
250 | req->bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE; | |
251 | req->bRequest = cmd; | |
252 | req->wValue = value; | |
253 | req->wIndex = index; | |
254 | req->wLength = size; | |
255 | ||
256 | usb_fill_control_urb(urb, dev->udev, | |
257 | usb_sndctrlpipe(dev->udev, 0), | |
258 | (void *)req, data, size, | |
259 | asix_async_cmd_callback, req); | |
260 | ||
261 | if((status = usb_submit_urb(urb, GFP_ATOMIC)) < 0) { | |
262 | deverr(dev, "Error submitting the control message: status=%d", | |
263 | status); | |
264 | kfree(req); | |
265 | usb_free_urb(urb); | |
266 | } | |
267 | } | |
268 | ||
269 | static int asix_rx_fixup(struct usbnet *dev, struct sk_buff *skb) | |
270 | { | |
271 | u8 *head; | |
272 | u32 header; | |
273 | char *packet; | |
274 | struct sk_buff *ax_skb; | |
275 | u16 size; | |
276 | ||
277 | head = (u8 *) skb->data; | |
278 | memcpy(&header, head, sizeof(header)); | |
279 | le32_to_cpus(&header); | |
280 | packet = head + sizeof(header); | |
281 | ||
282 | skb_pull(skb, 4); | |
283 | ||
284 | while (skb->len > 0) { | |
285 | if ((short)(header & 0x0000ffff) != | |
286 | ~((short)((header & 0xffff0000) >> 16))) { | |
287 | deverr(dev,"asix_rx_fixup() Bad Header Length"); | |
288 | } | |
289 | /* get the packet length */ | |
290 | size = (u16) (header & 0x0000ffff); | |
291 | ||
292 | if ((skb->len) - ((size + 1) & 0xfffe) == 0) | |
293 | return 2; | |
294 | if (size > ETH_FRAME_LEN) { | |
295 | deverr(dev,"asix_rx_fixup() Bad RX Length %d", size); | |
296 | return 0; | |
297 | } | |
298 | ax_skb = skb_clone(skb, GFP_ATOMIC); | |
299 | if (ax_skb) { | |
300 | ax_skb->len = size; | |
301 | ax_skb->data = packet; | |
302 | ax_skb->tail = packet + size; | |
303 | usbnet_skb_return(dev, ax_skb); | |
304 | } else { | |
305 | return 0; | |
306 | } | |
307 | ||
308 | skb_pull(skb, (size + 1) & 0xfffe); | |
309 | ||
310 | if (skb->len == 0) | |
311 | break; | |
312 | ||
313 | head = (u8 *) skb->data; | |
314 | memcpy(&header, head, sizeof(header)); | |
315 | le32_to_cpus(&header); | |
316 | packet = head + sizeof(header); | |
317 | skb_pull(skb, 4); | |
318 | } | |
319 | ||
320 | if (skb->len < 0) { | |
321 | deverr(dev,"asix_rx_fixup() Bad SKB Length %d", skb->len); | |
322 | return 0; | |
323 | } | |
324 | return 1; | |
325 | } | |
326 | ||
327 | static struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb, | |
328 | gfp_t flags) | |
329 | { | |
330 | int padlen; | |
331 | int headroom = skb_headroom(skb); | |
332 | int tailroom = skb_tailroom(skb); | |
333 | u32 packet_len; | |
334 | u32 padbytes = 0xffff0000; | |
335 | ||
336 | padlen = ((skb->len + 4) % 512) ? 0 : 4; | |
337 | ||
338 | if ((!skb_cloned(skb)) | |
339 | && ((headroom + tailroom) >= (4 + padlen))) { | |
340 | if ((headroom < 4) || (tailroom < padlen)) { | |
341 | skb->data = memmove(skb->head + 4, skb->data, skb->len); | |
342 | skb->tail = skb->data + skb->len; | |
343 | } | |
344 | } else { | |
345 | struct sk_buff *skb2; | |
346 | skb2 = skb_copy_expand(skb, 4, padlen, flags); | |
347 | dev_kfree_skb_any(skb); | |
348 | skb = skb2; | |
349 | if (!skb) | |
350 | return NULL; | |
351 | } | |
352 | ||
353 | skb_push(skb, 4); | |
354 | packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); | |
355 | memcpy(skb->data, &packet_len, sizeof(packet_len)); | |
356 | ||
357 | if ((skb->len % 512) == 0) { | |
358 | memcpy( skb->tail, &padbytes, sizeof(padbytes)); | |
359 | skb_put(skb, sizeof(padbytes)); | |
360 | } | |
361 | return skb; | |
362 | } | |
363 | ||
364 | static void asix_status(struct usbnet *dev, struct urb *urb) | |
365 | { | |
366 | struct ax88172_int_data *event; | |
367 | int link; | |
368 | ||
369 | if (urb->actual_length < 8) | |
370 | return; | |
371 | ||
372 | event = urb->transfer_buffer; | |
373 | link = event->link & 0x01; | |
374 | if (netif_carrier_ok(dev->net) != link) { | |
375 | if (link) { | |
376 | netif_carrier_on(dev->net); | |
377 | usbnet_defer_kevent (dev, EVENT_LINK_RESET ); | |
378 | } else | |
379 | netif_carrier_off(dev->net); | |
380 | devdbg(dev, "Link Status is: %d", link); | |
381 | } | |
382 | } | |
383 | ||
48b1be6a DH |
384 | static inline int asix_set_sw_mii(struct usbnet *dev) |
385 | { | |
386 | int ret; | |
387 | ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); | |
388 | if (ret < 0) | |
933a27d3 | 389 | deverr(dev, "Failed to enable software MII access"); |
48b1be6a DH |
390 | return ret; |
391 | } | |
392 | ||
393 | static inline int asix_set_hw_mii(struct usbnet *dev) | |
394 | { | |
395 | int ret; | |
396 | ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); | |
397 | if (ret < 0) | |
933a27d3 | 398 | deverr(dev, "Failed to enable hardware MII access"); |
48b1be6a DH |
399 | return ret; |
400 | } | |
401 | ||
933a27d3 | 402 | static inline int asix_get_phy_addr(struct usbnet *dev) |
48b1be6a DH |
403 | { |
404 | int ret = 0; | |
405 | void *buf; | |
406 | ||
933a27d3 DH |
407 | devdbg(dev, "asix_get_phy_addr()"); |
408 | ||
48b1be6a DH |
409 | buf = kmalloc(2, GFP_KERNEL); |
410 | if (!buf) | |
411 | goto out1; | |
412 | ||
413 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, | |
414 | 0, 0, 2, buf)) < 2) { | |
933a27d3 | 415 | deverr(dev, "Error reading PHYID register: %02x", ret); |
48b1be6a DH |
416 | goto out2; |
417 | } | |
933a27d3 | 418 | devdbg(dev, "asix_get_phy_addr() returning 0x%04x", *((u16 *)buf)); |
48b1be6a DH |
419 | ret = *((u8 *)buf + 1); |
420 | out2: | |
421 | kfree(buf); | |
422 | out1: | |
423 | return ret; | |
424 | } | |
425 | ||
426 | static int asix_sw_reset(struct usbnet *dev, u8 flags) | |
427 | { | |
428 | int ret; | |
429 | ||
430 | ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL); | |
431 | if (ret < 0) | |
933a27d3 DH |
432 | deverr(dev,"Failed to send software reset: %02x", ret); |
433 | ||
434 | return ret; | |
435 | } | |
48b1be6a | 436 | |
933a27d3 DH |
437 | static u16 asix_read_rx_ctl(struct usbnet *dev) |
438 | { | |
439 | u16 ret = 0; | |
440 | void *buf; | |
441 | ||
442 | buf = kmalloc(2, GFP_KERNEL); | |
443 | if (!buf) | |
444 | goto out1; | |
445 | ||
446 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, | |
447 | 0, 0, 2, buf)) < 2) { | |
448 | deverr(dev, "Error reading RX_CTL register: %02x", ret); | |
449 | goto out2; | |
450 | } | |
451 | ret = le16_to_cpu(*((u16 *)buf)); | |
452 | out2: | |
453 | kfree(buf); | |
454 | out1: | |
48b1be6a DH |
455 | return ret; |
456 | } | |
457 | ||
458 | static int asix_write_rx_ctl(struct usbnet *dev, u16 mode) | |
459 | { | |
460 | int ret; | |
461 | ||
933a27d3 | 462 | devdbg(dev,"asix_write_rx_ctl() - mode = 0x%04x", mode); |
48b1be6a DH |
463 | ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); |
464 | if (ret < 0) | |
933a27d3 DH |
465 | deverr(dev, "Failed to write RX_CTL mode to 0x%04x: %02x", |
466 | mode, ret); | |
48b1be6a DH |
467 | |
468 | return ret; | |
469 | } | |
470 | ||
933a27d3 | 471 | static u16 asix_read_medium_status(struct usbnet *dev) |
2e55cc72 | 472 | { |
933a27d3 DH |
473 | u16 ret = 0; |
474 | void *buf; | |
2e55cc72 | 475 | |
933a27d3 DH |
476 | buf = kmalloc(2, GFP_KERNEL); |
477 | if (!buf) | |
478 | goto out1; | |
2e55cc72 | 479 | |
933a27d3 DH |
480 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_MEDIUM_STATUS, |
481 | 0, 0, 2, buf)) < 2) { | |
482 | deverr(dev, "Error reading Medium Status register: %02x", ret); | |
483 | goto out2; | |
2e55cc72 | 484 | } |
933a27d3 DH |
485 | ret = le16_to_cpu(*((u16 *)buf)); |
486 | out2: | |
487 | kfree(buf); | |
488 | out1: | |
489 | return ret; | |
2e55cc72 DB |
490 | } |
491 | ||
933a27d3 | 492 | static int asix_write_medium_mode(struct usbnet *dev, u16 mode) |
2e55cc72 | 493 | { |
933a27d3 | 494 | int ret; |
2e55cc72 | 495 | |
933a27d3 DH |
496 | devdbg(dev,"asix_write_medium_mode() - mode = 0x%04x", mode); |
497 | ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); | |
498 | if (ret < 0) | |
499 | deverr(dev, "Failed to write Medium Mode mode to 0x%04x: %02x", | |
500 | mode, ret); | |
2e55cc72 | 501 | |
933a27d3 DH |
502 | return ret; |
503 | } | |
2e55cc72 | 504 | |
933a27d3 DH |
505 | static int asix_write_gpio(struct usbnet *dev, u16 value, int sleep) |
506 | { | |
507 | int ret; | |
2e55cc72 | 508 | |
933a27d3 DH |
509 | devdbg(dev,"asix_write_gpio() - value = 0x%04x", value); |
510 | ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL); | |
511 | if (ret < 0) | |
512 | deverr(dev, "Failed to write GPIO value 0x%04x: %02x", | |
513 | value, ret); | |
2e55cc72 | 514 | |
933a27d3 DH |
515 | if (sleep) |
516 | msleep(sleep); | |
517 | ||
518 | return ret; | |
2e55cc72 DB |
519 | } |
520 | ||
933a27d3 DH |
521 | /* |
522 | * AX88772 & AX88178 have a 16-bit RX_CTL value | |
523 | */ | |
48b1be6a | 524 | static void asix_set_multicast(struct net_device *net) |
2e55cc72 DB |
525 | { |
526 | struct usbnet *dev = netdev_priv(net); | |
48b1be6a | 527 | struct asix_data *data = (struct asix_data *)&dev->data; |
933a27d3 | 528 | u16 rx_ctl = AX_DEFAULT_RX_CTL; |
2e55cc72 DB |
529 | |
530 | if (net->flags & IFF_PROMISC) { | |
933a27d3 | 531 | rx_ctl |= AX_RX_CTL_PRO; |
2e55cc72 DB |
532 | } else if (net->flags & IFF_ALLMULTI |
533 | || net->mc_count > AX_MAX_MCAST) { | |
933a27d3 | 534 | rx_ctl |= AX_RX_CTL_AMALL; |
2e55cc72 DB |
535 | } else if (net->mc_count == 0) { |
536 | /* just broadcast and directed */ | |
537 | } else { | |
538 | /* We use the 20 byte dev->data | |
539 | * for our 8 byte filter buffer | |
540 | * to avoid allocating memory that | |
541 | * is tricky to free later */ | |
542 | struct dev_mc_list *mc_list = net->mc_list; | |
543 | u32 crc_bits; | |
544 | int i; | |
545 | ||
546 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
547 | ||
548 | /* Build the multicast hash filter. */ | |
549 | for (i = 0; i < net->mc_count; i++) { | |
550 | crc_bits = | |
551 | ether_crc(ETH_ALEN, | |
552 | mc_list->dmi_addr) >> 26; | |
553 | data->multi_filter[crc_bits >> 3] |= | |
554 | 1 << (crc_bits & 7); | |
555 | mc_list = mc_list->next; | |
556 | } | |
557 | ||
48b1be6a | 558 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, |
2e55cc72 DB |
559 | AX_MCAST_FILTER_SIZE, data->multi_filter); |
560 | ||
933a27d3 | 561 | rx_ctl |= AX_RX_CTL_AM; |
2e55cc72 DB |
562 | } |
563 | ||
48b1be6a | 564 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); |
2e55cc72 DB |
565 | } |
566 | ||
48b1be6a | 567 | static int asix_mdio_read(struct net_device *netdev, int phy_id, int loc) |
2e55cc72 DB |
568 | { |
569 | struct usbnet *dev = netdev_priv(netdev); | |
570 | u16 res; | |
2e55cc72 | 571 | |
48b1be6a DH |
572 | asix_set_sw_mii(dev); |
573 | asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, | |
2e55cc72 | 574 | (__u16)loc, 2, (u16 *)&res); |
48b1be6a | 575 | asix_set_hw_mii(dev); |
2e55cc72 | 576 | |
933a27d3 | 577 | devdbg(dev, "asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x", phy_id, loc, le16_to_cpu(res & 0xffff)); |
2e55cc72 | 578 | |
933a27d3 | 579 | return le16_to_cpu(res & 0xffff); |
2e55cc72 DB |
580 | } |
581 | ||
582 | static void | |
48b1be6a | 583 | asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val) |
2e55cc72 DB |
584 | { |
585 | struct usbnet *dev = netdev_priv(netdev); | |
933a27d3 | 586 | u16 res = cpu_to_le16(val); |
2e55cc72 | 587 | |
933a27d3 | 588 | devdbg(dev, "asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x", phy_id, loc, val); |
48b1be6a DH |
589 | asix_set_sw_mii(dev); |
590 | asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, | |
2e55cc72 | 591 | (__u16)loc, 2, (u16 *)&res); |
48b1be6a | 592 | asix_set_hw_mii(dev); |
2e55cc72 DB |
593 | } |
594 | ||
933a27d3 DH |
595 | /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ |
596 | static u32 asix_get_phyid(struct usbnet *dev) | |
2e55cc72 | 597 | { |
933a27d3 DH |
598 | int phy_reg; |
599 | u32 phy_id; | |
2e55cc72 | 600 | |
933a27d3 DH |
601 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); |
602 | if (phy_reg < 0) | |
603 | return 0; | |
2e55cc72 | 604 | |
933a27d3 | 605 | phy_id = (phy_reg & 0xffff) << 16; |
2e55cc72 | 606 | |
933a27d3 DH |
607 | phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); |
608 | if (phy_reg < 0) | |
609 | return 0; | |
610 | ||
611 | phy_id |= (phy_reg & 0xffff); | |
612 | ||
613 | return phy_id; | |
2e55cc72 DB |
614 | } |
615 | ||
616 | static void | |
48b1be6a | 617 | asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
618 | { |
619 | struct usbnet *dev = netdev_priv(net); | |
620 | u8 opt; | |
621 | ||
48b1be6a | 622 | if (asix_read_cmd(dev, AX_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { |
2e55cc72 DB |
623 | wolinfo->supported = 0; |
624 | wolinfo->wolopts = 0; | |
625 | return; | |
626 | } | |
627 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC; | |
628 | wolinfo->wolopts = 0; | |
629 | if (opt & AX_MONITOR_MODE) { | |
630 | if (opt & AX_MONITOR_LINK) | |
631 | wolinfo->wolopts |= WAKE_PHY; | |
632 | if (opt & AX_MONITOR_MAGIC) | |
633 | wolinfo->wolopts |= WAKE_MAGIC; | |
634 | } | |
635 | } | |
636 | ||
637 | static int | |
48b1be6a | 638 | asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) |
2e55cc72 DB |
639 | { |
640 | struct usbnet *dev = netdev_priv(net); | |
641 | u8 opt = 0; | |
642 | u8 buf[1]; | |
643 | ||
644 | if (wolinfo->wolopts & WAKE_PHY) | |
645 | opt |= AX_MONITOR_LINK; | |
646 | if (wolinfo->wolopts & WAKE_MAGIC) | |
647 | opt |= AX_MONITOR_MAGIC; | |
648 | if (opt != 0) | |
649 | opt |= AX_MONITOR_MODE; | |
650 | ||
48b1be6a | 651 | if (asix_write_cmd(dev, AX_CMD_WRITE_MONITOR_MODE, |
2e55cc72 DB |
652 | opt, 0, 0, &buf) < 0) |
653 | return -EINVAL; | |
654 | ||
655 | return 0; | |
656 | } | |
657 | ||
48b1be6a | 658 | static int asix_get_eeprom_len(struct net_device *net) |
2e55cc72 | 659 | { |
933a27d3 DH |
660 | struct usbnet *dev = netdev_priv(net); |
661 | struct asix_data *data = (struct asix_data *)&dev->data; | |
662 | ||
663 | return data->eeprom_len; | |
2e55cc72 DB |
664 | } |
665 | ||
48b1be6a | 666 | static int asix_get_eeprom(struct net_device *net, |
2e55cc72 DB |
667 | struct ethtool_eeprom *eeprom, u8 *data) |
668 | { | |
669 | struct usbnet *dev = netdev_priv(net); | |
670 | u16 *ebuf = (u16 *)data; | |
671 | int i; | |
672 | ||
673 | /* Crude hack to ensure that we don't overwrite memory | |
674 | * if an odd length is supplied | |
675 | */ | |
676 | if (eeprom->len % 2) | |
677 | return -EINVAL; | |
678 | ||
679 | eeprom->magic = AX_EEPROM_MAGIC; | |
680 | ||
681 | /* ax8817x returns 2 bytes from eeprom on read */ | |
682 | for (i=0; i < eeprom->len / 2; i++) { | |
48b1be6a | 683 | if (asix_read_cmd(dev, AX_CMD_READ_EEPROM, |
2e55cc72 DB |
684 | eeprom->offset + i, 0, 2, &ebuf[i]) < 0) |
685 | return -EINVAL; | |
686 | } | |
687 | return 0; | |
688 | } | |
689 | ||
48b1be6a | 690 | static void asix_get_drvinfo (struct net_device *net, |
2e55cc72 DB |
691 | struct ethtool_drvinfo *info) |
692 | { | |
933a27d3 DH |
693 | struct usbnet *dev = netdev_priv(net); |
694 | struct asix_data *data = (struct asix_data *)&dev->data; | |
695 | ||
2e55cc72 DB |
696 | /* Inherit standard device info */ |
697 | usbnet_get_drvinfo(net, info); | |
933a27d3 DH |
698 | strncpy (info->driver, driver_name, sizeof info->driver); |
699 | strncpy (info->version, DRIVER_VERSION, sizeof info->version); | |
700 | info->eedump_len = data->eeprom_len; | |
2e55cc72 DB |
701 | } |
702 | ||
48b1be6a | 703 | static int asix_get_settings(struct net_device *net, struct ethtool_cmd *cmd) |
2e55cc72 DB |
704 | { |
705 | struct usbnet *dev = netdev_priv(net); | |
706 | ||
707 | return mii_ethtool_gset(&dev->mii,cmd); | |
708 | } | |
709 | ||
48b1be6a | 710 | static int asix_set_settings(struct net_device *net, struct ethtool_cmd *cmd) |
2e55cc72 DB |
711 | { |
712 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
713 | int res = mii_ethtool_sset(&dev->mii,cmd); |
714 | ||
715 | /* link speed/duplex might have changed */ | |
716 | if (dev->driver_info->link_reset) | |
717 | dev->driver_info->link_reset(dev); | |
2e55cc72 | 718 | |
933a27d3 | 719 | return res; |
2e55cc72 DB |
720 | } |
721 | ||
933a27d3 DH |
722 | static int asix_nway_reset(struct net_device *net) |
723 | { | |
724 | struct usbnet *dev = netdev_priv(net); | |
725 | ||
726 | return mii_nway_restart(&dev->mii); | |
727 | } | |
728 | ||
729 | static u32 asix_get_link(struct net_device *net) | |
730 | { | |
731 | struct usbnet *dev = netdev_priv(net); | |
732 | ||
733 | return mii_link_ok(&dev->mii); | |
734 | } | |
735 | ||
736 | static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd) | |
737 | { | |
738 | struct usbnet *dev = netdev_priv(net); | |
739 | ||
740 | return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); | |
741 | } | |
742 | ||
743 | /* We need to override some ethtool_ops so we require our | |
744 | own structure so we don't interfere with other usbnet | |
745 | devices that may be connected at the same time. */ | |
746 | static struct ethtool_ops ax88172_ethtool_ops = { | |
747 | .get_drvinfo = asix_get_drvinfo, | |
748 | .get_link = asix_get_link, | |
749 | .nway_reset = asix_nway_reset, | |
750 | .get_msglevel = usbnet_get_msglevel, | |
2e55cc72 | 751 | .set_msglevel = usbnet_set_msglevel, |
48b1be6a DH |
752 | .get_wol = asix_get_wol, |
753 | .set_wol = asix_set_wol, | |
754 | .get_eeprom_len = asix_get_eeprom_len, | |
755 | .get_eeprom = asix_get_eeprom, | |
756 | .get_settings = asix_get_settings, | |
757 | .set_settings = asix_set_settings, | |
2e55cc72 DB |
758 | }; |
759 | ||
933a27d3 | 760 | static void ax88172_set_multicast(struct net_device *net) |
2e55cc72 DB |
761 | { |
762 | struct usbnet *dev = netdev_priv(net); | |
933a27d3 DH |
763 | struct asix_data *data = (struct asix_data *)&dev->data; |
764 | u8 rx_ctl = 0x8c; | |
2e55cc72 | 765 | |
933a27d3 DH |
766 | if (net->flags & IFF_PROMISC) { |
767 | rx_ctl |= 0x01; | |
768 | } else if (net->flags & IFF_ALLMULTI | |
769 | || net->mc_count > AX_MAX_MCAST) { | |
770 | rx_ctl |= 0x02; | |
771 | } else if (net->mc_count == 0) { | |
772 | /* just broadcast and directed */ | |
773 | } else { | |
774 | /* We use the 20 byte dev->data | |
775 | * for our 8 byte filter buffer | |
776 | * to avoid allocating memory that | |
777 | * is tricky to free later */ | |
778 | struct dev_mc_list *mc_list = net->mc_list; | |
779 | u32 crc_bits; | |
780 | int i; | |
781 | ||
782 | memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE); | |
783 | ||
784 | /* Build the multicast hash filter. */ | |
785 | for (i = 0; i < net->mc_count; i++) { | |
786 | crc_bits = | |
787 | ether_crc(ETH_ALEN, | |
788 | mc_list->dmi_addr) >> 26; | |
789 | data->multi_filter[crc_bits >> 3] |= | |
790 | 1 << (crc_bits & 7); | |
791 | mc_list = mc_list->next; | |
792 | } | |
793 | ||
794 | asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0, | |
795 | AX_MCAST_FILTER_SIZE, data->multi_filter); | |
796 | ||
797 | rx_ctl |= 0x10; | |
798 | } | |
799 | ||
800 | asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); | |
801 | } | |
802 | ||
803 | static int ax88172_link_reset(struct usbnet *dev) | |
804 | { | |
805 | u8 mode; | |
806 | struct ethtool_cmd ecmd; | |
807 | ||
808 | mii_check_media(&dev->mii, 1, 1); | |
809 | mii_ethtool_gset(&dev->mii, &ecmd); | |
810 | mode = AX88172_MEDIUM_DEFAULT; | |
811 | ||
812 | if (ecmd.duplex != DUPLEX_FULL) | |
813 | mode |= ~AX88172_MEDIUM_FD; | |
814 | ||
815 | devdbg(dev, "ax88172_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
816 | ||
817 | asix_write_medium_mode(dev, mode); | |
818 | ||
819 | return 0; | |
2e55cc72 DB |
820 | } |
821 | ||
48b1be6a | 822 | static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf) |
2e55cc72 DB |
823 | { |
824 | int ret = 0; | |
825 | void *buf; | |
826 | int i; | |
827 | unsigned long gpio_bits = dev->driver_info->data; | |
933a27d3 DH |
828 | struct asix_data *data = (struct asix_data *)&dev->data; |
829 | ||
830 | data->eeprom_len = AX88172_EEPROM_LEN; | |
2e55cc72 DB |
831 | |
832 | usbnet_get_endpoints(dev,intf); | |
833 | ||
834 | buf = kmalloc(ETH_ALEN, GFP_KERNEL); | |
835 | if(!buf) { | |
836 | ret = -ENOMEM; | |
837 | goto out1; | |
838 | } | |
839 | ||
840 | /* Toggle the GPIOs in a manufacturer/model specific way */ | |
841 | for (i = 2; i >= 0; i--) { | |
48b1be6a | 842 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, |
2e55cc72 DB |
843 | (gpio_bits >> (i * 8)) & 0xff, 0, 0, |
844 | buf)) < 0) | |
845 | goto out2; | |
846 | msleep(5); | |
847 | } | |
848 | ||
933a27d3 | 849 | if ((ret = asix_write_rx_ctl(dev, 0x80)) < 0) |
2e55cc72 | 850 | goto out2; |
2e55cc72 DB |
851 | |
852 | /* Get the MAC address */ | |
853 | memset(buf, 0, ETH_ALEN); | |
933a27d3 | 854 | if ((ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, |
2e55cc72 DB |
855 | 0, 0, 6, buf)) < 0) { |
856 | dbg("read AX_CMD_READ_NODE_ID failed: %d", ret); | |
857 | goto out2; | |
858 | } | |
859 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
860 | ||
2e55cc72 DB |
861 | /* Initialize MII structure */ |
862 | dev->mii.dev = dev->net; | |
48b1be6a DH |
863 | dev->mii.mdio_read = asix_mdio_read; |
864 | dev->mii.mdio_write = asix_mdio_write; | |
2e55cc72 DB |
865 | dev->mii.phy_id_mask = 0x3f; |
866 | dev->mii.reg_num_mask = 0x1f; | |
933a27d3 | 867 | dev->mii.phy_id = asix_get_phy_addr(dev); |
48b1be6a | 868 | dev->net->do_ioctl = asix_ioctl; |
2e55cc72 | 869 | |
933a27d3 | 870 | dev->net->set_multicast_list = ax88172_set_multicast; |
48b1be6a | 871 | dev->net->ethtool_ops = &ax88172_ethtool_ops; |
2e55cc72 | 872 | |
933a27d3 DH |
873 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
874 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
875 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); |
876 | mii_nway_restart(&dev->mii); | |
877 | ||
878 | return 0; | |
879 | out2: | |
880 | kfree(buf); | |
881 | out1: | |
882 | return ret; | |
883 | } | |
884 | ||
885 | static struct ethtool_ops ax88772_ethtool_ops = { | |
48b1be6a | 886 | .get_drvinfo = asix_get_drvinfo, |
933a27d3 DH |
887 | .get_link = asix_get_link, |
888 | .nway_reset = asix_nway_reset, | |
2e55cc72 DB |
889 | .get_msglevel = usbnet_get_msglevel, |
890 | .set_msglevel = usbnet_set_msglevel, | |
48b1be6a DH |
891 | .get_wol = asix_get_wol, |
892 | .set_wol = asix_set_wol, | |
893 | .get_eeprom_len = asix_get_eeprom_len, | |
894 | .get_eeprom = asix_get_eeprom, | |
895 | .get_settings = asix_get_settings, | |
896 | .set_settings = asix_set_settings, | |
2e55cc72 DB |
897 | }; |
898 | ||
933a27d3 DH |
899 | static int ax88772_link_reset(struct usbnet *dev) |
900 | { | |
901 | u16 mode; | |
902 | struct ethtool_cmd ecmd; | |
903 | ||
904 | mii_check_media(&dev->mii, 1, 1); | |
905 | mii_ethtool_gset(&dev->mii, &ecmd); | |
906 | mode = AX88772_MEDIUM_DEFAULT; | |
907 | ||
908 | if (ecmd.speed != SPEED_100) | |
909 | mode &= ~AX_MEDIUM_PS; | |
910 | ||
911 | if (ecmd.duplex != DUPLEX_FULL) | |
912 | mode &= ~AX_MEDIUM_FD; | |
913 | ||
914 | devdbg(dev, "ax88772_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
915 | ||
916 | asix_write_medium_mode(dev, mode); | |
917 | ||
918 | return 0; | |
919 | } | |
920 | ||
2e55cc72 DB |
921 | static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf) |
922 | { | |
923 | int ret; | |
924 | void *buf; | |
933a27d3 DH |
925 | u16 rx_ctl; |
926 | struct asix_data *data = (struct asix_data *)&dev->data; | |
927 | u32 phyid; | |
928 | ||
929 | data->eeprom_len = AX88772_EEPROM_LEN; | |
2e55cc72 DB |
930 | |
931 | usbnet_get_endpoints(dev,intf); | |
932 | ||
933 | buf = kmalloc(6, GFP_KERNEL); | |
934 | if(!buf) { | |
935 | dbg ("Cannot allocate memory for buffer"); | |
936 | ret = -ENOMEM; | |
937 | goto out1; | |
938 | } | |
939 | ||
933a27d3 DH |
940 | if ((ret = asix_write_gpio(dev, |
941 | AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5)) < 0) | |
2e55cc72 DB |
942 | goto out2; |
943 | ||
48b1be6a | 944 | if ((ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, |
933a27d3 | 945 | 0x0000, 0, 0, buf)) < 0) { |
2e55cc72 DB |
946 | dbg("Select PHY #1 failed: %d", ret); |
947 | goto out2; | |
948 | } | |
949 | ||
48b1be6a | 950 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPPD)) < 0) |
2e55cc72 | 951 | goto out2; |
2e55cc72 DB |
952 | |
953 | msleep(150); | |
48b1be6a | 954 | if ((ret = asix_sw_reset(dev, AX_SWRESET_CLEAR)) < 0) |
2e55cc72 | 955 | goto out2; |
2e55cc72 DB |
956 | |
957 | msleep(150); | |
48b1be6a | 958 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0) |
2e55cc72 | 959 | goto out2; |
2e55cc72 DB |
960 | |
961 | msleep(150); | |
933a27d3 DH |
962 | rx_ctl = asix_read_rx_ctl(dev); |
963 | dbg("RX_CTL is 0x%04x after software reset", rx_ctl); | |
964 | if ((ret = asix_write_rx_ctl(dev, 0x0000)) < 0) | |
2e55cc72 | 965 | goto out2; |
2e55cc72 | 966 | |
933a27d3 DH |
967 | rx_ctl = asix_read_rx_ctl(dev); |
968 | dbg("RX_CTL is 0x%04x setting to 0x0000", rx_ctl); | |
969 | ||
2e55cc72 DB |
970 | /* Get the MAC address */ |
971 | memset(buf, 0, ETH_ALEN); | |
933a27d3 | 972 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, |
2e55cc72 DB |
973 | 0, 0, ETH_ALEN, buf)) < 0) { |
974 | dbg("Failed to read MAC address: %d", ret); | |
975 | goto out2; | |
976 | } | |
977 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); | |
978 | ||
2e55cc72 DB |
979 | /* Initialize MII structure */ |
980 | dev->mii.dev = dev->net; | |
48b1be6a DH |
981 | dev->mii.mdio_read = asix_mdio_read; |
982 | dev->mii.mdio_write = asix_mdio_write; | |
933a27d3 DH |
983 | dev->mii.phy_id_mask = 0x1f; |
984 | dev->mii.reg_num_mask = 0x1f; | |
48b1be6a | 985 | dev->net->do_ioctl = asix_ioctl; |
933a27d3 DH |
986 | dev->mii.phy_id = asix_get_phy_addr(dev); |
987 | ||
988 | phyid = asix_get_phyid(dev); | |
989 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 990 | |
48b1be6a | 991 | if ((ret = asix_sw_reset(dev, AX_SWRESET_PRL)) < 0) |
2e55cc72 | 992 | goto out2; |
2e55cc72 | 993 | |
2e55cc72 | 994 | msleep(150); |
48b1be6a DH |
995 | |
996 | if ((ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL)) < 0) | |
2e55cc72 | 997 | goto out2; |
2e55cc72 | 998 | |
48b1be6a | 999 | msleep(150); |
2e55cc72 | 1000 | |
48b1be6a | 1001 | dev->net->set_multicast_list = asix_set_multicast; |
2e55cc72 DB |
1002 | dev->net->ethtool_ops = &ax88772_ethtool_ops; |
1003 | ||
933a27d3 DH |
1004 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); |
1005 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
2e55cc72 DB |
1006 | ADVERTISE_ALL | ADVERTISE_CSMA); |
1007 | mii_nway_restart(&dev->mii); | |
1008 | ||
933a27d3 | 1009 | if ((ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT)) < 0) |
2e55cc72 | 1010 | goto out2; |
2e55cc72 | 1011 | |
48b1be6a | 1012 | if ((ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0, |
2e55cc72 DB |
1013 | AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, |
1014 | AX88772_IPG2_DEFAULT, 0, buf)) < 0) { | |
1015 | dbg("Write IPG,IPG1,IPG2 failed: %d", ret); | |
1016 | goto out2; | |
1017 | } | |
2e55cc72 DB |
1018 | |
1019 | /* Set RX_CTL to default values with 2k buffer, and enable cactus */ | |
933a27d3 | 1020 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) |
2e55cc72 | 1021 | goto out2; |
2e55cc72 | 1022 | |
933a27d3 DH |
1023 | rx_ctl = asix_read_rx_ctl(dev); |
1024 | dbg("RX_CTL is 0x%04x after all initializations", rx_ctl); | |
1025 | ||
1026 | rx_ctl = asix_read_medium_status(dev); | |
1027 | dbg("Medium Status is 0x%04x after all initializations", rx_ctl); | |
1028 | ||
2e55cc72 DB |
1029 | kfree(buf); |
1030 | ||
1031 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1032 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1033 | /* hard_mtu is still the default - the device does not support | |
1034 | jumbo eth frames */ | |
1035 | dev->rx_urb_size = 2048; | |
1036 | } | |
1037 | ||
1038 | return 0; | |
1039 | ||
1040 | out2: | |
1041 | kfree(buf); | |
1042 | out1: | |
1043 | return ret; | |
1044 | } | |
1045 | ||
933a27d3 DH |
1046 | static struct ethtool_ops ax88178_ethtool_ops = { |
1047 | .get_drvinfo = asix_get_drvinfo, | |
1048 | .get_link = asix_get_link, | |
1049 | .nway_reset = asix_nway_reset, | |
1050 | .get_msglevel = usbnet_get_msglevel, | |
1051 | .set_msglevel = usbnet_set_msglevel, | |
1052 | .get_wol = asix_get_wol, | |
1053 | .set_wol = asix_set_wol, | |
1054 | .get_eeprom_len = asix_get_eeprom_len, | |
1055 | .get_eeprom = asix_get_eeprom, | |
1056 | .get_settings = asix_get_settings, | |
1057 | .set_settings = asix_set_settings, | |
1058 | }; | |
1059 | ||
1060 | static int marvell_phy_init(struct usbnet *dev) | |
2e55cc72 | 1061 | { |
933a27d3 DH |
1062 | struct asix_data *data = (struct asix_data *)&dev->data; |
1063 | u16 reg; | |
2e55cc72 | 1064 | |
933a27d3 | 1065 | devdbg(dev,"marvell_phy_init()"); |
2e55cc72 | 1066 | |
933a27d3 DH |
1067 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS); |
1068 | devdbg(dev,"MII_MARVELL_STATUS = 0x%04x", reg); | |
2e55cc72 | 1069 | |
933a27d3 DH |
1070 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL, |
1071 | MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY); | |
2e55cc72 | 1072 | |
933a27d3 DH |
1073 | if (data->ledmode) { |
1074 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, | |
1075 | MII_MARVELL_LED_CTRL); | |
1076 | devdbg(dev,"MII_MARVELL_LED_CTRL (1) = 0x%04x", reg); | |
2e55cc72 | 1077 | |
933a27d3 DH |
1078 | reg &= 0xf8ff; |
1079 | reg |= (1 + 0x0100); | |
1080 | asix_mdio_write(dev->net, dev->mii.phy_id, | |
1081 | MII_MARVELL_LED_CTRL, reg); | |
2e55cc72 | 1082 | |
933a27d3 DH |
1083 | reg = asix_mdio_read(dev->net, dev->mii.phy_id, |
1084 | MII_MARVELL_LED_CTRL); | |
1085 | devdbg(dev,"MII_MARVELL_LED_CTRL (2) = 0x%04x", reg); | |
1086 | reg &= 0xfc0f; | |
1087 | } | |
2e55cc72 | 1088 | |
933a27d3 DH |
1089 | return 0; |
1090 | } | |
1091 | ||
1092 | static int marvell_led_status(struct usbnet *dev, u16 speed) | |
1093 | { | |
1094 | u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL); | |
1095 | ||
1096 | devdbg(dev, "marvell_led_status() read 0x%04x", reg); | |
1097 | ||
1098 | /* Clear out the center LED bits - 0x03F0 */ | |
1099 | reg &= 0xfc0f; | |
1100 | ||
1101 | switch (speed) { | |
1102 | case SPEED_1000: | |
1103 | reg |= 0x03e0; | |
1104 | break; | |
1105 | case SPEED_100: | |
1106 | reg |= 0x03b0; | |
1107 | break; | |
1108 | default: | |
1109 | reg |= 0x02f0; | |
2e55cc72 DB |
1110 | } |
1111 | ||
933a27d3 DH |
1112 | devdbg(dev, "marvell_led_status() writing 0x%04x", reg); |
1113 | asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg); | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static int ax88178_link_reset(struct usbnet *dev) | |
1119 | { | |
1120 | u16 mode; | |
1121 | struct ethtool_cmd ecmd; | |
1122 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1123 | ||
1124 | devdbg(dev,"ax88178_link_reset()"); | |
1125 | ||
1126 | mii_check_media(&dev->mii, 1, 1); | |
1127 | mii_ethtool_gset(&dev->mii, &ecmd); | |
1128 | mode = AX88178_MEDIUM_DEFAULT; | |
1129 | ||
1130 | if (ecmd.speed == SPEED_1000) | |
1131 | mode |= AX_MEDIUM_GM | AX_MEDIUM_ENCK; | |
1132 | else if (ecmd.speed == SPEED_100) | |
1133 | mode |= AX_MEDIUM_PS; | |
1134 | else | |
1135 | mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM); | |
1136 | ||
1137 | if (ecmd.duplex == DUPLEX_FULL) | |
1138 | mode |= AX_MEDIUM_FD; | |
1139 | else | |
1140 | mode &= ~AX_MEDIUM_FD; | |
1141 | ||
1142 | devdbg(dev, "ax88178_link_reset() speed: %d duplex: %d setting mode to 0x%04x", ecmd.speed, ecmd.duplex, mode); | |
1143 | ||
1144 | asix_write_medium_mode(dev, mode); | |
1145 | ||
1146 | if (data->phymode == PHY_MODE_MARVELL && data->ledmode) | |
1147 | marvell_led_status(dev, ecmd.speed); | |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | static void ax88178_set_mfb(struct usbnet *dev) | |
1153 | { | |
1154 | u16 mfb = AX_RX_CTL_MFB_16384; | |
1155 | u16 rxctl; | |
1156 | u16 medium; | |
1157 | int old_rx_urb_size = dev->rx_urb_size; | |
1158 | ||
1159 | if (dev->hard_mtu < 2048) { | |
1160 | dev->rx_urb_size = 2048; | |
1161 | mfb = AX_RX_CTL_MFB_2048; | |
1162 | } else if (dev->hard_mtu < 4096) { | |
1163 | dev->rx_urb_size = 4096; | |
1164 | mfb = AX_RX_CTL_MFB_4096; | |
1165 | } else if (dev->hard_mtu < 8192) { | |
1166 | dev->rx_urb_size = 8192; | |
1167 | mfb = AX_RX_CTL_MFB_8192; | |
1168 | } else if (dev->hard_mtu < 16384) { | |
1169 | dev->rx_urb_size = 16384; | |
1170 | mfb = AX_RX_CTL_MFB_16384; | |
2e55cc72 | 1171 | } |
933a27d3 DH |
1172 | |
1173 | rxctl = asix_read_rx_ctl(dev); | |
1174 | asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb); | |
1175 | ||
1176 | medium = asix_read_medium_status(dev); | |
1177 | if (dev->net->mtu > 1500) | |
1178 | medium |= AX_MEDIUM_JFE; | |
1179 | else | |
1180 | medium &= ~AX_MEDIUM_JFE; | |
1181 | asix_write_medium_mode(dev, medium); | |
1182 | ||
1183 | if (dev->rx_urb_size > old_rx_urb_size) | |
1184 | usbnet_unlink_rx_urbs(dev); | |
2e55cc72 DB |
1185 | } |
1186 | ||
933a27d3 | 1187 | static int ax88178_change_mtu(struct net_device *net, int new_mtu) |
2e55cc72 | 1188 | { |
933a27d3 DH |
1189 | struct usbnet *dev = netdev_priv(net); |
1190 | int ll_mtu = new_mtu + net->hard_header_len + 4; | |
2e55cc72 | 1191 | |
933a27d3 | 1192 | devdbg(dev, "ax88178_change_mtu() new_mtu=%d", new_mtu); |
2e55cc72 | 1193 | |
933a27d3 DH |
1194 | if (new_mtu <= 0 || ll_mtu > 16384) |
1195 | return -EINVAL; | |
1196 | ||
1197 | if ((ll_mtu % dev->maxpacket) == 0) | |
1198 | return -EDOM; | |
1199 | ||
1200 | net->mtu = new_mtu; | |
1201 | dev->hard_mtu = net->mtu + net->hard_header_len; | |
1202 | ax88178_set_mfb(dev); | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf) | |
1208 | { | |
1209 | struct asix_data *data = (struct asix_data *)&dev->data; | |
1210 | int ret; | |
1211 | void *buf; | |
1212 | u16 eeprom; | |
1213 | int gpio0 = 0; | |
1214 | u32 phyid; | |
1215 | ||
1216 | usbnet_get_endpoints(dev,intf); | |
1217 | ||
1218 | buf = kmalloc(6, GFP_KERNEL); | |
1219 | if(!buf) { | |
1220 | dbg ("Cannot allocate memory for buffer"); | |
1221 | ret = -ENOMEM; | |
1222 | goto out1; | |
1223 | } | |
1224 | ||
1225 | eeprom = 0; | |
1226 | asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &eeprom); | |
1227 | dbg("GPIO Status: 0x%04x", eeprom); | |
1228 | ||
1229 | asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL); | |
1230 | asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom); | |
1231 | asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL); | |
1232 | ||
1233 | dbg("EEPROM index 0x17 is 0x%04x", eeprom); | |
1234 | ||
1235 | if (eeprom == 0xffff) { | |
1236 | data->phymode = PHY_MODE_MARVELL; | |
1237 | data->ledmode = 0; | |
1238 | gpio0 = 1; | |
2e55cc72 | 1239 | } else { |
933a27d3 DH |
1240 | data->phymode = eeprom & 7; |
1241 | data->ledmode = eeprom >> 8; | |
1242 | gpio0 = (eeprom & 0x80) ? 0 : 1; | |
2e55cc72 | 1243 | } |
933a27d3 | 1244 | dbg("GPIO0: %d, PhyMode: %d", gpio0, data->phymode); |
2e55cc72 | 1245 | |
933a27d3 DH |
1246 | asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40); |
1247 | if ((eeprom >> 8) != 1) { | |
1248 | asix_write_gpio(dev, 0x003c, 30); | |
1249 | asix_write_gpio(dev, 0x001c, 300); | |
1250 | asix_write_gpio(dev, 0x003c, 30); | |
1251 | } else { | |
1252 | dbg("gpio phymode == 1 path"); | |
1253 | asix_write_gpio(dev, AX_GPIO_GPO1EN, 30); | |
1254 | asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30); | |
1255 | } | |
2e55cc72 | 1256 | |
933a27d3 DH |
1257 | asix_sw_reset(dev, 0); |
1258 | msleep(150); | |
1259 | ||
1260 | asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD); | |
1261 | msleep(150); | |
1262 | ||
1263 | asix_write_rx_ctl(dev, 0); | |
1264 | ||
1265 | /* Get the MAC address */ | |
1266 | memset(buf, 0, ETH_ALEN); | |
1267 | if ((ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, | |
1268 | 0, 0, ETH_ALEN, buf)) < 0) { | |
1269 | dbg("Failed to read MAC address: %d", ret); | |
1270 | goto out2; | |
2e55cc72 | 1271 | } |
933a27d3 | 1272 | memcpy(dev->net->dev_addr, buf, ETH_ALEN); |
2e55cc72 | 1273 | |
933a27d3 DH |
1274 | /* Initialize MII structure */ |
1275 | dev->mii.dev = dev->net; | |
1276 | dev->mii.mdio_read = asix_mdio_read; | |
1277 | dev->mii.mdio_write = asix_mdio_write; | |
1278 | dev->mii.phy_id_mask = 0x1f; | |
1279 | dev->mii.reg_num_mask = 0xff; | |
1280 | dev->mii.supports_gmii = 1; | |
1281 | dev->net->do_ioctl = asix_ioctl; | |
1282 | dev->mii.phy_id = asix_get_phy_addr(dev); | |
1283 | dev->net->set_multicast_list = asix_set_multicast; | |
1284 | dev->net->ethtool_ops = &ax88178_ethtool_ops; | |
1285 | dev->net->change_mtu = &ax88178_change_mtu; | |
2e55cc72 | 1286 | |
933a27d3 DH |
1287 | phyid = asix_get_phyid(dev); |
1288 | dbg("PHYID=0x%08x", phyid); | |
2e55cc72 | 1289 | |
933a27d3 DH |
1290 | if (data->phymode == PHY_MODE_MARVELL) { |
1291 | marvell_phy_init(dev); | |
1292 | msleep(60); | |
1293 | } | |
1294 | ||
1295 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, | |
1296 | BMCR_RESET | BMCR_ANENABLE); | |
1297 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, | |
1298 | ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
1299 | asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000, | |
1300 | ADVERTISE_1000FULL); | |
1301 | ||
1302 | mii_nway_restart(&dev->mii); | |
1303 | ||
1304 | if ((ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT)) < 0) | |
1305 | goto out2; | |
1306 | ||
1307 | if ((ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL)) < 0) | |
1308 | goto out2; | |
1309 | ||
1310 | kfree(buf); | |
1311 | ||
1312 | /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */ | |
1313 | if (dev->driver_info->flags & FLAG_FRAMING_AX) { | |
1314 | /* hard_mtu is still the default - the device does not support | |
1315 | jumbo eth frames */ | |
1316 | dev->rx_urb_size = 2048; | |
1317 | } | |
2e55cc72 DB |
1318 | |
1319 | return 0; | |
933a27d3 DH |
1320 | |
1321 | out2: | |
1322 | kfree(buf); | |
1323 | out1: | |
1324 | return ret; | |
2e55cc72 DB |
1325 | } |
1326 | ||
1327 | static const struct driver_info ax8817x_info = { | |
1328 | .description = "ASIX AX8817x USB 2.0 Ethernet", | |
48b1be6a DH |
1329 | .bind = ax88172_bind, |
1330 | .status = asix_status, | |
2e55cc72 DB |
1331 | .link_reset = ax88172_link_reset, |
1332 | .reset = ax88172_link_reset, | |
1333 | .flags = FLAG_ETHER, | |
1334 | .data = 0x00130103, | |
1335 | }; | |
1336 | ||
1337 | static const struct driver_info dlink_dub_e100_info = { | |
1338 | .description = "DLink DUB-E100 USB Ethernet", | |
48b1be6a DH |
1339 | .bind = ax88172_bind, |
1340 | .status = asix_status, | |
2e55cc72 DB |
1341 | .link_reset = ax88172_link_reset, |
1342 | .reset = ax88172_link_reset, | |
1343 | .flags = FLAG_ETHER, | |
1344 | .data = 0x009f9d9f, | |
1345 | }; | |
1346 | ||
1347 | static const struct driver_info netgear_fa120_info = { | |
1348 | .description = "Netgear FA-120 USB Ethernet", | |
48b1be6a DH |
1349 | .bind = ax88172_bind, |
1350 | .status = asix_status, | |
2e55cc72 DB |
1351 | .link_reset = ax88172_link_reset, |
1352 | .reset = ax88172_link_reset, | |
1353 | .flags = FLAG_ETHER, | |
1354 | .data = 0x00130103, | |
1355 | }; | |
1356 | ||
1357 | static const struct driver_info hawking_uf200_info = { | |
1358 | .description = "Hawking UF200 USB Ethernet", | |
48b1be6a DH |
1359 | .bind = ax88172_bind, |
1360 | .status = asix_status, | |
2e55cc72 DB |
1361 | .link_reset = ax88172_link_reset, |
1362 | .reset = ax88172_link_reset, | |
1363 | .flags = FLAG_ETHER, | |
1364 | .data = 0x001f1d1f, | |
1365 | }; | |
1366 | ||
1367 | static const struct driver_info ax88772_info = { | |
1368 | .description = "ASIX AX88772 USB 2.0 Ethernet", | |
1369 | .bind = ax88772_bind, | |
48b1be6a | 1370 | .status = asix_status, |
2e55cc72 DB |
1371 | .link_reset = ax88772_link_reset, |
1372 | .reset = ax88772_link_reset, | |
1373 | .flags = FLAG_ETHER | FLAG_FRAMING_AX, | |
933a27d3 DH |
1374 | .rx_fixup = asix_rx_fixup, |
1375 | .tx_fixup = asix_tx_fixup, | |
1376 | }; | |
1377 | ||
1378 | static const struct driver_info ax88178_info = { | |
1379 | .description = "ASIX AX88178 USB 2.0 Ethernet", | |
1380 | .bind = ax88178_bind, | |
1381 | .status = asix_status, | |
1382 | .link_reset = ax88178_link_reset, | |
1383 | .reset = ax88178_link_reset, | |
1384 | .flags = FLAG_ETHER | FLAG_FRAMING_AX, | |
1385 | .rx_fixup = asix_rx_fixup, | |
1386 | .tx_fixup = asix_tx_fixup, | |
2e55cc72 DB |
1387 | }; |
1388 | ||
1389 | static const struct usb_device_id products [] = { | |
1390 | { | |
1391 | // Linksys USB200M | |
1392 | USB_DEVICE (0x077b, 0x2226), | |
1393 | .driver_info = (unsigned long) &ax8817x_info, | |
1394 | }, { | |
1395 | // Netgear FA120 | |
1396 | USB_DEVICE (0x0846, 0x1040), | |
1397 | .driver_info = (unsigned long) &netgear_fa120_info, | |
1398 | }, { | |
1399 | // DLink DUB-E100 | |
1400 | USB_DEVICE (0x2001, 0x1a00), | |
1401 | .driver_info = (unsigned long) &dlink_dub_e100_info, | |
1402 | }, { | |
1403 | // Intellinet, ST Lab USB Ethernet | |
1404 | USB_DEVICE (0x0b95, 0x1720), | |
1405 | .driver_info = (unsigned long) &ax8817x_info, | |
1406 | }, { | |
1407 | // Hawking UF200, TrendNet TU2-ET100 | |
1408 | USB_DEVICE (0x07b8, 0x420a), | |
1409 | .driver_info = (unsigned long) &hawking_uf200_info, | |
1410 | }, { | |
1411 | // Billionton Systems, USB2AR | |
1412 | USB_DEVICE (0x08dd, 0x90ff), | |
1413 | .driver_info = (unsigned long) &ax8817x_info, | |
1414 | }, { | |
1415 | // ATEN UC210T | |
1416 | USB_DEVICE (0x0557, 0x2009), | |
1417 | .driver_info = (unsigned long) &ax8817x_info, | |
1418 | }, { | |
1419 | // Buffalo LUA-U2-KTX | |
1420 | USB_DEVICE (0x0411, 0x003d), | |
1421 | .driver_info = (unsigned long) &ax8817x_info, | |
1422 | }, { | |
1423 | // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter" | |
1424 | USB_DEVICE (0x6189, 0x182d), | |
1425 | .driver_info = (unsigned long) &ax8817x_info, | |
1426 | }, { | |
1427 | // corega FEther USB2-TX | |
1428 | USB_DEVICE (0x07aa, 0x0017), | |
1429 | .driver_info = (unsigned long) &ax8817x_info, | |
1430 | }, { | |
1431 | // Surecom EP-1427X-2 | |
1432 | USB_DEVICE (0x1189, 0x0893), | |
1433 | .driver_info = (unsigned long) &ax8817x_info, | |
1434 | }, { | |
1435 | // goodway corp usb gwusb2e | |
1436 | USB_DEVICE (0x1631, 0x6200), | |
1437 | .driver_info = (unsigned long) &ax8817x_info, | |
1438 | }, { | |
1439 | // ASIX AX88772 10/100 | |
1440 | USB_DEVICE (0x0b95, 0x7720), | |
1441 | .driver_info = (unsigned long) &ax88772_info, | |
7327413c EW |
1442 | }, { |
1443 | // ASIX AX88178 10/100/1000 | |
1444 | USB_DEVICE (0x0b95, 0x1780), | |
933a27d3 | 1445 | .driver_info = (unsigned long) &ax88178_info, |
5e0f76c6 DH |
1446 | }, { |
1447 | // Linksys USB200M Rev 2 | |
1448 | USB_DEVICE (0x13b1, 0x0018), | |
1449 | .driver_info = (unsigned long) &ax88772_info, | |
5732ce84 DH |
1450 | }, { |
1451 | // 0Q0 cable ethernet | |
1452 | USB_DEVICE (0x1557, 0x7720), | |
1453 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1454 | }, { |
1455 | // DLink DUB-E100 H/W Ver B1 | |
1456 | USB_DEVICE (0x07d1, 0x3c05), | |
1457 | .driver_info = (unsigned long) &ax88772_info, | |
b923e7fc DH |
1458 | }, { |
1459 | // DLink DUB-E100 H/W Ver B1 Alternate | |
1460 | USB_DEVICE (0x2001, 0x3c05), | |
1461 | .driver_info = (unsigned long) &ax88772_info, | |
933a27d3 DH |
1462 | }, { |
1463 | // Linksys USB1000 | |
1464 | USB_DEVICE (0x1737, 0x0039), | |
1465 | .driver_info = (unsigned long) &ax88178_info, | |
2e55cc72 DB |
1466 | }, |
1467 | { }, // END | |
1468 | }; | |
1469 | MODULE_DEVICE_TABLE(usb, products); | |
1470 | ||
1471 | static struct usb_driver asix_driver = { | |
2e55cc72 DB |
1472 | .name = "asix", |
1473 | .id_table = products, | |
1474 | .probe = usbnet_probe, | |
1475 | .suspend = usbnet_suspend, | |
1476 | .resume = usbnet_resume, | |
1477 | .disconnect = usbnet_disconnect, | |
1478 | }; | |
1479 | ||
1480 | static int __init asix_init(void) | |
1481 | { | |
1482 | return usb_register(&asix_driver); | |
1483 | } | |
1484 | module_init(asix_init); | |
1485 | ||
1486 | static void __exit asix_exit(void) | |
1487 | { | |
1488 | usb_deregister(&asix_driver); | |
1489 | } | |
1490 | module_exit(asix_exit); | |
1491 | ||
1492 | MODULE_AUTHOR("David Hollis"); | |
1493 | MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices"); | |
1494 | MODULE_LICENSE("GPL"); | |
1495 |