[linux-2.6-block.git] / drivers / usb / musb / tusb6010_omap.c

// SPDX-License-Identifier: GPL-2.0
/*
 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/usb.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/dmaengine.h>

#include "musb_core.h"
#include "tusb6010.h"

#define to_chdat(c)		((struct tusb_omap_dma_ch *)(c)->private_data)

#define MAX_DMAREQ		5	/* REVISIT: Really 6, but req5 not OK */

struct tusb_dma_data {
	s8			dmareq;
	struct dma_chan		*chan;
};

struct tusb_omap_dma_ch {
	struct musb		*musb;
	void __iomem		*tbase;
	unsigned long		phys_offset;
	int			epnum;
	u8			tx;
	struct musb_hw_ep	*hw_ep;

	struct tusb_dma_data	*dma_data;

	struct tusb_omap_dma	*tusb_dma;

	dma_addr_t		dma_addr;

	u32			len;
	u16			packet_sz;
	u16			transfer_packet_sz;
	u32			transfer_len;
	u32			completed_len;
};

struct tusb_omap_dma {
	struct dma_controller		controller;
	void __iomem			*tbase;

	struct tusb_dma_data		dma_pool[MAX_DMAREQ];
	unsigned			multichannel:1;
};

/*
 * Allocate dmareq0 to the current channel unless it's already taken
 */
static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
{
	u32		reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);

	if (reg != 0) {
		dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
			chdat->epnum, reg & 0xf);
		return -EAGAIN;
	}

	if (chdat->tx)
		reg = (1 << 4) | chdat->epnum;
	else
		reg = chdat->epnum;

	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);

	return 0;
}

static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
{
	u32		reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);

	if ((reg & 0xf) != chdat->epnum) {
		printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
			chdat->epnum, reg & 0xf);
		return;
	}
	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
}

/*
 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in
 * musb_gadget.c.
 */
static void tusb_omap_dma_cb(void *data)
{
	struct dma_channel	*channel = (struct dma_channel *)data;
	struct tusb_omap_dma_ch	*chdat = to_chdat(channel);
	struct tusb_omap_dma	*tusb_dma = chdat->tusb_dma;
	struct musb		*musb = chdat->musb;
	struct device		*dev = musb->controller;
	struct musb_hw_ep	*hw_ep = chdat->hw_ep;
	void __iomem		*ep_conf = hw_ep->conf;
	void __iomem		*mbase = musb->mregs;
	unsigned long		remaining, flags, pio;

	spin_lock_irqsave(&musb->lock, flags);

	dev_dbg(musb->controller, "ep%i %s dma callback\n",
		chdat->epnum, chdat->tx ? "tx" : "rx");

	if (chdat->tx)
		remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
	else
		remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);

	remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);

	/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
	if (unlikely(remaining > chdat->transfer_len)) {
		dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n",
			chdat->tx ? "tx" : "rx", remaining);
		remaining = 0;
	}

	channel->actual_len = chdat->transfer_len - remaining;
	pio = chdat->len - channel->actual_len;

	dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);

	/* Transfer remaining 1 - 31 bytes */
	if (pio > 0 && pio < 32) {
		u8	*buf;

		dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
		buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
		if (chdat->tx) {
			dma_unmap_single(dev, chdat->dma_addr,
						chdat->transfer_len,
						DMA_TO_DEVICE);
			musb_write_fifo(hw_ep, pio, buf);
		} else {
			dma_unmap_single(dev, chdat->dma_addr,
						chdat->transfer_len,
						DMA_FROM_DEVICE);
			musb_read_fifo(hw_ep, pio, buf);
		}
		channel->actual_len += pio;
	}

	if (!tusb_dma->multichannel)
		tusb_omap_free_shared_dmareq(chdat);

	channel->status = MUSB_DMA_STATUS_FREE;

	musb_dma_completion(musb, chdat->epnum, chdat->tx);

	/* We must terminate short tx transfers manually by setting TXPKTRDY.
	 * REVISIT: This same problem may occur with other MUSB dma as well.
	 * Easy to test with g_ether by pinging the MUSB board with ping -s54.
	 */
	if ((chdat->transfer_len < chdat->packet_sz)
			|| (chdat->transfer_len % chdat->packet_sz != 0)) {
		u16	csr;

		if (chdat->tx) {
			dev_dbg(musb->controller, "terminating short tx packet\n");
			musb_ep_select(mbase, chdat->epnum);
			csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
			csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
				| MUSB_TXCSR_P_WZC_BITS;
			musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
		}
	}

	spin_unlock_irqrestore(&musb->lock, flags);
}

static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
				u8 rndis_mode, dma_addr_t dma_addr, u32 len)
{
	struct tusb_omap_dma_ch		*chdat = to_chdat(channel);
	struct tusb_omap_dma		*tusb_dma = chdat->tusb_dma;
	struct musb			*musb = chdat->musb;
	struct device			*dev = musb->controller;
	struct musb_hw_ep		*hw_ep = chdat->hw_ep;
	void __iomem			*mbase = musb->mregs;
	void __iomem			*ep_conf = hw_ep->conf;
	dma_addr_t			fifo_addr = hw_ep->fifo_sync;
	u32				dma_remaining;
	u16				csr;
	u32				psize;
	struct tusb_dma_data		*dma_data;
	struct dma_async_tx_descriptor	*dma_desc;
	struct dma_slave_config		dma_cfg;
	enum dma_transfer_direction	dma_dir;
	u32				port_window;
	int				ret;

	if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz))
		return false;

	/*
	 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE
	 * register which will cause missed DMA interrupt. We could try to
	 * use a timer for the callback, but it is unsafe as the XFR_SIZE
	 * register is corrupt, and we won't know if the DMA worked.
	 */
	if (dma_addr & 0x2)
		return false;

	/*
	 * Because of HW issue #10, it seems like mixing sync DMA and async
	 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
	 * using the channel for DMA.
	 */
	if (chdat->tx)
		dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
	else
		dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);

	dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
	if (dma_remaining) {
		dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n",
			chdat->tx ? "tx" : "rx", dma_remaining);
		return false;
	}

	chdat->transfer_len = len & ~0x1f;

	if (len < packet_sz)
		chdat->transfer_packet_sz = chdat->transfer_len;
	else
		chdat->transfer_packet_sz = packet_sz;

	dma_data = chdat->dma_data;
	if (!tusb_dma->multichannel) {
		if (tusb_omap_use_shared_dmareq(chdat) != 0) {
			dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
			return false;
		}
		if (dma_data->dmareq < 0) {
			/* REVISIT: This should get blocked earlier, happens
			 * with MSC ErrorRecoveryTest
			 */
			WARN_ON(1);
			return false;
		}
	}

	chdat->packet_sz = packet_sz;
	chdat->len = len;
	channel->actual_len = 0;
	chdat->dma_addr = dma_addr;
	channel->status = MUSB_DMA_STATUS_BUSY;

	/* Since we're recycling dma areas, we need to clean or invalidate */
	if (chdat->tx) {
		dma_dir = DMA_MEM_TO_DEV;
		dma_map_single(dev, phys_to_virt(dma_addr), len,
				DMA_TO_DEVICE);
	} else {
		dma_dir = DMA_DEV_TO_MEM;
		dma_map_single(dev, phys_to_virt(dma_addr), len,
				DMA_FROM_DEVICE);
	}

	memset(&dma_cfg, 0, sizeof(dma_cfg));

	/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
	if ((dma_addr & 0x3) == 0) {
		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		port_window = 8;
	} else {
		dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
		port_window = 16;

		fifo_addr = hw_ep->fifo_async;
	}

	dev_dbg(musb->controller,
		"ep%i %s dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
		chdat->epnum, chdat->tx ? "tx" : "rx", &dma_addr,
		chdat->transfer_len, len, chdat->transfer_packet_sz, packet_sz);

	dma_cfg.src_addr = fifo_addr;
	dma_cfg.dst_addr = fifo_addr;
	dma_cfg.src_port_window_size = port_window;
	dma_cfg.src_maxburst = port_window;
	dma_cfg.dst_port_window_size = port_window;
	dma_cfg.dst_maxburst = port_window;

	ret = dmaengine_slave_config(dma_data->chan, &dma_cfg);
	if (ret) {
		dev_err(musb->controller, "DMA slave config failed: %d\n", ret);
		return false;
	}

	dma_desc = dmaengine_prep_slave_single(dma_data->chan, dma_addr,
					chdat->transfer_len, dma_dir,
					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!dma_desc) {
		dev_err(musb->controller, "DMA prep_slave_single failed\n");
		return false;
	}

	dma_desc->callback = tusb_omap_dma_cb;
	dma_desc->callback_param = channel;
	dmaengine_submit(dma_desc);

	dev_dbg(musb->controller,
		"ep%i %s using %i-bit %s dma from %pad to %pad\n",
		chdat->epnum, chdat->tx ? "tx" : "rx",
		dma_cfg.src_addr_width * 8,
		((dma_addr & 0x3) == 0) ? "sync" : "async",
		(dma_dir == DMA_MEM_TO_DEV) ? &dma_addr : &fifo_addr,
		(dma_dir == DMA_MEM_TO_DEV) ? &fifo_addr : &dma_addr);

	/*
	 * Prepare MUSB for DMA transfer
	 */
	musb_ep_select(mbase, chdat->epnum);
	if (chdat->tx) {
		csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
		csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB
			| MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE);
		csr &= ~MUSB_TXCSR_P_UNDERRUN;
		musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
	} else {
		csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
		csr |= MUSB_RXCSR_DMAENAB;
		csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE);
		musb_writew(hw_ep->regs, MUSB_RXCSR,
			csr | MUSB_RXCSR_P_WZC_BITS);
	}

	/* Start DMA transfer */
	dma_async_issue_pending(dma_data->chan);

	if (chdat->tx) {
		/* Send transfer_packet_sz packets at a time */
		psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
		psize &= ~0x7ff;
		psize |= chdat->transfer_packet_sz;
		musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);

		musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
			TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
	} else {
		/* Receive transfer_packet_sz packets at a time */
		psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
		psize &= ~(0x7ff << 16);
		psize |= (chdat->transfer_packet_sz << 16);
		musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);

		musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
			TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
	}

	return true;
}

static int tusb_omap_dma_abort(struct dma_channel *channel)
{
	struct tusb_omap_dma_ch	*chdat = to_chdat(channel);

	if (chdat->dma_data)
		dmaengine_terminate_all(chdat->dma_data->chan);

	channel->status = MUSB_DMA_STATUS_FREE;

	return 0;
}

static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
{
	u32		reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
	int		i, dmareq_nr = -1;

	for (i = 0; i < MAX_DMAREQ; i++) {
		int cur = (reg & (0xf << (i * 5))) >> (i * 5);
		if (cur == 0) {
			dmareq_nr = i;
			break;
		}
	}

	if (dmareq_nr == -1)
		return -EAGAIN;

	reg |= (chdat->epnum << (dmareq_nr * 5));
	if (chdat->tx)
		reg |= ((1 << 4) << (dmareq_nr * 5));
	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);

	chdat->dma_data = &chdat->tusb_dma->dma_pool[dmareq_nr];

	return 0;
}

static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
{
	u32 reg;

	if (!chdat || !chdat->dma_data || chdat->dma_data->dmareq < 0)
		return;

	reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
	reg &= ~(0x1f << (chdat->dma_data->dmareq * 5));
	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);

	chdat->dma_data = NULL;
}

static struct dma_channel *dma_channel_pool[MAX_DMAREQ];

static struct dma_channel *
tusb_omap_dma_allocate(struct dma_controller *c,
		struct musb_hw_ep *hw_ep,
		u8 tx)
{
	int ret, i;
	struct tusb_omap_dma	*tusb_dma;
	struct musb		*musb;
	struct dma_channel	*channel = NULL;
	struct tusb_omap_dma_ch	*chdat = NULL;
	struct tusb_dma_data	*dma_data = NULL;

	tusb_dma = container_of(c, struct tusb_omap_dma, controller);
	musb = tusb_dma->controller.musb;

	/* REVISIT: Why does dmareq5 not work? */
	if (hw_ep->epnum == 0) {
		dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
		return NULL;
	}

	for (i = 0; i < MAX_DMAREQ; i++) {
		struct dma_channel *ch = dma_channel_pool[i];
		if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
			ch->status = MUSB_DMA_STATUS_FREE;
			channel = ch;
			chdat = ch->private_data;
			break;
		}
	}

	if (!channel)
		return NULL;

	chdat->musb = tusb_dma->controller.musb;
	chdat->tbase = tusb_dma->tbase;
	chdat->hw_ep = hw_ep;
	chdat->epnum = hw_ep->epnum;
	chdat->completed_len = 0;
	chdat->tusb_dma = tusb_dma;
	if (tx)
		chdat->tx = 1;
	else
		chdat->tx = 0;

	channel->max_len = 0x7fffffff;
	channel->desired_mode = 0;
	channel->actual_len = 0;

	if (!chdat->dma_data) {
		if (tusb_dma->multichannel) {
			ret = tusb_omap_dma_allocate_dmareq(chdat);
			if (ret != 0)
				goto free_dmareq;
		} else {
			chdat->dma_data = &tusb_dma->dma_pool[0];
		}
	}

	dma_data = chdat->dma_data;

	dev_dbg(musb->controller, "ep%i %s dma: %s dmareq%i\n",
		chdat->epnum,
		chdat->tx ? "tx" : "rx",
		tusb_dma->multichannel ? "shared" : "dedicated",
		dma_data->dmareq);

	return channel;

free_dmareq:
	tusb_omap_dma_free_dmareq(chdat);

	dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
	channel->status = MUSB_DMA_STATUS_UNKNOWN;

	return NULL;
}

static void tusb_omap_dma_release(struct dma_channel *channel)
{
	struct tusb_omap_dma_ch	*chdat = to_chdat(channel);
	struct musb		*musb = chdat->musb;

	dev_dbg(musb->controller, "Release for ep%i\n", chdat->epnum);

	channel->status = MUSB_DMA_STATUS_UNKNOWN;

	dmaengine_terminate_sync(chdat->dma_data->chan);
	tusb_omap_dma_free_dmareq(chdat);

	channel = NULL;
}

void tusb_dma_controller_destroy(struct dma_controller *c)
{
	struct tusb_omap_dma	*tusb_dma;
	int			i;

	tusb_dma = container_of(c, struct tusb_omap_dma, controller);
	for (i = 0; i < MAX_DMAREQ; i++) {
		struct dma_channel *ch = dma_channel_pool[i];
		if (ch) {
			kfree(ch->private_data);
			kfree(ch);
		}

		/* Free up the DMA channels */
		if (tusb_dma && tusb_dma->dma_pool[i].chan)
			dma_release_channel(tusb_dma->dma_pool[i].chan);
	}

	kfree(tusb_dma);
}
EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);

static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
{
	struct musb *musb = tusb_dma->controller.musb;
	int i;
	int ret = 0;

	for (i = 0; i < MAX_DMAREQ; i++) {
		struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];

		/*
		 * Request DMA channels:
		 * - one channel in case of non multichannel mode
		 * - MAX_DMAREQ number of channels in multichannel mode
		 */
		if (i == 0 || tusb_dma->multichannel) {
			char ch_name[8];

			sprintf(ch_name, "dmareq%d", i);
			dma_data->chan = dma_request_chan(musb->controller,
							  ch_name);
			if (IS_ERR(dma_data->chan)) {
				dev_err(musb->controller,
					"Failed to request %s\n", ch_name);
				ret = PTR_ERR(dma_data->chan);
				goto dma_error;
			}

			dma_data->dmareq = i;
		} else {
			dma_data->dmareq = -1;
		}
	}

	return 0;

dma_error:
	for (; i >= 0; i--) {
		struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];

		if (dma_data->dmareq >= 0)
			dma_release_channel(dma_data->chan);
	}

	return ret;
}

struct dma_controller *
tusb_dma_controller_create(struct musb *musb, void __iomem *base)
{
	void __iomem		*tbase = musb->ctrl_base;
	struct tusb_omap_dma	*tusb_dma;
	int			i;

	/* REVISIT: Get dmareq lines used from board-*.c */

	musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
	musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);

	musb_writel(tbase, TUSB_DMA_REQ_CONF,
		TUSB_DMA_REQ_CONF_BURST_SIZE(2)
		| TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
		| TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));

	tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
	if (!tusb_dma)
		goto out;

	tusb_dma->controller.musb = musb;
	tusb_dma->tbase = musb->ctrl_base;

	tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
	tusb_dma->controller.channel_release = tusb_omap_dma_release;
	tusb_dma->controller.channel_program = tusb_omap_dma_program;
	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;

	if (musb->tusb_revision >= TUSB_REV_30)
		tusb_dma->multichannel = 1;

	for (i = 0; i < MAX_DMAREQ; i++) {
		struct dma_channel	*ch;
		struct tusb_omap_dma_ch	*chdat;

		ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
		if (!ch)
			goto cleanup;

		dma_channel_pool[i] = ch;

		chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
		if (!chdat)
			goto cleanup;

		ch->status = MUSB_DMA_STATUS_UNKNOWN;
		ch->private_data = chdat;
	}

	if (tusb_omap_allocate_dma_pool(tusb_dma))
		goto cleanup;

	return &tusb_dma->controller;

cleanup:
	musb_dma_controller_destroy(&tusb_dma->controller);
out:
	return NULL;
}
EXPORT_SYMBOL_GPL(tusb_dma_controller_create);
Commit	Line	Data
5fd54ace	1	// SPDX-License-Identifier: GPL-2.0
550a7375 FB	2	/*
	3	* TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface
	4	*
	5	* Copyright (C) 2006 Nokia Corporation
	6	* Tony Lindgren <tony@atomide.com>
550a7375 FB	7	*/
	8	#include <linux/module.h>
	9	#include <linux/kernel.h>
	10	#include <linux/errno.h>
550a7375 FB	11	#include <linux/usb.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/dma-mapping.h>
5a0e3ad6	14	#include <linux/slab.h>
9c691cc9	15	#include <linux/dmaengine.h>
550a7375 FB	16
550a7375 FB	17	#include "musb_core.h"
240a16e2	18	#include "tusb6010.h"
550a7375 FB	19
	20	#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data)
	21
	22	#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */
	23
1df9d9ec	24	struct tusb_dma_data {
1df9d9ec	25	s8 dmareq;
9c691cc9	26	struct dma_chan *chan;
1df9d9ec PU	27	};
1df9d9ec PU	28
550a7375 FB	29	struct tusb_omap_dma_ch {
	30	struct musb *musb;
	31	void __iomem *tbase;
	32	unsigned long phys_offset;
	33	int epnum;
	34	u8 tx;
	35	struct musb_hw_ep *hw_ep;
	36
4cadc711	37	struct tusb_dma_data *dma_data;
550a7375 FB	38
	39	struct tusb_omap_dma *tusb_dma;
	40
1d0f11b3	41	dma_addr_t dma_addr;
550a7375 FB	42
	43	u32 len;
	44	u16 packet_sz;
	45	u16 transfer_packet_sz;
	46	u32 transfer_len;
	47	u32 completed_len;
	48	};
	49
	50	struct tusb_omap_dma {
	51	struct dma_controller controller;
550a7375 FB	52	void __iomem *tbase;
550a7375 FB	53
4cadc711	54	struct tusb_dma_data dma_pool[MAX_DMAREQ];
550a7375 FB	55	unsigned multichannel:1;
	56	};
	57
550a7375 FB	58	/*
	59	* Allocate dmareq0 to the current channel unless it's already taken
	60	*/
	61	static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat)
	62	{
	63	u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
	64
	65	if (reg != 0) {
74c6f3a4	66	dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n",
550a7375 FB	67	chdat->epnum, reg & 0xf);
	68	return -EAGAIN;
	69	}
	70
	71	if (chdat->tx)
	72	reg = (1 << 4) \| chdat->epnum;
	73	else
	74	reg = chdat->epnum;
	75
	76	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
	77
	78	return 0;
	79	}
	80
	81	static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat)
	82	{
	83	u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
	84
	85	if ((reg & 0xf) != chdat->epnum) {
	86	printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n",
	87	chdat->epnum, reg & 0xf);
	88	return;
	89	}
	90	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0);
	91	}
	92
	93	/*
	94	* See also musb_dma_completion in plat_uds.c and musb_g_[tx\|rx]() in
	95	* musb_gadget.c.
	96	*/
9c691cc9	97	static void tusb_omap_dma_cb(void *data)
550a7375 FB	98	{
	99	struct dma_channel channel = (struct dma_channel )data;
	100	struct tusb_omap_dma_ch *chdat = to_chdat(channel);
	101	struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
	102	struct musb *musb = chdat->musb;
1d0f11b3	103	struct device *dev = musb->controller;
550a7375 FB	104	struct musb_hw_ep *hw_ep = chdat->hw_ep;
	105	void __iomem *ep_conf = hw_ep->conf;
	106	void __iomem *mbase = musb->mregs;
	107	unsigned long remaining, flags, pio;
550a7375 FB	108
	109	spin_lock_irqsave(&musb->lock, flags);
	110
9c691cc9 PU	111	dev_dbg(musb->controller, "ep%i %s dma callback\n",
9c691cc9 PU	112	chdat->epnum, chdat->tx ? "tx" : "rx");
550a7375 FB	113
	114	if (chdat->tx)
	115	remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
	116	else
	117	remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
	118
	119	remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining);
	120
	121	/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
	122	if (unlikely(remaining > chdat->transfer_len)) {
9c691cc9 PU	123	dev_dbg(musb->controller, "Corrupt %s XFR_SIZE: 0x%08lx\n",
9c691cc9 PU	124	chdat->tx ? "tx" : "rx", remaining);
550a7375 FB	125	remaining = 0;
	126	}
	127
	128	channel->actual_len = chdat->transfer_len - remaining;
	129	pio = chdat->len - channel->actual_len;
	130
5c8a86e1	131	dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
550a7375 FB	132
	133	/* Transfer remaining 1 - 31 bytes */
	134	if (pio > 0 && pio < 32) {
	135	u8 *buf;
	136
5c8a86e1	137	dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
550a7375 FB	138	buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
550a7375 FB	139	if (chdat->tx) {
1d0f11b3 TL	140	dma_unmap_single(dev, chdat->dma_addr,
	141	chdat->transfer_len,
	142	DMA_TO_DEVICE);
550a7375 FB	143	musb_write_fifo(hw_ep, pio, buf);
550a7375 FB	144	} else {
1d0f11b3 TL	145	dma_unmap_single(dev, chdat->dma_addr,
	146	chdat->transfer_len,
	147	DMA_FROM_DEVICE);
550a7375	148	musb_read_fifo(hw_ep, pio, buf);
550a7375 FB	149	}
	150	channel->actual_len += pio;
	151	}
	152
	153	if (!tusb_dma->multichannel)
	154	tusb_omap_free_shared_dmareq(chdat);
	155
	156	channel->status = MUSB_DMA_STATUS_FREE;
	157
47699b0a	158	musb_dma_completion(musb, chdat->epnum, chdat->tx);
550a7375 FB	159
	160	/* We must terminate short tx transfers manually by setting TXPKTRDY.
	161	* REVISIT: This same problem may occur with other MUSB dma as well.
	162	* Easy to test with g_ether by pinging the MUSB board with ping -s54.
	163	*/
	164	if ((chdat->transfer_len < chdat->packet_sz)
	165	\|\| (chdat->transfer_len % chdat->packet_sz != 0)) {
	166	u16 csr;
	167
	168	if (chdat->tx) {
5c8a86e1	169	dev_dbg(musb->controller, "terminating short tx packet\n");
550a7375 FB	170	musb_ep_select(mbase, chdat->epnum);
	171	csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
	172	csr \|= MUSB_TXCSR_MODE \| MUSB_TXCSR_TXPKTRDY
	173	\| MUSB_TXCSR_P_WZC_BITS;
	174	musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
	175	}
	176	}
	177
	178	spin_unlock_irqrestore(&musb->lock, flags);
	179	}
	180
	181	static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz,
	182	u8 rndis_mode, dma_addr_t dma_addr, u32 len)
	183	{
	184	struct tusb_omap_dma_ch *chdat = to_chdat(channel);
	185	struct tusb_omap_dma *tusb_dma = chdat->tusb_dma;
	186	struct musb *musb = chdat->musb;
1d0f11b3	187	struct device *dev = musb->controller;
550a7375 FB	188	struct musb_hw_ep *hw_ep = chdat->hw_ep;
	189	void __iomem *mbase = musb->mregs;
	190	void __iomem *ep_conf = hw_ep->conf;
9c691cc9	191	dma_addr_t fifo_addr = hw_ep->fifo_sync;
550a7375	192	u32 dma_remaining;
550a7375	193	u16 csr;
6df2b42f	194	u32 psize;
1df9d9ec	195	struct tusb_dma_data *dma_data;
9c691cc9 PU	196	struct dma_async_tx_descriptor *dma_desc;
	197	struct dma_slave_config dma_cfg;
	198	enum dma_transfer_direction dma_dir;
	199	u32 port_window;
	200	int ret;
550a7375 FB	201
	202	if (unlikely(dma_addr & 0x1) \|\| (len < 32) \|\| (len > packet_sz))
	203	return false;
	204
	205	/*
	206	* HW issue #10: Async dma will eventually corrupt the XFR_SIZE
	207	* register which will cause missed DMA interrupt. We could try to
	208	* use a timer for the callback, but it is unsafe as the XFR_SIZE
	209	* register is corrupt, and we won't know if the DMA worked.
	210	*/
	211	if (dma_addr & 0x2)
	212	return false;
	213
	214	/*
	215	* Because of HW issue #10, it seems like mixing sync DMA and async
	216	* PIO access can confuse the DMA. Make sure XFR_SIZE is reset before
	217	* using the channel for DMA.
	218	*/
	219	if (chdat->tx)
	220	dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET);
	221	else
	222	dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET);
	223
	224	dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
	225	if (dma_remaining) {
9c691cc9 PU	226	dev_dbg(musb->controller, "Busy %s dma, not using: %08x\n",
9c691cc9 PU	227	chdat->tx ? "tx" : "rx", dma_remaining);
550a7375 FB	228	return false;
	229	}
	230
	231	chdat->transfer_len = len & ~0x1f;
	232
	233	if (len < packet_sz)
	234	chdat->transfer_packet_sz = chdat->transfer_len;
	235	else
	236	chdat->transfer_packet_sz = packet_sz;
	237
4cadc711 PU	238	dma_data = chdat->dma_data;
4cadc711 PU	239	if (!tusb_dma->multichannel) {
550a7375	240	if (tusb_omap_use_shared_dmareq(chdat) != 0) {
5c8a86e1	241	dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
550a7375 FB	242	return false;
550a7375 FB	243	}
9c691cc9	244	if (dma_data->dmareq < 0) {
550a7375 FB	245	/* REVISIT: This should get blocked earlier, happens
	246	* with MSC ErrorRecoveryTest
	247	*/
	248	WARN_ON(1);
	249	return false;
	250	}
550a7375 FB	251	}
	252
	253	chdat->packet_sz = packet_sz;
	254	chdat->len = len;
	255	channel->actual_len = 0;
1d0f11b3	256	chdat->dma_addr = dma_addr;
550a7375 FB	257	channel->status = MUSB_DMA_STATUS_BUSY;
	258
	259	/* Since we're recycling dma areas, we need to clean or invalidate */
9c691cc9 PU	260	if (chdat->tx) {
9c691cc9 PU	261	dma_dir = DMA_MEM_TO_DEV;
1d0f11b3 TL	262	dma_map_single(dev, phys_to_virt(dma_addr), len,
1d0f11b3 TL	263	DMA_TO_DEVICE);
9c691cc9 PU	264	} else {
9c691cc9 PU	265	dma_dir = DMA_DEV_TO_MEM;
1d0f11b3 TL	266	dma_map_single(dev, phys_to_virt(dma_addr), len,
1d0f11b3 TL	267	DMA_FROM_DEVICE);
9c691cc9 PU	268	}
	269
	270	memset(&dma_cfg, 0, sizeof(dma_cfg));
550a7375 FB	271
	272	/* Use 16-bit transfer if dma_addr is not 32-bit aligned */
	273	if ((dma_addr & 0x3) == 0) {
9c691cc9 PU	274	dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	275	dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	276	port_window = 8;
550a7375	277	} else {
9c691cc9 PU	278	dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	279	dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	280	port_window = 16;
550a7375	281
9c691cc9 PU	282	fifo_addr = hw_ep->fifo_async;
9c691cc9 PU	283	}
550a7375	284
9c691cc9 PU	285	dev_dbg(musb->controller,
	286	"ep%i %s dma: %pad len: %u(%u) packet_sz: %i(%i)\n",
	287	chdat->epnum, chdat->tx ? "tx" : "rx", &dma_addr,
	288	chdat->transfer_len, len, chdat->transfer_packet_sz, packet_sz);
	289
	290	dma_cfg.src_addr = fifo_addr;
	291	dma_cfg.dst_addr = fifo_addr;
	292	dma_cfg.src_port_window_size = port_window;
	293	dma_cfg.src_maxburst = port_window;
	294	dma_cfg.dst_port_window_size = port_window;
	295	dma_cfg.dst_maxburst = port_window;
	296
	297	ret = dmaengine_slave_config(dma_data->chan, &dma_cfg);
	298	if (ret) {
	299	dev_err(musb->controller, "DMA slave config failed: %d\n", ret);
	300	return false;
	301	}
550a7375	302
9c691cc9 PU	303	dma_desc = dmaengine_prep_slave_single(dma_data->chan, dma_addr,
	304	chdat->transfer_len, dma_dir,
	305	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
	306	if (!dma_desc) {
	307	dev_err(musb->controller, "DMA prep_slave_single failed\n");
	308	return false;
550a7375 FB	309	}
550a7375 FB	310
9c691cc9 PU	311	dma_desc->callback = tusb_omap_dma_cb;
	312	dma_desc->callback_param = channel;
	313	dmaengine_submit(dma_desc);
	314
	315	dev_dbg(musb->controller,
	316	"ep%i %s using %i-bit %s dma from %pad to %pad\n",
550a7375	317	chdat->epnum, chdat->tx ? "tx" : "rx",
9c691cc9	318	dma_cfg.src_addr_width * 8,
550a7375	319	((dma_addr & 0x3) == 0) ? "sync" : "async",
9c691cc9 PU	320	(dma_dir == DMA_MEM_TO_DEV) ? &dma_addr : &fifo_addr,
9c691cc9 PU	321	(dma_dir == DMA_MEM_TO_DEV) ? &fifo_addr : &dma_addr);
550a7375 FB	322
	323	/*
	324	* Prepare MUSB for DMA transfer
	325	*/
3565b787	326	musb_ep_select(mbase, chdat->epnum);
550a7375	327	if (chdat->tx) {
550a7375 FB	328	csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
	329	csr \|= (MUSB_TXCSR_AUTOSET \| MUSB_TXCSR_DMAENAB
	330	\| MUSB_TXCSR_DMAMODE \| MUSB_TXCSR_MODE);
	331	csr &= ~MUSB_TXCSR_P_UNDERRUN;
	332	musb_writew(hw_ep->regs, MUSB_TXCSR, csr);
	333	} else {
550a7375 FB	334	csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
	335	csr \|= MUSB_RXCSR_DMAENAB;
	336	csr &= ~(MUSB_RXCSR_AUTOCLEAR \| MUSB_RXCSR_DMAMODE);
	337	musb_writew(hw_ep->regs, MUSB_RXCSR,
	338	csr \| MUSB_RXCSR_P_WZC_BITS);
	339	}
	340
9c691cc9 PU	341	/* Start DMA transfer */
9c691cc9 PU	342	dma_async_issue_pending(dma_data->chan);
550a7375 FB	343
	344	if (chdat->tx) {
	345	/* Send transfer_packet_sz packets at a time */
6df2b42f PU	346	psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
	347	psize &= ~0x7ff;
	348	psize \|= chdat->transfer_packet_sz;
	349	musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
550a7375 FB	350
	351	musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
	352	TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
	353	} else {
	354	/* Receive transfer_packet_sz packets at a time */
6df2b42f PU	355	psize = musb_readl(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET);
	356	psize &= ~(0x7ff << 16);
	357	psize \|= (chdat->transfer_packet_sz << 16);
	358	musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, psize);
550a7375 FB	359
	360	musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
	361	TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len));
	362	}
	363
	364	return true;
	365	}
	366
	367	static int tusb_omap_dma_abort(struct dma_channel *channel)
	368	{
	369	struct tusb_omap_dma_ch *chdat = to_chdat(channel);
550a7375	370
4cadc711	371	if (chdat->dma_data)
9c691cc9	372	dmaengine_terminate_all(chdat->dma_data->chan);
550a7375 FB	373
	374	channel->status = MUSB_DMA_STATUS_FREE;
	375
	376	return 0;
	377	}
	378
	379	static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat)
	380	{
	381	u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
	382	int i, dmareq_nr = -1;
	383
550a7375 FB	384	for (i = 0; i < MAX_DMAREQ; i++) {
	385	int cur = (reg & (0xf << (i * 5))) >> (i * 5);
	386	if (cur == 0) {
	387	dmareq_nr = i;
	388	break;
	389	}
	390	}
	391
	392	if (dmareq_nr == -1)
	393	return -EAGAIN;
	394
	395	reg \|= (chdat->epnum << (dmareq_nr * 5));
	396	if (chdat->tx)
	397	reg \|= ((1 << 4) << (dmareq_nr * 5));
	398	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
	399
4cadc711	400	chdat->dma_data = &chdat->tusb_dma->dma_pool[dmareq_nr];
550a7375 FB	401
	402	return 0;
	403	}
	404
	405	static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat)
	406	{
	407	u32 reg;
	408
4cadc711	409	if (!chdat \|\| !chdat->dma_data \|\| chdat->dma_data->dmareq < 0)
550a7375 FB	410	return;
	411
	412	reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
4cadc711	413	reg &= ~(0x1f << (chdat->dma_data->dmareq * 5));
550a7375 FB	414	musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg);
550a7375 FB	415
4cadc711	416	chdat->dma_data = NULL;
550a7375 FB	417	}
	418
	419	static struct dma_channel *dma_channel_pool[MAX_DMAREQ];
	420
	421	static struct dma_channel *
	422	tusb_omap_dma_allocate(struct dma_controller *c,
	423	struct musb_hw_ep *hw_ep,
	424	u8 tx)
	425	{
	426	int ret, i;
550a7375 FB	427	struct tusb_omap_dma *tusb_dma;
550a7375 FB	428	struct musb *musb;
550a7375 FB	429	struct dma_channel *channel = NULL;
550a7375 FB	430	struct tusb_omap_dma_ch *chdat = NULL;
1df9d9ec	431	struct tusb_dma_data *dma_data = NULL;
550a7375 FB	432
550a7375 FB	433	tusb_dma = container_of(c, struct tusb_omap_dma, controller);
a96ca0d2	434	musb = tusb_dma->controller.musb;
550a7375 FB	435
	436	/* REVISIT: Why does dmareq5 not work? */
	437	if (hw_ep->epnum == 0) {
5c8a86e1	438	dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
550a7375 FB	439	return NULL;
	440	}
	441
	442	for (i = 0; i < MAX_DMAREQ; i++) {
	443	struct dma_channel *ch = dma_channel_pool[i];
	444	if (ch->status == MUSB_DMA_STATUS_UNKNOWN) {
	445	ch->status = MUSB_DMA_STATUS_FREE;
	446	channel = ch;
	447	chdat = ch->private_data;
	448	break;
	449	}
	450	}
	451
	452	if (!channel)
	453	return NULL;
	454
a96ca0d2	455	chdat->musb = tusb_dma->controller.musb;
550a7375 FB	456	chdat->tbase = tusb_dma->tbase;
	457	chdat->hw_ep = hw_ep;
	458	chdat->epnum = hw_ep->epnum;
550a7375 FB	459	chdat->completed_len = 0;
550a7375 FB	460	chdat->tusb_dma = tusb_dma;
1df9d9ec PU	461	if (tx)
	462	chdat->tx = 1;
	463	else
	464	chdat->tx = 0;
550a7375 FB	465
	466	channel->max_len = 0x7fffffff;
	467	channel->desired_mode = 0;
	468	channel->actual_len = 0;
	469
4cadc711 PU	470	if (!chdat->dma_data) {
	471	if (tusb_dma->multichannel) {
	472	ret = tusb_omap_dma_allocate_dmareq(chdat);
	473	if (ret != 0)
	474	goto free_dmareq;
	475	} else {
	476	chdat->dma_data = &tusb_dma->dma_pool[0];
	477	}
1df9d9ec PU	478	}
1df9d9ec PU	479
4cadc711	480	dma_data = chdat->dma_data;
550a7375	481
9c691cc9	482	dev_dbg(musb->controller, "ep%i %s dma: %s dmareq%i\n",
550a7375 FB	483	chdat->epnum,
550a7375 FB	484	chdat->tx ? "tx" : "rx",
4cadc711	485	tusb_dma->multichannel ? "shared" : "dedicated",
9c691cc9	486	dma_data->dmareq);
550a7375 FB	487
	488	return channel;
	489
	490	free_dmareq:
	491	tusb_omap_dma_free_dmareq(chdat);
	492
5c8a86e1	493	dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
550a7375 FB	494	channel->status = MUSB_DMA_STATUS_UNKNOWN;
	495
	496	return NULL;
	497	}
	498
	499	static void tusb_omap_dma_release(struct dma_channel *channel)
	500	{
	501	struct tusb_omap_dma_ch *chdat = to_chdat(channel);
	502	struct musb *musb = chdat->musb;
550a7375	503
9c691cc9	504	dev_dbg(musb->controller, "Release for ep%i\n", chdat->epnum);
550a7375	505
550a7375 FB	506	channel->status = MUSB_DMA_STATUS_UNKNOWN;
550a7375 FB	507
9c691cc9	508	dmaengine_terminate_sync(chdat->dma_data->chan);
4cadc711	509	tusb_omap_dma_free_dmareq(chdat);
550a7375 FB	510
	511	channel = NULL;
	512	}
	513
7f6283ed	514	void tusb_dma_controller_destroy(struct dma_controller *c)
550a7375 FB	515	{
	516	struct tusb_omap_dma *tusb_dma;
	517	int i;
	518
	519	tusb_dma = container_of(c, struct tusb_omap_dma, controller);
	520	for (i = 0; i < MAX_DMAREQ; i++) {
	521	struct dma_channel *ch = dma_channel_pool[i];
	522	if (ch) {
	523	kfree(ch->private_data);
	524	kfree(ch);
	525	}
550a7375	526
4cadc711	527	/* Free up the DMA channels */
9c691cc9 PU	528	if (tusb_dma && tusb_dma->dma_pool[i].chan)
9c691cc9 PU	529	dma_release_channel(tusb_dma->dma_pool[i].chan);
4cadc711	530	}
550a7375 FB	531
	532	kfree(tusb_dma);
	533	}
7f6283ed	534	EXPORT_SYMBOL_GPL(tusb_dma_controller_destroy);
550a7375	535
4cadc711 PU	536	static int tusb_omap_allocate_dma_pool(struct tusb_omap_dma *tusb_dma)
4cadc711 PU	537	{
9c691cc9	538	struct musb *musb = tusb_dma->controller.musb;
4cadc711 PU	539	int i;
4cadc711 PU	540	int ret = 0;
4cadc711 PU	541
	542	for (i = 0; i < MAX_DMAREQ; i++) {
	543	struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
	544
	545	/*
	546	* Request DMA channels:
	547	* - one channel in case of non multichannel mode
	548	* - MAX_DMAREQ number of channels in multichannel mode
	549	*/
	550	if (i == 0 \|\| tusb_dma->multichannel) {
	551	char ch_name[8];
	552
	553	sprintf(ch_name, "dmareq%d", i);
9c691cc9 PU	554	dma_data->chan = dma_request_chan(musb->controller,
	555	ch_name);
	556	if (IS_ERR(dma_data->chan)) {
	557	dev_err(musb->controller,
4cadc711	558	"Failed to request %s\n", ch_name);
9c691cc9	559	ret = PTR_ERR(dma_data->chan);
4cadc711 PU	560	goto dma_error;
	561	}
	562
	563	dma_data->dmareq = i;
	564	} else {
	565	dma_data->dmareq = -1;
4cadc711 PU	566	}
	567	}
	568
	569	return 0;
	570
	571	dma_error:
	572	for (; i >= 0; i--) {
	573	struct tusb_dma_data *dma_data = &tusb_dma->dma_pool[i];
	574
9c691cc9 PU	575	if (dma_data->dmareq >= 0)
9c691cc9 PU	576	dma_release_channel(dma_data->chan);
4cadc711 PU	577	}
	578
	579	return ret;
	580	}
	581
7f6283ed TL	582	struct dma_controller *
7f6283ed TL	583	tusb_dma_controller_create(struct musb musb, void __iomem base)
550a7375 FB	584	{
	585	void __iomem *tbase = musb->ctrl_base;
	586	struct tusb_omap_dma *tusb_dma;
	587	int i;
	588
	589	/* REVISIT: Get dmareq lines used from board-.c /
	590
	591	musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff);
	592	musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0);
	593
	594	musb_writel(tbase, TUSB_DMA_REQ_CONF,
	595	TUSB_DMA_REQ_CONF_BURST_SIZE(2)
	596	\| TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f)
	597	\| TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
	598
	599	tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL);
	600	if (!tusb_dma)
c88ba39c	601	goto out;
550a7375	602
a96ca0d2	603	tusb_dma->controller.musb = musb;
550a7375 FB	604	tusb_dma->tbase = musb->ctrl_base;
550a7375 FB	605
550a7375 FB	606	tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate;
	607	tusb_dma->controller.channel_release = tusb_omap_dma_release;
	608	tusb_dma->controller.channel_program = tusb_omap_dma_program;
	609	tusb_dma->controller.channel_abort = tusb_omap_dma_abort;
	610
7751b6fb	611	if (musb->tusb_revision >= TUSB_REV_30)
550a7375 FB	612	tusb_dma->multichannel = 1;
	613
	614	for (i = 0; i < MAX_DMAREQ; i++) {
	615	struct dma_channel *ch;
	616	struct tusb_omap_dma_ch *chdat;
	617
	618	ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL);
	619	if (!ch)
	620	goto cleanup;
	621
	622	dma_channel_pool[i] = ch;
	623
	624	chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL);
	625	if (!chdat)
	626	goto cleanup;
	627
	628	ch->status = MUSB_DMA_STATUS_UNKNOWN;
	629	ch->private_data = chdat;
	630	}
	631
4cadc711 PU	632	if (tusb_omap_allocate_dma_pool(tusb_dma))
	633	goto cleanup;
	634
550a7375 FB	635	return &tusb_dma->controller;
	636
	637	cleanup:
7f6283ed	638	musb_dma_controller_destroy(&tusb_dma->controller);
c88ba39c	639	out:
550a7375 FB	640	return NULL;
550a7375 FB	641	}
7f6283ed	642	EXPORT_SYMBOL_GPL(tusb_dma_controller_create);