Commit | Line | Data |
---|---|---|
550a7375 FB |
1 | /* |
2 | * TUSB6010 USB 2.0 OTG Dual Role controller | |
3 | * | |
4 | * Copyright (C) 2006 Nokia Corporation | |
550a7375 FB |
5 | * Tony Lindgren <tony@atomide.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * Notes: | |
12 | * - Driver assumes that interface to external host (main CPU) is | |
13 | * configured for NOR FLASH interface instead of VLYNQ serial | |
14 | * interface. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/errno.h> | |
ded017ee | 20 | #include <linux/err.h> |
240a16e2 | 21 | #include <linux/prefetch.h> |
550a7375 FB |
22 | #include <linux/usb.h> |
23 | #include <linux/irq.h> | |
56c82cdc | 24 | #include <linux/io.h> |
cdfe35fb | 25 | #include <linux/device.h> |
550a7375 | 26 | #include <linux/platform_device.h> |
18688fbe | 27 | #include <linux/dma-mapping.h> |
d7078df6 | 28 | #include <linux/usb/usb_phy_generic.h> |
550a7375 FB |
29 | |
30 | #include "musb_core.h" | |
31 | ||
1add75d2 FB |
32 | struct tusb6010_glue { |
33 | struct device *dev; | |
34 | struct platform_device *musb; | |
2f36ff69 | 35 | struct platform_device *phy; |
1add75d2 FB |
36 | }; |
37 | ||
743411b3 | 38 | static void tusb_musb_set_vbus(struct musb *musb, int is_on); |
550a7375 FB |
39 | |
40 | #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf) | |
41 | #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf) | |
42 | ||
43 | /* | |
44 | * Checks the revision. We need to use the DMA register as 3.0 does not | |
45 | * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV. | |
46 | */ | |
7751b6fb | 47 | static u8 tusb_get_revision(struct musb *musb) |
550a7375 FB |
48 | { |
49 | void __iomem *tbase = musb->ctrl_base; | |
50 | u32 die_id; | |
51 | u8 rev; | |
52 | ||
53 | rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff; | |
54 | if (TUSB_REV_MAJOR(rev) == 3) { | |
55 | die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, | |
56 | TUSB_DIDR1_HI)); | |
57 | if (die_id >= TUSB_DIDR1_HI_REV_31) | |
58 | rev |= 1; | |
59 | } | |
60 | ||
61 | return rev; | |
62 | } | |
63 | ||
7751b6fb | 64 | static void tusb_print_revision(struct musb *musb) |
550a7375 FB |
65 | { |
66 | void __iomem *tbase = musb->ctrl_base; | |
67 | u8 rev; | |
68 | ||
7751b6fb | 69 | rev = musb->tusb_revision; |
550a7375 FB |
70 | |
71 | pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n", | |
72 | "prcm", | |
73 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)), | |
74 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)), | |
75 | "int", | |
76 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), | |
77 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)), | |
78 | "gpio", | |
79 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)), | |
80 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)), | |
81 | "dma", | |
82 | TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), | |
83 | TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)), | |
84 | "dieid", | |
85 | TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)), | |
86 | "rev", | |
87 | TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev)); | |
550a7375 FB |
88 | } |
89 | ||
90 | #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \ | |
91 | | TUSB_PHY_OTG_CTRL_TESTM0) | |
92 | ||
93 | /* | |
94 | * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0. | |
95 | * Disables power detection in PHY for the duration of idle. | |
96 | */ | |
97 | static void tusb_wbus_quirk(struct musb *musb, int enabled) | |
98 | { | |
99 | void __iomem *tbase = musb->ctrl_base; | |
100 | static u32 phy_otg_ctrl, phy_otg_ena; | |
101 | u32 tmp; | |
102 | ||
103 | if (enabled) { | |
104 | phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
105 | phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
106 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | |
107 | | phy_otg_ena | WBUS_QUIRK_MASK; | |
108 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); | |
109 | tmp = phy_otg_ena & ~WBUS_QUIRK_MASK; | |
110 | tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2; | |
111 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); | |
5c8a86e1 | 112 | dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", |
550a7375 FB |
113 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
114 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); | |
115 | } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE) | |
116 | & TUSB_PHY_OTG_CTRL_TESTM2) { | |
117 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl; | |
118 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp); | |
119 | tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena; | |
120 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp); | |
5c8a86e1 | 121 | dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n", |
550a7375 FB |
122 | musb_readl(tbase, TUSB_PHY_OTG_CTRL), |
123 | musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)); | |
124 | phy_otg_ctrl = 0; | |
125 | phy_otg_ena = 0; | |
126 | } | |
127 | } | |
128 | ||
9d506fc6 TL |
129 | static u32 tusb_fifo_offset(u8 epnum) |
130 | { | |
131 | return 0x200 + (epnum * 0x20); | |
132 | } | |
133 | ||
d026e9c7 TL |
134 | static u32 tusb_ep_offset(u8 epnum, u16 offset) |
135 | { | |
136 | return 0x10 + offset; | |
137 | } | |
138 | ||
139 | /* TUSB mapping: "flat" plus ep0 special cases */ | |
140 | static void tusb_ep_select(void __iomem *mbase, u8 epnum) | |
141 | { | |
142 | musb_writeb(mbase, MUSB_INDEX, epnum); | |
143 | } | |
144 | ||
9d506fc6 TL |
145 | /* |
146 | * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum. | |
147 | */ | |
148 | static u8 tusb_readb(const void __iomem *addr, unsigned offset) | |
149 | { | |
150 | u16 tmp; | |
151 | u8 val; | |
152 | ||
153 | tmp = __raw_readw(addr + (offset & ~1)); | |
154 | if (offset & 1) | |
155 | val = (tmp >> 8); | |
156 | else | |
157 | val = tmp & 0xff; | |
158 | ||
159 | return val; | |
160 | } | |
161 | ||
162 | static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data) | |
163 | { | |
164 | u16 tmp; | |
165 | ||
166 | tmp = __raw_readw(addr + (offset & ~1)); | |
167 | if (offset & 1) | |
168 | tmp = (data << 8) | (tmp & 0xff); | |
169 | else | |
170 | tmp = (tmp & 0xff00) | data; | |
171 | ||
172 | __raw_writew(tmp, addr + (offset & ~1)); | |
173 | } | |
174 | ||
550a7375 FB |
175 | /* |
176 | * TUSB 6010 may use a parallel bus that doesn't support byte ops; | |
177 | * so both loading and unloading FIFOs need explicit byte counts. | |
178 | */ | |
179 | ||
180 | static inline void | |
181 | tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len) | |
182 | { | |
183 | u32 val; | |
184 | int i; | |
185 | ||
186 | if (len > 4) { | |
187 | for (i = 0; i < (len >> 2); i++) { | |
188 | memcpy(&val, buf, 4); | |
189 | musb_writel(fifo, 0, val); | |
190 | buf += 4; | |
191 | } | |
192 | len %= 4; | |
193 | } | |
194 | if (len > 0) { | |
195 | /* Write the rest 1 - 3 bytes to FIFO */ | |
196 | memcpy(&val, buf, len); | |
197 | musb_writel(fifo, 0, val); | |
198 | } | |
199 | } | |
200 | ||
201 | static inline void tusb_fifo_read_unaligned(void __iomem *fifo, | |
a156544b | 202 | void *buf, u16 len) |
550a7375 FB |
203 | { |
204 | u32 val; | |
205 | int i; | |
206 | ||
207 | if (len > 4) { | |
208 | for (i = 0; i < (len >> 2); i++) { | |
209 | val = musb_readl(fifo, 0); | |
210 | memcpy(buf, &val, 4); | |
211 | buf += 4; | |
212 | } | |
213 | len %= 4; | |
214 | } | |
215 | if (len > 0) { | |
216 | /* Read the rest 1 - 3 bytes from FIFO */ | |
217 | val = musb_readl(fifo, 0); | |
218 | memcpy(buf, &val, len); | |
219 | } | |
220 | } | |
221 | ||
1b40fc57 | 222 | static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf) |
550a7375 | 223 | { |
28e49705 | 224 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
225 | void __iomem *ep_conf = hw_ep->conf; |
226 | void __iomem *fifo = hw_ep->fifo; | |
227 | u8 epnum = hw_ep->epnum; | |
228 | ||
229 | prefetch(buf); | |
230 | ||
5c8a86e1 | 231 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
232 | 'T', epnum, fifo, len, buf); |
233 | ||
234 | if (epnum) | |
235 | musb_writel(ep_conf, TUSB_EP_TX_OFFSET, | |
236 | TUSB_EP_CONFIG_XFR_SIZE(len)); | |
237 | else | |
238 | musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX | | |
239 | TUSB_EP0_CONFIG_XFR_SIZE(len)); | |
240 | ||
241 | if (likely((0x01 & (unsigned long) buf) == 0)) { | |
242 | ||
243 | /* Best case is 32bit-aligned destination address */ | |
244 | if ((0x02 & (unsigned long) buf) == 0) { | |
245 | if (len >= 4) { | |
56c82cdc | 246 | iowrite32_rep(fifo, buf, len >> 2); |
550a7375 FB |
247 | buf += (len & ~0x03); |
248 | len &= 0x03; | |
249 | } | |
250 | } else { | |
251 | if (len >= 2) { | |
252 | u32 val; | |
253 | int i; | |
254 | ||
255 | /* Cannot use writesw, fifo is 32-bit */ | |
256 | for (i = 0; i < (len >> 2); i++) { | |
257 | val = (u32)(*(u16 *)buf); | |
258 | buf += 2; | |
259 | val |= (*(u16 *)buf) << 16; | |
260 | buf += 2; | |
261 | musb_writel(fifo, 0, val); | |
262 | } | |
263 | len &= 0x03; | |
264 | } | |
265 | } | |
266 | } | |
267 | ||
268 | if (len > 0) | |
269 | tusb_fifo_write_unaligned(fifo, buf, len); | |
270 | } | |
271 | ||
1b40fc57 | 272 | static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf) |
550a7375 | 273 | { |
28e49705 | 274 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
275 | void __iomem *ep_conf = hw_ep->conf; |
276 | void __iomem *fifo = hw_ep->fifo; | |
277 | u8 epnum = hw_ep->epnum; | |
278 | ||
5c8a86e1 | 279 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
280 | 'R', epnum, fifo, len, buf); |
281 | ||
282 | if (epnum) | |
283 | musb_writel(ep_conf, TUSB_EP_RX_OFFSET, | |
284 | TUSB_EP_CONFIG_XFR_SIZE(len)); | |
285 | else | |
286 | musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len)); | |
287 | ||
288 | if (likely((0x01 & (unsigned long) buf) == 0)) { | |
289 | ||
290 | /* Best case is 32bit-aligned destination address */ | |
291 | if ((0x02 & (unsigned long) buf) == 0) { | |
292 | if (len >= 4) { | |
56c82cdc | 293 | ioread32_rep(fifo, buf, len >> 2); |
550a7375 FB |
294 | buf += (len & ~0x03); |
295 | len &= 0x03; | |
296 | } | |
297 | } else { | |
298 | if (len >= 2) { | |
299 | u32 val; | |
300 | int i; | |
301 | ||
302 | /* Cannot use readsw, fifo is 32-bit */ | |
303 | for (i = 0; i < (len >> 2); i++) { | |
304 | val = musb_readl(fifo, 0); | |
305 | *(u16 *)buf = (u16)(val & 0xffff); | |
306 | buf += 2; | |
307 | *(u16 *)buf = (u16)(val >> 16); | |
308 | buf += 2; | |
309 | } | |
310 | len &= 0x03; | |
311 | } | |
312 | } | |
313 | } | |
314 | ||
315 | if (len > 0) | |
316 | tusb_fifo_read_unaligned(fifo, buf, len); | |
317 | } | |
318 | ||
84e250ff DB |
319 | static struct musb *the_musb; |
320 | ||
550a7375 FB |
321 | /* This is used by gadget drivers, and OTG transceiver logic, allowing |
322 | * at most mA current to be drawn from VBUS during a Default-B session | |
323 | * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host | |
324 | * mode), or low power Default-B sessions, something else supplies power. | |
325 | * Caller must take care of locking. | |
326 | */ | |
86753811 | 327 | static int tusb_draw_power(struct usb_phy *x, unsigned mA) |
550a7375 | 328 | { |
84e250ff | 329 | struct musb *musb = the_musb; |
550a7375 FB |
330 | void __iomem *tbase = musb->ctrl_base; |
331 | u32 reg; | |
332 | ||
550a7375 FB |
333 | /* tps65030 seems to consume max 100mA, with maybe 60mA available |
334 | * (measured on one board) for things other than tps and tusb. | |
335 | * | |
336 | * Boards sharing the CPU clock with CLKIN will need to prevent | |
337 | * certain idle sleep states while the USB link is active. | |
338 | * | |
339 | * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }. | |
340 | * The actual current usage would be very board-specific. For now, | |
341 | * it's simpler to just use an aggregate (also board-specific). | |
342 | */ | |
d445b6da | 343 | if (x->otg->default_a || mA < (musb->min_power << 1)) |
550a7375 FB |
344 | mA = 0; |
345 | ||
346 | reg = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
347 | if (mA) { | |
348 | musb->is_bus_powered = 1; | |
349 | reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN; | |
350 | } else { | |
351 | musb->is_bus_powered = 0; | |
352 | reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); | |
353 | } | |
354 | musb_writel(tbase, TUSB_PRCM_MNGMT, reg); | |
355 | ||
5c8a86e1 | 356 | dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA); |
550a7375 FB |
357 | return 0; |
358 | } | |
359 | ||
550a7375 FB |
360 | /* workaround for issue 13: change clock during chip idle |
361 | * (to be fixed in rev3 silicon) ... symptoms include disconnect | |
362 | * or looping suspend/resume cycles | |
363 | */ | |
364 | static void tusb_set_clock_source(struct musb *musb, unsigned mode) | |
365 | { | |
366 | void __iomem *tbase = musb->ctrl_base; | |
367 | u32 reg; | |
368 | ||
369 | reg = musb_readl(tbase, TUSB_PRCM_CONF); | |
370 | reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3); | |
371 | ||
372 | /* 0 = refclk (clkin, XI) | |
373 | * 1 = PHY 60 MHz (internal PLL) | |
374 | * 2 = not supported | |
375 | * 3 = what? | |
376 | */ | |
377 | if (mode > 0) | |
378 | reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3); | |
379 | ||
380 | musb_writel(tbase, TUSB_PRCM_CONF, reg); | |
381 | ||
382 | /* FIXME tusb6010_platform_retime(mode == 0); */ | |
383 | } | |
384 | ||
385 | /* | |
386 | * Idle TUSB6010 until next wake-up event; NOR access always wakes. | |
387 | * Other code ensures that we idle unless we're connected _and_ the | |
388 | * USB link is not suspended ... and tells us the relevant wakeup | |
389 | * events. SW_EN for voltage is handled separately. | |
390 | */ | |
743411b3 | 391 | static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables) |
550a7375 FB |
392 | { |
393 | void __iomem *tbase = musb->ctrl_base; | |
394 | u32 reg; | |
395 | ||
396 | if ((wakeup_enables & TUSB_PRCM_WBUS) | |
7751b6fb | 397 | && (musb->tusb_revision == TUSB_REV_30)) |
550a7375 FB |
398 | tusb_wbus_quirk(musb, 1); |
399 | ||
400 | tusb_set_clock_source(musb, 0); | |
401 | ||
402 | wakeup_enables |= TUSB_PRCM_WNORCS; | |
403 | musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables); | |
404 | ||
405 | /* REVISIT writeup of WID implies that if WID set and ID is grounded, | |
406 | * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared. | |
407 | * Presumably that's mostly to save power, hence WID is immaterial ... | |
408 | */ | |
409 | ||
410 | reg = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
411 | /* issue 4: when driving vbus, use hipower (vbus_det) comparator */ | |
412 | if (is_host_active(musb)) { | |
413 | reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
414 | reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN; | |
415 | } else { | |
416 | reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN; | |
417 | reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
418 | } | |
419 | reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE; | |
420 | musb_writel(tbase, TUSB_PRCM_MNGMT, reg); | |
421 | ||
5c8a86e1 | 422 | dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables); |
550a7375 FB |
423 | } |
424 | ||
425 | /* | |
426 | * Updates cable VBUS status. Caller must take care of locking. | |
427 | */ | |
743411b3 | 428 | static int tusb_musb_vbus_status(struct musb *musb) |
550a7375 FB |
429 | { |
430 | void __iomem *tbase = musb->ctrl_base; | |
431 | u32 otg_stat, prcm_mngmt; | |
432 | int ret = 0; | |
433 | ||
434 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
435 | prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
436 | ||
437 | /* Temporarily enable VBUS detection if it was disabled for | |
438 | * suspend mode. Unless it's enabled otg_stat and devctl will | |
439 | * not show correct VBUS state. | |
440 | */ | |
441 | if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) { | |
442 | u32 tmp = prcm_mngmt; | |
443 | tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN; | |
444 | musb_writel(tbase, TUSB_PRCM_MNGMT, tmp); | |
445 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
446 | musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt); | |
447 | } | |
448 | ||
449 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) | |
450 | ret = 1; | |
451 | ||
452 | return ret; | |
453 | } | |
454 | ||
455 | static struct timer_list musb_idle_timer; | |
456 | ||
457 | static void musb_do_idle(unsigned long _musb) | |
458 | { | |
459 | struct musb *musb = (void *)_musb; | |
460 | unsigned long flags; | |
461 | ||
462 | spin_lock_irqsave(&musb->lock, flags); | |
463 | ||
e47d9254 | 464 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
465 | case OTG_STATE_A_WAIT_BCON: |
466 | if ((musb->a_wait_bcon != 0) | |
467 | && (musb->idle_timeout == 0 | |
468 | || time_after(jiffies, musb->idle_timeout))) { | |
5c8a86e1 | 469 | dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n", |
e47d9254 | 470 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
471 | } |
472 | /* FALLTHROUGH */ | |
473 | case OTG_STATE_A_IDLE: | |
743411b3 | 474 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
475 | default: |
476 | break; | |
477 | } | |
478 | ||
479 | if (!musb->is_active) { | |
480 | u32 wakeups; | |
481 | ||
37ebb549 | 482 | /* wait until hub_wq handles port change status */ |
550a7375 FB |
483 | if (is_host_active(musb) && (musb->port1_status >> 16)) |
484 | goto done; | |
485 | ||
032ec49f | 486 | if (!musb->gadget_driver) { |
550a7375 | 487 | wakeups = 0; |
62285963 | 488 | } else { |
550a7375 | 489 | wakeups = TUSB_PRCM_WHOSTDISCON |
62285963 | 490 | | TUSB_PRCM_WBUS |
550a7375 | 491 | | TUSB_PRCM_WVBUS; |
032ec49f | 492 | wakeups |= TUSB_PRCM_WID; |
550a7375 | 493 | } |
550a7375 FB |
494 | tusb_allow_idle(musb, wakeups); |
495 | } | |
496 | done: | |
497 | spin_unlock_irqrestore(&musb->lock, flags); | |
498 | } | |
499 | ||
500 | /* | |
501 | * Maybe put TUSB6010 into idle mode mode depending on USB link status, | |
502 | * like "disconnected" or "suspended". We'll be woken out of it by | |
503 | * connect, resume, or disconnect. | |
504 | * | |
505 | * Needs to be called as the last function everywhere where there is | |
506 | * register access to TUSB6010 because of NOR flash wake-up. | |
507 | * Caller should own controller spinlock. | |
508 | * | |
509 | * Delay because peripheral enables D+ pullup 3msec after SE0, and | |
510 | * we don't want to treat that full speed J as a wakeup event. | |
511 | * ... peripherals must draw only suspend current after 10 msec. | |
512 | */ | |
743411b3 | 513 | static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout) |
550a7375 FB |
514 | { |
515 | unsigned long default_timeout = jiffies + msecs_to_jiffies(3); | |
516 | static unsigned long last_timer; | |
517 | ||
518 | if (timeout == 0) | |
519 | timeout = default_timeout; | |
520 | ||
521 | /* Never idle if active, or when VBUS timeout is not set as host */ | |
522 | if (musb->is_active || ((musb->a_wait_bcon == 0) | |
e47d9254 | 523 | && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) { |
5c8a86e1 | 524 | dev_dbg(musb->controller, "%s active, deleting timer\n", |
e47d9254 | 525 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
526 | del_timer(&musb_idle_timer); |
527 | last_timer = jiffies; | |
528 | return; | |
529 | } | |
530 | ||
531 | if (time_after(last_timer, timeout)) { | |
532 | if (!timer_pending(&musb_idle_timer)) | |
533 | last_timer = timeout; | |
534 | else { | |
5c8a86e1 | 535 | dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n"); |
550a7375 FB |
536 | return; |
537 | } | |
538 | } | |
539 | last_timer = timeout; | |
540 | ||
5c8a86e1 | 541 | dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n", |
e47d9254 | 542 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 FB |
543 | (unsigned long)jiffies_to_msecs(timeout - jiffies)); |
544 | mod_timer(&musb_idle_timer, timeout); | |
545 | } | |
546 | ||
547 | /* ticks of 60 MHz clock */ | |
548 | #define DEVCLOCK 60000000 | |
549 | #define OTG_TIMER_MS(msecs) ((msecs) \ | |
550 | ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \ | |
551 | | TUSB_DEV_OTG_TIMER_ENABLE) \ | |
552 | : 0) | |
553 | ||
743411b3 | 554 | static void tusb_musb_set_vbus(struct musb *musb, int is_on) |
550a7375 FB |
555 | { |
556 | void __iomem *tbase = musb->ctrl_base; | |
557 | u32 conf, prcm, timer; | |
558 | u8 devctl; | |
d445b6da | 559 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 FB |
560 | |
561 | /* HDRC controls CPEN, but beware current surges during device | |
562 | * connect. They can trigger transient overcurrent conditions | |
563 | * that must be ignored. | |
564 | */ | |
565 | ||
566 | prcm = musb_readl(tbase, TUSB_PRCM_MNGMT); | |
567 | conf = musb_readl(tbase, TUSB_DEV_CONF); | |
568 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
569 | ||
570 | if (is_on) { | |
550a7375 | 571 | timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE); |
d445b6da | 572 | otg->default_a = 1; |
e47d9254 | 573 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE; |
550a7375 FB |
574 | devctl |= MUSB_DEVCTL_SESSION; |
575 | ||
576 | conf |= TUSB_DEV_CONF_USB_HOST_MODE; | |
577 | MUSB_HST_MODE(musb); | |
578 | } else { | |
579 | u32 otg_stat; | |
580 | ||
581 | timer = 0; | |
582 | ||
583 | /* If ID pin is grounded, we want to be a_idle */ | |
584 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
585 | if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) { | |
e47d9254 | 586 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
587 | case OTG_STATE_A_WAIT_VRISE: |
588 | case OTG_STATE_A_WAIT_BCON: | |
e47d9254 | 589 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
590 | break; |
591 | case OTG_STATE_A_WAIT_VFALL: | |
e47d9254 | 592 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 FB |
593 | break; |
594 | default: | |
e47d9254 | 595 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 FB |
596 | } |
597 | musb->is_active = 0; | |
d445b6da | 598 | otg->default_a = 1; |
550a7375 FB |
599 | MUSB_HST_MODE(musb); |
600 | } else { | |
601 | musb->is_active = 0; | |
d445b6da | 602 | otg->default_a = 0; |
e47d9254 | 603 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
550a7375 FB |
604 | MUSB_DEV_MODE(musb); |
605 | } | |
606 | ||
607 | devctl &= ~MUSB_DEVCTL_SESSION; | |
608 | conf &= ~TUSB_DEV_CONF_USB_HOST_MODE; | |
550a7375 FB |
609 | } |
610 | prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN); | |
611 | ||
612 | musb_writel(tbase, TUSB_PRCM_MNGMT, prcm); | |
613 | musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer); | |
614 | musb_writel(tbase, TUSB_DEV_CONF, conf); | |
615 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
616 | ||
5c8a86e1 | 617 | dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n", |
e47d9254 | 618 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 FB |
619 | musb_readb(musb->mregs, MUSB_DEVCTL), |
620 | musb_readl(tbase, TUSB_DEV_OTG_STAT), | |
621 | conf, prcm); | |
622 | } | |
623 | ||
624 | /* | |
625 | * Sets the mode to OTG, peripheral or host by changing the ID detection. | |
626 | * Caller must take care of locking. | |
627 | * | |
628 | * Note that if a mini-A cable is plugged in the ID line will stay down as | |
629 | * the weak ID pull-up is not able to pull the ID up. | |
550a7375 | 630 | */ |
743411b3 | 631 | static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode) |
550a7375 FB |
632 | { |
633 | void __iomem *tbase = musb->ctrl_base; | |
634 | u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf; | |
635 | ||
550a7375 FB |
636 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); |
637 | phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
638 | phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
639 | dev_conf = musb_readl(tbase, TUSB_DEV_CONF); | |
640 | ||
641 | switch (musb_mode) { | |
642 | ||
550a7375 FB |
643 | case MUSB_HOST: /* Disable PHY ID detect, ground ID */ |
644 | phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
645 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
646 | dev_conf |= TUSB_DEV_CONF_ID_SEL; | |
647 | dev_conf &= ~TUSB_DEV_CONF_SOFT_ID; | |
648 | break; | |
550a7375 FB |
649 | case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */ |
650 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
651 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
652 | dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); | |
653 | break; | |
550a7375 FB |
654 | case MUSB_OTG: /* Use PHY ID detection */ |
655 | phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
656 | phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
657 | dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID); | |
658 | break; | |
550a7375 FB |
659 | |
660 | default: | |
5c8a86e1 | 661 | dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode); |
96a274d1 | 662 | return -EINVAL; |
550a7375 FB |
663 | } |
664 | ||
665 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, | |
666 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl); | |
667 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, | |
668 | TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena); | |
669 | musb_writel(tbase, TUSB_DEV_CONF, dev_conf); | |
670 | ||
671 | otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
672 | if ((musb_mode == MUSB_PERIPHERAL) && | |
673 | !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) | |
674 | INFO("Cannot be peripheral with mini-A cable " | |
675 | "otg_stat: %08x\n", otg_stat); | |
96a274d1 DB |
676 | |
677 | return 0; | |
550a7375 FB |
678 | } |
679 | ||
680 | static inline unsigned long | |
681 | tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase) | |
682 | { | |
683 | u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT); | |
684 | unsigned long idle_timeout = 0; | |
d445b6da | 685 | struct usb_otg *otg = musb->xceiv->otg; |
550a7375 FB |
686 | |
687 | /* ID pin */ | |
688 | if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) { | |
689 | int default_a; | |
690 | ||
032ec49f | 691 | default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS); |
5c8a86e1 | 692 | dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B'); |
d445b6da | 693 | otg->default_a = default_a; |
743411b3 | 694 | tusb_musb_set_vbus(musb, default_a); |
550a7375 FB |
695 | |
696 | /* Don't allow idling immediately */ | |
697 | if (default_a) | |
698 | idle_timeout = jiffies + (HZ * 3); | |
699 | } | |
700 | ||
701 | /* VBUS state change */ | |
702 | if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) { | |
703 | ||
704 | /* B-dev state machine: no vbus ~= disconnect */ | |
032ec49f | 705 | if (!otg->default_a) { |
550a7375 FB |
706 | /* ? musb_root_disconnect(musb); */ |
707 | musb->port1_status &= | |
708 | ~(USB_PORT_STAT_CONNECTION | |
709 | | USB_PORT_STAT_ENABLE | |
710 | | USB_PORT_STAT_LOW_SPEED | |
711 | | USB_PORT_STAT_HIGH_SPEED | |
712 | | USB_PORT_STAT_TEST | |
713 | ); | |
550a7375 FB |
714 | |
715 | if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) { | |
5c8a86e1 | 716 | dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n"); |
e47d9254 | 717 | if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) { |
550a7375 | 718 | /* INTR_DISCONNECT can hide... */ |
e47d9254 | 719 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
550a7375 FB |
720 | musb->int_usb |= MUSB_INTR_DISCONNECT; |
721 | } | |
722 | musb->is_active = 0; | |
723 | } | |
5c8a86e1 | 724 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", |
e47d9254 | 725 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 726 | idle_timeout = jiffies + (1 * HZ); |
2bff3916 | 727 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 FB |
728 | |
729 | } else /* A-dev state machine */ { | |
5c8a86e1 | 730 | dev_dbg(musb->controller, "vbus change, %s, otg %03x\n", |
e47d9254 | 731 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 732 | |
e47d9254 | 733 | switch (musb->xceiv->otg->state) { |
550a7375 | 734 | case OTG_STATE_A_IDLE: |
5c8a86e1 | 735 | dev_dbg(musb->controller, "Got SRP, turning on VBUS\n"); |
743411b3 | 736 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
737 | |
738 | /* CONNECT can wake if a_wait_bcon is set */ | |
739 | if (musb->a_wait_bcon != 0) | |
740 | musb->is_active = 0; | |
741 | else | |
742 | musb->is_active = 1; | |
743 | ||
744 | /* | |
745 | * OPT FS A TD.4.6 needs few seconds for | |
746 | * A_WAIT_VRISE | |
747 | */ | |
748 | idle_timeout = jiffies + (2 * HZ); | |
749 | ||
750 | break; | |
751 | case OTG_STATE_A_WAIT_VRISE: | |
752 | /* ignore; A-session-valid < VBUS_VALID/2, | |
753 | * we monitor this with the timer | |
754 | */ | |
755 | break; | |
756 | case OTG_STATE_A_WAIT_VFALL: | |
757 | /* REVISIT this irq triggers during short | |
758 | * spikes caused by enumeration ... | |
759 | */ | |
760 | if (musb->vbuserr_retry) { | |
761 | musb->vbuserr_retry--; | |
743411b3 | 762 | tusb_musb_set_vbus(musb, 1); |
550a7375 FB |
763 | } else { |
764 | musb->vbuserr_retry | |
765 | = VBUSERR_RETRY_COUNT; | |
743411b3 | 766 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
767 | } |
768 | break; | |
769 | default: | |
770 | break; | |
771 | } | |
772 | } | |
773 | } | |
774 | ||
775 | /* OTG timer expiration */ | |
776 | if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) { | |
777 | u8 devctl; | |
778 | ||
5c8a86e1 | 779 | dev_dbg(musb->controller, "%s timer, %03x\n", |
e47d9254 | 780 | usb_otg_state_string(musb->xceiv->otg->state), otg_stat); |
550a7375 | 781 | |
e47d9254 | 782 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
783 | case OTG_STATE_A_WAIT_VRISE: |
784 | /* VBUS has probably been valid for a while now, | |
785 | * but may well have bounced out of range a bit | |
786 | */ | |
787 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
788 | if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) { | |
789 | if ((devctl & MUSB_DEVCTL_VBUS) | |
790 | != MUSB_DEVCTL_VBUS) { | |
5c8a86e1 | 791 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 FB |
792 | break; |
793 | } | |
e47d9254 | 794 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; |
550a7375 FB |
795 | musb->is_active = 0; |
796 | idle_timeout = jiffies | |
797 | + msecs_to_jiffies(musb->a_wait_bcon); | |
798 | } else { | |
799 | /* REVISIT report overcurrent to hub? */ | |
800 | ERR("vbus too slow, devctl %02x\n", devctl); | |
743411b3 | 801 | tusb_musb_set_vbus(musb, 0); |
550a7375 FB |
802 | } |
803 | break; | |
804 | case OTG_STATE_A_WAIT_BCON: | |
805 | if (musb->a_wait_bcon != 0) | |
806 | idle_timeout = jiffies | |
807 | + msecs_to_jiffies(musb->a_wait_bcon); | |
808 | break; | |
809 | case OTG_STATE_A_SUSPEND: | |
810 | break; | |
811 | case OTG_STATE_B_WAIT_ACON: | |
812 | break; | |
813 | default: | |
814 | break; | |
815 | } | |
816 | } | |
2bff3916 | 817 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 FB |
818 | |
819 | return idle_timeout; | |
820 | } | |
821 | ||
743411b3 | 822 | static irqreturn_t tusb_musb_interrupt(int irq, void *__hci) |
550a7375 FB |
823 | { |
824 | struct musb *musb = __hci; | |
825 | void __iomem *tbase = musb->ctrl_base; | |
826 | unsigned long flags, idle_timeout = 0; | |
827 | u32 int_mask, int_src; | |
828 | ||
829 | spin_lock_irqsave(&musb->lock, flags); | |
830 | ||
831 | /* Mask all interrupts to allow using both edge and level GPIO irq */ | |
832 | int_mask = musb_readl(tbase, TUSB_INT_MASK); | |
833 | musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); | |
834 | ||
835 | int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS; | |
5c8a86e1 | 836 | dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src); |
550a7375 FB |
837 | |
838 | musb->int_usb = (u8) int_src; | |
839 | ||
840 | /* Acknowledge wake-up source interrupts */ | |
841 | if (int_src & TUSB_INT_SRC_DEV_WAKEUP) { | |
842 | u32 reg; | |
843 | u32 i; | |
844 | ||
7751b6fb | 845 | if (musb->tusb_revision == TUSB_REV_30) |
550a7375 FB |
846 | tusb_wbus_quirk(musb, 0); |
847 | ||
848 | /* there are issues re-locking the PLL on wakeup ... */ | |
849 | ||
850 | /* work around issue 8 */ | |
851 | for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) { | |
852 | musb_writel(tbase, TUSB_SCRATCH_PAD, 0); | |
853 | musb_writel(tbase, TUSB_SCRATCH_PAD, i); | |
854 | reg = musb_readl(tbase, TUSB_SCRATCH_PAD); | |
855 | if (reg == i) | |
856 | break; | |
5c8a86e1 | 857 | dev_dbg(musb->controller, "TUSB NOR not ready\n"); |
550a7375 FB |
858 | } |
859 | ||
860 | /* work around issue 13 (2nd half) */ | |
861 | tusb_set_clock_source(musb, 1); | |
862 | ||
863 | reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE); | |
864 | musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg); | |
865 | if (reg & ~TUSB_PRCM_WNORCS) { | |
866 | musb->is_active = 1; | |
2bff3916 | 867 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 | 868 | } |
5c8a86e1 | 869 | dev_dbg(musb->controller, "wake %sactive %02x\n", |
550a7375 FB |
870 | musb->is_active ? "" : "in", reg); |
871 | ||
872 | /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */ | |
873 | } | |
874 | ||
875 | if (int_src & TUSB_INT_SRC_USB_IP_CONN) | |
876 | del_timer(&musb_idle_timer); | |
877 | ||
878 | /* OTG state change reports (annoyingly) not issued by Mentor core */ | |
879 | if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG | |
880 | | TUSB_INT_SRC_OTG_TIMEOUT | |
881 | | TUSB_INT_SRC_ID_STATUS_CHNG)) | |
882 | idle_timeout = tusb_otg_ints(musb, int_src, tbase); | |
883 | ||
47699b0a PU |
884 | /* |
885 | * Just clear the DMA interrupt if it comes as the completion for both | |
886 | * TX and RX is handled by the DMA callback in tusb6010_omap | |
550a7375 FB |
887 | */ |
888 | if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) { | |
889 | u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC); | |
550a7375 | 890 | |
5c8a86e1 | 891 | dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src); |
550a7375 FB |
892 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src); |
893 | } | |
894 | ||
895 | /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */ | |
896 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) { | |
897 | u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC); | |
898 | ||
899 | musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src); | |
900 | musb->int_rx = (((musb_src >> 16) & 0xffff) << 1); | |
901 | musb->int_tx = (musb_src & 0xffff); | |
902 | } else { | |
903 | musb->int_rx = 0; | |
904 | musb->int_tx = 0; | |
905 | } | |
906 | ||
907 | if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff)) | |
908 | musb_interrupt(musb); | |
909 | ||
910 | /* Acknowledge TUSB interrupts. Clear only non-reserved bits */ | |
911 | musb_writel(tbase, TUSB_INT_SRC_CLEAR, | |
912 | int_src & ~TUSB_INT_MASK_RESERVED_BITS); | |
913 | ||
743411b3 | 914 | tusb_musb_try_idle(musb, idle_timeout); |
550a7375 FB |
915 | |
916 | musb_writel(tbase, TUSB_INT_MASK, int_mask); | |
917 | spin_unlock_irqrestore(&musb->lock, flags); | |
918 | ||
919 | return IRQ_HANDLED; | |
920 | } | |
921 | ||
922 | static int dma_off; | |
923 | ||
924 | /* | |
925 | * Enables TUSB6010. Caller must take care of locking. | |
926 | * REVISIT: | |
927 | * - Check what is unnecessary in MGC_HdrcStart() | |
928 | */ | |
743411b3 | 929 | static void tusb_musb_enable(struct musb *musb) |
550a7375 FB |
930 | { |
931 | void __iomem *tbase = musb->ctrl_base; | |
932 | ||
933 | /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF. | |
934 | * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */ | |
935 | musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF); | |
936 | ||
937 | /* Setup TUSB interrupt, disable DMA and GPIO interrupts */ | |
938 | musb_writel(tbase, TUSB_USBIP_INT_MASK, 0); | |
939 | musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); | |
940 | musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); | |
941 | ||
942 | /* Clear all subsystem interrups */ | |
943 | musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff); | |
944 | musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff); | |
945 | musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff); | |
946 | ||
947 | /* Acknowledge pending interrupt(s) */ | |
948 | musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS); | |
949 | ||
950 | /* Only 0 clock cycles for minimum interrupt de-assertion time and | |
951 | * interrupt polarity active low seems to work reliably here */ | |
952 | musb_writel(tbase, TUSB_INT_CTRL_CONF, | |
953 | TUSB_INT_CTRL_CONF_INT_RELCYC(0)); | |
954 | ||
dced35ae | 955 | irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW); |
550a7375 FB |
956 | |
957 | /* maybe force into the Default-A OTG state machine */ | |
958 | if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT) | |
959 | & TUSB_DEV_OTG_STAT_ID_STATUS)) | |
960 | musb_writel(tbase, TUSB_INT_SRC_SET, | |
961 | TUSB_INT_SRC_ID_STATUS_CHNG); | |
962 | ||
963 | if (is_dma_capable() && dma_off) | |
964 | printk(KERN_WARNING "%s %s: dma not reactivated\n", | |
965 | __FILE__, __func__); | |
966 | else | |
967 | dma_off = 1; | |
968 | } | |
969 | ||
970 | /* | |
971 | * Disables TUSB6010. Caller must take care of locking. | |
972 | */ | |
743411b3 | 973 | static void tusb_musb_disable(struct musb *musb) |
550a7375 FB |
974 | { |
975 | void __iomem *tbase = musb->ctrl_base; | |
976 | ||
977 | /* FIXME stop DMA, IRQs, timers, ... */ | |
978 | ||
979 | /* disable all IRQs */ | |
980 | musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS); | |
981 | musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff); | |
982 | musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff); | |
983 | musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff); | |
984 | ||
985 | del_timer(&musb_idle_timer); | |
986 | ||
987 | if (is_dma_capable() && !dma_off) { | |
988 | printk(KERN_WARNING "%s %s: dma still active\n", | |
989 | __FILE__, __func__); | |
990 | dma_off = 1; | |
991 | } | |
992 | } | |
993 | ||
994 | /* | |
995 | * Sets up TUSB6010 CPU interface specific signals and registers | |
996 | * Note: Settings optimized for OMAP24xx | |
997 | */ | |
743411b3 | 998 | static void tusb_setup_cpu_interface(struct musb *musb) |
550a7375 FB |
999 | { |
1000 | void __iomem *tbase = musb->ctrl_base; | |
1001 | ||
1002 | /* | |
1003 | * Disable GPIO[5:0] pullups (used as output DMA requests) | |
1004 | * Don't disable GPIO[7:6] as they are needed for wake-up. | |
1005 | */ | |
1006 | musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F); | |
1007 | ||
1008 | /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */ | |
1009 | musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF); | |
1010 | ||
1011 | /* Turn GPIO[5:0] to DMAREQ[5:0] signals */ | |
1012 | musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f)); | |
1013 | ||
1014 | /* Burst size 16x16 bits, all six DMA requests enabled, DMA request | |
1015 | * de-assertion time 2 system clocks p 62 */ | |
1016 | musb_writel(tbase, TUSB_DMA_REQ_CONF, | |
1017 | TUSB_DMA_REQ_CONF_BURST_SIZE(2) | | |
1018 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) | | |
1019 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); | |
1020 | ||
1021 | /* Set 0 wait count for synchronous burst access */ | |
1022 | musb_writel(tbase, TUSB_WAIT_COUNT, 1); | |
1023 | } | |
1024 | ||
743411b3 | 1025 | static int tusb_musb_start(struct musb *musb) |
550a7375 FB |
1026 | { |
1027 | void __iomem *tbase = musb->ctrl_base; | |
1028 | int ret = 0; | |
1029 | unsigned long flags; | |
1030 | u32 reg; | |
1031 | ||
1032 | if (musb->board_set_power) | |
1033 | ret = musb->board_set_power(1); | |
1034 | if (ret != 0) { | |
1035 | printk(KERN_ERR "tusb: Cannot enable TUSB6010\n"); | |
1036 | return ret; | |
1037 | } | |
1038 | ||
1039 | spin_lock_irqsave(&musb->lock, flags); | |
1040 | ||
1041 | if (musb_readl(tbase, TUSB_PROD_TEST_RESET) != | |
1042 | TUSB_PROD_TEST_RESET_VAL) { | |
1043 | printk(KERN_ERR "tusb: Unable to detect TUSB6010\n"); | |
1044 | goto err; | |
1045 | } | |
1046 | ||
8c240dc1 | 1047 | musb->tusb_revision = tusb_get_revision(musb); |
7751b6fb MK |
1048 | tusb_print_revision(musb); |
1049 | if (musb->tusb_revision < 2) { | |
550a7375 | 1050 | printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n", |
7751b6fb | 1051 | musb->tusb_revision); |
550a7375 FB |
1052 | goto err; |
1053 | } | |
1054 | ||
1055 | /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when | |
1056 | * NOR FLASH interface is used */ | |
1057 | musb_writel(tbase, TUSB_VLYNQ_CTRL, 8); | |
1058 | ||
1059 | /* Select PHY free running 60MHz as a system clock */ | |
1060 | tusb_set_clock_source(musb, 1); | |
1061 | ||
1062 | /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for | |
1063 | * power saving, enable VBus detect and session end comparators, | |
1064 | * enable IDpullup, enable VBus charging */ | |
1065 | musb_writel(tbase, TUSB_PRCM_MNGMT, | |
1066 | TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) | | |
1067 | TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN | | |
1068 | TUSB_PRCM_MNGMT_OTG_SESS_END_EN | | |
1069 | TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN | | |
1070 | TUSB_PRCM_MNGMT_OTG_ID_PULLUP); | |
1071 | tusb_setup_cpu_interface(musb); | |
1072 | ||
1073 | /* simplify: always sense/pullup ID pins, as if in OTG mode */ | |
1074 | reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE); | |
1075 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
1076 | musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg); | |
1077 | ||
1078 | reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL); | |
1079 | reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP; | |
1080 | musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg); | |
1081 | ||
1082 | spin_unlock_irqrestore(&musb->lock, flags); | |
1083 | ||
1084 | return 0; | |
1085 | ||
1086 | err: | |
1087 | spin_unlock_irqrestore(&musb->lock, flags); | |
1088 | ||
1089 | if (musb->board_set_power) | |
1090 | musb->board_set_power(0); | |
1091 | ||
1092 | return -ENODEV; | |
1093 | } | |
1094 | ||
743411b3 | 1095 | static int tusb_musb_init(struct musb *musb) |
550a7375 FB |
1096 | { |
1097 | struct platform_device *pdev; | |
1098 | struct resource *mem; | |
84e250ff | 1099 | void __iomem *sync = NULL; |
550a7375 FB |
1100 | int ret; |
1101 | ||
662dca54 | 1102 | musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2); |
ded017ee | 1103 | if (IS_ERR_OR_NULL(musb->xceiv)) |
25736e0c | 1104 | return -EPROBE_DEFER; |
84e250ff | 1105 | |
550a7375 FB |
1106 | pdev = to_platform_device(musb->controller); |
1107 | ||
1108 | /* dma address for async dma */ | |
1109 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1110 | musb->async = mem->start; | |
1111 | ||
1112 | /* dma address for sync dma */ | |
1113 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1114 | if (!mem) { | |
1115 | pr_debug("no sync dma resource?\n"); | |
84e250ff DB |
1116 | ret = -ENODEV; |
1117 | goto done; | |
550a7375 FB |
1118 | } |
1119 | musb->sync = mem->start; | |
1120 | ||
3d268645 | 1121 | sync = ioremap(mem->start, resource_size(mem)); |
550a7375 FB |
1122 | if (!sync) { |
1123 | pr_debug("ioremap for sync failed\n"); | |
84e250ff DB |
1124 | ret = -ENOMEM; |
1125 | goto done; | |
550a7375 FB |
1126 | } |
1127 | musb->sync_va = sync; | |
1128 | ||
1129 | /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400, | |
1130 | * FIFOs at 0x600, TUSB at 0x800 | |
1131 | */ | |
1132 | musb->mregs += TUSB_BASE_OFFSET; | |
1133 | ||
743411b3 | 1134 | ret = tusb_musb_start(musb); |
550a7375 FB |
1135 | if (ret) { |
1136 | printk(KERN_ERR "Could not start tusb6010 (%d)\n", | |
1137 | ret); | |
84e250ff | 1138 | goto done; |
550a7375 | 1139 | } |
743411b3 | 1140 | musb->isr = tusb_musb_interrupt; |
550a7375 | 1141 | |
032ec49f FB |
1142 | musb->xceiv->set_power = tusb_draw_power; |
1143 | the_musb = musb; | |
550a7375 FB |
1144 | |
1145 | setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb); | |
1146 | ||
84e250ff DB |
1147 | done: |
1148 | if (ret < 0) { | |
1149 | if (sync) | |
1150 | iounmap(sync); | |
f4053874 | 1151 | |
721002ec | 1152 | usb_put_phy(musb->xceiv); |
84e250ff | 1153 | } |
550a7375 FB |
1154 | return ret; |
1155 | } | |
1156 | ||
743411b3 | 1157 | static int tusb_musb_exit(struct musb *musb) |
550a7375 FB |
1158 | { |
1159 | del_timer_sync(&musb_idle_timer); | |
84e250ff | 1160 | the_musb = NULL; |
550a7375 FB |
1161 | |
1162 | if (musb->board_set_power) | |
1163 | musb->board_set_power(0); | |
1164 | ||
1165 | iounmap(musb->sync_va); | |
f4053874 | 1166 | |
721002ec | 1167 | usb_put_phy(musb->xceiv); |
550a7375 FB |
1168 | return 0; |
1169 | } | |
743411b3 | 1170 | |
f7ec9437 | 1171 | static const struct musb_platform_ops tusb_ops = { |
0efc1356 PU |
1172 | .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB | |
1173 | MUSB_G_NO_SKB_RESERVE, | |
743411b3 FB |
1174 | .init = tusb_musb_init, |
1175 | .exit = tusb_musb_exit, | |
1176 | ||
d026e9c7 TL |
1177 | .ep_offset = tusb_ep_offset, |
1178 | .ep_select = tusb_ep_select, | |
9d506fc6 TL |
1179 | .fifo_offset = tusb_fifo_offset, |
1180 | .readb = tusb_readb, | |
1181 | .writeb = tusb_writeb, | |
1b40fc57 TL |
1182 | .read_fifo = tusb_read_fifo, |
1183 | .write_fifo = tusb_write_fifo, | |
7f6283ed TL |
1184 | #ifdef CONFIG_USB_TUSB_OMAP_DMA |
1185 | .dma_init = tusb_dma_controller_create, | |
1186 | .dma_exit = tusb_dma_controller_destroy, | |
1187 | #endif | |
743411b3 FB |
1188 | .enable = tusb_musb_enable, |
1189 | .disable = tusb_musb_disable, | |
1190 | ||
1191 | .set_mode = tusb_musb_set_mode, | |
1192 | .try_idle = tusb_musb_try_idle, | |
1193 | ||
1194 | .vbus_status = tusb_musb_vbus_status, | |
1195 | .set_vbus = tusb_musb_set_vbus, | |
1196 | }; | |
18688fbe | 1197 | |
af384875 RK |
1198 | static const struct platform_device_info tusb_dev_info = { |
1199 | .name = "musb-hdrc", | |
1200 | .id = PLATFORM_DEVID_AUTO, | |
1201 | .dma_mask = DMA_BIT_MASK(32), | |
1202 | }; | |
18688fbe | 1203 | |
41ac7b3a | 1204 | static int tusb_probe(struct platform_device *pdev) |
18688fbe | 1205 | { |
c1f01be4 | 1206 | struct resource musb_resources[3]; |
c1a7d67c | 1207 | struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
18688fbe | 1208 | struct platform_device *musb; |
1add75d2 | 1209 | struct tusb6010_glue *glue; |
af384875 | 1210 | struct platform_device_info pinfo; |
cdfe35fb | 1211 | int ret; |
18688fbe | 1212 | |
cdfe35fb | 1213 | glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL); |
6a58856f | 1214 | if (!glue) |
cdfe35fb | 1215 | return -ENOMEM; |
1add75d2 | 1216 | |
1add75d2 | 1217 | glue->dev = &pdev->dev; |
1add75d2 | 1218 | |
f7ec9437 FB |
1219 | pdata->platform_ops = &tusb_ops; |
1220 | ||
e741e637 | 1221 | usb_phy_generic_register(); |
1add75d2 | 1222 | platform_set_drvdata(pdev, glue); |
18688fbe | 1223 | |
09fc7d22 FB |
1224 | memset(musb_resources, 0x00, sizeof(*musb_resources) * |
1225 | ARRAY_SIZE(musb_resources)); | |
1226 | ||
1227 | musb_resources[0].name = pdev->resource[0].name; | |
1228 | musb_resources[0].start = pdev->resource[0].start; | |
1229 | musb_resources[0].end = pdev->resource[0].end; | |
1230 | musb_resources[0].flags = pdev->resource[0].flags; | |
1231 | ||
1232 | musb_resources[1].name = pdev->resource[1].name; | |
1233 | musb_resources[1].start = pdev->resource[1].start; | |
1234 | musb_resources[1].end = pdev->resource[1].end; | |
1235 | musb_resources[1].flags = pdev->resource[1].flags; | |
1236 | ||
c1f01be4 KVA |
1237 | musb_resources[2].name = pdev->resource[2].name; |
1238 | musb_resources[2].start = pdev->resource[2].start; | |
1239 | musb_resources[2].end = pdev->resource[2].end; | |
1240 | musb_resources[2].flags = pdev->resource[2].flags; | |
1241 | ||
af384875 RK |
1242 | pinfo = tusb_dev_info; |
1243 | pinfo.parent = &pdev->dev; | |
1244 | pinfo.res = musb_resources; | |
1245 | pinfo.num_res = ARRAY_SIZE(musb_resources); | |
1246 | pinfo.data = pdata; | |
1247 | pinfo.size_data = sizeof(*pdata); | |
1248 | ||
1249 | glue->musb = musb = platform_device_register_full(&pinfo); | |
1250 | if (IS_ERR(musb)) { | |
1251 | ret = PTR_ERR(musb); | |
1252 | dev_err(&pdev->dev, "failed to register musb device: %d\n", ret); | |
cdfe35fb | 1253 | return ret; |
18688fbe FB |
1254 | } |
1255 | ||
1256 | return 0; | |
18688fbe FB |
1257 | } |
1258 | ||
fb4e98ab | 1259 | static int tusb_remove(struct platform_device *pdev) |
18688fbe | 1260 | { |
1add75d2 | 1261 | struct tusb6010_glue *glue = platform_get_drvdata(pdev); |
18688fbe | 1262 | |
a81a01f9 | 1263 | platform_device_unregister(glue->musb); |
2f36ff69 | 1264 | usb_phy_generic_unregister(glue->phy); |
18688fbe FB |
1265 | |
1266 | return 0; | |
1267 | } | |
1268 | ||
1269 | static struct platform_driver tusb_driver = { | |
e9e8c85e | 1270 | .probe = tusb_probe, |
7690417d | 1271 | .remove = tusb_remove, |
18688fbe FB |
1272 | .driver = { |
1273 | .name = "musb-tusb", | |
1274 | }, | |
1275 | }; | |
1276 | ||
1277 | MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer"); | |
1278 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); | |
1279 | MODULE_LICENSE("GPL v2"); | |
01380c08 | 1280 | module_platform_driver(tusb_driver); |