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Merge tag 'phy-for-4.7-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon...
[linux-2.6-block.git] / drivers / usb / musb / sunxi.c
CommitLineData
744543c5
HG		 1/*
2 * Allwinner sun4i MUSB Glue Layer
3 *
4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on code from
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/extcon.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/phy/phy-sun4i-usb.h>
28#include <linux/platform_device.h>
132e2377 29#include <linux/reset.h>
744543c5
HG		 30#include <linux/soc/sunxi/sunxi_sram.h>
31#include <linux/usb/musb.h>
32#include <linux/usb/of.h>
33#include <linux/usb/usb_phy_generic.h>
34#include <linux/workqueue.h>
35#include "musb_core.h"
36
37/*
38 * Register offsets, note sunxi musb has a different layout then most
39 * musb implementations, we translate the layout in musb_readb & friends.
40 */
41#define SUNXI_MUSB_POWER 0x0040
42#define SUNXI_MUSB_DEVCTL 0x0041
43#define SUNXI_MUSB_INDEX 0x0042
44#define SUNXI_MUSB_VEND0 0x0043
45#define SUNXI_MUSB_INTRTX 0x0044
46#define SUNXI_MUSB_INTRRX 0x0046
47#define SUNXI_MUSB_INTRTXE 0x0048
48#define SUNXI_MUSB_INTRRXE 0x004a
49#define SUNXI_MUSB_INTRUSB 0x004c
50#define SUNXI_MUSB_INTRUSBE 0x0050
51#define SUNXI_MUSB_FRAME 0x0054
52#define SUNXI_MUSB_TXFIFOSZ 0x0090
53#define SUNXI_MUSB_TXFIFOADD 0x0092
54#define SUNXI_MUSB_RXFIFOSZ 0x0094
55#define SUNXI_MUSB_RXFIFOADD 0x0096
56#define SUNXI_MUSB_FADDR 0x0098
57#define SUNXI_MUSB_TXFUNCADDR 0x0098
58#define SUNXI_MUSB_TXHUBADDR 0x009a
59#define SUNXI_MUSB_TXHUBPORT 0x009b
60#define SUNXI_MUSB_RXFUNCADDR 0x009c
61#define SUNXI_MUSB_RXHUBADDR 0x009e
62#define SUNXI_MUSB_RXHUBPORT 0x009f
63#define SUNXI_MUSB_CONFIGDATA 0x00c0
64
65/* VEND0 bits */
66#define SUNXI_MUSB_VEND0_PIO_MODE 0
67
68/* flags */
69#define SUNXI_MUSB_FL_ENABLED 0
70#define SUNXI_MUSB_FL_HOSTMODE 1
71#define SUNXI_MUSB_FL_HOSTMODE_PEND 2
72#define SUNXI_MUSB_FL_VBUS_ON 3
73#define SUNXI_MUSB_FL_PHY_ON 4
132e2377
HG		 74#define SUNXI_MUSB_FL_HAS_SRAM 5
75#define SUNXI_MUSB_FL_HAS_RESET 6
d91de093 76#define SUNXI_MUSB_FL_NO_CONFIGDATA 7
744543c5
HG		 77
78/* Our read/write methods need access and do not get passed in a musb ref :| */
79static struct musb *sunxi_musb;
80
81struct sunxi_glue {
82 struct device *dev;
83 struct platform_device *musb;
84 struct clk *clk;
132e2377 85 struct reset_control *rst;
744543c5
HG		 86 struct phy *phy;
87 struct platform_device *usb_phy;
88 struct usb_phy *xceiv;
89 unsigned long flags;
90 struct work_struct work;
91 struct extcon_dev *extcon;
92 struct notifier_block host_nb;
93};
94
95/* phy_power_on / off may sleep, so we use a workqueue */
96static void sunxi_musb_work(struct work_struct *work)
97{
98 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
99 bool vbus_on, phy_on;
100
101 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
102 return;
103
104 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
105 struct musb *musb = platform_get_drvdata(glue->musb);
106 unsigned long flags;
107 u8 devctl;
108
109 spin_lock_irqsave(&musb->lock, flags);
110
111 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
112 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
113 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
114 musb->xceiv->otg->default_a = 1;
a60d541a 115 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
744543c5
HG		 116 MUSB_HST_MODE(musb);
117 devctl |= MUSB_DEVCTL_SESSION;
118 } else {
119 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
120 musb->xceiv->otg->default_a = 0;
121 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
122 MUSB_DEV_MODE(musb);
123 devctl &= ~MUSB_DEVCTL_SESSION;
124 }
125 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
126
127 spin_unlock_irqrestore(&musb->lock, flags);
128 }
129
130 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
131 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
132
133 if (phy_on != vbus_on) {
134 if (vbus_on) {
135 phy_power_on(glue->phy);
136 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
137 } else {
138 phy_power_off(glue->phy);
139 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
140 }
141 }
142}
143
144static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
145{
146 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
147
a60d541a 148 if (is_on) {
744543c5 149 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
a60d541a
HG		 150 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
151 } else {
744543c5 152 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
a60d541a 153 }
744543c5
HG		 154
155 schedule_work(&glue->work);
156}
157
158static void sunxi_musb_pre_root_reset_end(struct musb *musb)
159{
160 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
161
162 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
163}
164
165static void sunxi_musb_post_root_reset_end(struct musb *musb)
166{
167 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
168
169 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
170}
171
172static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
173{
174 struct musb *musb = __hci;
175 unsigned long flags;
176
177 spin_lock_irqsave(&musb->lock, flags);
178
179 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
180 if (musb->int_usb)
181 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
182
183 /*
184 * sunxi musb often signals babble on low / full speed device
185 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
186 * normally babble never happens treat it as disconnect.
187 */
188 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
189 musb->int_usb &= ~MUSB_INTR_BABBLE;
190 musb->int_usb |= MUSB_INTR_DISCONNECT;
191 }
192
193 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
194 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
195 musb_ep_select(musb->mregs, 0);
196 musb_writeb(musb->mregs, MUSB_FADDR, 0);
197 }
198
199 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
200 if (musb->int_tx)
201 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
202
203 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
204 if (musb->int_rx)
205 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
206
207 musb_interrupt(musb);
208
209 spin_unlock_irqrestore(&musb->lock, flags);
210
211 return IRQ_HANDLED;
212}
213
214static int sunxi_musb_host_notifier(struct notifier_block *nb,
215 unsigned long event, void *ptr)
216{
217 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
218
219 if (event)
220 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
221 else
222 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
223
224 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
225 schedule_work(&glue->work);
226
227 return NOTIFY_DONE;
228}
229
230static int sunxi_musb_init(struct musb *musb)
231{
232 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
233 int ret;
234
235 sunxi_musb = musb;
236 musb->phy = glue->phy;
237 musb->xceiv = glue->xceiv;
238
132e2377
HG		 239 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
240 ret = sunxi_sram_claim(musb->controller->parent);
241 if (ret)
242 return ret;
243 }
744543c5
HG		 244
245 ret = clk_prepare_enable(glue->clk);
246 if (ret)
247 goto error_sram_release;
248
132e2377
HG		 249 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
250 ret = reset_control_deassert(glue->rst);
251 if (ret)
252 goto error_clk_disable;
253 }
254
744543c5
HG		 255 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
256
257 /* Register notifier before calling phy_init() */
258 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) {
259 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
260 &glue->host_nb);
261 if (ret)
132e2377 262 goto error_reset_assert;
744543c5
HG		 263 }
264
265 ret = phy_init(glue->phy);
266 if (ret)
267 goto error_unregister_notifier;
268
744543c5
HG		 269 musb->isr = sunxi_musb_interrupt;
270
271 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
272 pm_runtime_get(musb->controller);
273
274 return 0;
275
744543c5
HG		 276error_unregister_notifier:
277 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
278 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
279 &glue->host_nb);
132e2377
HG		 280error_reset_assert:
281 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
282 reset_control_assert(glue->rst);
744543c5
HG		 283error_clk_disable:
284 clk_disable_unprepare(glue->clk);
285error_sram_release:
132e2377
HG		 286 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
287 sunxi_sram_release(musb->controller->parent);
744543c5
HG		 288 return ret;
289}
290
291static int sunxi_musb_exit(struct musb *musb)
292{
293 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
294
295 pm_runtime_put(musb->controller);
296
297 cancel_work_sync(&glue->work);
298 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
299 phy_power_off(glue->phy);
300
301 phy_exit(glue->phy);
302
303 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
304 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
305 &glue->host_nb);
306
132e2377
HG		 307 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
308 reset_control_assert(glue->rst);
309
744543c5 310 clk_disable_unprepare(glue->clk);
132e2377
HG		 311 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
312 sunxi_sram_release(musb->controller->parent);
744543c5
HG		 313
314 return 0;
315}
316
37f30d88
HG		 317static int sunxi_set_mode(struct musb *musb, u8 mode)
318{
319 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
320 int ret;
321
322 if (mode == MUSB_HOST) {
323 ret = phy_power_on(glue->phy);
324 if (ret)
325 return ret;
326
327 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
328 /* Stop musb work from turning vbus off again */
329 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
a60d541a 330 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
37f30d88
HG		 331 }
332
333 return 0;
334}
335
744543c5
HG		 336static void sunxi_musb_enable(struct musb *musb)
337{
338 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
339
340 /* musb_core does not call us in a balanced manner */
341 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
342 return;
343
344 schedule_work(&glue->work);
345}
346
347static void sunxi_musb_disable(struct musb *musb)
348{
349 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
350
351 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
352}
353
f301fe22
HG		 354struct dma_controller *sunxi_musb_dma_controller_create(struct musb *musb,
355 void __iomem *base)
356{
357 return NULL;
358}
359
360void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
361{
362}
363
744543c5
HG		 364/*
365 * sunxi musb register layout
366 * 0x00 - 0x17 fifo regs, 1 long per fifo
367 * 0x40 - 0x57 generic control regs (power - frame)
368 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
369 * 0x90 - 0x97 fifo control regs (indexed)
370 * 0x98 - 0x9f multipoint / busctl regs (indexed)
371 * 0xc0 configdata reg
372 */
373
374static u32 sunxi_musb_fifo_offset(u8 epnum)
375{
376 return (epnum * 4);
377}
378
379static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
380{
381 WARN_ONCE(offset != 0,
382 "sunxi_musb_ep_offset called with non 0 offset\n");
383
384 return 0x80; /* indexed, so ignore epnum */
385}
386
387static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
388{
389 return SUNXI_MUSB_TXFUNCADDR + offset;
390}
391
392static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
393{
d91de093
HG		 394 struct sunxi_glue *glue;
395
744543c5
HG		 396 if (addr == sunxi_musb->mregs) {
397 /* generic control or fifo control reg access */
398 switch (offset) {
399 case MUSB_FADDR:
400 return readb(addr + SUNXI_MUSB_FADDR);
401 case MUSB_POWER:
402 return readb(addr + SUNXI_MUSB_POWER);
403 case MUSB_INTRUSB:
404 return readb(addr + SUNXI_MUSB_INTRUSB);
405 case MUSB_INTRUSBE:
406 return readb(addr + SUNXI_MUSB_INTRUSBE);
407 case MUSB_INDEX:
408 return readb(addr + SUNXI_MUSB_INDEX);
409 case MUSB_TESTMODE:
410 return 0; /* No testmode on sunxi */
411 case MUSB_DEVCTL:
412 return readb(addr + SUNXI_MUSB_DEVCTL);
413 case MUSB_TXFIFOSZ:
414 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
415 case MUSB_RXFIFOSZ:
416 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
417 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
d91de093
HG		 418 glue = dev_get_drvdata(sunxi_musb->controller->parent);
419 /* A33 saves a reg, and we get to hardcode this */
420 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
421 &glue->flags))
422 return 0xde;
423
744543c5
HG		 424 return readb(addr + SUNXI_MUSB_CONFIGDATA);
425 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
426 case SUNXI_MUSB_TXFUNCADDR:
427 case SUNXI_MUSB_TXHUBADDR:
428 case SUNXI_MUSB_TXHUBPORT:
429 case SUNXI_MUSB_RXFUNCADDR:
430 case SUNXI_MUSB_RXHUBADDR:
431 case SUNXI_MUSB_RXHUBPORT:
432 /* multipoint / busctl reg access */
433 return readb(addr + offset);
434 default:
435 dev_err(sunxi_musb->controller->parent,
436 "Error unknown readb offset %u\n", offset);
437 return 0;
438 }
439 } else if (addr == (sunxi_musb->mregs + 0x80)) {
440 /* ep control reg access */
441 /* sunxi has a 2 byte hole before the txtype register */
442 if (offset >= MUSB_TXTYPE)
443 offset += 2;
444 return readb(addr + offset);
445 }
446
447 dev_err(sunxi_musb->controller->parent,
448 "Error unknown readb at 0x%x bytes offset\n",
449 (int)(addr - sunxi_musb->mregs));
450 return 0;
451}
452
453static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
454{
455 if (addr == sunxi_musb->mregs) {
456 /* generic control or fifo control reg access */
457 switch (offset) {
458 case MUSB_FADDR:
459 return writeb(data, addr + SUNXI_MUSB_FADDR);
460 case MUSB_POWER:
461 return writeb(data, addr + SUNXI_MUSB_POWER);
462 case MUSB_INTRUSB:
463 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
464 case MUSB_INTRUSBE:
465 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
466 case MUSB_INDEX:
467 return writeb(data, addr + SUNXI_MUSB_INDEX);
468 case MUSB_TESTMODE:
469 if (data)
470 dev_warn(sunxi_musb->controller->parent,
471 "sunxi-musb does not have testmode\n");
472 return;
473 case MUSB_DEVCTL:
474 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
475 case MUSB_TXFIFOSZ:
476 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
477 case MUSB_RXFIFOSZ:
478 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
479 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
480 case SUNXI_MUSB_TXFUNCADDR:
481 case SUNXI_MUSB_TXHUBADDR:
482 case SUNXI_MUSB_TXHUBPORT:
483 case SUNXI_MUSB_RXFUNCADDR:
484 case SUNXI_MUSB_RXHUBADDR:
485 case SUNXI_MUSB_RXHUBPORT:
486 /* multipoint / busctl reg access */
487 return writeb(data, addr + offset);
488 default:
489 dev_err(sunxi_musb->controller->parent,
490 "Error unknown writeb offset %u\n", offset);
491 return;
492 }
493 } else if (addr == (sunxi_musb->mregs + 0x80)) {
494 /* ep control reg access */
495 if (offset >= MUSB_TXTYPE)
496 offset += 2;
497 return writeb(data, addr + offset);
498 }
499
500 dev_err(sunxi_musb->controller->parent,
501 "Error unknown writeb at 0x%x bytes offset\n",
502 (int)(addr - sunxi_musb->mregs));
503}
504
505static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
506{
507 if (addr == sunxi_musb->mregs) {
508 /* generic control or fifo control reg access */
509 switch (offset) {
510 case MUSB_INTRTX:
511 return readw(addr + SUNXI_MUSB_INTRTX);
512 case MUSB_INTRRX:
513 return readw(addr + SUNXI_MUSB_INTRRX);
514 case MUSB_INTRTXE:
515 return readw(addr + SUNXI_MUSB_INTRTXE);
516 case MUSB_INTRRXE:
517 return readw(addr + SUNXI_MUSB_INTRRXE);
518 case MUSB_FRAME:
519 return readw(addr + SUNXI_MUSB_FRAME);
520 case MUSB_TXFIFOADD:
521 return readw(addr + SUNXI_MUSB_TXFIFOADD);
522 case MUSB_RXFIFOADD:
523 return readw(addr + SUNXI_MUSB_RXFIFOADD);
524 case MUSB_HWVERS:
525 return 0; /* sunxi musb version is not known */
526 default:
527 dev_err(sunxi_musb->controller->parent,
528 "Error unknown readw offset %u\n", offset);
529 return 0;
530 }
531 } else if (addr == (sunxi_musb->mregs + 0x80)) {
532 /* ep control reg access */
533 return readw(addr + offset);
534 }
535
536 dev_err(sunxi_musb->controller->parent,
537 "Error unknown readw at 0x%x bytes offset\n",
538 (int)(addr - sunxi_musb->mregs));
539 return 0;
540}
541
542static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
543{
544 if (addr == sunxi_musb->mregs) {
545 /* generic control or fifo control reg access */
546 switch (offset) {
547 case MUSB_INTRTX:
548 return writew(data, addr + SUNXI_MUSB_INTRTX);
549 case MUSB_INTRRX:
550 return writew(data, addr + SUNXI_MUSB_INTRRX);
551 case MUSB_INTRTXE:
552 return writew(data, addr + SUNXI_MUSB_INTRTXE);
553 case MUSB_INTRRXE:
554 return writew(data, addr + SUNXI_MUSB_INTRRXE);
555 case MUSB_FRAME:
556 return writew(data, addr + SUNXI_MUSB_FRAME);
557 case MUSB_TXFIFOADD:
558 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
559 case MUSB_RXFIFOADD:
560 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
561 default:
562 dev_err(sunxi_musb->controller->parent,
563 "Error unknown writew offset %u\n", offset);
564 return;
565 }
566 } else if (addr == (sunxi_musb->mregs + 0x80)) {
567 /* ep control reg access */
568 return writew(data, addr + offset);
569 }
570
571 dev_err(sunxi_musb->controller->parent,
572 "Error unknown writew at 0x%x bytes offset\n",
573 (int)(addr - sunxi_musb->mregs));
574}
575
576static const struct musb_platform_ops sunxi_musb_ops = {
577 .quirks = MUSB_INDEXED_EP,
578 .init = sunxi_musb_init,
579 .exit = sunxi_musb_exit,
580 .enable = sunxi_musb_enable,
581 .disable = sunxi_musb_disable,
37f30d88 582 .set_mode = sunxi_set_mode,
744543c5
HG		 583 .fifo_offset = sunxi_musb_fifo_offset,
584 .ep_offset = sunxi_musb_ep_offset,
585 .busctl_offset = sunxi_musb_busctl_offset,
586 .readb = sunxi_musb_readb,
587 .writeb = sunxi_musb_writeb,
588 .readw = sunxi_musb_readw,
589 .writew = sunxi_musb_writew,
f301fe22
HG		 590 .dma_init = sunxi_musb_dma_controller_create,
591 .dma_exit = sunxi_musb_dma_controller_destroy,
744543c5
HG		 592 .set_vbus = sunxi_musb_set_vbus,
593 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
594 .post_root_reset_end = sunxi_musb_post_root_reset_end,
595};
596
597/* Allwinner OTG supports up to 5 endpoints */
598#define SUNXI_MUSB_MAX_EP_NUM 6
599#define SUNXI_MUSB_RAM_BITS 11
600
601static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
602 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
603 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
604 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
605 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
606 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
607 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
608 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
609 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
610 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
611 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
612};
613
614static struct musb_hdrc_config sunxi_musb_hdrc_config = {
615 .fifo_cfg = sunxi_musb_mode_cfg,
616 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
617 .multipoint = true,
618 .dyn_fifo = true,
619 .soft_con = true,
620 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
621 .ram_bits = SUNXI_MUSB_RAM_BITS,
622 .dma = 0,
623};
624
625static int sunxi_musb_probe(struct platform_device *pdev)
626{
627 struct musb_hdrc_platform_data pdata;
628 struct platform_device_info pinfo;
629 struct sunxi_glue *glue;
630 struct device_node *np = pdev->dev.of_node;
631 int ret;
632
633 if (!np) {
634 dev_err(&pdev->dev, "Error no device tree node found\n");
635 return -EINVAL;
636 }
637
638 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
639 if (!glue)
640 return -ENOMEM;
641
642 memset(&pdata, 0, sizeof(pdata));
06e7114f 643 switch (usb_get_dr_mode(&pdev->dev)) {
744543c5
HG		 644#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
645 case USB_DR_MODE_HOST:
646 pdata.mode = MUSB_PORT_MODE_HOST;
647 break;
648#endif
649#ifdef CONFIG_USB_MUSB_DUAL_ROLE
650 case USB_DR_MODE_OTG:
651 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
652 if (IS_ERR(glue->extcon)) {
653 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
654 return -EPROBE_DEFER;
655 dev_err(&pdev->dev, "Invalid or missing extcon\n");
656 return PTR_ERR(glue->extcon);
657 }
658 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
659 break;
660#endif
661 default:
662 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
663 return -EINVAL;
664 }
665 pdata.platform_ops = &sunxi_musb_ops;
666 pdata.config = &sunxi_musb_hdrc_config;
667
668 glue->dev = &pdev->dev;
669 INIT_WORK(&glue->work, sunxi_musb_work);
670 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
671
132e2377
HG		 672 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
673 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
674
675 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
676 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
677
d91de093
HG		 678 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) {
679 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
680 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
681 }
682
744543c5
HG		 683 glue->clk = devm_clk_get(&pdev->dev, NULL);
684 if (IS_ERR(glue->clk)) {
685 dev_err(&pdev->dev, "Error getting clock: %ld\n",
686 PTR_ERR(glue->clk));
687 return PTR_ERR(glue->clk);
688 }
689
132e2377
HG		 690 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
691 glue->rst = devm_reset_control_get(&pdev->dev, NULL);
692 if (IS_ERR(glue->rst)) {
693 if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
694 return -EPROBE_DEFER;
695 dev_err(&pdev->dev, "Error getting reset %ld\n",
696 PTR_ERR(glue->rst));
697 return PTR_ERR(glue->rst);
698 }
699 }
700
744543c5
HG		 701 glue->phy = devm_phy_get(&pdev->dev, "usb");
702 if (IS_ERR(glue->phy)) {
703 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
704 return -EPROBE_DEFER;
705 dev_err(&pdev->dev, "Error getting phy %ld\n",
706 PTR_ERR(glue->phy));
707 return PTR_ERR(glue->phy);
708 }
709
710 glue->usb_phy = usb_phy_generic_register();
711 if (IS_ERR(glue->usb_phy)) {
712 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
713 PTR_ERR(glue->usb_phy));
714 return PTR_ERR(glue->usb_phy);
715 }
716
717 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
718 if (IS_ERR(glue->xceiv)) {
719 ret = PTR_ERR(glue->xceiv);
720 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
721 goto err_unregister_usb_phy;
722 }
723
724 platform_set_drvdata(pdev, glue);
725
726 memset(&pinfo, 0, sizeof(pinfo));
727 pinfo.name = "musb-hdrc";
728 pinfo.id = PLATFORM_DEVID_AUTO;
729 pinfo.parent = &pdev->dev;
730 pinfo.res = pdev->resource;
731 pinfo.num_res = pdev->num_resources;
732 pinfo.data = &pdata;
733 pinfo.size_data = sizeof(pdata);
734
735 glue->musb = platform_device_register_full(&pinfo);
736 if (IS_ERR(glue->musb)) {
737 ret = PTR_ERR(glue->musb);
738 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
739 goto err_unregister_usb_phy;
740 }
741
742 return 0;
743
744err_unregister_usb_phy:
745 usb_phy_generic_unregister(glue->usb_phy);
746 return ret;
747}
748
749static int sunxi_musb_remove(struct platform_device *pdev)
750{
751 struct sunxi_glue *glue = platform_get_drvdata(pdev);
752 struct platform_device *usb_phy = glue->usb_phy;
753
754 platform_device_unregister(glue->musb); /* Frees glue ! */
755 usb_phy_generic_unregister(usb_phy);
756
757 return 0;
758}
759
760static const struct of_device_id sunxi_musb_match[] = {
761 { .compatible = "allwinner,sun4i-a10-musb", },
132e2377 762 { .compatible = "allwinner,sun6i-a31-musb", },
d91de093 763 { .compatible = "allwinner,sun8i-a33-musb", },
744543c5
HG		 764 {}
765};
76485d8e 766MODULE_DEVICE_TABLE(of, sunxi_musb_match);
744543c5
HG		 767
768static struct platform_driver sunxi_musb_driver = {
769 .probe = sunxi_musb_probe,
770 .remove = sunxi_musb_remove,
771 .driver = {
772 .name = "musb-sunxi",
773 .of_match_table = sunxi_musb_match,
774 },
775};
776module_platform_driver(sunxi_musb_driver);
777
778MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
779MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
780MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)