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usb: musb: sunxi: Add set_mode platform function
[linux-2.6-block.git] / drivers / usb / musb / sunxi.c
CommitLineData
744543c5
HG		 1/*
2 * Allwinner sun4i MUSB Glue Layer
3 *
4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 *
6 * Based on code from
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/clk.h>
21#include <linux/err.h>
22#include <linux/extcon.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/phy/phy-sun4i-usb.h>
28#include <linux/platform_device.h>
132e2377 29#include <linux/reset.h>
744543c5
HG		 30#include <linux/soc/sunxi/sunxi_sram.h>
31#include <linux/usb/musb.h>
32#include <linux/usb/of.h>
33#include <linux/usb/usb_phy_generic.h>
34#include <linux/workqueue.h>
35#include "musb_core.h"
36
37/*
38 * Register offsets, note sunxi musb has a different layout then most
39 * musb implementations, we translate the layout in musb_readb & friends.
40 */
41#define SUNXI_MUSB_POWER 0x0040
42#define SUNXI_MUSB_DEVCTL 0x0041
43#define SUNXI_MUSB_INDEX 0x0042
44#define SUNXI_MUSB_VEND0 0x0043
45#define SUNXI_MUSB_INTRTX 0x0044
46#define SUNXI_MUSB_INTRRX 0x0046
47#define SUNXI_MUSB_INTRTXE 0x0048
48#define SUNXI_MUSB_INTRRXE 0x004a
49#define SUNXI_MUSB_INTRUSB 0x004c
50#define SUNXI_MUSB_INTRUSBE 0x0050
51#define SUNXI_MUSB_FRAME 0x0054
52#define SUNXI_MUSB_TXFIFOSZ 0x0090
53#define SUNXI_MUSB_TXFIFOADD 0x0092
54#define SUNXI_MUSB_RXFIFOSZ 0x0094
55#define SUNXI_MUSB_RXFIFOADD 0x0096
56#define SUNXI_MUSB_FADDR 0x0098
57#define SUNXI_MUSB_TXFUNCADDR 0x0098
58#define SUNXI_MUSB_TXHUBADDR 0x009a
59#define SUNXI_MUSB_TXHUBPORT 0x009b
60#define SUNXI_MUSB_RXFUNCADDR 0x009c
61#define SUNXI_MUSB_RXHUBADDR 0x009e
62#define SUNXI_MUSB_RXHUBPORT 0x009f
63#define SUNXI_MUSB_CONFIGDATA 0x00c0
64
65/* VEND0 bits */
66#define SUNXI_MUSB_VEND0_PIO_MODE 0
67
68/* flags */
69#define SUNXI_MUSB_FL_ENABLED 0
70#define SUNXI_MUSB_FL_HOSTMODE 1
71#define SUNXI_MUSB_FL_HOSTMODE_PEND 2
72#define SUNXI_MUSB_FL_VBUS_ON 3
73#define SUNXI_MUSB_FL_PHY_ON 4
132e2377
HG		 74#define SUNXI_MUSB_FL_HAS_SRAM 5
75#define SUNXI_MUSB_FL_HAS_RESET 6
d91de093 76#define SUNXI_MUSB_FL_NO_CONFIGDATA 7
744543c5
HG		 77
78/* Our read/write methods need access and do not get passed in a musb ref :| */
79static struct musb *sunxi_musb;
80
81struct sunxi_glue {
82 struct device *dev;
83 struct platform_device *musb;
84 struct clk *clk;
132e2377 85 struct reset_control *rst;
744543c5
HG		 86 struct phy *phy;
87 struct platform_device *usb_phy;
88 struct usb_phy *xceiv;
89 unsigned long flags;
90 struct work_struct work;
91 struct extcon_dev *extcon;
92 struct notifier_block host_nb;
93};
94
95/* phy_power_on / off may sleep, so we use a workqueue */
96static void sunxi_musb_work(struct work_struct *work)
97{
98 struct sunxi_glue *glue = container_of(work, struct sunxi_glue, work);
99 bool vbus_on, phy_on;
100
101 if (!test_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
102 return;
103
104 if (test_and_clear_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags)) {
105 struct musb *musb = platform_get_drvdata(glue->musb);
106 unsigned long flags;
107 u8 devctl;
108
109 spin_lock_irqsave(&musb->lock, flags);
110
111 devctl = readb(musb->mregs + SUNXI_MUSB_DEVCTL);
112 if (test_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags)) {
113 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
114 musb->xceiv->otg->default_a = 1;
115 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
116 MUSB_HST_MODE(musb);
117 devctl |= MUSB_DEVCTL_SESSION;
118 } else {
119 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
120 musb->xceiv->otg->default_a = 0;
121 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
122 MUSB_DEV_MODE(musb);
123 devctl &= ~MUSB_DEVCTL_SESSION;
124 }
125 writeb(devctl, musb->mregs + SUNXI_MUSB_DEVCTL);
126
127 spin_unlock_irqrestore(&musb->lock, flags);
128 }
129
130 vbus_on = test_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
131 phy_on = test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
132
133 if (phy_on != vbus_on) {
134 if (vbus_on) {
135 phy_power_on(glue->phy);
136 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
137 } else {
138 phy_power_off(glue->phy);
139 clear_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
140 }
141 }
142}
143
144static void sunxi_musb_set_vbus(struct musb *musb, int is_on)
145{
146 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
147
148 if (is_on)
149 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
150 else
151 clear_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
152
153 schedule_work(&glue->work);
154}
155
156static void sunxi_musb_pre_root_reset_end(struct musb *musb)
157{
158 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
159
160 sun4i_usb_phy_set_squelch_detect(glue->phy, false);
161}
162
163static void sunxi_musb_post_root_reset_end(struct musb *musb)
164{
165 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
166
167 sun4i_usb_phy_set_squelch_detect(glue->phy, true);
168}
169
170static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
171{
172 struct musb *musb = __hci;
173 unsigned long flags;
174
175 spin_lock_irqsave(&musb->lock, flags);
176
177 musb->int_usb = readb(musb->mregs + SUNXI_MUSB_INTRUSB);
178 if (musb->int_usb)
179 writeb(musb->int_usb, musb->mregs + SUNXI_MUSB_INTRUSB);
180
181 /*
182 * sunxi musb often signals babble on low / full speed device
183 * disconnect, without ever raising MUSB_INTR_DISCONNECT, since
184 * normally babble never happens treat it as disconnect.
185 */
186 if ((musb->int_usb & MUSB_INTR_BABBLE) && is_host_active(musb)) {
187 musb->int_usb &= ~MUSB_INTR_BABBLE;
188 musb->int_usb |= MUSB_INTR_DISCONNECT;
189 }
190
191 if ((musb->int_usb & MUSB_INTR_RESET) && !is_host_active(musb)) {
192 /* ep0 FADDR must be 0 when (re)entering peripheral mode */
193 musb_ep_select(musb->mregs, 0);
194 musb_writeb(musb->mregs, MUSB_FADDR, 0);
195 }
196
197 musb->int_tx = readw(musb->mregs + SUNXI_MUSB_INTRTX);
198 if (musb->int_tx)
199 writew(musb->int_tx, musb->mregs + SUNXI_MUSB_INTRTX);
200
201 musb->int_rx = readw(musb->mregs + SUNXI_MUSB_INTRRX);
202 if (musb->int_rx)
203 writew(musb->int_rx, musb->mregs + SUNXI_MUSB_INTRRX);
204
205 musb_interrupt(musb);
206
207 spin_unlock_irqrestore(&musb->lock, flags);
208
209 return IRQ_HANDLED;
210}
211
212static int sunxi_musb_host_notifier(struct notifier_block *nb,
213 unsigned long event, void *ptr)
214{
215 struct sunxi_glue *glue = container_of(nb, struct sunxi_glue, host_nb);
216
217 if (event)
218 set_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
219 else
220 clear_bit(SUNXI_MUSB_FL_HOSTMODE, &glue->flags);
221
222 set_bit(SUNXI_MUSB_FL_HOSTMODE_PEND, &glue->flags);
223 schedule_work(&glue->work);
224
225 return NOTIFY_DONE;
226}
227
228static int sunxi_musb_init(struct musb *musb)
229{
230 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
231 int ret;
232
233 sunxi_musb = musb;
234 musb->phy = glue->phy;
235 musb->xceiv = glue->xceiv;
236
132e2377
HG		 237 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags)) {
238 ret = sunxi_sram_claim(musb->controller->parent);
239 if (ret)
240 return ret;
241 }
744543c5
HG		 242
243 ret = clk_prepare_enable(glue->clk);
244 if (ret)
245 goto error_sram_release;
246
132e2377
HG		 247 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
248 ret = reset_control_deassert(glue->rst);
249 if (ret)
250 goto error_clk_disable;
251 }
252
744543c5
HG		 253 writeb(SUNXI_MUSB_VEND0_PIO_MODE, musb->mregs + SUNXI_MUSB_VEND0);
254
255 /* Register notifier before calling phy_init() */
256 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE) {
257 ret = extcon_register_notifier(glue->extcon, EXTCON_USB_HOST,
258 &glue->host_nb);
259 if (ret)
132e2377 260 goto error_reset_assert;
744543c5
HG		 261 }
262
263 ret = phy_init(glue->phy);
264 if (ret)
265 goto error_unregister_notifier;
266
744543c5
HG		 267 musb->isr = sunxi_musb_interrupt;
268
269 /* Stop the musb-core from doing runtime pm (not supported on sunxi) */
270 pm_runtime_get(musb->controller);
271
272 return 0;
273
744543c5
HG		 274error_unregister_notifier:
275 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
276 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
277 &glue->host_nb);
132e2377
HG		 278error_reset_assert:
279 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
280 reset_control_assert(glue->rst);
744543c5
HG		 281error_clk_disable:
282 clk_disable_unprepare(glue->clk);
283error_sram_release:
132e2377
HG		 284 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
285 sunxi_sram_release(musb->controller->parent);
744543c5
HG		 286 return ret;
287}
288
289static int sunxi_musb_exit(struct musb *musb)
290{
291 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
292
293 pm_runtime_put(musb->controller);
294
295 cancel_work_sync(&glue->work);
296 if (test_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags))
297 phy_power_off(glue->phy);
298
299 phy_exit(glue->phy);
300
301 if (musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
302 extcon_unregister_notifier(glue->extcon, EXTCON_USB_HOST,
303 &glue->host_nb);
304
132e2377
HG		 305 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags))
306 reset_control_assert(glue->rst);
307
744543c5 308 clk_disable_unprepare(glue->clk);
132e2377
HG		 309 if (test_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags))
310 sunxi_sram_release(musb->controller->parent);
744543c5
HG		 311
312 return 0;
313}
314
37f30d88
HG		 315static int sunxi_set_mode(struct musb *musb, u8 mode)
316{
317 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
318 int ret;
319
320 if (mode == MUSB_HOST) {
321 ret = phy_power_on(glue->phy);
322 if (ret)
323 return ret;
324
325 set_bit(SUNXI_MUSB_FL_PHY_ON, &glue->flags);
326 /* Stop musb work from turning vbus off again */
327 set_bit(SUNXI_MUSB_FL_VBUS_ON, &glue->flags);
328 }
329
330 return 0;
331}
332
744543c5
HG		 333static void sunxi_musb_enable(struct musb *musb)
334{
335 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
336
337 /* musb_core does not call us in a balanced manner */
338 if (test_and_set_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags))
339 return;
340
341 schedule_work(&glue->work);
342}
343
344static void sunxi_musb_disable(struct musb *musb)
345{
346 struct sunxi_glue *glue = dev_get_drvdata(musb->controller->parent);
347
348 clear_bit(SUNXI_MUSB_FL_ENABLED, &glue->flags);
349}
350
f301fe22
HG		 351struct dma_controller *sunxi_musb_dma_controller_create(struct musb *musb,
352 void __iomem *base)
353{
354 return NULL;
355}
356
357void sunxi_musb_dma_controller_destroy(struct dma_controller *c)
358{
359}
360
744543c5
HG		 361/*
362 * sunxi musb register layout
363 * 0x00 - 0x17 fifo regs, 1 long per fifo
364 * 0x40 - 0x57 generic control regs (power - frame)
365 * 0x80 - 0x8f ep control regs (addressed through hw_ep->regs, indexed)
366 * 0x90 - 0x97 fifo control regs (indexed)
367 * 0x98 - 0x9f multipoint / busctl regs (indexed)
368 * 0xc0 configdata reg
369 */
370
371static u32 sunxi_musb_fifo_offset(u8 epnum)
372{
373 return (epnum * 4);
374}
375
376static u32 sunxi_musb_ep_offset(u8 epnum, u16 offset)
377{
378 WARN_ONCE(offset != 0,
379 "sunxi_musb_ep_offset called with non 0 offset\n");
380
381 return 0x80; /* indexed, so ignore epnum */
382}
383
384static u32 sunxi_musb_busctl_offset(u8 epnum, u16 offset)
385{
386 return SUNXI_MUSB_TXFUNCADDR + offset;
387}
388
389static u8 sunxi_musb_readb(const void __iomem *addr, unsigned offset)
390{
d91de093
HG		 391 struct sunxi_glue *glue;
392
744543c5
HG		 393 if (addr == sunxi_musb->mregs) {
394 /* generic control or fifo control reg access */
395 switch (offset) {
396 case MUSB_FADDR:
397 return readb(addr + SUNXI_MUSB_FADDR);
398 case MUSB_POWER:
399 return readb(addr + SUNXI_MUSB_POWER);
400 case MUSB_INTRUSB:
401 return readb(addr + SUNXI_MUSB_INTRUSB);
402 case MUSB_INTRUSBE:
403 return readb(addr + SUNXI_MUSB_INTRUSBE);
404 case MUSB_INDEX:
405 return readb(addr + SUNXI_MUSB_INDEX);
406 case MUSB_TESTMODE:
407 return 0; /* No testmode on sunxi */
408 case MUSB_DEVCTL:
409 return readb(addr + SUNXI_MUSB_DEVCTL);
410 case MUSB_TXFIFOSZ:
411 return readb(addr + SUNXI_MUSB_TXFIFOSZ);
412 case MUSB_RXFIFOSZ:
413 return readb(addr + SUNXI_MUSB_RXFIFOSZ);
414 case MUSB_CONFIGDATA + 0x10: /* See musb_read_configdata() */
d91de093
HG		 415 glue = dev_get_drvdata(sunxi_musb->controller->parent);
416 /* A33 saves a reg, and we get to hardcode this */
417 if (test_bit(SUNXI_MUSB_FL_NO_CONFIGDATA,
418 &glue->flags))
419 return 0xde;
420
744543c5
HG		 421 return readb(addr + SUNXI_MUSB_CONFIGDATA);
422 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
423 case SUNXI_MUSB_TXFUNCADDR:
424 case SUNXI_MUSB_TXHUBADDR:
425 case SUNXI_MUSB_TXHUBPORT:
426 case SUNXI_MUSB_RXFUNCADDR:
427 case SUNXI_MUSB_RXHUBADDR:
428 case SUNXI_MUSB_RXHUBPORT:
429 /* multipoint / busctl reg access */
430 return readb(addr + offset);
431 default:
432 dev_err(sunxi_musb->controller->parent,
433 "Error unknown readb offset %u\n", offset);
434 return 0;
435 }
436 } else if (addr == (sunxi_musb->mregs + 0x80)) {
437 /* ep control reg access */
438 /* sunxi has a 2 byte hole before the txtype register */
439 if (offset >= MUSB_TXTYPE)
440 offset += 2;
441 return readb(addr + offset);
442 }
443
444 dev_err(sunxi_musb->controller->parent,
445 "Error unknown readb at 0x%x bytes offset\n",
446 (int)(addr - sunxi_musb->mregs));
447 return 0;
448}
449
450static void sunxi_musb_writeb(void __iomem *addr, unsigned offset, u8 data)
451{
452 if (addr == sunxi_musb->mregs) {
453 /* generic control or fifo control reg access */
454 switch (offset) {
455 case MUSB_FADDR:
456 return writeb(data, addr + SUNXI_MUSB_FADDR);
457 case MUSB_POWER:
458 return writeb(data, addr + SUNXI_MUSB_POWER);
459 case MUSB_INTRUSB:
460 return writeb(data, addr + SUNXI_MUSB_INTRUSB);
461 case MUSB_INTRUSBE:
462 return writeb(data, addr + SUNXI_MUSB_INTRUSBE);
463 case MUSB_INDEX:
464 return writeb(data, addr + SUNXI_MUSB_INDEX);
465 case MUSB_TESTMODE:
466 if (data)
467 dev_warn(sunxi_musb->controller->parent,
468 "sunxi-musb does not have testmode\n");
469 return;
470 case MUSB_DEVCTL:
471 return writeb(data, addr + SUNXI_MUSB_DEVCTL);
472 case MUSB_TXFIFOSZ:
473 return writeb(data, addr + SUNXI_MUSB_TXFIFOSZ);
474 case MUSB_RXFIFOSZ:
475 return writeb(data, addr + SUNXI_MUSB_RXFIFOSZ);
476 /* Offset for these is fixed by sunxi_musb_busctl_offset() */
477 case SUNXI_MUSB_TXFUNCADDR:
478 case SUNXI_MUSB_TXHUBADDR:
479 case SUNXI_MUSB_TXHUBPORT:
480 case SUNXI_MUSB_RXFUNCADDR:
481 case SUNXI_MUSB_RXHUBADDR:
482 case SUNXI_MUSB_RXHUBPORT:
483 /* multipoint / busctl reg access */
484 return writeb(data, addr + offset);
485 default:
486 dev_err(sunxi_musb->controller->parent,
487 "Error unknown writeb offset %u\n", offset);
488 return;
489 }
490 } else if (addr == (sunxi_musb->mregs + 0x80)) {
491 /* ep control reg access */
492 if (offset >= MUSB_TXTYPE)
493 offset += 2;
494 return writeb(data, addr + offset);
495 }
496
497 dev_err(sunxi_musb->controller->parent,
498 "Error unknown writeb at 0x%x bytes offset\n",
499 (int)(addr - sunxi_musb->mregs));
500}
501
502static u16 sunxi_musb_readw(const void __iomem *addr, unsigned offset)
503{
504 if (addr == sunxi_musb->mregs) {
505 /* generic control or fifo control reg access */
506 switch (offset) {
507 case MUSB_INTRTX:
508 return readw(addr + SUNXI_MUSB_INTRTX);
509 case MUSB_INTRRX:
510 return readw(addr + SUNXI_MUSB_INTRRX);
511 case MUSB_INTRTXE:
512 return readw(addr + SUNXI_MUSB_INTRTXE);
513 case MUSB_INTRRXE:
514 return readw(addr + SUNXI_MUSB_INTRRXE);
515 case MUSB_FRAME:
516 return readw(addr + SUNXI_MUSB_FRAME);
517 case MUSB_TXFIFOADD:
518 return readw(addr + SUNXI_MUSB_TXFIFOADD);
519 case MUSB_RXFIFOADD:
520 return readw(addr + SUNXI_MUSB_RXFIFOADD);
521 case MUSB_HWVERS:
522 return 0; /* sunxi musb version is not known */
523 default:
524 dev_err(sunxi_musb->controller->parent,
525 "Error unknown readw offset %u\n", offset);
526 return 0;
527 }
528 } else if (addr == (sunxi_musb->mregs + 0x80)) {
529 /* ep control reg access */
530 return readw(addr + offset);
531 }
532
533 dev_err(sunxi_musb->controller->parent,
534 "Error unknown readw at 0x%x bytes offset\n",
535 (int)(addr - sunxi_musb->mregs));
536 return 0;
537}
538
539static void sunxi_musb_writew(void __iomem *addr, unsigned offset, u16 data)
540{
541 if (addr == sunxi_musb->mregs) {
542 /* generic control or fifo control reg access */
543 switch (offset) {
544 case MUSB_INTRTX:
545 return writew(data, addr + SUNXI_MUSB_INTRTX);
546 case MUSB_INTRRX:
547 return writew(data, addr + SUNXI_MUSB_INTRRX);
548 case MUSB_INTRTXE:
549 return writew(data, addr + SUNXI_MUSB_INTRTXE);
550 case MUSB_INTRRXE:
551 return writew(data, addr + SUNXI_MUSB_INTRRXE);
552 case MUSB_FRAME:
553 return writew(data, addr + SUNXI_MUSB_FRAME);
554 case MUSB_TXFIFOADD:
555 return writew(data, addr + SUNXI_MUSB_TXFIFOADD);
556 case MUSB_RXFIFOADD:
557 return writew(data, addr + SUNXI_MUSB_RXFIFOADD);
558 default:
559 dev_err(sunxi_musb->controller->parent,
560 "Error unknown writew offset %u\n", offset);
561 return;
562 }
563 } else if (addr == (sunxi_musb->mregs + 0x80)) {
564 /* ep control reg access */
565 return writew(data, addr + offset);
566 }
567
568 dev_err(sunxi_musb->controller->parent,
569 "Error unknown writew at 0x%x bytes offset\n",
570 (int)(addr - sunxi_musb->mregs));
571}
572
573static const struct musb_platform_ops sunxi_musb_ops = {
574 .quirks = MUSB_INDEXED_EP,
575 .init = sunxi_musb_init,
576 .exit = sunxi_musb_exit,
577 .enable = sunxi_musb_enable,
578 .disable = sunxi_musb_disable,
37f30d88 579 .set_mode = sunxi_set_mode,
744543c5
HG		 580 .fifo_offset = sunxi_musb_fifo_offset,
581 .ep_offset = sunxi_musb_ep_offset,
582 .busctl_offset = sunxi_musb_busctl_offset,
583 .readb = sunxi_musb_readb,
584 .writeb = sunxi_musb_writeb,
585 .readw = sunxi_musb_readw,
586 .writew = sunxi_musb_writew,
f301fe22
HG		 587 .dma_init = sunxi_musb_dma_controller_create,
588 .dma_exit = sunxi_musb_dma_controller_destroy,
744543c5
HG		 589 .set_vbus = sunxi_musb_set_vbus,
590 .pre_root_reset_end = sunxi_musb_pre_root_reset_end,
591 .post_root_reset_end = sunxi_musb_post_root_reset_end,
592};
593
594/* Allwinner OTG supports up to 5 endpoints */
595#define SUNXI_MUSB_MAX_EP_NUM 6
596#define SUNXI_MUSB_RAM_BITS 11
597
598static struct musb_fifo_cfg sunxi_musb_mode_cfg[] = {
599 MUSB_EP_FIFO_SINGLE(1, FIFO_TX, 512),
600 MUSB_EP_FIFO_SINGLE(1, FIFO_RX, 512),
601 MUSB_EP_FIFO_SINGLE(2, FIFO_TX, 512),
602 MUSB_EP_FIFO_SINGLE(2, FIFO_RX, 512),
603 MUSB_EP_FIFO_SINGLE(3, FIFO_TX, 512),
604 MUSB_EP_FIFO_SINGLE(3, FIFO_RX, 512),
605 MUSB_EP_FIFO_SINGLE(4, FIFO_TX, 512),
606 MUSB_EP_FIFO_SINGLE(4, FIFO_RX, 512),
607 MUSB_EP_FIFO_SINGLE(5, FIFO_TX, 512),
608 MUSB_EP_FIFO_SINGLE(5, FIFO_RX, 512),
609};
610
611static struct musb_hdrc_config sunxi_musb_hdrc_config = {
612 .fifo_cfg = sunxi_musb_mode_cfg,
613 .fifo_cfg_size = ARRAY_SIZE(sunxi_musb_mode_cfg),
614 .multipoint = true,
615 .dyn_fifo = true,
616 .soft_con = true,
617 .num_eps = SUNXI_MUSB_MAX_EP_NUM,
618 .ram_bits = SUNXI_MUSB_RAM_BITS,
619 .dma = 0,
620};
621
622static int sunxi_musb_probe(struct platform_device *pdev)
623{
624 struct musb_hdrc_platform_data pdata;
625 struct platform_device_info pinfo;
626 struct sunxi_glue *glue;
627 struct device_node *np = pdev->dev.of_node;
628 int ret;
629
630 if (!np) {
631 dev_err(&pdev->dev, "Error no device tree node found\n");
632 return -EINVAL;
633 }
634
635 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
636 if (!glue)
637 return -ENOMEM;
638
639 memset(&pdata, 0, sizeof(pdata));
06e7114f 640 switch (usb_get_dr_mode(&pdev->dev)) {
744543c5
HG		 641#if defined CONFIG_USB_MUSB_DUAL_ROLE || defined CONFIG_USB_MUSB_HOST
642 case USB_DR_MODE_HOST:
643 pdata.mode = MUSB_PORT_MODE_HOST;
644 break;
645#endif
646#ifdef CONFIG_USB_MUSB_DUAL_ROLE
647 case USB_DR_MODE_OTG:
648 glue->extcon = extcon_get_edev_by_phandle(&pdev->dev, 0);
649 if (IS_ERR(glue->extcon)) {
650 if (PTR_ERR(glue->extcon) == -EPROBE_DEFER)
651 return -EPROBE_DEFER;
652 dev_err(&pdev->dev, "Invalid or missing extcon\n");
653 return PTR_ERR(glue->extcon);
654 }
655 pdata.mode = MUSB_PORT_MODE_DUAL_ROLE;
656 break;
657#endif
658 default:
659 dev_err(&pdev->dev, "Invalid or missing 'dr_mode' property\n");
660 return -EINVAL;
661 }
662 pdata.platform_ops = &sunxi_musb_ops;
663 pdata.config = &sunxi_musb_hdrc_config;
664
665 glue->dev = &pdev->dev;
666 INIT_WORK(&glue->work, sunxi_musb_work);
667 glue->host_nb.notifier_call = sunxi_musb_host_notifier;
668
132e2377
HG		 669 if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
670 set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
671
672 if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
673 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
674
d91de093
HG		 675 if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb")) {
676 set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
677 set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
678 }
679
744543c5
HG		 680 glue->clk = devm_clk_get(&pdev->dev, NULL);
681 if (IS_ERR(glue->clk)) {
682 dev_err(&pdev->dev, "Error getting clock: %ld\n",
683 PTR_ERR(glue->clk));
684 return PTR_ERR(glue->clk);
685 }
686
132e2377
HG		 687 if (test_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags)) {
688 glue->rst = devm_reset_control_get(&pdev->dev, NULL);
689 if (IS_ERR(glue->rst)) {
690 if (PTR_ERR(glue->rst) == -EPROBE_DEFER)
691 return -EPROBE_DEFER;
692 dev_err(&pdev->dev, "Error getting reset %ld\n",
693 PTR_ERR(glue->rst));
694 return PTR_ERR(glue->rst);
695 }
696 }
697
744543c5
HG		 698 glue->phy = devm_phy_get(&pdev->dev, "usb");
699 if (IS_ERR(glue->phy)) {
700 if (PTR_ERR(glue->phy) == -EPROBE_DEFER)
701 return -EPROBE_DEFER;
702 dev_err(&pdev->dev, "Error getting phy %ld\n",
703 PTR_ERR(glue->phy));
704 return PTR_ERR(glue->phy);
705 }
706
707 glue->usb_phy = usb_phy_generic_register();
708 if (IS_ERR(glue->usb_phy)) {
709 dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
710 PTR_ERR(glue->usb_phy));
711 return PTR_ERR(glue->usb_phy);
712 }
713
714 glue->xceiv = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
715 if (IS_ERR(glue->xceiv)) {
716 ret = PTR_ERR(glue->xceiv);
717 dev_err(&pdev->dev, "Error getting usb-phy %d\n", ret);
718 goto err_unregister_usb_phy;
719 }
720
721 platform_set_drvdata(pdev, glue);
722
723 memset(&pinfo, 0, sizeof(pinfo));
724 pinfo.name = "musb-hdrc";
725 pinfo.id = PLATFORM_DEVID_AUTO;
726 pinfo.parent = &pdev->dev;
727 pinfo.res = pdev->resource;
728 pinfo.num_res = pdev->num_resources;
729 pinfo.data = &pdata;
730 pinfo.size_data = sizeof(pdata);
731
732 glue->musb = platform_device_register_full(&pinfo);
733 if (IS_ERR(glue->musb)) {
734 ret = PTR_ERR(glue->musb);
735 dev_err(&pdev->dev, "Error registering musb dev: %d\n", ret);
736 goto err_unregister_usb_phy;
737 }
738
739 return 0;
740
741err_unregister_usb_phy:
742 usb_phy_generic_unregister(glue->usb_phy);
743 return ret;
744}
745
746static int sunxi_musb_remove(struct platform_device *pdev)
747{
748 struct sunxi_glue *glue = platform_get_drvdata(pdev);
749 struct platform_device *usb_phy = glue->usb_phy;
750
751 platform_device_unregister(glue->musb); /* Frees glue ! */
752 usb_phy_generic_unregister(usb_phy);
753
754 return 0;
755}
756
757static const struct of_device_id sunxi_musb_match[] = {
758 { .compatible = "allwinner,sun4i-a10-musb", },
132e2377 759 { .compatible = "allwinner,sun6i-a31-musb", },
d91de093 760 { .compatible = "allwinner,sun8i-a33-musb", },
744543c5
HG		 761 {}
762};
76485d8e 763MODULE_DEVICE_TABLE(of, sunxi_musb_match);
744543c5
HG		 764
765static struct platform_driver sunxi_musb_driver = {
766 .probe = sunxi_musb_probe,
767 .remove = sunxi_musb_remove,
768 .driver = {
769 .name = "musb-sunxi",
770 .of_match_table = sunxi_musb_match,
771 },
772};
773module_platform_driver(sunxi_musb_driver);
774
775MODULE_DESCRIPTION("Allwinner sunxi MUSB Glue Layer");
776MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
777MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)