[linux-2.6-block.git] / drivers / usb / musb / musbhsdma.c

/*
 * MUSB OTG driver - support for Mentor's DMA controller
 *
 * Copyright 2005 Mentor Graphics Corporation
 * Copyright (C) 2005-2007 by Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include "musb_core.h"

#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
#include "omap2430.h"
#endif

#define MUSB_HSDMA_BASE		0x200
#define MUSB_HSDMA_INTR		(MUSB_HSDMA_BASE + 0)
#define MUSB_HSDMA_CONTROL		0x4
#define MUSB_HSDMA_ADDRESS		0x8
#define MUSB_HSDMA_COUNT		0xc

#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset)		\
		(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)

/* control register (16-bit): */
#define MUSB_HSDMA_ENABLE_SHIFT		0
#define MUSB_HSDMA_TRANSMIT_SHIFT		1
#define MUSB_HSDMA_MODE1_SHIFT		2
#define MUSB_HSDMA_IRQENABLE_SHIFT		3
#define MUSB_HSDMA_ENDPOINT_SHIFT		4
#define MUSB_HSDMA_BUSERROR_SHIFT		8
#define MUSB_HSDMA_BURSTMODE_SHIFT		9
#define MUSB_HSDMA_BURSTMODE		(3 << MUSB_HSDMA_BURSTMODE_SHIFT)
#define MUSB_HSDMA_BURSTMODE_UNSPEC	0
#define MUSB_HSDMA_BURSTMODE_INCR4	1
#define MUSB_HSDMA_BURSTMODE_INCR8	2
#define MUSB_HSDMA_BURSTMODE_INCR16	3

#define MUSB_HSDMA_CHANNELS		8

struct musb_dma_controller;

struct musb_dma_channel {
	struct dma_channel		Channel;
	struct musb_dma_controller	*controller;
	u32				dwStartAddress;
	u32				len;
	u16				wMaxPacketSize;
	u8				bIndex;
	u8				epnum;
	u8				transmit;
};

struct musb_dma_controller {
	struct dma_controller		Controller;
	struct musb_dma_channel		aChannel[MUSB_HSDMA_CHANNELS];
	void				*pDmaPrivate;
	void __iomem			*pCoreBase;
	u8				bChannelCount;
	u8				bmUsedChannels;
	u8				irq;
};

static int dma_controller_start(struct dma_controller *c)
{
	/* nothing to do */
	return 0;
}

static void dma_channel_release(struct dma_channel *pChannel);

static int dma_controller_stop(struct dma_controller *c)
{
	struct musb_dma_controller *controller =
		container_of(c, struct musb_dma_controller, Controller);
	struct musb *musb = (struct musb *) controller->pDmaPrivate;
	struct dma_channel *pChannel;
	u8 bBit;

	if (controller->bmUsedChannels != 0) {
		dev_err(musb->controller,
			"Stopping DMA controller while channel active\n");

		for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
			if (controller->bmUsedChannels & (1 << bBit)) {
				pChannel = &controller->aChannel[bBit].Channel;
				dma_channel_release(pChannel);

				if (!controller->bmUsedChannels)
					break;
			}
		}
	}
	return 0;
}

static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 transmit)
{
	u8 bBit;
	struct dma_channel *pChannel = NULL;
	struct musb_dma_channel *pImplChannel = NULL;
	struct musb_dma_controller *controller =
			container_of(c, struct musb_dma_controller, Controller);

	for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
		if (!(controller->bmUsedChannels & (1 << bBit))) {
			controller->bmUsedChannels |= (1 << bBit);
			pImplChannel = &(controller->aChannel[bBit]);
			pImplChannel->controller = controller;
			pImplChannel->bIndex = bBit;
			pImplChannel->epnum = hw_ep->epnum;
			pImplChannel->transmit = transmit;
			pChannel = &(pImplChannel->Channel);
			pChannel->private_data = pImplChannel;
			pChannel->status = MUSB_DMA_STATUS_FREE;
			pChannel->max_len = 0x10000;
			/* Tx => mode 1; Rx => mode 0 */
			pChannel->desired_mode = transmit;
			pChannel->actual_len = 0;
			break;
		}
	}
	return pChannel;
}

static void dma_channel_release(struct dma_channel *pChannel)
{
	struct musb_dma_channel *pImplChannel =
		(struct musb_dma_channel *) pChannel->private_data;

	pChannel->actual_len = 0;
	pImplChannel->dwStartAddress = 0;
	pImplChannel->len = 0;

	pImplChannel->controller->bmUsedChannels &=
		~(1 << pImplChannel->bIndex);

	pChannel->status = MUSB_DMA_STATUS_UNKNOWN;
}

static void configure_channel(struct dma_channel *pChannel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *pImplChannel =
		(struct musb_dma_channel *) pChannel->private_data;
	struct musb_dma_controller *controller = pImplChannel->controller;
	void __iomem *mbase = controller->pCoreBase;
	u8 bChannel = pImplChannel->bIndex;
	u16 csr = 0;

	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
			pChannel, packet_sz, dma_addr, len, mode);

	if (mode) {
		csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
		BUG_ON(len < packet_sz);

		if (packet_sz >= 64) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR16
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 32) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR8
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		} else if (packet_sz >= 16) {
			csr |= MUSB_HSDMA_BURSTMODE_INCR4
					<< MUSB_HSDMA_BURSTMODE_SHIFT;
		}
	}

	csr |= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
		| (1 << MUSB_HSDMA_ENABLE_SHIFT)
		| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
		| (pImplChannel->transmit
				? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
				: 0);

	/* address/count */
	musb_writel(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
		dma_addr);
	musb_writel(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
		len);

	/* control (this should start things) */
	musb_writew(mbase,
		MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
		csr);
}

static int dma_channel_program(struct dma_channel *pChannel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct musb_dma_channel *pImplChannel =
			(struct musb_dma_channel *) pChannel->private_data;

	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
		pImplChannel->epnum,
		pImplChannel->transmit ? "Tx" : "Rx",
		packet_sz, dma_addr, len, mode);

	BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN ||
		pChannel->status == MUSB_DMA_STATUS_BUSY);

	pChannel->actual_len = 0;
	pImplChannel->dwStartAddress = dma_addr;
	pImplChannel->len = len;
	pImplChannel->wMaxPacketSize = packet_sz;
	pChannel->status = MUSB_DMA_STATUS_BUSY;

	if ((mode == 1) && (len >= packet_sz))
		configure_channel(pChannel, packet_sz, 1, dma_addr, len);
	else
		configure_channel(pChannel, packet_sz, 0, dma_addr, len);

	return true;
}

static int dma_channel_abort(struct dma_channel *pChannel)
{
	struct musb_dma_channel *pImplChannel =
		(struct musb_dma_channel *) pChannel->private_data;
	u8 bChannel = pImplChannel->bIndex;
	void __iomem *mbase = pImplChannel->controller->pCoreBase;
	u16 csr;

	if (pChannel->status == MUSB_DMA_STATUS_BUSY) {
		if (pImplChannel->transmit) {

			csr = musb_readw(mbase,
				MUSB_EP_OFFSET(pImplChannel->epnum,
						MUSB_TXCSR));
			csr &= ~(MUSB_TXCSR_AUTOSET |
				 MUSB_TXCSR_DMAENAB |
				 MUSB_TXCSR_DMAMODE);
			musb_writew(mbase,
				MUSB_EP_OFFSET(pImplChannel->epnum,
						MUSB_TXCSR),
				csr);
		} else {
			csr = musb_readw(mbase,
				MUSB_EP_OFFSET(pImplChannel->epnum,
						MUSB_RXCSR));
			csr &= ~(MUSB_RXCSR_AUTOCLEAR |
				 MUSB_RXCSR_DMAENAB |
				 MUSB_RXCSR_DMAMODE);
			musb_writew(mbase,
				MUSB_EP_OFFSET(pImplChannel->epnum,
						MUSB_RXCSR),
				csr);
		}

		musb_writew(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
			0);
		musb_writel(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
			0);
		musb_writel(mbase,
			MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
			0);

		pChannel->status = MUSB_DMA_STATUS_FREE;
	}
	return 0;
}

static irqreturn_t dma_controller_irq(int irq, void *private_data)
{
	struct musb_dma_controller *controller =
		(struct musb_dma_controller *)private_data;
	struct musb_dma_channel *pImplChannel;
	struct musb *musb = controller->pDmaPrivate;
	void __iomem *mbase = controller->pCoreBase;
	struct dma_channel *pChannel;
	u8 bChannel;
	u16 csr;
	u32 dwAddress;
	u8 int_hsdma;
	irqreturn_t retval = IRQ_NONE;
	unsigned long flags;

	spin_lock_irqsave(&musb->lock, flags);

	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
	if (!int_hsdma)
		goto done;

	for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
		if (int_hsdma & (1 << bChannel)) {
			pImplChannel = (struct musb_dma_channel *)
					&(controller->aChannel[bChannel]);
			pChannel = &pImplChannel->Channel;

			csr = musb_readw(mbase,
					MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
							MUSB_HSDMA_CONTROL));

			if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT))
				pImplChannel->Channel.status =
					MUSB_DMA_STATUS_BUS_ABORT;
			else {
				u8 devctl;

				dwAddress = musb_readl(mbase,
						MUSB_HSDMA_CHANNEL_OFFSET(
							bChannel,
							MUSB_HSDMA_ADDRESS));
				pChannel->actual_len = dwAddress
					- pImplChannel->dwStartAddress;

				DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
					pChannel, pImplChannel->dwStartAddress,
					dwAddress, pChannel->actual_len,
					pImplChannel->len,
					(pChannel->actual_len
						< pImplChannel->len) ?
					"=> reconfig 0" : "=> complete");

				devctl = musb_readb(mbase, MUSB_DEVCTL);

				pChannel->status = MUSB_DMA_STATUS_FREE;

				/* completed */
				if ((devctl & MUSB_DEVCTL_HM)
					&& (pImplChannel->transmit)
					&& ((pChannel->desired_mode == 0)
					    || (pChannel->actual_len &
					    (pImplChannel->wMaxPacketSize - 1)))
					 ) {
					/* Send out the packet */
					musb_ep_select(mbase,
						pImplChannel->epnum);
					musb_writew(mbase, MUSB_EP_OFFSET(
							pImplChannel->epnum,
							MUSB_TXCSR),
						MUSB_TXCSR_TXPKTRDY);
				} else
					musb_dma_completion(
						musb,
						pImplChannel->epnum,
						pImplChannel->transmit);
			}
		}
	}
	retval = IRQ_HANDLED;
done:
	spin_unlock_irqrestore(&musb->lock, flags);
	return retval;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct musb_dma_controller *controller;

	controller = container_of(c, struct musb_dma_controller, Controller);
	if (!controller)
		return;

	if (controller->irq)
		free_irq(controller->irq, c);

	kfree(controller);
}

struct dma_controller *__init
dma_controller_create(struct musb *musb, void __iomem *pCoreBase)
{
	struct musb_dma_controller *controller;
	struct device *dev = musb->controller;
	struct platform_device *pdev = to_platform_device(dev);
	int irq = platform_get_irq(pdev, 1);

	if (irq == 0) {
		dev_err(dev, "No DMA interrupt line!\n");
		return NULL;
	}

	controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL);
	if (!controller)
		return NULL;

	controller->bChannelCount = MUSB_HSDMA_CHANNELS;
	controller->pDmaPrivate = musb;
	controller->pCoreBase = pCoreBase;

	controller->Controller.start = dma_controller_start;
	controller->Controller.stop = dma_controller_stop;
	controller->Controller.channel_alloc = dma_channel_allocate;
	controller->Controller.channel_release = dma_channel_release;
	controller->Controller.channel_program = dma_channel_program;
	controller->Controller.channel_abort = dma_channel_abort;

	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
			musb->controller->bus_id, &controller->Controller)) {
		dev_err(dev, "request_irq %d failed!\n", irq);
		dma_controller_destroy(&controller->Controller);
		return NULL;
	}

	controller->irq = irq;

	return &controller->Controller;
}
Commit	Line	Data
550a7375 FB	1	/*
	2	* MUSB OTG driver - support for Mentor's DMA controller
	3	*
	4	* Copyright 2005 Mentor Graphics Corporation
	5	* Copyright (C) 2005-2007 by Texas Instruments
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	19	* 02110-1301 USA
	20	*
	21	* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
	22	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	23	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	24	* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
	25	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	26	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	27	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	28	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	30	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*
	32	*/
	33	#include <linux/device.h>
	34	#include <linux/interrupt.h>
	35	#include <linux/platform_device.h>
	36	#include "musb_core.h"
	37
	38	#if defined(CONFIG_ARCH_OMAP2430) \|\| defined(CONFIG_ARCH_OMAP3430)
	39	#include "omap2430.h"
	40	#endif
	41
	42	#define MUSB_HSDMA_BASE 0x200
	43	#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
	44	#define MUSB_HSDMA_CONTROL 0x4
	45	#define MUSB_HSDMA_ADDRESS 0x8
	46	#define MUSB_HSDMA_COUNT 0xc
	47
	48	#define MUSB_HSDMA_CHANNEL_OFFSET(_bChannel, _offset) \
	49	(MUSB_HSDMA_BASE + (_bChannel << 4) + _offset)
	50
	51	/* control register (16-bit): */
	52	#define MUSB_HSDMA_ENABLE_SHIFT 0
	53	#define MUSB_HSDMA_TRANSMIT_SHIFT 1
	54	#define MUSB_HSDMA_MODE1_SHIFT 2
	55	#define MUSB_HSDMA_IRQENABLE_SHIFT 3
	56	#define MUSB_HSDMA_ENDPOINT_SHIFT 4
	57	#define MUSB_HSDMA_BUSERROR_SHIFT 8
	58	#define MUSB_HSDMA_BURSTMODE_SHIFT 9
	59	#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
	60	#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
	61	#define MUSB_HSDMA_BURSTMODE_INCR4 1
	62	#define MUSB_HSDMA_BURSTMODE_INCR8 2
	63	#define MUSB_HSDMA_BURSTMODE_INCR16 3
	64
65	#define MUSB_HSDMA_CHANNELS 8
66
67	struct musb_dma_controller;
68
69	struct musb_dma_channel {
70	struct dma_channel Channel;
71	struct musb_dma_controller *controller;
72	u32 dwStartAddress;
73	u32 len;
74	u16 wMaxPacketSize;
75	u8 bIndex;
76	u8 epnum;
77	u8 transmit;
78	};
79
80	struct musb_dma_controller {
81	struct dma_controller Controller;
82	struct musb_dma_channel aChannel[MUSB_HSDMA_CHANNELS];
83	void *pDmaPrivate;
84	void __iomem *pCoreBase;
85	u8 bChannelCount;
86	u8 bmUsedChannels;
87	u8 irq;
88	};
89
90	static int dma_controller_start(struct dma_controller *c)
91	{
92	/* nothing to do */
93	return 0;
94	}
95
96	static void dma_channel_release(struct dma_channel *pChannel);
97
98	static int dma_controller_stop(struct dma_controller *c)
99	{
100	struct musb_dma_controller *controller =
101	container_of(c, struct musb_dma_controller, Controller);
102	struct musb musb = (struct musb ) controller->pDmaPrivate;
103	struct dma_channel *pChannel;
104	u8 bBit;
105
106	if (controller->bmUsedChannels != 0) {
107	dev_err(musb->controller,
108	"Stopping DMA controller while channel active\n");
109
110	for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
111	if (controller->bmUsedChannels & (1 << bBit)) {
112	pChannel = &controller->aChannel[bBit].Channel;
113	dma_channel_release(pChannel);
114
115	if (!controller->bmUsedChannels)
116	break;
117	}
118	}
119	}
120	return 0;
121	}
122
123	static struct dma_channel dma_channel_allocate(struct dma_controller c,
124	struct musb_hw_ep *hw_ep, u8 transmit)
125	{
126	u8 bBit;
127	struct dma_channel *pChannel = NULL;
128	struct musb_dma_channel *pImplChannel = NULL;
129	struct musb_dma_controller *controller =
130	container_of(c, struct musb_dma_controller, Controller);
131
132	for (bBit = 0; bBit < MUSB_HSDMA_CHANNELS; bBit++) {
133	if (!(controller->bmUsedChannels & (1 << bBit))) {
134	controller->bmUsedChannels \|= (1 << bBit);
135	pImplChannel = &(controller->aChannel[bBit]);
136	pImplChannel->controller = controller;
137	pImplChannel->bIndex = bBit;
138	pImplChannel->epnum = hw_ep->epnum;
139	pImplChannel->transmit = transmit;
140	pChannel = &(pImplChannel->Channel);
141	pChannel->private_data = pImplChannel;
142	pChannel->status = MUSB_DMA_STATUS_FREE;
143	pChannel->max_len = 0x10000;
144	/* Tx => mode 1; Rx => mode 0 */
145	pChannel->desired_mode = transmit;
146	pChannel->actual_len = 0;
147	break;
148	}
149	}
150	return pChannel;
151	}
152
153	static void dma_channel_release(struct dma_channel *pChannel)
154	{
155	struct musb_dma_channel *pImplChannel =
156	(struct musb_dma_channel *) pChannel->private_data;
157
158	pChannel->actual_len = 0;
159	pImplChannel->dwStartAddress = 0;
160	pImplChannel->len = 0;
161
162	pImplChannel->controller->bmUsedChannels &=
163	~(1 << pImplChannel->bIndex);
164
165	pChannel->status = MUSB_DMA_STATUS_UNKNOWN;
166	}
167
168	static void configure_channel(struct dma_channel *pChannel,
169	u16 packet_sz, u8 mode,
170	dma_addr_t dma_addr, u32 len)
171	{
172	struct musb_dma_channel *pImplChannel =
173	(struct musb_dma_channel *) pChannel->private_data;
174	struct musb_dma_controller *controller = pImplChannel->controller;
175	void __iomem *mbase = controller->pCoreBase;
176	u8 bChannel = pImplChannel->bIndex;
177	u16 csr = 0;
178
179	DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
180	pChannel, packet_sz, dma_addr, len, mode);
181
182	if (mode) {
183	csr \|= 1 << MUSB_HSDMA_MODE1_SHIFT;
184	BUG_ON(len < packet_sz);
185
186	if (packet_sz >= 64) {
187	csr \|= MUSB_HSDMA_BURSTMODE_INCR16
188	<< MUSB_HSDMA_BURSTMODE_SHIFT;
189	} else if (packet_sz >= 32) {
190	csr \|= MUSB_HSDMA_BURSTMODE_INCR8
191	<< MUSB_HSDMA_BURSTMODE_SHIFT;
192	} else if (packet_sz >= 16) {
193	csr \|= MUSB_HSDMA_BURSTMODE_INCR4
194	<< MUSB_HSDMA_BURSTMODE_SHIFT;
195	}
196	}
197
198	csr \|= (pImplChannel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
199	\| (1 << MUSB_HSDMA_ENABLE_SHIFT)
200	\| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
201	\| (pImplChannel->transmit
202	? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
203	: 0);
204
205	/* address/count */
206	musb_writel(mbase,
207	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
208	dma_addr);
209	musb_writel(mbase,
210	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
211	len);
212
213	/* control (this should start things) */
214	musb_writew(mbase,
215	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
216	csr);
217	}
218
219	static int dma_channel_program(struct dma_channel *pChannel,
220	u16 packet_sz, u8 mode,
221	dma_addr_t dma_addr, u32 len)
222	{
223	struct musb_dma_channel *pImplChannel =
224	(struct musb_dma_channel *) pChannel->private_data;
225
226	DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
227	pImplChannel->epnum,
228	pImplChannel->transmit ? "Tx" : "Rx",
229	packet_sz, dma_addr, len, mode);
230
231	BUG_ON(pChannel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
232	pChannel->status == MUSB_DMA_STATUS_BUSY);
233
234	pChannel->actual_len = 0;
235	pImplChannel->dwStartAddress = dma_addr;
236	pImplChannel->len = len;
237	pImplChannel->wMaxPacketSize = packet_sz;
238	pChannel->status = MUSB_DMA_STATUS_BUSY;
239
240	if ((mode == 1) && (len >= packet_sz))
241	configure_channel(pChannel, packet_sz, 1, dma_addr, len);
242	else
243	configure_channel(pChannel, packet_sz, 0, dma_addr, len);
244
245	return true;
246	}
247
248	static int dma_channel_abort(struct dma_channel *pChannel)
249	{
250	struct musb_dma_channel *pImplChannel =
251	(struct musb_dma_channel *) pChannel->private_data;
252	u8 bChannel = pImplChannel->bIndex;
253	void __iomem *mbase = pImplChannel->controller->pCoreBase;
254	u16 csr;
255
256	if (pChannel->status == MUSB_DMA_STATUS_BUSY) {
257	if (pImplChannel->transmit) {
258
259	csr = musb_readw(mbase,
260	MUSB_EP_OFFSET(pImplChannel->epnum,
261	MUSB_TXCSR));
262	csr &= ~(MUSB_TXCSR_AUTOSET \|
263	MUSB_TXCSR_DMAENAB \|
264	MUSB_TXCSR_DMAMODE);
265	musb_writew(mbase,
266	MUSB_EP_OFFSET(pImplChannel->epnum,
267	MUSB_TXCSR),
268	csr);
269	} else {
270	csr = musb_readw(mbase,
271	MUSB_EP_OFFSET(pImplChannel->epnum,
272	MUSB_RXCSR));
273	csr &= ~(MUSB_RXCSR_AUTOCLEAR \|
274	MUSB_RXCSR_DMAENAB \|
275	MUSB_RXCSR_DMAMODE);
276	musb_writew(mbase,
277	MUSB_EP_OFFSET(pImplChannel->epnum,
278	MUSB_RXCSR),
279	csr);
280	}
281
282	musb_writew(mbase,
283	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_CONTROL),
284	0);
285	musb_writel(mbase,
286	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_ADDRESS),
287	0);
288	musb_writel(mbase,
289	MUSB_HSDMA_CHANNEL_OFFSET(bChannel, MUSB_HSDMA_COUNT),
290	0);
291
292	pChannel->status = MUSB_DMA_STATUS_FREE;
293	}
294	return 0;
295	}
296
297	static irqreturn_t dma_controller_irq(int irq, void *private_data)
298	{
299	struct musb_dma_controller *controller =
300	(struct musb_dma_controller *)private_data;
301	struct musb_dma_channel *pImplChannel;
302	struct musb *musb = controller->pDmaPrivate;
303	void __iomem *mbase = controller->pCoreBase;
304	struct dma_channel *pChannel;
305	u8 bChannel;
306	u16 csr;
307	u32 dwAddress;
308	u8 int_hsdma;
309	irqreturn_t retval = IRQ_NONE;
310	unsigned long flags;
311
312	spin_lock_irqsave(&musb->lock, flags);
313
314	int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
315	if (!int_hsdma)
316	goto done;
317
318	for (bChannel = 0; bChannel < MUSB_HSDMA_CHANNELS; bChannel++) {
319	if (int_hsdma & (1 << bChannel)) {
320	pImplChannel = (struct musb_dma_channel *)
321	&(controller->aChannel[bChannel]);
322	pChannel = &pImplChannel->Channel;
323
324	csr = musb_readw(mbase,
325	MUSB_HSDMA_CHANNEL_OFFSET(bChannel,
326	MUSB_HSDMA_CONTROL));
327
328	if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT))
329	pImplChannel->Channel.status =
330	MUSB_DMA_STATUS_BUS_ABORT;
331	else {
332	u8 devctl;
333
334	dwAddress = musb_readl(mbase,
335	MUSB_HSDMA_CHANNEL_OFFSET(
336	bChannel,
337	MUSB_HSDMA_ADDRESS));
338	pChannel->actual_len = dwAddress
339	- pImplChannel->dwStartAddress;
340
341	DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
342	pChannel, pImplChannel->dwStartAddress,
343	dwAddress, pChannel->actual_len,
344	pImplChannel->len,
345	(pChannel->actual_len
346	< pImplChannel->len) ?
347	"=> reconfig 0" : "=> complete");
348
349	devctl = musb_readb(mbase, MUSB_DEVCTL);
350
351	pChannel->status = MUSB_DMA_STATUS_FREE;
352
353	/* completed */
354	if ((devctl & MUSB_DEVCTL_HM)
355	&& (pImplChannel->transmit)
356	&& ((pChannel->desired_mode == 0)
357	\|\| (pChannel->actual_len &
358	(pImplChannel->wMaxPacketSize - 1)))
359	) {
360	/* Send out the packet */
361	musb_ep_select(mbase,
362	pImplChannel->epnum);
363	musb_writew(mbase, MUSB_EP_OFFSET(
364	pImplChannel->epnum,
365	MUSB_TXCSR),
366	MUSB_TXCSR_TXPKTRDY);
367	} else
368	musb_dma_completion(
369	musb,
370	pImplChannel->epnum,
371	pImplChannel->transmit);
372	}
373	}
374	}
375	retval = IRQ_HANDLED;
376	done:
377	spin_unlock_irqrestore(&musb->lock, flags);
378	return retval;
379	}
380
381	void dma_controller_destroy(struct dma_controller *c)
382	{
383	struct musb_dma_controller *controller;
384
385	controller = container_of(c, struct musb_dma_controller, Controller);
386	if (!controller)
387	return;
388
389	if (controller->irq)
390	free_irq(controller->irq, c);
391
392	kfree(controller);
393	}
394
395	struct dma_controller *__init
396	dma_controller_create(struct musb musb, void __iomem pCoreBase)
397	{
398	struct musb_dma_controller *controller;
399	struct device *dev = musb->controller;
400	struct platform_device *pdev = to_platform_device(dev);
401	int irq = platform_get_irq(pdev, 1);
402
403	if (irq == 0) {
404	dev_err(dev, "No DMA interrupt line!\n");
405	return NULL;
406	}
407
408	controller = kzalloc(sizeof(struct musb_dma_controller), GFP_KERNEL);
409	if (!controller)
410	return NULL;
411
412	controller->bChannelCount = MUSB_HSDMA_CHANNELS;
413	controller->pDmaPrivate = musb;
414	controller->pCoreBase = pCoreBase;
415
416	controller->Controller.start = dma_controller_start;
417	controller->Controller.stop = dma_controller_stop;
418	controller->Controller.channel_alloc = dma_channel_allocate;
419	controller->Controller.channel_release = dma_channel_release;
420	controller->Controller.channel_program = dma_channel_program;
421	controller->Controller.channel_abort = dma_channel_abort;
422
423	if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
424	musb->controller->bus_id, &controller->Controller)) {
425	dev_err(dev, "request_irq %d failed!\n", irq);
426	dma_controller_destroy(&controller->Controller);
427	return NULL;
428	}
429
430	controller->irq = irq;
431
432	return &controller->Controller;
433	}