Commit | Line | Data |
---|---|---|
550a7375 FB |
1 | /* |
2 | * MUSB OTG driver host support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
c7bbc056 | 7 | * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/kernel.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/sched.h> | |
40 | #include <linux/slab.h> | |
41 | #include <linux/errno.h> | |
550a7375 | 42 | #include <linux/list.h> |
496dda70 | 43 | #include <linux/dma-mapping.h> |
550a7375 FB |
44 | |
45 | #include "musb_core.h" | |
46 | #include "musb_host.h" | |
19ca682e | 47 | #include "musb_trace.h" |
550a7375 | 48 | |
550a7375 FB |
49 | /* MUSB HOST status 22-mar-2006 |
50 | * | |
51 | * - There's still lots of partial code duplication for fault paths, so | |
52 | * they aren't handled as consistently as they need to be. | |
53 | * | |
54 | * - PIO mostly behaved when last tested. | |
55 | * + including ep0, with all usbtest cases 9, 10 | |
56 | * + usbtest 14 (ep0out) doesn't seem to run at all | |
57 | * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest | |
58 | * configurations, but otherwise double buffering passes basic tests. | |
59 | * + for 2.6.N, for N > ~10, needs API changes for hcd framework. | |
60 | * | |
61 | * - DMA (CPPI) ... partially behaves, not currently recommended | |
62 | * + about 1/15 the speed of typical EHCI implementations (PCI) | |
63 | * + RX, all too often reqpkt seems to misbehave after tx | |
64 | * + TX, no known issues (other than evident silicon issue) | |
65 | * | |
66 | * - DMA (Mentor/OMAP) ...has at least toggle update problems | |
67 | * | |
1e0320f0 AKG |
68 | * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet |
69 | * starvation ... nothing yet for TX, interrupt, or bulk. | |
550a7375 FB |
70 | * |
71 | * - Not tested with HNP, but some SRP paths seem to behave. | |
72 | * | |
73 | * NOTE 24-August-2006: | |
74 | * | |
75 | * - Bulk traffic finally uses both sides of hardware ep1, freeing up an | |
76 | * extra endpoint for periodic use enabling hub + keybd + mouse. That | |
77 | * mostly works, except that with "usbnet" it's easy to trigger cases | |
78 | * with "ping" where RX loses. (a) ping to davinci, even "ping -f", | |
79 | * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses | |
80 | * although ARP RX wins. (That test was done with a full speed link.) | |
81 | */ | |
82 | ||
83 | ||
84 | /* | |
85 | * NOTE on endpoint usage: | |
86 | * | |
87 | * CONTROL transfers all go through ep0. BULK ones go through dedicated IN | |
88 | * and OUT endpoints ... hardware is dedicated for those "async" queue(s). | |
550a7375 | 89 | * (Yes, bulk _could_ use more of the endpoints than that, and would even |
1e0320f0 | 90 | * benefit from it.) |
550a7375 FB |
91 | * |
92 | * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints. | |
93 | * So far that scheduling is both dumb and optimistic: the endpoint will be | |
94 | * "claimed" until its software queue is no longer refilled. No multiplexing | |
95 | * of transfers between endpoints, or anything clever. | |
96 | */ | |
97 | ||
74c2e936 DM |
98 | struct musb *hcd_to_musb(struct usb_hcd *hcd) |
99 | { | |
100 | return *(struct musb **) hcd->hcd_priv; | |
101 | } | |
102 | ||
550a7375 FB |
103 | |
104 | static void musb_ep_program(struct musb *musb, u8 epnum, | |
6b6e9710 SS |
105 | struct urb *urb, int is_out, |
106 | u8 *buf, u32 offset, u32 len); | |
550a7375 FB |
107 | |
108 | /* | |
109 | * Clear TX fifo. Needed to avoid BABBLE errors. | |
110 | */ | |
c767c1c6 | 111 | static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep) |
550a7375 | 112 | { |
5c8a86e1 | 113 | struct musb *musb = ep->musb; |
550a7375 FB |
114 | void __iomem *epio = ep->regs; |
115 | u16 csr; | |
116 | int retries = 1000; | |
117 | ||
118 | csr = musb_readw(epio, MUSB_TXCSR); | |
119 | while (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
2ccc6d30 | 120 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; |
550a7375 FB |
121 | musb_writew(epio, MUSB_TXCSR, csr); |
122 | csr = musb_readw(epio, MUSB_TXCSR); | |
68fe05e2 BL |
123 | |
124 | /* | |
125 | * FIXME: sometimes the tx fifo flush failed, it has been | |
126 | * observed during device disconnect on AM335x. | |
127 | * | |
128 | * To reproduce the issue, ensure tx urb(s) are queued when | |
129 | * unplug the usb device which is connected to AM335x usb | |
130 | * host port. | |
131 | * | |
132 | * I found using a usb-ethernet device and running iperf | |
133 | * (client on AM335x) has very high chance to trigger it. | |
134 | * | |
b99d3659 | 135 | * Better to turn on musb_dbg() in musb_cleanup_urb() with |
68fe05e2 BL |
136 | * CPPI enabled to see the issue when aborting the tx channel. |
137 | */ | |
138 | if (dev_WARN_ONCE(musb->controller, retries-- < 1, | |
bb1c9ef1 DB |
139 | "Could not flush host TX%d fifo: csr: %04x\n", |
140 | ep->epnum, csr)) | |
550a7375 | 141 | return; |
45d73860 | 142 | mdelay(1); |
550a7375 FB |
143 | } |
144 | } | |
145 | ||
78322c1a DB |
146 | static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep) |
147 | { | |
148 | void __iomem *epio = ep->regs; | |
149 | u16 csr; | |
150 | int retries = 5; | |
151 | ||
152 | /* scrub any data left in the fifo */ | |
153 | do { | |
154 | csr = musb_readw(epio, MUSB_TXCSR); | |
155 | if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) | |
156 | break; | |
157 | musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO); | |
158 | csr = musb_readw(epio, MUSB_TXCSR); | |
159 | udelay(10); | |
160 | } while (--retries); | |
161 | ||
162 | WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", | |
163 | ep->epnum, csr); | |
164 | ||
165 | /* and reset for the next transfer */ | |
166 | musb_writew(epio, MUSB_TXCSR, 0); | |
167 | } | |
168 | ||
550a7375 FB |
169 | /* |
170 | * Start transmit. Caller is responsible for locking shared resources. | |
171 | * musb must be locked. | |
172 | */ | |
173 | static inline void musb_h_tx_start(struct musb_hw_ep *ep) | |
174 | { | |
175 | u16 txcsr; | |
176 | ||
177 | /* NOTE: no locks here; caller should lock and select EP */ | |
178 | if (ep->epnum) { | |
179 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); | |
180 | txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS; | |
181 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); | |
182 | } else { | |
183 | txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY; | |
184 | musb_writew(ep->regs, MUSB_CSR0, txcsr); | |
185 | } | |
186 | ||
187 | } | |
188 | ||
c7bbc056 | 189 | static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep) |
550a7375 FB |
190 | { |
191 | u16 txcsr; | |
192 | ||
193 | /* NOTE: no locks here; caller should lock and select EP */ | |
194 | txcsr = musb_readw(ep->regs, MUSB_TXCSR); | |
195 | txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS; | |
f8e9f34f | 196 | if (is_cppi_enabled(ep->musb)) |
c7bbc056 | 197 | txcsr |= MUSB_TXCSR_DMAMODE; |
550a7375 FB |
198 | musb_writew(ep->regs, MUSB_TXCSR, txcsr); |
199 | } | |
200 | ||
3e5c6dc7 SS |
201 | static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh) |
202 | { | |
203 | if (is_in != 0 || ep->is_shared_fifo) | |
204 | ep->in_qh = qh; | |
205 | if (is_in == 0 || ep->is_shared_fifo) | |
206 | ep->out_qh = qh; | |
207 | } | |
208 | ||
209 | static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in) | |
210 | { | |
211 | return is_in ? ep->in_qh : ep->out_qh; | |
212 | } | |
213 | ||
550a7375 FB |
214 | /* |
215 | * Start the URB at the front of an endpoint's queue | |
216 | * end must be claimed from the caller. | |
217 | * | |
218 | * Context: controller locked, irqs blocked | |
219 | */ | |
220 | static void | |
221 | musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh) | |
222 | { | |
223 | u16 frame; | |
224 | u32 len; | |
550a7375 FB |
225 | void __iomem *mbase = musb->mregs; |
226 | struct urb *urb = next_urb(qh); | |
6b6e9710 SS |
227 | void *buf = urb->transfer_buffer; |
228 | u32 offset = 0; | |
550a7375 | 229 | struct musb_hw_ep *hw_ep = qh->hw_ep; |
550a7375 FB |
230 | int epnum = hw_ep->epnum; |
231 | ||
232 | /* initialize software qh state */ | |
233 | qh->offset = 0; | |
234 | qh->segsize = 0; | |
235 | ||
236 | /* gather right source of data */ | |
237 | switch (qh->type) { | |
238 | case USB_ENDPOINT_XFER_CONTROL: | |
239 | /* control transfers always start with SETUP */ | |
240 | is_in = 0; | |
550a7375 FB |
241 | musb->ep0_stage = MUSB_EP0_START; |
242 | buf = urb->setup_packet; | |
243 | len = 8; | |
244 | break; | |
245 | case USB_ENDPOINT_XFER_ISOC: | |
246 | qh->iso_idx = 0; | |
247 | qh->frame = 0; | |
6b6e9710 | 248 | offset = urb->iso_frame_desc[0].offset; |
550a7375 FB |
249 | len = urb->iso_frame_desc[0].length; |
250 | break; | |
251 | default: /* bulk, interrupt */ | |
1e0320f0 AKG |
252 | /* actual_length may be nonzero on retry paths */ |
253 | buf = urb->transfer_buffer + urb->actual_length; | |
254 | len = urb->transfer_buffer_length - urb->actual_length; | |
550a7375 FB |
255 | } |
256 | ||
19ca682e | 257 | trace_musb_urb_start(musb, urb); |
550a7375 FB |
258 | |
259 | /* Configure endpoint */ | |
3e5c6dc7 | 260 | musb_ep_set_qh(hw_ep, is_in, qh); |
6b6e9710 | 261 | musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len); |
550a7375 FB |
262 | |
263 | /* transmit may have more work: start it when it is time */ | |
264 | if (is_in) | |
265 | return; | |
266 | ||
267 | /* determine if the time is right for a periodic transfer */ | |
268 | switch (qh->type) { | |
269 | case USB_ENDPOINT_XFER_ISOC: | |
270 | case USB_ENDPOINT_XFER_INT: | |
b99d3659 | 271 | musb_dbg(musb, "check whether there's still time for periodic Tx"); |
550a7375 FB |
272 | frame = musb_readw(mbase, MUSB_FRAME); |
273 | /* FIXME this doesn't implement that scheduling policy ... | |
274 | * or handle framecounter wrapping | |
275 | */ | |
8a1ea51f | 276 | if (1) { /* Always assume URB_ISO_ASAP */ |
550a7375 FB |
277 | /* REVISIT the SOF irq handler shouldn't duplicate |
278 | * this code; and we don't init urb->start_frame... | |
279 | */ | |
280 | qh->frame = 0; | |
281 | goto start; | |
282 | } else { | |
283 | qh->frame = urb->start_frame; | |
284 | /* enable SOF interrupt so we can count down */ | |
b99d3659 | 285 | musb_dbg(musb, "SOF for %d", epnum); |
550a7375 FB |
286 | #if 1 /* ifndef CONFIG_ARCH_DAVINCI */ |
287 | musb_writeb(mbase, MUSB_INTRUSBE, 0xff); | |
288 | #endif | |
289 | } | |
290 | break; | |
291 | default: | |
292 | start: | |
b99d3659 | 293 | musb_dbg(musb, "Start TX%d %s", epnum, |
550a7375 FB |
294 | hw_ep->tx_channel ? "dma" : "pio"); |
295 | ||
296 | if (!hw_ep->tx_channel) | |
297 | musb_h_tx_start(hw_ep); | |
f8e9f34f | 298 | else if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) |
c7bbc056 | 299 | musb_h_tx_dma_start(hw_ep); |
550a7375 FB |
300 | } |
301 | } | |
302 | ||
c9cd06b3 SS |
303 | /* Context: caller owns controller lock, IRQs are blocked */ |
304 | static void musb_giveback(struct musb *musb, struct urb *urb, int status) | |
550a7375 FB |
305 | __releases(musb->lock) |
306 | __acquires(musb->lock) | |
307 | { | |
19ca682e | 308 | trace_musb_urb_gb(musb, urb); |
550a7375 | 309 | |
8b125df5 | 310 | usb_hcd_unlink_urb_from_ep(musb->hcd, urb); |
550a7375 | 311 | spin_unlock(&musb->lock); |
8b125df5 | 312 | usb_hcd_giveback_urb(musb->hcd, urb, status); |
550a7375 FB |
313 | spin_lock(&musb->lock); |
314 | } | |
315 | ||
846099a6 SS |
316 | /* For bulk/interrupt endpoints only */ |
317 | static inline void musb_save_toggle(struct musb_qh *qh, int is_in, | |
318 | struct urb *urb) | |
550a7375 | 319 | { |
846099a6 | 320 | void __iomem *epio = qh->hw_ep->regs; |
550a7375 | 321 | u16 csr; |
550a7375 | 322 | |
846099a6 SS |
323 | /* |
324 | * FIXME: the current Mentor DMA code seems to have | |
550a7375 FB |
325 | * problems getting toggle correct. |
326 | */ | |
327 | ||
846099a6 SS |
328 | if (is_in) |
329 | csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; | |
550a7375 | 330 | else |
846099a6 | 331 | csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; |
550a7375 | 332 | |
846099a6 | 333 | usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); |
550a7375 FB |
334 | } |
335 | ||
c9cd06b3 SS |
336 | /* |
337 | * Advance this hardware endpoint's queue, completing the specified URB and | |
338 | * advancing to either the next URB queued to that qh, or else invalidating | |
339 | * that qh and advancing to the next qh scheduled after the current one. | |
340 | * | |
341 | * Context: caller owns controller lock, IRQs are blocked | |
342 | */ | |
343 | static void musb_advance_schedule(struct musb *musb, struct urb *urb, | |
344 | struct musb_hw_ep *hw_ep, int is_in) | |
550a7375 | 345 | { |
c9cd06b3 | 346 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); |
550a7375 | 347 | struct musb_hw_ep *ep = qh->hw_ep; |
550a7375 | 348 | int ready = qh->is_ready; |
c9cd06b3 SS |
349 | int status; |
350 | ||
351 | status = (urb->status == -EINPROGRESS) ? 0 : urb->status; | |
550a7375 | 352 | |
550a7375 FB |
353 | /* save toggle eagerly, for paranoia */ |
354 | switch (qh->type) { | |
355 | case USB_ENDPOINT_XFER_BULK: | |
356 | case USB_ENDPOINT_XFER_INT: | |
846099a6 | 357 | musb_save_toggle(qh, is_in, urb); |
550a7375 FB |
358 | break; |
359 | case USB_ENDPOINT_XFER_ISOC: | |
1fe975f9 | 360 | if (status == 0 && urb->error_count) |
550a7375 FB |
361 | status = -EXDEV; |
362 | break; | |
363 | } | |
364 | ||
550a7375 | 365 | qh->is_ready = 0; |
c9cd06b3 | 366 | musb_giveback(musb, urb, status); |
550a7375 FB |
367 | qh->is_ready = ready; |
368 | ||
369 | /* reclaim resources (and bandwidth) ASAP; deschedule it, and | |
370 | * invalidate qh as soon as list_empty(&hep->urb_list) | |
371 | */ | |
372 | if (list_empty(&qh->hep->urb_list)) { | |
373 | struct list_head *head; | |
8c778db9 | 374 | struct dma_controller *dma = musb->dma_controller; |
550a7375 | 375 | |
8c778db9 | 376 | if (is_in) { |
550a7375 | 377 | ep->rx_reinit = 1; |
8c778db9 AKG |
378 | if (ep->rx_channel) { |
379 | dma->channel_release(ep->rx_channel); | |
380 | ep->rx_channel = NULL; | |
381 | } | |
382 | } else { | |
550a7375 | 383 | ep->tx_reinit = 1; |
8c778db9 AKG |
384 | if (ep->tx_channel) { |
385 | dma->channel_release(ep->tx_channel); | |
386 | ep->tx_channel = NULL; | |
387 | } | |
388 | } | |
550a7375 | 389 | |
3e5c6dc7 SS |
390 | /* Clobber old pointers to this qh */ |
391 | musb_ep_set_qh(ep, is_in, NULL); | |
550a7375 FB |
392 | qh->hep->hcpriv = NULL; |
393 | ||
394 | switch (qh->type) { | |
395 | ||
23d15e07 AKG |
396 | case USB_ENDPOINT_XFER_CONTROL: |
397 | case USB_ENDPOINT_XFER_BULK: | |
398 | /* fifo policy for these lists, except that NAKing | |
399 | * should rotate a qh to the end (for fairness). | |
400 | */ | |
401 | if (qh->mux == 1) { | |
402 | head = qh->ring.prev; | |
403 | list_del(&qh->ring); | |
404 | kfree(qh); | |
405 | qh = first_qh(head); | |
406 | break; | |
407 | } | |
408 | ||
550a7375 FB |
409 | case USB_ENDPOINT_XFER_ISOC: |
410 | case USB_ENDPOINT_XFER_INT: | |
411 | /* this is where periodic bandwidth should be | |
412 | * de-allocated if it's tracked and allocated; | |
413 | * and where we'd update the schedule tree... | |
414 | */ | |
550a7375 FB |
415 | kfree(qh); |
416 | qh = NULL; | |
417 | break; | |
550a7375 FB |
418 | } |
419 | } | |
550a7375 | 420 | |
dbac5d07 BL |
421 | /* |
422 | * The pipe must be broken if current urb->status is set, so don't | |
423 | * start next urb. | |
424 | * TODO: to minimize the risk of regression, only check urb->status | |
425 | * for RX, until we have a test case to understand the behavior of TX. | |
426 | */ | |
427 | if ((!status || !is_in) && qh && qh->is_ready) { | |
b99d3659 | 428 | musb_dbg(musb, "... next ep%d %cX urb %p", |
c9cd06b3 | 429 | hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); |
550a7375 FB |
430 | musb_start_urb(musb, is_in, qh); |
431 | } | |
432 | } | |
433 | ||
c767c1c6 | 434 | static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) |
550a7375 FB |
435 | { |
436 | /* we don't want fifo to fill itself again; | |
437 | * ignore dma (various models), | |
438 | * leave toggle alone (may not have been saved yet) | |
439 | */ | |
440 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; | |
441 | csr &= ~(MUSB_RXCSR_H_REQPKT | |
442 | | MUSB_RXCSR_H_AUTOREQ | |
443 | | MUSB_RXCSR_AUTOCLEAR); | |
444 | ||
445 | /* write 2x to allow double buffering */ | |
446 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
447 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
448 | ||
449 | /* flush writebuffer */ | |
450 | return musb_readw(hw_ep->regs, MUSB_RXCSR); | |
451 | } | |
452 | ||
453 | /* | |
454 | * PIO RX for a packet (or part of it). | |
455 | */ | |
456 | static bool | |
457 | musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err) | |
458 | { | |
459 | u16 rx_count; | |
460 | u8 *buf; | |
461 | u16 csr; | |
462 | bool done = false; | |
463 | u32 length; | |
464 | int do_flush = 0; | |
465 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
466 | void __iomem *epio = hw_ep->regs; | |
467 | struct musb_qh *qh = hw_ep->in_qh; | |
468 | int pipe = urb->pipe; | |
469 | void *buffer = urb->transfer_buffer; | |
470 | ||
471 | /* musb_ep_select(mbase, epnum); */ | |
472 | rx_count = musb_readw(epio, MUSB_RXCOUNT); | |
b99d3659 | 473 | musb_dbg(musb, "RX%d count %d, buffer %p len %d/%d", epnum, rx_count, |
550a7375 FB |
474 | urb->transfer_buffer, qh->offset, |
475 | urb->transfer_buffer_length); | |
476 | ||
477 | /* unload FIFO */ | |
478 | if (usb_pipeisoc(pipe)) { | |
479 | int status = 0; | |
480 | struct usb_iso_packet_descriptor *d; | |
481 | ||
482 | if (iso_err) { | |
483 | status = -EILSEQ; | |
484 | urb->error_count++; | |
485 | } | |
486 | ||
487 | d = urb->iso_frame_desc + qh->iso_idx; | |
488 | buf = buffer + d->offset; | |
489 | length = d->length; | |
490 | if (rx_count > length) { | |
491 | if (status == 0) { | |
492 | status = -EOVERFLOW; | |
493 | urb->error_count++; | |
494 | } | |
b99d3659 | 495 | musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length); |
550a7375 FB |
496 | do_flush = 1; |
497 | } else | |
498 | length = rx_count; | |
499 | urb->actual_length += length; | |
500 | d->actual_length = length; | |
501 | ||
502 | d->status = status; | |
503 | ||
504 | /* see if we are done */ | |
505 | done = (++qh->iso_idx >= urb->number_of_packets); | |
506 | } else { | |
507 | /* non-isoch */ | |
508 | buf = buffer + qh->offset; | |
509 | length = urb->transfer_buffer_length - qh->offset; | |
510 | if (rx_count > length) { | |
511 | if (urb->status == -EINPROGRESS) | |
512 | urb->status = -EOVERFLOW; | |
b99d3659 | 513 | musb_dbg(musb, "OVERFLOW %d into %d", rx_count, length); |
550a7375 FB |
514 | do_flush = 1; |
515 | } else | |
516 | length = rx_count; | |
517 | urb->actual_length += length; | |
518 | qh->offset += length; | |
519 | ||
520 | /* see if we are done */ | |
521 | done = (urb->actual_length == urb->transfer_buffer_length) | |
522 | || (rx_count < qh->maxpacket) | |
523 | || (urb->status != -EINPROGRESS); | |
524 | if (done | |
525 | && (urb->status == -EINPROGRESS) | |
526 | && (urb->transfer_flags & URB_SHORT_NOT_OK) | |
527 | && (urb->actual_length | |
528 | < urb->transfer_buffer_length)) | |
529 | urb->status = -EREMOTEIO; | |
530 | } | |
531 | ||
532 | musb_read_fifo(hw_ep, length, buf); | |
533 | ||
534 | csr = musb_readw(epio, MUSB_RXCSR); | |
535 | csr |= MUSB_RXCSR_H_WZC_BITS; | |
536 | if (unlikely(do_flush)) | |
537 | musb_h_flush_rxfifo(hw_ep, csr); | |
538 | else { | |
539 | /* REVISIT this assumes AUTOCLEAR is never set */ | |
540 | csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); | |
541 | if (!done) | |
542 | csr |= MUSB_RXCSR_H_REQPKT; | |
543 | musb_writew(epio, MUSB_RXCSR, csr); | |
544 | } | |
545 | ||
546 | return done; | |
547 | } | |
548 | ||
549 | /* we don't always need to reinit a given side of an endpoint... | |
550 | * when we do, use tx/rx reinit routine and then construct a new CSR | |
551 | * to address data toggle, NYET, and DMA or PIO. | |
552 | * | |
553 | * it's possible that driver bugs (especially for DMA) or aborting a | |
554 | * transfer might have left the endpoint busier than it should be. | |
555 | * the busy/not-empty tests are basically paranoia. | |
556 | */ | |
557 | static void | |
0cb74b3d | 558 | musb_rx_reinit(struct musb *musb, struct musb_qh *qh, u8 epnum) |
550a7375 | 559 | { |
0cb74b3d | 560 | struct musb_hw_ep *ep = musb->endpoints + epnum; |
550a7375 FB |
561 | u16 csr; |
562 | ||
563 | /* NOTE: we know the "rx" fifo reinit never triggers for ep0. | |
564 | * That always uses tx_reinit since ep0 repurposes TX register | |
565 | * offsets; the initial SETUP packet is also a kind of OUT. | |
566 | */ | |
567 | ||
568 | /* if programmed for Tx, put it in RX mode */ | |
569 | if (ep->is_shared_fifo) { | |
570 | csr = musb_readw(ep->regs, MUSB_TXCSR); | |
571 | if (csr & MUSB_TXCSR_MODE) { | |
572 | musb_h_tx_flush_fifo(ep); | |
b6e434a5 | 573 | csr = musb_readw(ep->regs, MUSB_TXCSR); |
550a7375 | 574 | musb_writew(ep->regs, MUSB_TXCSR, |
b6e434a5 | 575 | csr | MUSB_TXCSR_FRCDATATOG); |
550a7375 | 576 | } |
b6e434a5 SS |
577 | |
578 | /* | |
579 | * Clear the MODE bit (and everything else) to enable Rx. | |
580 | * NOTE: we mustn't clear the DMAMODE bit before DMAENAB. | |
581 | */ | |
582 | if (csr & MUSB_TXCSR_DMAMODE) | |
583 | musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); | |
550a7375 FB |
584 | musb_writew(ep->regs, MUSB_TXCSR, 0); |
585 | ||
586 | /* scrub all previous state, clearing toggle */ | |
550a7375 | 587 | } |
f3eec0cf AG |
588 | csr = musb_readw(ep->regs, MUSB_RXCSR); |
589 | if (csr & MUSB_RXCSR_RXPKTRDY) | |
590 | WARNING("rx%d, packet/%d ready?\n", ep->epnum, | |
591 | musb_readw(ep->regs, MUSB_RXCOUNT)); | |
592 | ||
593 | musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG); | |
550a7375 FB |
594 | |
595 | /* target addr and (for multipoint) hub addr/port */ | |
596 | if (musb->is_multipoint) { | |
6cc2af6d HG |
597 | musb_write_rxfunaddr(musb, epnum, qh->addr_reg); |
598 | musb_write_rxhubaddr(musb, epnum, qh->h_addr_reg); | |
599 | musb_write_rxhubport(musb, epnum, qh->h_port_reg); | |
550a7375 FB |
600 | } else |
601 | musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); | |
602 | ||
603 | /* protocol/endpoint, interval/NAKlimit, i/o size */ | |
604 | musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); | |
605 | musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); | |
606 | /* NOTE: bulk combining rewrites high bits of maxpacket */ | |
9f445cb2 CC |
607 | /* Set RXMAXP with the FIFO size of the endpoint |
608 | * to disable double buffer mode. | |
609 | */ | |
06624818 | 610 | if (musb->double_buffer_not_ok) |
9f445cb2 CC |
611 | musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); |
612 | else | |
613 | musb_writew(ep->regs, MUSB_RXMAXP, | |
614 | qh->maxpacket | ((qh->hb_mult - 1) << 11)); | |
550a7375 FB |
615 | |
616 | ep->rx_reinit = 0; | |
617 | } | |
618 | ||
b6a6631d | 619 | static void musb_tx_dma_set_mode_mentor(struct dma_controller *dma, |
6b6e9710 | 620 | struct musb_hw_ep *hw_ep, struct musb_qh *qh, |
754fe4a9 TL |
621 | struct urb *urb, u32 offset, |
622 | u32 *length, u8 *mode) | |
6b6e9710 SS |
623 | { |
624 | struct dma_channel *channel = hw_ep->tx_channel; | |
625 | void __iomem *epio = hw_ep->regs; | |
626 | u16 pkt_size = qh->maxpacket; | |
627 | u16 csr; | |
6b6e9710 | 628 | |
754fe4a9 TL |
629 | if (*length > channel->max_len) |
630 | *length = channel->max_len; | |
6b6e9710 SS |
631 | |
632 | csr = musb_readw(epio, MUSB_TXCSR); | |
754fe4a9 TL |
633 | if (*length > pkt_size) { |
634 | *mode = 1; | |
a483d706 AKG |
635 | csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; |
636 | /* autoset shouldn't be set in high bandwidth */ | |
f2786281 | 637 | /* |
638 | * Enable Autoset according to table | |
639 | * below | |
640 | * bulk_split hb_mult Autoset_Enable | |
641 | * 0 1 Yes(Normal) | |
642 | * 0 >1 No(High BW ISO) | |
643 | * 1 1 Yes(HS bulk) | |
644 | * 1 >1 Yes(FS bulk) | |
645 | */ | |
646 | if (qh->hb_mult == 1 || (qh->hb_mult > 1 && | |
647 | can_bulk_split(hw_ep->musb, qh->type))) | |
a483d706 | 648 | csr |= MUSB_TXCSR_AUTOSET; |
6b6e9710 | 649 | } else { |
754fe4a9 | 650 | *mode = 0; |
6b6e9710 SS |
651 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); |
652 | csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ | |
653 | } | |
bba40e69 | 654 | channel->desired_mode = *mode; |
6b6e9710 | 655 | musb_writew(epio, MUSB_TXCSR, csr); |
754fe4a9 TL |
656 | } |
657 | ||
b6a6631d SS |
658 | static void musb_tx_dma_set_mode_cppi_tusb(struct dma_controller *dma, |
659 | struct musb_hw_ep *hw_ep, | |
660 | struct musb_qh *qh, | |
661 | struct urb *urb, | |
662 | u32 offset, | |
663 | u32 *length, | |
664 | u8 *mode) | |
754fe4a9 TL |
665 | { |
666 | struct dma_channel *channel = hw_ep->tx_channel; | |
667 | ||
6b6e9710 SS |
668 | channel->actual_len = 0; |
669 | ||
670 | /* | |
671 | * TX uses "RNDIS" mode automatically but needs help | |
672 | * to identify the zero-length-final-packet case. | |
673 | */ | |
754fe4a9 | 674 | *mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; |
754fe4a9 TL |
675 | } |
676 | ||
677 | static bool musb_tx_dma_program(struct dma_controller *dma, | |
678 | struct musb_hw_ep *hw_ep, struct musb_qh *qh, | |
679 | struct urb *urb, u32 offset, u32 length) | |
680 | { | |
681 | struct dma_channel *channel = hw_ep->tx_channel; | |
682 | u16 pkt_size = qh->maxpacket; | |
683 | u8 mode; | |
754fe4a9 TL |
684 | |
685 | if (musb_dma_inventra(hw_ep->musb) || musb_dma_ux500(hw_ep->musb)) | |
b6a6631d SS |
686 | musb_tx_dma_set_mode_mentor(dma, hw_ep, qh, urb, offset, |
687 | &length, &mode); | |
858b9be7 | 688 | else if (is_cppi_enabled(hw_ep->musb) || tusb_dma_omap(hw_ep->musb)) |
b6a6631d SS |
689 | musb_tx_dma_set_mode_cppi_tusb(dma, hw_ep, qh, urb, offset, |
690 | &length, &mode); | |
858b9be7 SS |
691 | else |
692 | return false; | |
6b6e9710 SS |
693 | |
694 | qh->segsize = length; | |
695 | ||
4c647338 SS |
696 | /* |
697 | * Ensure the data reaches to main memory before starting | |
698 | * DMA transfer | |
699 | */ | |
700 | wmb(); | |
701 | ||
6b6e9710 SS |
702 | if (!dma->channel_program(channel, pkt_size, mode, |
703 | urb->transfer_dma + offset, length)) { | |
754fe4a9 TL |
704 | void __iomem *epio = hw_ep->regs; |
705 | u16 csr; | |
706 | ||
6b6e9710 SS |
707 | dma->channel_release(channel); |
708 | hw_ep->tx_channel = NULL; | |
709 | ||
710 | csr = musb_readw(epio, MUSB_TXCSR); | |
711 | csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); | |
712 | musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); | |
713 | return false; | |
714 | } | |
715 | return true; | |
716 | } | |
550a7375 FB |
717 | |
718 | /* | |
719 | * Program an HDRC endpoint as per the given URB | |
720 | * Context: irqs blocked, controller lock held | |
721 | */ | |
722 | static void musb_ep_program(struct musb *musb, u8 epnum, | |
6b6e9710 SS |
723 | struct urb *urb, int is_out, |
724 | u8 *buf, u32 offset, u32 len) | |
550a7375 FB |
725 | { |
726 | struct dma_controller *dma_controller; | |
727 | struct dma_channel *dma_channel; | |
728 | u8 dma_ok; | |
729 | void __iomem *mbase = musb->mregs; | |
730 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
731 | void __iomem *epio = hw_ep->regs; | |
3e5c6dc7 SS |
732 | struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); |
733 | u16 packet_sz = qh->maxpacket; | |
3132122c AKG |
734 | u8 use_dma = 1; |
735 | u16 csr; | |
550a7375 | 736 | |
b99d3659 BL |
737 | musb_dbg(musb, "%s hw%d urb %p spd%d dev%d ep%d%s " |
738 | "h_addr%02x h_port%02x bytes %d", | |
550a7375 FB |
739 | is_out ? "-->" : "<--", |
740 | epnum, urb, urb->dev->speed, | |
741 | qh->addr_reg, qh->epnum, is_out ? "out" : "in", | |
742 | qh->h_addr_reg, qh->h_port_reg, | |
743 | len); | |
744 | ||
745 | musb_ep_select(mbase, epnum); | |
746 | ||
3132122c AKG |
747 | if (is_out && !len) { |
748 | use_dma = 0; | |
749 | csr = musb_readw(epio, MUSB_TXCSR); | |
750 | csr &= ~MUSB_TXCSR_DMAENAB; | |
751 | musb_writew(epio, MUSB_TXCSR, csr); | |
752 | hw_ep->tx_channel = NULL; | |
753 | } | |
754 | ||
550a7375 FB |
755 | /* candidate for DMA? */ |
756 | dma_controller = musb->dma_controller; | |
3132122c | 757 | if (use_dma && is_dma_capable() && epnum && dma_controller) { |
550a7375 FB |
758 | dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; |
759 | if (!dma_channel) { | |
760 | dma_channel = dma_controller->channel_alloc( | |
761 | dma_controller, hw_ep, is_out); | |
762 | if (is_out) | |
763 | hw_ep->tx_channel = dma_channel; | |
764 | else | |
765 | hw_ep->rx_channel = dma_channel; | |
766 | } | |
767 | } else | |
768 | dma_channel = NULL; | |
769 | ||
770 | /* make sure we clear DMAEnab, autoSet bits from previous run */ | |
771 | ||
772 | /* OUT/transmit/EP0 or IN/receive? */ | |
773 | if (is_out) { | |
774 | u16 csr; | |
775 | u16 int_txe; | |
776 | u16 load_count; | |
777 | ||
778 | csr = musb_readw(epio, MUSB_TXCSR); | |
779 | ||
780 | /* disable interrupt in case we flush */ | |
b18d26f6 | 781 | int_txe = musb->intrtxe; |
550a7375 FB |
782 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); |
783 | ||
784 | /* general endpoint setup */ | |
785 | if (epnum) { | |
550a7375 | 786 | /* flush all old state, set default */ |
a70b8442 | 787 | /* |
788 | * We could be flushing valid | |
789 | * packets in double buffering | |
790 | * case | |
791 | */ | |
792 | if (!hw_ep->tx_double_buffered) | |
793 | musb_h_tx_flush_fifo(hw_ep); | |
b6e434a5 SS |
794 | |
795 | /* | |
796 | * We must not clear the DMAMODE bit before or in | |
797 | * the same cycle with the DMAENAB bit, so we clear | |
798 | * the latter first... | |
799 | */ | |
550a7375 | 800 | csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT |
b6e434a5 SS |
801 | | MUSB_TXCSR_AUTOSET |
802 | | MUSB_TXCSR_DMAENAB | |
550a7375 FB |
803 | | MUSB_TXCSR_FRCDATATOG |
804 | | MUSB_TXCSR_H_RXSTALL | |
805 | | MUSB_TXCSR_H_ERROR | |
806 | | MUSB_TXCSR_TXPKTRDY | |
807 | ); | |
808 | csr |= MUSB_TXCSR_MODE; | |
809 | ||
a70b8442 | 810 | if (!hw_ep->tx_double_buffered) { |
811 | if (usb_gettoggle(urb->dev, qh->epnum, 1)) | |
812 | csr |= MUSB_TXCSR_H_WR_DATATOGGLE | |
813 | | MUSB_TXCSR_H_DATATOGGLE; | |
814 | else | |
815 | csr |= MUSB_TXCSR_CLRDATATOG; | |
816 | } | |
550a7375 | 817 | |
550a7375 FB |
818 | musb_writew(epio, MUSB_TXCSR, csr); |
819 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
b6e434a5 | 820 | csr &= ~MUSB_TXCSR_DMAMODE; |
550a7375 FB |
821 | musb_writew(epio, MUSB_TXCSR, csr); |
822 | csr = musb_readw(epio, MUSB_TXCSR); | |
823 | } else { | |
824 | /* endpoint 0: just flush */ | |
78322c1a | 825 | musb_h_ep0_flush_fifo(hw_ep); |
550a7375 FB |
826 | } |
827 | ||
828 | /* target addr and (for multipoint) hub addr/port */ | |
829 | if (musb->is_multipoint) { | |
6cc2af6d HG |
830 | musb_write_txfunaddr(musb, epnum, qh->addr_reg); |
831 | musb_write_txhubaddr(musb, epnum, qh->h_addr_reg); | |
832 | musb_write_txhubport(musb, epnum, qh->h_port_reg); | |
550a7375 FB |
833 | /* FIXME if !epnum, do the same for RX ... */ |
834 | } else | |
835 | musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); | |
836 | ||
837 | /* protocol/endpoint/interval/NAKlimit */ | |
838 | if (epnum) { | |
839 | musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); | |
f2786281 | 840 | if (musb->double_buffer_not_ok) { |
550a7375 | 841 | musb_writew(epio, MUSB_TXMAXP, |
06624818 | 842 | hw_ep->max_packet_sz_tx); |
f2786281 | 843 | } else if (can_bulk_split(musb, qh->type)) { |
844 | qh->hb_mult = hw_ep->max_packet_sz_tx | |
845 | / packet_sz; | |
ccc080c7 | 846 | musb_writew(epio, MUSB_TXMAXP, packet_sz |
f2786281 | 847 | | ((qh->hb_mult) - 1) << 11); |
848 | } else { | |
550a7375 | 849 | musb_writew(epio, MUSB_TXMAXP, |
06624818 FB |
850 | qh->maxpacket | |
851 | ((qh->hb_mult - 1) << 11)); | |
f2786281 | 852 | } |
550a7375 FB |
853 | musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); |
854 | } else { | |
855 | musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); | |
856 | if (musb->is_multipoint) | |
857 | musb_writeb(epio, MUSB_TYPE0, | |
858 | qh->type_reg); | |
859 | } | |
860 | ||
861 | if (can_bulk_split(musb, qh->type)) | |
862 | load_count = min((u32) hw_ep->max_packet_sz_tx, | |
863 | len); | |
864 | else | |
865 | load_count = min((u32) packet_sz, len); | |
866 | ||
6b6e9710 SS |
867 | if (dma_channel && musb_tx_dma_program(dma_controller, |
868 | hw_ep, qh, urb, offset, len)) | |
869 | load_count = 0; | |
550a7375 FB |
870 | |
871 | if (load_count) { | |
550a7375 FB |
872 | /* PIO to load FIFO */ |
873 | qh->segsize = load_count; | |
8e8a5516 VS |
874 | if (!buf) { |
875 | sg_miter_start(&qh->sg_miter, urb->sg, 1, | |
876 | SG_MITER_ATOMIC | |
877 | | SG_MITER_FROM_SG); | |
878 | if (!sg_miter_next(&qh->sg_miter)) { | |
879 | dev_err(musb->controller, | |
880 | "error: sg" | |
881 | "list empty\n"); | |
882 | sg_miter_stop(&qh->sg_miter); | |
883 | goto finish; | |
884 | } | |
885 | buf = qh->sg_miter.addr + urb->sg->offset + | |
886 | urb->actual_length; | |
887 | load_count = min_t(u32, load_count, | |
888 | qh->sg_miter.length); | |
889 | musb_write_fifo(hw_ep, load_count, buf); | |
890 | qh->sg_miter.consumed = load_count; | |
891 | sg_miter_stop(&qh->sg_miter); | |
892 | } else | |
893 | musb_write_fifo(hw_ep, load_count, buf); | |
550a7375 | 894 | } |
8e8a5516 | 895 | finish: |
550a7375 FB |
896 | /* re-enable interrupt */ |
897 | musb_writew(mbase, MUSB_INTRTXE, int_txe); | |
898 | ||
899 | /* IN/receive */ | |
900 | } else { | |
901 | u16 csr; | |
902 | ||
903 | if (hw_ep->rx_reinit) { | |
0cb74b3d | 904 | musb_rx_reinit(musb, qh, epnum); |
550a7375 FB |
905 | |
906 | /* init new state: toggle and NYET, maybe DMA later */ | |
907 | if (usb_gettoggle(urb->dev, qh->epnum, 0)) | |
908 | csr = MUSB_RXCSR_H_WR_DATATOGGLE | |
909 | | MUSB_RXCSR_H_DATATOGGLE; | |
910 | else | |
911 | csr = 0; | |
912 | if (qh->type == USB_ENDPOINT_XFER_INT) | |
913 | csr |= MUSB_RXCSR_DISNYET; | |
914 | ||
915 | } else { | |
916 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
917 | ||
918 | if (csr & (MUSB_RXCSR_RXPKTRDY | |
919 | | MUSB_RXCSR_DMAENAB | |
920 | | MUSB_RXCSR_H_REQPKT)) | |
921 | ERR("broken !rx_reinit, ep%d csr %04x\n", | |
922 | hw_ep->epnum, csr); | |
923 | ||
924 | /* scrub any stale state, leaving toggle alone */ | |
925 | csr &= MUSB_RXCSR_DISNYET; | |
926 | } | |
927 | ||
928 | /* kick things off */ | |
929 | ||
f8e9f34f | 930 | if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) { |
c51e36dc SS |
931 | /* Candidate for DMA */ |
932 | dma_channel->actual_len = 0L; | |
933 | qh->segsize = len; | |
934 | ||
935 | /* AUTOREQ is in a DMA register */ | |
936 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); | |
937 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
938 | ||
939 | /* | |
940 | * Unless caller treats short RX transfers as | |
941 | * errors, we dare not queue multiple transfers. | |
942 | */ | |
943 | dma_ok = dma_controller->channel_program(dma_channel, | |
944 | packet_sz, !(urb->transfer_flags & | |
945 | URB_SHORT_NOT_OK), | |
946 | urb->transfer_dma + offset, | |
947 | qh->segsize); | |
948 | if (!dma_ok) { | |
949 | dma_controller->channel_release(dma_channel); | |
950 | hw_ep->rx_channel = dma_channel = NULL; | |
951 | } else | |
952 | csr |= MUSB_RXCSR_DMAENAB; | |
550a7375 FB |
953 | } |
954 | ||
955 | csr |= MUSB_RXCSR_H_REQPKT; | |
b99d3659 | 956 | musb_dbg(musb, "RXCSR%d := %04x", epnum, csr); |
550a7375 FB |
957 | musb_writew(hw_ep->regs, MUSB_RXCSR, csr); |
958 | csr = musb_readw(hw_ep->regs, MUSB_RXCSR); | |
959 | } | |
960 | } | |
961 | ||
f283862f AKG |
962 | /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to |
963 | * the end; avoids starvation for other endpoints. | |
964 | */ | |
965 | static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep, | |
966 | int is_in) | |
967 | { | |
968 | struct dma_channel *dma; | |
969 | struct urb *urb; | |
970 | void __iomem *mbase = musb->mregs; | |
971 | void __iomem *epio = ep->regs; | |
972 | struct musb_qh *cur_qh, *next_qh; | |
973 | u16 rx_csr, tx_csr; | |
974 | ||
975 | musb_ep_select(mbase, ep->epnum); | |
976 | if (is_in) { | |
977 | dma = is_dma_capable() ? ep->rx_channel : NULL; | |
978 | ||
7b2c17f8 AG |
979 | /* |
980 | * Need to stop the transaction by clearing REQPKT first | |
981 | * then the NAK Timeout bit ref MUSBMHDRC USB 2.0 HIGH-SPEED | |
982 | * DUAL-ROLE CONTROLLER Programmer's Guide, section 9.2.2 | |
983 | */ | |
f283862f AKG |
984 | rx_csr = musb_readw(epio, MUSB_RXCSR); |
985 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; | |
7b2c17f8 AG |
986 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; |
987 | musb_writew(epio, MUSB_RXCSR, rx_csr); | |
f283862f AKG |
988 | rx_csr &= ~MUSB_RXCSR_DATAERROR; |
989 | musb_writew(epio, MUSB_RXCSR, rx_csr); | |
990 | ||
991 | cur_qh = first_qh(&musb->in_bulk); | |
992 | } else { | |
993 | dma = is_dma_capable() ? ep->tx_channel : NULL; | |
994 | ||
995 | /* clear nak timeout bit */ | |
996 | tx_csr = musb_readw(epio, MUSB_TXCSR); | |
997 | tx_csr |= MUSB_TXCSR_H_WZC_BITS; | |
998 | tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT; | |
999 | musb_writew(epio, MUSB_TXCSR, tx_csr); | |
1000 | ||
1001 | cur_qh = first_qh(&musb->out_bulk); | |
1002 | } | |
1003 | if (cur_qh) { | |
1004 | urb = next_urb(cur_qh); | |
1005 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1006 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
1007 | musb->dma_controller->channel_abort(dma); | |
1008 | urb->actual_length += dma->actual_len; | |
1009 | dma->actual_len = 0L; | |
1010 | } | |
1011 | musb_save_toggle(cur_qh, is_in, urb); | |
1012 | ||
1013 | if (is_in) { | |
1014 | /* move cur_qh to end of queue */ | |
1015 | list_move_tail(&cur_qh->ring, &musb->in_bulk); | |
1016 | ||
1017 | /* get the next qh from musb->in_bulk */ | |
1018 | next_qh = first_qh(&musb->in_bulk); | |
1019 | ||
1020 | /* set rx_reinit and schedule the next qh */ | |
1021 | ep->rx_reinit = 1; | |
1022 | } else { | |
1023 | /* move cur_qh to end of queue */ | |
1024 | list_move_tail(&cur_qh->ring, &musb->out_bulk); | |
1025 | ||
1026 | /* get the next qh from musb->out_bulk */ | |
1027 | next_qh = first_qh(&musb->out_bulk); | |
1028 | ||
1029 | /* set tx_reinit and schedule the next qh */ | |
1030 | ep->tx_reinit = 1; | |
1031 | } | |
1032 | musb_start_urb(musb, is_in, next_qh); | |
1033 | } | |
1034 | } | |
550a7375 FB |
1035 | |
1036 | /* | |
1037 | * Service the default endpoint (ep0) as host. | |
1038 | * Return true until it's time to start the status stage. | |
1039 | */ | |
1040 | static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb) | |
1041 | { | |
1042 | bool more = false; | |
1043 | u8 *fifo_dest = NULL; | |
1044 | u16 fifo_count = 0; | |
1045 | struct musb_hw_ep *hw_ep = musb->control_ep; | |
1046 | struct musb_qh *qh = hw_ep->in_qh; | |
1047 | struct usb_ctrlrequest *request; | |
1048 | ||
1049 | switch (musb->ep0_stage) { | |
1050 | case MUSB_EP0_IN: | |
1051 | fifo_dest = urb->transfer_buffer + urb->actual_length; | |
3ecdb9ac SS |
1052 | fifo_count = min_t(size_t, len, urb->transfer_buffer_length - |
1053 | urb->actual_length); | |
550a7375 FB |
1054 | if (fifo_count < len) |
1055 | urb->status = -EOVERFLOW; | |
1056 | ||
1057 | musb_read_fifo(hw_ep, fifo_count, fifo_dest); | |
1058 | ||
1059 | urb->actual_length += fifo_count; | |
1060 | if (len < qh->maxpacket) { | |
1061 | /* always terminate on short read; it's | |
1062 | * rarely reported as an error. | |
1063 | */ | |
1064 | } else if (urb->actual_length < | |
1065 | urb->transfer_buffer_length) | |
1066 | more = true; | |
1067 | break; | |
1068 | case MUSB_EP0_START: | |
1069 | request = (struct usb_ctrlrequest *) urb->setup_packet; | |
1070 | ||
1071 | if (!request->wLength) { | |
b99d3659 | 1072 | musb_dbg(musb, "start no-DATA"); |
550a7375 FB |
1073 | break; |
1074 | } else if (request->bRequestType & USB_DIR_IN) { | |
b99d3659 | 1075 | musb_dbg(musb, "start IN-DATA"); |
550a7375 FB |
1076 | musb->ep0_stage = MUSB_EP0_IN; |
1077 | more = true; | |
1078 | break; | |
1079 | } else { | |
b99d3659 | 1080 | musb_dbg(musb, "start OUT-DATA"); |
550a7375 FB |
1081 | musb->ep0_stage = MUSB_EP0_OUT; |
1082 | more = true; | |
1083 | } | |
1084 | /* FALLTHROUGH */ | |
1085 | case MUSB_EP0_OUT: | |
3ecdb9ac SS |
1086 | fifo_count = min_t(size_t, qh->maxpacket, |
1087 | urb->transfer_buffer_length - | |
1088 | urb->actual_length); | |
550a7375 FB |
1089 | if (fifo_count) { |
1090 | fifo_dest = (u8 *) (urb->transfer_buffer | |
1091 | + urb->actual_length); | |
b99d3659 | 1092 | musb_dbg(musb, "Sending %d byte%s to ep0 fifo %p", |
bb1c9ef1 DB |
1093 | fifo_count, |
1094 | (fifo_count == 1) ? "" : "s", | |
1095 | fifo_dest); | |
550a7375 FB |
1096 | musb_write_fifo(hw_ep, fifo_count, fifo_dest); |
1097 | ||
1098 | urb->actual_length += fifo_count; | |
1099 | more = true; | |
1100 | } | |
1101 | break; | |
1102 | default: | |
1103 | ERR("bogus ep0 stage %d\n", musb->ep0_stage); | |
1104 | break; | |
1105 | } | |
1106 | ||
1107 | return more; | |
1108 | } | |
1109 | ||
1110 | /* | |
1111 | * Handle default endpoint interrupt as host. Only called in IRQ time | |
c767c1c6 | 1112 | * from musb_interrupt(). |
550a7375 FB |
1113 | * |
1114 | * called with controller irqlocked | |
1115 | */ | |
1116 | irqreturn_t musb_h_ep0_irq(struct musb *musb) | |
1117 | { | |
1118 | struct urb *urb; | |
1119 | u16 csr, len; | |
1120 | int status = 0; | |
1121 | void __iomem *mbase = musb->mregs; | |
1122 | struct musb_hw_ep *hw_ep = musb->control_ep; | |
1123 | void __iomem *epio = hw_ep->regs; | |
1124 | struct musb_qh *qh = hw_ep->in_qh; | |
1125 | bool complete = false; | |
1126 | irqreturn_t retval = IRQ_NONE; | |
1127 | ||
1128 | /* ep0 only has one queue, "in" */ | |
1129 | urb = next_urb(qh); | |
1130 | ||
1131 | musb_ep_select(mbase, 0); | |
1132 | csr = musb_readw(epio, MUSB_CSR0); | |
1133 | len = (csr & MUSB_CSR0_RXPKTRDY) | |
1134 | ? musb_readb(epio, MUSB_COUNT0) | |
1135 | : 0; | |
1136 | ||
b99d3659 | 1137 | musb_dbg(musb, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d", |
550a7375 FB |
1138 | csr, qh, len, urb, musb->ep0_stage); |
1139 | ||
1140 | /* if we just did status stage, we are done */ | |
1141 | if (MUSB_EP0_STATUS == musb->ep0_stage) { | |
1142 | retval = IRQ_HANDLED; | |
1143 | complete = true; | |
1144 | } | |
1145 | ||
1146 | /* prepare status */ | |
1147 | if (csr & MUSB_CSR0_H_RXSTALL) { | |
b99d3659 | 1148 | musb_dbg(musb, "STALLING ENDPOINT"); |
550a7375 FB |
1149 | status = -EPIPE; |
1150 | ||
1151 | } else if (csr & MUSB_CSR0_H_ERROR) { | |
b99d3659 | 1152 | musb_dbg(musb, "no response, csr0 %04x", csr); |
550a7375 FB |
1153 | status = -EPROTO; |
1154 | ||
1155 | } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { | |
b99d3659 | 1156 | musb_dbg(musb, "control NAK timeout"); |
550a7375 FB |
1157 | |
1158 | /* NOTE: this code path would be a good place to PAUSE a | |
1159 | * control transfer, if another one is queued, so that | |
1e0320f0 AKG |
1160 | * ep0 is more likely to stay busy. That's already done |
1161 | * for bulk RX transfers. | |
550a7375 FB |
1162 | * |
1163 | * if (qh->ring.next != &musb->control), then | |
1164 | * we have a candidate... NAKing is *NOT* an error | |
1165 | */ | |
1166 | musb_writew(epio, MUSB_CSR0, 0); | |
1167 | retval = IRQ_HANDLED; | |
1168 | } | |
1169 | ||
1170 | if (status) { | |
b99d3659 | 1171 | musb_dbg(musb, "aborting"); |
550a7375 FB |
1172 | retval = IRQ_HANDLED; |
1173 | if (urb) | |
1174 | urb->status = status; | |
1175 | complete = true; | |
1176 | ||
1177 | /* use the proper sequence to abort the transfer */ | |
1178 | if (csr & MUSB_CSR0_H_REQPKT) { | |
1179 | csr &= ~MUSB_CSR0_H_REQPKT; | |
1180 | musb_writew(epio, MUSB_CSR0, csr); | |
1181 | csr &= ~MUSB_CSR0_H_NAKTIMEOUT; | |
1182 | musb_writew(epio, MUSB_CSR0, csr); | |
1183 | } else { | |
78322c1a | 1184 | musb_h_ep0_flush_fifo(hw_ep); |
550a7375 FB |
1185 | } |
1186 | ||
1187 | musb_writeb(epio, MUSB_NAKLIMIT0, 0); | |
1188 | ||
1189 | /* clear it */ | |
1190 | musb_writew(epio, MUSB_CSR0, 0); | |
1191 | } | |
1192 | ||
1193 | if (unlikely(!urb)) { | |
1194 | /* stop endpoint since we have no place for its data, this | |
1195 | * SHOULD NEVER HAPPEN! */ | |
1196 | ERR("no URB for end 0\n"); | |
1197 | ||
78322c1a | 1198 | musb_h_ep0_flush_fifo(hw_ep); |
550a7375 FB |
1199 | goto done; |
1200 | } | |
1201 | ||
1202 | if (!complete) { | |
1203 | /* call common logic and prepare response */ | |
1204 | if (musb_h_ep0_continue(musb, len, urb)) { | |
1205 | /* more packets required */ | |
1206 | csr = (MUSB_EP0_IN == musb->ep0_stage) | |
1207 | ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY; | |
1208 | } else { | |
1209 | /* data transfer complete; perform status phase */ | |
1210 | if (usb_pipeout(urb->pipe) | |
1211 | || !urb->transfer_buffer_length) | |
1212 | csr = MUSB_CSR0_H_STATUSPKT | |
1213 | | MUSB_CSR0_H_REQPKT; | |
1214 | else | |
1215 | csr = MUSB_CSR0_H_STATUSPKT | |
1216 | | MUSB_CSR0_TXPKTRDY; | |
1217 | ||
3c4653c1 AKG |
1218 | /* disable ping token in status phase */ |
1219 | csr |= MUSB_CSR0_H_DIS_PING; | |
1220 | ||
550a7375 FB |
1221 | /* flag status stage */ |
1222 | musb->ep0_stage = MUSB_EP0_STATUS; | |
1223 | ||
b99d3659 | 1224 | musb_dbg(musb, "ep0 STATUS, csr %04x", csr); |
550a7375 FB |
1225 | |
1226 | } | |
1227 | musb_writew(epio, MUSB_CSR0, csr); | |
1228 | retval = IRQ_HANDLED; | |
1229 | } else | |
1230 | musb->ep0_stage = MUSB_EP0_IDLE; | |
1231 | ||
1232 | /* call completion handler if done */ | |
1233 | if (complete) | |
1234 | musb_advance_schedule(musb, urb, hw_ep, 1); | |
1235 | done: | |
1236 | return retval; | |
1237 | } | |
1238 | ||
1239 | ||
1240 | #ifdef CONFIG_USB_INVENTRA_DMA | |
1241 | ||
1242 | /* Host side TX (OUT) using Mentor DMA works as follows: | |
1243 | submit_urb -> | |
1244 | - if queue was empty, Program Endpoint | |
1245 | - ... which starts DMA to fifo in mode 1 or 0 | |
1246 | ||
1247 | DMA Isr (transfer complete) -> TxAvail() | |
1248 | - Stop DMA (~DmaEnab) (<--- Alert ... currently happens | |
1249 | only in musb_cleanup_urb) | |
1250 | - TxPktRdy has to be set in mode 0 or for | |
1251 | short packets in mode 1. | |
1252 | */ | |
1253 | ||
1254 | #endif | |
1255 | ||
1256 | /* Service a Tx-Available or dma completion irq for the endpoint */ | |
1257 | void musb_host_tx(struct musb *musb, u8 epnum) | |
1258 | { | |
1259 | int pipe; | |
1260 | bool done = false; | |
1261 | u16 tx_csr; | |
6b6e9710 SS |
1262 | size_t length = 0; |
1263 | size_t offset = 0; | |
550a7375 FB |
1264 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
1265 | void __iomem *epio = hw_ep->regs; | |
3e5c6dc7 SS |
1266 | struct musb_qh *qh = hw_ep->out_qh; |
1267 | struct urb *urb = next_urb(qh); | |
550a7375 FB |
1268 | u32 status = 0; |
1269 | void __iomem *mbase = musb->mregs; | |
1270 | struct dma_channel *dma; | |
f8afbf7f | 1271 | bool transfer_pending = false; |
550a7375 | 1272 | |
550a7375 FB |
1273 | musb_ep_select(mbase, epnum); |
1274 | tx_csr = musb_readw(epio, MUSB_TXCSR); | |
1275 | ||
1276 | /* with CPPI, DMA sometimes triggers "extra" irqs */ | |
1277 | if (!urb) { | |
b99d3659 | 1278 | musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); |
6b6e9710 | 1279 | return; |
550a7375 FB |
1280 | } |
1281 | ||
1282 | pipe = urb->pipe; | |
1283 | dma = is_dma_capable() ? hw_ep->tx_channel : NULL; | |
19ca682e | 1284 | trace_musb_urb_tx(musb, urb); |
b99d3659 | 1285 | musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr, |
550a7375 FB |
1286 | dma ? ", dma" : ""); |
1287 | ||
1288 | /* check for errors */ | |
1289 | if (tx_csr & MUSB_TXCSR_H_RXSTALL) { | |
1290 | /* dma was disabled, fifo flushed */ | |
b99d3659 | 1291 | musb_dbg(musb, "TX end %d stall", epnum); |
550a7375 FB |
1292 | |
1293 | /* stall; record URB status */ | |
1294 | status = -EPIPE; | |
1295 | ||
1296 | } else if (tx_csr & MUSB_TXCSR_H_ERROR) { | |
1297 | /* (NON-ISO) dma was disabled, fifo flushed */ | |
b99d3659 | 1298 | musb_dbg(musb, "TX 3strikes on ep=%d", epnum); |
550a7375 FB |
1299 | |
1300 | status = -ETIMEDOUT; | |
1301 | ||
1302 | } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) { | |
f283862f AKG |
1303 | if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1 |
1304 | && !list_is_singular(&musb->out_bulk)) { | |
b99d3659 | 1305 | musb_dbg(musb, "NAK timeout on TX%d ep", epnum); |
f283862f AKG |
1306 | musb_bulk_nak_timeout(musb, hw_ep, 0); |
1307 | } else { | |
b99d3659 | 1308 | musb_dbg(musb, "TX ep%d device not responding", epnum); |
f283862f AKG |
1309 | /* NOTE: this code path would be a good place to PAUSE a |
1310 | * transfer, if there's some other (nonperiodic) tx urb | |
1311 | * that could use this fifo. (dma complicates it...) | |
1312 | * That's already done for bulk RX transfers. | |
1313 | * | |
1314 | * if (bulk && qh->ring.next != &musb->out_bulk), then | |
1315 | * we have a candidate... NAKing is *NOT* an error | |
1316 | */ | |
1317 | musb_ep_select(mbase, epnum); | |
1318 | musb_writew(epio, MUSB_TXCSR, | |
1319 | MUSB_TXCSR_H_WZC_BITS | |
1320 | | MUSB_TXCSR_TXPKTRDY); | |
1321 | } | |
1322 | return; | |
550a7375 FB |
1323 | } |
1324 | ||
8e8a5516 | 1325 | done: |
550a7375 FB |
1326 | if (status) { |
1327 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1328 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
9c547699 | 1329 | musb->dma_controller->channel_abort(dma); |
550a7375 FB |
1330 | } |
1331 | ||
1332 | /* do the proper sequence to abort the transfer in the | |
1333 | * usb core; the dma engine should already be stopped. | |
1334 | */ | |
1335 | musb_h_tx_flush_fifo(hw_ep); | |
1336 | tx_csr &= ~(MUSB_TXCSR_AUTOSET | |
1337 | | MUSB_TXCSR_DMAENAB | |
1338 | | MUSB_TXCSR_H_ERROR | |
1339 | | MUSB_TXCSR_H_RXSTALL | |
1340 | | MUSB_TXCSR_H_NAKTIMEOUT | |
1341 | ); | |
1342 | ||
1343 | musb_ep_select(mbase, epnum); | |
1344 | musb_writew(epio, MUSB_TXCSR, tx_csr); | |
1345 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
1346 | musb_writew(epio, MUSB_TXCSR, tx_csr); | |
1347 | musb_writeb(epio, MUSB_TXINTERVAL, 0); | |
1348 | ||
1349 | done = true; | |
1350 | } | |
1351 | ||
1352 | /* second cppi case */ | |
1353 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
b99d3659 | 1354 | musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); |
6b6e9710 | 1355 | return; |
550a7375 FB |
1356 | } |
1357 | ||
c7bbc056 SS |
1358 | if (is_dma_capable() && dma && !status) { |
1359 | /* | |
1360 | * DMA has completed. But if we're using DMA mode 1 (multi | |
1361 | * packet DMA), we need a terminal TXPKTRDY interrupt before | |
1362 | * we can consider this transfer completed, lest we trash | |
1363 | * its last packet when writing the next URB's data. So we | |
1364 | * switch back to mode 0 to get that interrupt; we'll come | |
1365 | * back here once it happens. | |
1366 | */ | |
1367 | if (tx_csr & MUSB_TXCSR_DMAMODE) { | |
1368 | /* | |
1369 | * We shouldn't clear DMAMODE with DMAENAB set; so | |
1370 | * clear them in a safe order. That should be OK | |
1371 | * once TXPKTRDY has been set (and I've never seen | |
1372 | * it being 0 at this moment -- DMA interrupt latency | |
1373 | * is significant) but if it hasn't been then we have | |
1374 | * no choice but to stop being polite and ignore the | |
1375 | * programmer's guide... :-) | |
1376 | * | |
1377 | * Note that we must write TXCSR with TXPKTRDY cleared | |
1378 | * in order not to re-trigger the packet send (this bit | |
1379 | * can't be cleared by CPU), and there's another caveat: | |
1380 | * TXPKTRDY may be set shortly and then cleared in the | |
1381 | * double-buffered FIFO mode, so we do an extra TXCSR | |
1382 | * read for debouncing... | |
1383 | */ | |
1384 | tx_csr &= musb_readw(epio, MUSB_TXCSR); | |
1385 | if (tx_csr & MUSB_TXCSR_TXPKTRDY) { | |
1386 | tx_csr &= ~(MUSB_TXCSR_DMAENAB | | |
1387 | MUSB_TXCSR_TXPKTRDY); | |
1388 | musb_writew(epio, MUSB_TXCSR, | |
1389 | tx_csr | MUSB_TXCSR_H_WZC_BITS); | |
1390 | } | |
1391 | tx_csr &= ~(MUSB_TXCSR_DMAMODE | | |
1392 | MUSB_TXCSR_TXPKTRDY); | |
1393 | musb_writew(epio, MUSB_TXCSR, | |
1394 | tx_csr | MUSB_TXCSR_H_WZC_BITS); | |
1395 | ||
1396 | /* | |
1397 | * There is no guarantee that we'll get an interrupt | |
1398 | * after clearing DMAMODE as we might have done this | |
1399 | * too late (after TXPKTRDY was cleared by controller). | |
1400 | * Re-read TXCSR as we have spoiled its previous value. | |
1401 | */ | |
1402 | tx_csr = musb_readw(epio, MUSB_TXCSR); | |
1403 | } | |
1404 | ||
1405 | /* | |
1406 | * We may get here from a DMA completion or TXPKTRDY interrupt. | |
1407 | * In any case, we must check the FIFO status here and bail out | |
1408 | * only if the FIFO still has data -- that should prevent the | |
1409 | * "missed" TXPKTRDY interrupts and deal with double-buffered | |
1410 | * FIFO mode too... | |
1411 | */ | |
1412 | if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) { | |
b99d3659 BL |
1413 | musb_dbg(musb, |
1414 | "DMA complete but FIFO not empty, CSR %04x", | |
1415 | tx_csr); | |
c7bbc056 SS |
1416 | return; |
1417 | } | |
1418 | } | |
1419 | ||
550a7375 FB |
1420 | if (!status || dma || usb_pipeisoc(pipe)) { |
1421 | if (dma) | |
6b6e9710 | 1422 | length = dma->actual_len; |
550a7375 | 1423 | else |
6b6e9710 SS |
1424 | length = qh->segsize; |
1425 | qh->offset += length; | |
550a7375 FB |
1426 | |
1427 | if (usb_pipeisoc(pipe)) { | |
1428 | struct usb_iso_packet_descriptor *d; | |
1429 | ||
1430 | d = urb->iso_frame_desc + qh->iso_idx; | |
6b6e9710 SS |
1431 | d->actual_length = length; |
1432 | d->status = status; | |
550a7375 FB |
1433 | if (++qh->iso_idx >= urb->number_of_packets) { |
1434 | done = true; | |
1435 | } else { | |
1436 | d++; | |
6b6e9710 SS |
1437 | offset = d->offset; |
1438 | length = d->length; | |
550a7375 | 1439 | } |
f8afbf7f | 1440 | } else if (dma && urb->transfer_buffer_length == qh->offset) { |
550a7375 FB |
1441 | done = true; |
1442 | } else { | |
1443 | /* see if we need to send more data, or ZLP */ | |
1444 | if (qh->segsize < qh->maxpacket) | |
1445 | done = true; | |
1446 | else if (qh->offset == urb->transfer_buffer_length | |
1447 | && !(urb->transfer_flags | |
1448 | & URB_ZERO_PACKET)) | |
1449 | done = true; | |
1450 | if (!done) { | |
6b6e9710 SS |
1451 | offset = qh->offset; |
1452 | length = urb->transfer_buffer_length - offset; | |
f8afbf7f | 1453 | transfer_pending = true; |
550a7375 FB |
1454 | } |
1455 | } | |
1456 | } | |
1457 | ||
1458 | /* urb->status != -EINPROGRESS means request has been faulted, | |
1459 | * so we must abort this transfer after cleanup | |
1460 | */ | |
1461 | if (urb->status != -EINPROGRESS) { | |
1462 | done = true; | |
1463 | if (status == 0) | |
1464 | status = urb->status; | |
1465 | } | |
1466 | ||
1467 | if (done) { | |
1468 | /* set status */ | |
1469 | urb->status = status; | |
1470 | urb->actual_length = qh->offset; | |
1471 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); | |
6b6e9710 | 1472 | return; |
f8afbf7f | 1473 | } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) { |
6b6e9710 | 1474 | if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, |
dfeffa53 | 1475 | offset, length)) { |
f8e9f34f | 1476 | if (is_cppi_enabled(musb) || tusb_dma_omap(musb)) |
dfeffa53 | 1477 | musb_h_tx_dma_start(hw_ep); |
6b6e9710 | 1478 | return; |
dfeffa53 | 1479 | } |
6b6e9710 | 1480 | } else if (tx_csr & MUSB_TXCSR_DMAENAB) { |
b99d3659 | 1481 | musb_dbg(musb, "not complete, but DMA enabled?"); |
6b6e9710 SS |
1482 | return; |
1483 | } | |
550a7375 | 1484 | |
6b6e9710 SS |
1485 | /* |
1486 | * PIO: start next packet in this URB. | |
1487 | * | |
1488 | * REVISIT: some docs say that when hw_ep->tx_double_buffered, | |
1489 | * (and presumably, FIFO is not half-full) we should write *two* | |
1490 | * packets before updating TXCSR; other docs disagree... | |
1491 | */ | |
1492 | if (length > qh->maxpacket) | |
1493 | length = qh->maxpacket; | |
496dda70 | 1494 | /* Unmap the buffer so that CPU can use it */ |
8b125df5 | 1495 | usb_hcd_unmap_urb_for_dma(musb->hcd, urb); |
8e8a5516 VS |
1496 | |
1497 | /* | |
1498 | * We need to map sg if the transfer_buffer is | |
1499 | * NULL. | |
1500 | */ | |
1501 | if (!urb->transfer_buffer) | |
ed74df12 | 1502 | qh->use_sg = true; |
8e8a5516 | 1503 | |
ed74df12 | 1504 | if (qh->use_sg) { |
8e8a5516 VS |
1505 | /* sg_miter_start is already done in musb_ep_program */ |
1506 | if (!sg_miter_next(&qh->sg_miter)) { | |
1507 | dev_err(musb->controller, "error: sg list empty\n"); | |
1508 | sg_miter_stop(&qh->sg_miter); | |
1509 | status = -EINVAL; | |
1510 | goto done; | |
1511 | } | |
1512 | urb->transfer_buffer = qh->sg_miter.addr; | |
1513 | length = min_t(u32, length, qh->sg_miter.length); | |
1514 | musb_write_fifo(hw_ep, length, urb->transfer_buffer); | |
1515 | qh->sg_miter.consumed = length; | |
1516 | sg_miter_stop(&qh->sg_miter); | |
1517 | } else { | |
1518 | musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); | |
1519 | } | |
1520 | ||
6b6e9710 | 1521 | qh->segsize = length; |
550a7375 | 1522 | |
ed74df12 | 1523 | if (qh->use_sg) { |
8e8a5516 | 1524 | if (offset + length >= urb->transfer_buffer_length) |
ed74df12 | 1525 | qh->use_sg = false; |
8e8a5516 VS |
1526 | } |
1527 | ||
6b6e9710 SS |
1528 | musb_ep_select(mbase, epnum); |
1529 | musb_writew(epio, MUSB_TXCSR, | |
1530 | MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY); | |
550a7375 FB |
1531 | } |
1532 | ||
069a3fd1 TL |
1533 | #ifdef CONFIG_USB_TI_CPPI41_DMA |
1534 | /* Seems to set up ISO for cppi41 and not advance len. See commit c57c41d */ | |
1535 | static int musb_rx_dma_iso_cppi41(struct dma_controller *dma, | |
1536 | struct musb_hw_ep *hw_ep, | |
1537 | struct musb_qh *qh, | |
1538 | struct urb *urb, | |
1539 | size_t len) | |
1540 | { | |
04471eb8 | 1541 | struct dma_channel *channel = hw_ep->rx_channel; |
069a3fd1 TL |
1542 | void __iomem *epio = hw_ep->regs; |
1543 | dma_addr_t *buf; | |
c68bb0ef | 1544 | u32 length; |
069a3fd1 TL |
1545 | u16 val; |
1546 | ||
1547 | buf = (void *)urb->iso_frame_desc[qh->iso_idx].offset + | |
1548 | (u32)urb->transfer_dma; | |
1549 | ||
1550 | length = urb->iso_frame_desc[qh->iso_idx].length; | |
1551 | ||
1552 | val = musb_readw(epio, MUSB_RXCSR); | |
1553 | val |= MUSB_RXCSR_DMAENAB; | |
1554 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); | |
1555 | ||
c68bb0ef | 1556 | return dma->channel_program(channel, qh->maxpacket, 0, |
069a3fd1 | 1557 | (u32)buf, length); |
069a3fd1 TL |
1558 | } |
1559 | #else | |
1560 | static inline int musb_rx_dma_iso_cppi41(struct dma_controller *dma, | |
1561 | struct musb_hw_ep *hw_ep, | |
1562 | struct musb_qh *qh, | |
1563 | struct urb *urb, | |
1564 | size_t len) | |
1565 | { | |
1566 | return false; | |
1567 | } | |
1568 | #endif | |
550a7375 | 1569 | |
cff84bdb TL |
1570 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) || \ |
1571 | defined(CONFIG_USB_TI_CPPI41_DMA) | |
550a7375 FB |
1572 | /* Host side RX (IN) using Mentor DMA works as follows: |
1573 | submit_urb -> | |
1574 | - if queue was empty, ProgramEndpoint | |
1575 | - first IN token is sent out (by setting ReqPkt) | |
1576 | LinuxIsr -> RxReady() | |
1577 | /\ => first packet is received | |
1578 | | - Set in mode 0 (DmaEnab, ~ReqPkt) | |
1579 | | -> DMA Isr (transfer complete) -> RxReady() | |
1580 | | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab) | |
1581 | | - if urb not complete, send next IN token (ReqPkt) | |
1582 | | | else complete urb. | |
1583 | | | | |
1584 | --------------------------- | |
1585 | * | |
1586 | * Nuances of mode 1: | |
1587 | * For short packets, no ack (+RxPktRdy) is sent automatically | |
1588 | * (even if AutoClear is ON) | |
1589 | * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent | |
1590 | * automatically => major problem, as collecting the next packet becomes | |
1591 | * difficult. Hence mode 1 is not used. | |
1592 | * | |
1593 | * REVISIT | |
1594 | * All we care about at this driver level is that | |
1595 | * (a) all URBs terminate with REQPKT cleared and fifo(s) empty; | |
1596 | * (b) termination conditions are: short RX, or buffer full; | |
1597 | * (c) fault modes include | |
1598 | * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO. | |
1599 | * (and that endpoint's dma queue stops immediately) | |
1600 | * - overflow (full, PLUS more bytes in the terminal packet) | |
1601 | * | |
1602 | * So for example, usb-storage sets URB_SHORT_NOT_OK, and would | |
1603 | * thus be a great candidate for using mode 1 ... for all but the | |
1604 | * last packet of one URB's transfer. | |
1605 | */ | |
cff84bdb TL |
1606 | static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, |
1607 | struct musb_hw_ep *hw_ep, | |
1608 | struct musb_qh *qh, | |
1609 | struct urb *urb, | |
1610 | size_t len) | |
1611 | { | |
1612 | struct dma_channel *channel = hw_ep->rx_channel; | |
1613 | void __iomem *epio = hw_ep->regs; | |
1614 | u16 val; | |
1615 | int pipe; | |
1616 | bool done; | |
1617 | ||
1618 | pipe = urb->pipe; | |
1619 | ||
1620 | if (usb_pipeisoc(pipe)) { | |
1621 | struct usb_iso_packet_descriptor *d; | |
1622 | ||
1623 | d = urb->iso_frame_desc + qh->iso_idx; | |
1624 | d->actual_length = len; | |
550a7375 | 1625 | |
cff84bdb TL |
1626 | /* even if there was an error, we did the dma |
1627 | * for iso_frame_desc->length | |
1628 | */ | |
1629 | if (d->status != -EILSEQ && d->status != -EOVERFLOW) | |
1630 | d->status = 0; | |
1631 | ||
1632 | if (++qh->iso_idx >= urb->number_of_packets) { | |
1633 | done = true; | |
1634 | } else { | |
1635 | /* REVISIT: Why ignore return value here? */ | |
1636 | if (musb_dma_cppi41(hw_ep->musb)) | |
1637 | done = musb_rx_dma_iso_cppi41(dma, hw_ep, qh, | |
1638 | urb, len); | |
1639 | done = false; | |
1640 | } | |
1641 | ||
1642 | } else { | |
1643 | /* done if urb buffer is full or short packet is recd */ | |
1644 | done = (urb->actual_length + len >= | |
1645 | urb->transfer_buffer_length | |
1646 | || channel->actual_len < qh->maxpacket | |
1647 | || channel->rx_packet_done); | |
1648 | } | |
1649 | ||
1650 | /* send IN token for next packet, without AUTOREQ */ | |
1651 | if (!done) { | |
1652 | val = musb_readw(epio, MUSB_RXCSR); | |
1653 | val |= MUSB_RXCSR_H_REQPKT; | |
1654 | musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); | |
1655 | } | |
1656 | ||
1657 | return done; | |
1658 | } | |
ac33cdb1 TL |
1659 | |
1660 | /* Disadvantage of using mode 1: | |
1661 | * It's basically usable only for mass storage class; essentially all | |
1662 | * other protocols also terminate transfers on short packets. | |
1663 | * | |
1664 | * Details: | |
1665 | * An extra IN token is sent at the end of the transfer (due to AUTOREQ) | |
1666 | * If you try to use mode 1 for (transfer_buffer_length - 512), and try | |
1667 | * to use the extra IN token to grab the last packet using mode 0, then | |
1668 | * the problem is that you cannot be sure when the device will send the | |
1669 | * last packet and RxPktRdy set. Sometimes the packet is recd too soon | |
1670 | * such that it gets lost when RxCSR is re-set at the end of the mode 1 | |
1671 | * transfer, while sometimes it is recd just a little late so that if you | |
1672 | * try to configure for mode 0 soon after the mode 1 transfer is | |
1673 | * completed, you will find rxcount 0. Okay, so you might think why not | |
1674 | * wait for an interrupt when the pkt is recd. Well, you won't get any! | |
1675 | */ | |
1676 | static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, | |
1677 | struct musb_hw_ep *hw_ep, | |
1678 | struct musb_qh *qh, | |
1679 | struct urb *urb, | |
1680 | size_t len, | |
1681 | u8 iso_err) | |
1682 | { | |
1683 | struct musb *musb = hw_ep->musb; | |
1684 | void __iomem *epio = hw_ep->regs; | |
1685 | struct dma_channel *channel = hw_ep->rx_channel; | |
1686 | u16 rx_count, val; | |
1687 | int length, pipe, done; | |
1688 | dma_addr_t buf; | |
1689 | ||
1690 | rx_count = musb_readw(epio, MUSB_RXCOUNT); | |
1691 | pipe = urb->pipe; | |
1692 | ||
1693 | if (usb_pipeisoc(pipe)) { | |
1694 | int d_status = 0; | |
1695 | struct usb_iso_packet_descriptor *d; | |
1696 | ||
1697 | d = urb->iso_frame_desc + qh->iso_idx; | |
1698 | ||
1699 | if (iso_err) { | |
1700 | d_status = -EILSEQ; | |
1701 | urb->error_count++; | |
1702 | } | |
1703 | if (rx_count > d->length) { | |
1704 | if (d_status == 0) { | |
1705 | d_status = -EOVERFLOW; | |
1706 | urb->error_count++; | |
1707 | } | |
b99d3659 | 1708 | musb_dbg(musb, "** OVERFLOW %d into %d", |
ac33cdb1 TL |
1709 | rx_count, d->length); |
1710 | ||
1711 | length = d->length; | |
1712 | } else | |
1713 | length = rx_count; | |
1714 | d->status = d_status; | |
1715 | buf = urb->transfer_dma + d->offset; | |
1716 | } else { | |
1717 | length = rx_count; | |
1718 | buf = urb->transfer_dma + urb->actual_length; | |
1719 | } | |
1720 | ||
1721 | channel->desired_mode = 0; | |
1722 | #ifdef USE_MODE1 | |
1723 | /* because of the issue below, mode 1 will | |
1724 | * only rarely behave with correct semantics. | |
1725 | */ | |
1726 | if ((urb->transfer_flags & URB_SHORT_NOT_OK) | |
1727 | && (urb->transfer_buffer_length - urb->actual_length) | |
1728 | > qh->maxpacket) | |
1729 | channel->desired_mode = 1; | |
1730 | if (rx_count < hw_ep->max_packet_sz_rx) { | |
1731 | length = rx_count; | |
1732 | channel->desired_mode = 0; | |
1733 | } else { | |
1734 | length = urb->transfer_buffer_length; | |
1735 | } | |
1736 | #endif | |
1737 | ||
1738 | /* See comments above on disadvantages of using mode 1 */ | |
1739 | val = musb_readw(epio, MUSB_RXCSR); | |
1740 | val &= ~MUSB_RXCSR_H_REQPKT; | |
1741 | ||
1742 | if (channel->desired_mode == 0) | |
1743 | val &= ~MUSB_RXCSR_H_AUTOREQ; | |
1744 | else | |
1745 | val |= MUSB_RXCSR_H_AUTOREQ; | |
1746 | val |= MUSB_RXCSR_DMAENAB; | |
1747 | ||
1748 | /* autoclear shouldn't be set in high bandwidth */ | |
1749 | if (qh->hb_mult == 1) | |
1750 | val |= MUSB_RXCSR_AUTOCLEAR; | |
1751 | ||
1752 | musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val); | |
1753 | ||
1754 | /* REVISIT if when actual_length != 0, | |
1755 | * transfer_buffer_length needs to be | |
1756 | * adjusted first... | |
1757 | */ | |
1758 | done = dma->channel_program(channel, qh->maxpacket, | |
1759 | channel->desired_mode, | |
1760 | buf, length); | |
1761 | ||
1762 | if (!done) { | |
1763 | dma->channel_release(channel); | |
1764 | hw_ep->rx_channel = NULL; | |
1765 | channel = NULL; | |
1766 | val = musb_readw(epio, MUSB_RXCSR); | |
1767 | val &= ~(MUSB_RXCSR_DMAENAB | |
1768 | | MUSB_RXCSR_H_AUTOREQ | |
1769 | | MUSB_RXCSR_AUTOCLEAR); | |
1770 | musb_writew(epio, MUSB_RXCSR, val); | |
1771 | } | |
1772 | ||
1773 | return done; | |
1774 | } | |
cff84bdb TL |
1775 | #else |
1776 | static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma, | |
1777 | struct musb_hw_ep *hw_ep, | |
1778 | struct musb_qh *qh, | |
1779 | struct urb *urb, | |
1780 | size_t len) | |
1781 | { | |
1782 | return false; | |
1783 | } | |
ac33cdb1 TL |
1784 | |
1785 | static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma, | |
1786 | struct musb_hw_ep *hw_ep, | |
1787 | struct musb_qh *qh, | |
1788 | struct urb *urb, | |
1789 | size_t len, | |
1790 | u8 iso_err) | |
1791 | { | |
1792 | return false; | |
1793 | } | |
550a7375 FB |
1794 | #endif |
1795 | ||
1796 | /* | |
1797 | * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso, | |
1798 | * and high-bandwidth IN transfer cases. | |
1799 | */ | |
1800 | void musb_host_rx(struct musb *musb, u8 epnum) | |
1801 | { | |
1802 | struct urb *urb; | |
1803 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
cff84bdb | 1804 | struct dma_controller *c = musb->dma_controller; |
550a7375 FB |
1805 | void __iomem *epio = hw_ep->regs; |
1806 | struct musb_qh *qh = hw_ep->in_qh; | |
1807 | size_t xfer_len; | |
1808 | void __iomem *mbase = musb->mregs; | |
1809 | int pipe; | |
1810 | u16 rx_csr, val; | |
1811 | bool iso_err = false; | |
1812 | bool done = false; | |
1813 | u32 status; | |
1814 | struct dma_channel *dma; | |
8e8a5516 | 1815 | unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG; |
550a7375 FB |
1816 | |
1817 | musb_ep_select(mbase, epnum); | |
1818 | ||
1819 | urb = next_urb(qh); | |
1820 | dma = is_dma_capable() ? hw_ep->rx_channel : NULL; | |
1821 | status = 0; | |
1822 | xfer_len = 0; | |
1823 | ||
1824 | rx_csr = musb_readw(epio, MUSB_RXCSR); | |
1825 | val = rx_csr; | |
1826 | ||
1827 | if (unlikely(!urb)) { | |
1828 | /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least | |
1829 | * usbtest #11 (unlinks) triggers it regularly, sometimes | |
1830 | * with fifo full. (Only with DMA??) | |
1831 | */ | |
b99d3659 BL |
1832 | musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d", |
1833 | epnum, val, musb_readw(epio, MUSB_RXCOUNT)); | |
550a7375 FB |
1834 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); |
1835 | return; | |
1836 | } | |
1837 | ||
1838 | pipe = urb->pipe; | |
1839 | ||
19ca682e | 1840 | trace_musb_urb_rx(musb, urb); |
550a7375 FB |
1841 | |
1842 | /* check for errors, concurrent stall & unlink is not really | |
1843 | * handled yet! */ | |
1844 | if (rx_csr & MUSB_RXCSR_H_RXSTALL) { | |
b99d3659 | 1845 | musb_dbg(musb, "RX end %d STALL", epnum); |
550a7375 FB |
1846 | |
1847 | /* stall; record URB status */ | |
1848 | status = -EPIPE; | |
1849 | ||
1850 | } else if (rx_csr & MUSB_RXCSR_H_ERROR) { | |
b99d3659 | 1851 | musb_dbg(musb, "end %d RX proto error", epnum); |
550a7375 FB |
1852 | |
1853 | status = -EPROTO; | |
1854 | musb_writeb(epio, MUSB_RXINTERVAL, 0); | |
1855 | ||
b5801212 BL |
1856 | rx_csr &= ~MUSB_RXCSR_H_ERROR; |
1857 | musb_writew(epio, MUSB_RXCSR, rx_csr); | |
1858 | ||
550a7375 FB |
1859 | } else if (rx_csr & MUSB_RXCSR_DATAERROR) { |
1860 | ||
1861 | if (USB_ENDPOINT_XFER_ISOC != qh->type) { | |
b99d3659 | 1862 | musb_dbg(musb, "RX end %d NAK timeout", epnum); |
1e0320f0 AKG |
1863 | |
1864 | /* NOTE: NAKing is *NOT* an error, so we want to | |
1865 | * continue. Except ... if there's a request for | |
1866 | * another QH, use that instead of starving it. | |
550a7375 | 1867 | * |
1e0320f0 AKG |
1868 | * Devices like Ethernet and serial adapters keep |
1869 | * reads posted at all times, which will starve | |
1870 | * other devices without this logic. | |
550a7375 | 1871 | */ |
1e0320f0 AKG |
1872 | if (usb_pipebulk(urb->pipe) |
1873 | && qh->mux == 1 | |
1874 | && !list_is_singular(&musb->in_bulk)) { | |
f283862f | 1875 | musb_bulk_nak_timeout(musb, hw_ep, 1); |
1e0320f0 AKG |
1876 | return; |
1877 | } | |
550a7375 | 1878 | musb_ep_select(mbase, epnum); |
1e0320f0 AKG |
1879 | rx_csr |= MUSB_RXCSR_H_WZC_BITS; |
1880 | rx_csr &= ~MUSB_RXCSR_DATAERROR; | |
1881 | musb_writew(epio, MUSB_RXCSR, rx_csr); | |
550a7375 FB |
1882 | |
1883 | goto finish; | |
1884 | } else { | |
b99d3659 | 1885 | musb_dbg(musb, "RX end %d ISO data error", epnum); |
550a7375 FB |
1886 | /* packet error reported later */ |
1887 | iso_err = true; | |
1888 | } | |
a483d706 | 1889 | } else if (rx_csr & MUSB_RXCSR_INCOMPRX) { |
b99d3659 | 1890 | musb_dbg(musb, "end %d high bandwidth incomplete ISO packet RX", |
a483d706 AKG |
1891 | epnum); |
1892 | status = -EPROTO; | |
550a7375 FB |
1893 | } |
1894 | ||
1895 | /* faults abort the transfer */ | |
1896 | if (status) { | |
1897 | /* clean up dma and collect transfer count */ | |
1898 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1899 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
9c547699 | 1900 | musb->dma_controller->channel_abort(dma); |
550a7375 FB |
1901 | xfer_len = dma->actual_len; |
1902 | } | |
1903 | musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); | |
1904 | musb_writeb(epio, MUSB_RXINTERVAL, 0); | |
1905 | done = true; | |
1906 | goto finish; | |
1907 | } | |
1908 | ||
1909 | if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) { | |
1910 | /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */ | |
1911 | ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); | |
1912 | goto finish; | |
1913 | } | |
1914 | ||
1915 | /* thorough shutdown for now ... given more precise fault handling | |
1916 | * and better queueing support, we might keep a DMA pipeline going | |
1917 | * while processing this irq for earlier completions. | |
1918 | */ | |
1919 | ||
1920 | /* FIXME this is _way_ too much in-line logic for Mentor DMA */ | |
557d543e TL |
1921 | if (!musb_dma_inventra(musb) && !musb_dma_ux500(musb) && |
1922 | (rx_csr & MUSB_RXCSR_H_REQPKT)) { | |
550a7375 FB |
1923 | /* REVISIT this happened for a while on some short reads... |
1924 | * the cleanup still needs investigation... looks bad... | |
1925 | * and also duplicates dma cleanup code above ... plus, | |
1926 | * shouldn't this be the "half full" double buffer case? | |
1927 | */ | |
1928 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
1929 | dma->status = MUSB_DMA_STATUS_CORE_ABORT; | |
9c547699 | 1930 | musb->dma_controller->channel_abort(dma); |
550a7375 FB |
1931 | xfer_len = dma->actual_len; |
1932 | done = true; | |
1933 | } | |
1934 | ||
b99d3659 | 1935 | musb_dbg(musb, "RXCSR%d %04x, reqpkt, len %zu%s", epnum, rx_csr, |
550a7375 FB |
1936 | xfer_len, dma ? ", dma" : ""); |
1937 | rx_csr &= ~MUSB_RXCSR_H_REQPKT; | |
1938 | ||
1939 | musb_ep_select(mbase, epnum); | |
1940 | musb_writew(epio, MUSB_RXCSR, | |
1941 | MUSB_RXCSR_H_WZC_BITS | rx_csr); | |
1942 | } | |
557d543e | 1943 | |
550a7375 FB |
1944 | if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) { |
1945 | xfer_len = dma->actual_len; | |
1946 | ||
1947 | val &= ~(MUSB_RXCSR_DMAENAB | |
1948 | | MUSB_RXCSR_H_AUTOREQ | |
1949 | | MUSB_RXCSR_AUTOCLEAR | |
1950 | | MUSB_RXCSR_RXPKTRDY); | |
1951 | musb_writew(hw_ep->regs, MUSB_RXCSR, val); | |
1952 | ||
cff84bdb TL |
1953 | if (musb_dma_inventra(musb) || musb_dma_ux500(musb) || |
1954 | musb_dma_cppi41(musb)) { | |
1955 | done = musb_rx_dma_inventra_cppi41(c, hw_ep, qh, urb, xfer_len); | |
b99d3659 BL |
1956 | musb_dbg(hw_ep->musb, |
1957 | "ep %d dma %s, rxcsr %04x, rxcount %d", | |
cff84bdb TL |
1958 | epnum, done ? "off" : "reset", |
1959 | musb_readw(epio, MUSB_RXCSR), | |
1960 | musb_readw(epio, MUSB_RXCOUNT)); | |
1961 | } else { | |
1962 | done = true; | |
550a7375 FB |
1963 | } |
1964 | ||
550a7375 FB |
1965 | } else if (urb->status == -EINPROGRESS) { |
1966 | /* if no errors, be sure a packet is ready for unloading */ | |
1967 | if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) { | |
1968 | status = -EPROTO; | |
1969 | ERR("Rx interrupt with no errors or packet!\n"); | |
1970 | ||
1971 | /* FIXME this is another "SHOULD NEVER HAPPEN" */ | |
1972 | ||
1973 | /* SCRUB (RX) */ | |
1974 | /* do the proper sequence to abort the transfer */ | |
1975 | musb_ep_select(mbase, epnum); | |
1976 | val &= ~MUSB_RXCSR_H_REQPKT; | |
1977 | musb_writew(epio, MUSB_RXCSR, val); | |
1978 | goto finish; | |
1979 | } | |
1980 | ||
1981 | /* we are expecting IN packets */ | |
e530bb8f TL |
1982 | if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) || |
1983 | musb_dma_cppi41(musb)) && dma) { | |
b99d3659 BL |
1984 | musb_dbg(hw_ep->musb, |
1985 | "RX%d count %d, buffer 0x%llx len %d/%d", | |
ac33cdb1 TL |
1986 | epnum, musb_readw(epio, MUSB_RXCOUNT), |
1987 | (unsigned long long) urb->transfer_dma | |
1988 | + urb->actual_length, | |
1989 | qh->offset, | |
1990 | urb->transfer_buffer_length); | |
1991 | ||
4c2ba0c6 CB |
1992 | if (musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh, urb, |
1993 | xfer_len, iso_err)) | |
ac33cdb1 | 1994 | goto finish; |
550a7375 | 1995 | else |
ac33cdb1 | 1996 | dev_err(musb->controller, "error: rx_dma failed\n"); |
550a7375 | 1997 | } |
550a7375 FB |
1998 | |
1999 | if (!dma) { | |
8e8a5516 VS |
2000 | unsigned int received_len; |
2001 | ||
496dda70 | 2002 | /* Unmap the buffer so that CPU can use it */ |
8b125df5 | 2003 | usb_hcd_unmap_urb_for_dma(musb->hcd, urb); |
8e8a5516 VS |
2004 | |
2005 | /* | |
2006 | * We need to map sg if the transfer_buffer is | |
2007 | * NULL. | |
2008 | */ | |
2009 | if (!urb->transfer_buffer) { | |
ed74df12 | 2010 | qh->use_sg = true; |
8e8a5516 VS |
2011 | sg_miter_start(&qh->sg_miter, urb->sg, 1, |
2012 | sg_flags); | |
2013 | } | |
2014 | ||
ed74df12 | 2015 | if (qh->use_sg) { |
8e8a5516 VS |
2016 | if (!sg_miter_next(&qh->sg_miter)) { |
2017 | dev_err(musb->controller, "error: sg list empty\n"); | |
2018 | sg_miter_stop(&qh->sg_miter); | |
2019 | status = -EINVAL; | |
2020 | done = true; | |
2021 | goto finish; | |
2022 | } | |
2023 | urb->transfer_buffer = qh->sg_miter.addr; | |
2024 | received_len = urb->actual_length; | |
2025 | qh->offset = 0x0; | |
2026 | done = musb_host_packet_rx(musb, urb, epnum, | |
2027 | iso_err); | |
2028 | /* Calculate the number of bytes received */ | |
2029 | received_len = urb->actual_length - | |
2030 | received_len; | |
2031 | qh->sg_miter.consumed = received_len; | |
2032 | sg_miter_stop(&qh->sg_miter); | |
2033 | } else { | |
2034 | done = musb_host_packet_rx(musb, urb, | |
2035 | epnum, iso_err); | |
2036 | } | |
b99d3659 | 2037 | musb_dbg(musb, "read %spacket", done ? "last " : ""); |
550a7375 FB |
2038 | } |
2039 | } | |
2040 | ||
550a7375 FB |
2041 | finish: |
2042 | urb->actual_length += xfer_len; | |
2043 | qh->offset += xfer_len; | |
2044 | if (done) { | |
ed74df12 VS |
2045 | if (qh->use_sg) |
2046 | qh->use_sg = false; | |
8e8a5516 | 2047 | |
550a7375 FB |
2048 | if (urb->status == -EINPROGRESS) |
2049 | urb->status = status; | |
2050 | musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | /* schedule nodes correspond to peripheral endpoints, like an OHCI QH. | |
2055 | * the software schedule associates multiple such nodes with a given | |
2056 | * host side hardware endpoint + direction; scheduling may activate | |
2057 | * that hardware endpoint. | |
2058 | */ | |
2059 | static int musb_schedule( | |
2060 | struct musb *musb, | |
2061 | struct musb_qh *qh, | |
2062 | int is_in) | |
2063 | { | |
eac44dc4 | 2064 | int idle = 0; |
550a7375 FB |
2065 | int best_diff; |
2066 | int best_end, epnum; | |
2067 | struct musb_hw_ep *hw_ep = NULL; | |
2068 | struct list_head *head = NULL; | |
5274dab6 S |
2069 | u8 toggle; |
2070 | u8 txtype; | |
2071 | struct urb *urb = next_urb(qh); | |
550a7375 FB |
2072 | |
2073 | /* use fixed hardware for control and bulk */ | |
23d15e07 | 2074 | if (qh->type == USB_ENDPOINT_XFER_CONTROL) { |
550a7375 FB |
2075 | head = &musb->control; |
2076 | hw_ep = musb->control_ep; | |
550a7375 FB |
2077 | goto success; |
2078 | } | |
2079 | ||
2080 | /* else, periodic transfers get muxed to other endpoints */ | |
2081 | ||
5d67a851 SS |
2082 | /* |
2083 | * We know this qh hasn't been scheduled, so all we need to do | |
550a7375 FB |
2084 | * is choose which hardware endpoint to put it on ... |
2085 | * | |
2086 | * REVISIT what we really want here is a regular schedule tree | |
5d67a851 | 2087 | * like e.g. OHCI uses. |
550a7375 FB |
2088 | */ |
2089 | best_diff = 4096; | |
2090 | best_end = -1; | |
2091 | ||
5d67a851 SS |
2092 | for (epnum = 1, hw_ep = musb->endpoints + 1; |
2093 | epnum < musb->nr_endpoints; | |
2094 | epnum++, hw_ep++) { | |
550a7375 FB |
2095 | int diff; |
2096 | ||
3e5c6dc7 | 2097 | if (musb_ep_get_qh(hw_ep, is_in) != NULL) |
550a7375 | 2098 | continue; |
5d67a851 | 2099 | |
550a7375 FB |
2100 | if (hw_ep == musb->bulk_ep) |
2101 | continue; | |
2102 | ||
2103 | if (is_in) | |
a483d706 | 2104 | diff = hw_ep->max_packet_sz_rx; |
550a7375 | 2105 | else |
a483d706 AKG |
2106 | diff = hw_ep->max_packet_sz_tx; |
2107 | diff -= (qh->maxpacket * qh->hb_mult); | |
550a7375 | 2108 | |
23d15e07 | 2109 | if (diff >= 0 && best_diff > diff) { |
5274dab6 S |
2110 | |
2111 | /* | |
2112 | * Mentor controller has a bug in that if we schedule | |
2113 | * a BULK Tx transfer on an endpoint that had earlier | |
2114 | * handled ISOC then the BULK transfer has to start on | |
2115 | * a zero toggle. If the BULK transfer starts on a 1 | |
2116 | * toggle then this transfer will fail as the mentor | |
2117 | * controller starts the Bulk transfer on a 0 toggle | |
2118 | * irrespective of the programming of the toggle bits | |
2119 | * in the TXCSR register. Check for this condition | |
2120 | * while allocating the EP for a Tx Bulk transfer. If | |
2121 | * so skip this EP. | |
2122 | */ | |
2123 | hw_ep = musb->endpoints + epnum; | |
2124 | toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); | |
2125 | txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) | |
2126 | >> 4) & 0x3; | |
2127 | if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && | |
2128 | toggle && (txtype == USB_ENDPOINT_XFER_ISOC)) | |
2129 | continue; | |
2130 | ||
550a7375 FB |
2131 | best_diff = diff; |
2132 | best_end = epnum; | |
2133 | } | |
2134 | } | |
23d15e07 | 2135 | /* use bulk reserved ep1 if no other ep is free */ |
aa5cbbec | 2136 | if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { |
23d15e07 AKG |
2137 | hw_ep = musb->bulk_ep; |
2138 | if (is_in) | |
2139 | head = &musb->in_bulk; | |
2140 | else | |
2141 | head = &musb->out_bulk; | |
1e0320f0 | 2142 | |
f283862f | 2143 | /* Enable bulk RX/TX NAK timeout scheme when bulk requests are |
5ae477b0 | 2144 | * multiplexed. This scheme does not work in high speed to full |
1e0320f0 AKG |
2145 | * speed scenario as NAK interrupts are not coming from a |
2146 | * full speed device connected to a high speed device. | |
2147 | * NAK timeout interval is 8 (128 uframe or 16ms) for HS and | |
2148 | * 4 (8 frame or 8ms) for FS device. | |
2149 | */ | |
f283862f | 2150 | if (qh->dev) |
1e0320f0 AKG |
2151 | qh->intv_reg = |
2152 | (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; | |
23d15e07 AKG |
2153 | goto success; |
2154 | } else if (best_end < 0) { | |
a2f65606 BL |
2155 | dev_err(musb->controller, |
2156 | "%s hwep alloc failed for %dx%d\n", | |
2157 | musb_ep_xfertype_string(qh->type), | |
2158 | qh->hb_mult, qh->maxpacket); | |
550a7375 | 2159 | return -ENOSPC; |
23d15e07 | 2160 | } |
550a7375 FB |
2161 | |
2162 | idle = 1; | |
23d15e07 | 2163 | qh->mux = 0; |
550a7375 | 2164 | hw_ep = musb->endpoints + best_end; |
b99d3659 | 2165 | musb_dbg(musb, "qh %p periodic slot %d", qh, best_end); |
550a7375 | 2166 | success: |
23d15e07 AKG |
2167 | if (head) { |
2168 | idle = list_empty(head); | |
2169 | list_add_tail(&qh->ring, head); | |
2170 | qh->mux = 1; | |
2171 | } | |
550a7375 FB |
2172 | qh->hw_ep = hw_ep; |
2173 | qh->hep->hcpriv = qh; | |
2174 | if (idle) | |
2175 | musb_start_urb(musb, is_in, qh); | |
2176 | return 0; | |
2177 | } | |
2178 | ||
2179 | static int musb_urb_enqueue( | |
2180 | struct usb_hcd *hcd, | |
2181 | struct urb *urb, | |
2182 | gfp_t mem_flags) | |
2183 | { | |
2184 | unsigned long flags; | |
2185 | struct musb *musb = hcd_to_musb(hcd); | |
2186 | struct usb_host_endpoint *hep = urb->ep; | |
74bb3508 | 2187 | struct musb_qh *qh; |
550a7375 FB |
2188 | struct usb_endpoint_descriptor *epd = &hep->desc; |
2189 | int ret; | |
2190 | unsigned type_reg; | |
2191 | unsigned interval; | |
2192 | ||
2193 | /* host role must be active */ | |
2194 | if (!is_host_active(musb) || !musb->is_active) | |
2195 | return -ENODEV; | |
2196 | ||
19ca682e BL |
2197 | trace_musb_urb_enq(musb, urb); |
2198 | ||
550a7375 FB |
2199 | spin_lock_irqsave(&musb->lock, flags); |
2200 | ret = usb_hcd_link_urb_to_ep(hcd, urb); | |
74bb3508 DB |
2201 | qh = ret ? NULL : hep->hcpriv; |
2202 | if (qh) | |
2203 | urb->hcpriv = qh; | |
550a7375 | 2204 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 FB |
2205 | |
2206 | /* DMA mapping was already done, if needed, and this urb is on | |
74bb3508 DB |
2207 | * hep->urb_list now ... so we're done, unless hep wasn't yet |
2208 | * scheduled onto a live qh. | |
550a7375 FB |
2209 | * |
2210 | * REVISIT best to keep hep->hcpriv valid until the endpoint gets | |
2211 | * disabled, testing for empty qh->ring and avoiding qh setup costs | |
2212 | * except for the first urb queued after a config change. | |
2213 | */ | |
74bb3508 DB |
2214 | if (qh || ret) |
2215 | return ret; | |
550a7375 FB |
2216 | |
2217 | /* Allocate and initialize qh, minimizing the work done each time | |
2218 | * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it. | |
2219 | * | |
2220 | * REVISIT consider a dedicated qh kmem_cache, so it's harder | |
2221 | * for bugs in other kernel code to break this driver... | |
2222 | */ | |
2223 | qh = kzalloc(sizeof *qh, mem_flags); | |
2224 | if (!qh) { | |
2492e674 | 2225 | spin_lock_irqsave(&musb->lock, flags); |
550a7375 | 2226 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
2492e674 | 2227 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 FB |
2228 | return -ENOMEM; |
2229 | } | |
2230 | ||
2231 | qh->hep = hep; | |
2232 | qh->dev = urb->dev; | |
2233 | INIT_LIST_HEAD(&qh->ring); | |
2234 | qh->is_ready = 1; | |
2235 | ||
29cc8897 | 2236 | qh->maxpacket = usb_endpoint_maxp(epd); |
a483d706 | 2237 | qh->type = usb_endpoint_type(epd); |
550a7375 | 2238 | |
a483d706 AKG |
2239 | /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier. |
2240 | * Some musb cores don't support high bandwidth ISO transfers; and | |
2241 | * we don't (yet!) support high bandwidth interrupt transfers. | |
2242 | */ | |
6ddcabc2 | 2243 | qh->hb_mult = usb_endpoint_maxp_mult(epd); |
a483d706 AKG |
2244 | if (qh->hb_mult > 1) { |
2245 | int ok = (qh->type == USB_ENDPOINT_XFER_ISOC); | |
2246 | ||
2247 | if (ok) | |
2248 | ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx) | |
2249 | || (usb_pipeout(urb->pipe) && musb->hb_iso_tx); | |
2250 | if (!ok) { | |
2251 | ret = -EMSGSIZE; | |
2252 | goto done; | |
2253 | } | |
2254 | qh->maxpacket &= 0x7ff; | |
550a7375 FB |
2255 | } |
2256 | ||
96bcd090 | 2257 | qh->epnum = usb_endpoint_num(epd); |
550a7375 FB |
2258 | |
2259 | /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */ | |
2260 | qh->addr_reg = (u8) usb_pipedevice(urb->pipe); | |
2261 | ||
2262 | /* precompute rxtype/txtype/type0 register */ | |
2263 | type_reg = (qh->type << 4) | qh->epnum; | |
2264 | switch (urb->dev->speed) { | |
2265 | case USB_SPEED_LOW: | |
2266 | type_reg |= 0xc0; | |
2267 | break; | |
2268 | case USB_SPEED_FULL: | |
2269 | type_reg |= 0x80; | |
2270 | break; | |
2271 | default: | |
2272 | type_reg |= 0x40; | |
2273 | } | |
2274 | qh->type_reg = type_reg; | |
2275 | ||
136733d6 | 2276 | /* Precompute RXINTERVAL/TXINTERVAL register */ |
550a7375 FB |
2277 | switch (qh->type) { |
2278 | case USB_ENDPOINT_XFER_INT: | |
136733d6 SS |
2279 | /* |
2280 | * Full/low speeds use the linear encoding, | |
2281 | * high speed uses the logarithmic encoding. | |
2282 | */ | |
2283 | if (urb->dev->speed <= USB_SPEED_FULL) { | |
2284 | interval = max_t(u8, epd->bInterval, 1); | |
2285 | break; | |
550a7375 FB |
2286 | } |
2287 | /* FALLTHROUGH */ | |
2288 | case USB_ENDPOINT_XFER_ISOC: | |
136733d6 SS |
2289 | /* ISO always uses logarithmic encoding */ |
2290 | interval = min_t(u8, epd->bInterval, 16); | |
550a7375 FB |
2291 | break; |
2292 | default: | |
2293 | /* REVISIT we actually want to use NAK limits, hinting to the | |
2294 | * transfer scheduling logic to try some other qh, e.g. try | |
2295 | * for 2 msec first: | |
2296 | * | |
2297 | * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2; | |
2298 | * | |
2299 | * The downside of disabling this is that transfer scheduling | |
2300 | * gets VERY unfair for nonperiodic transfers; a misbehaving | |
1e0320f0 AKG |
2301 | * peripheral could make that hurt. That's perfectly normal |
2302 | * for reads from network or serial adapters ... so we have | |
2303 | * partial NAKlimit support for bulk RX. | |
550a7375 | 2304 | * |
1e0320f0 | 2305 | * The upside of disabling it is simpler transfer scheduling. |
550a7375 FB |
2306 | */ |
2307 | interval = 0; | |
2308 | } | |
2309 | qh->intv_reg = interval; | |
2310 | ||
2311 | /* precompute addressing for external hub/tt ports */ | |
2312 | if (musb->is_multipoint) { | |
2313 | struct usb_device *parent = urb->dev->parent; | |
2314 | ||
2315 | if (parent != hcd->self.root_hub) { | |
2316 | qh->h_addr_reg = (u8) parent->devnum; | |
2317 | ||
2318 | /* set up tt info if needed */ | |
2319 | if (urb->dev->tt) { | |
2320 | qh->h_port_reg = (u8) urb->dev->ttport; | |
ae5ad296 AKG |
2321 | if (urb->dev->tt->hub) |
2322 | qh->h_addr_reg = | |
2323 | (u8) urb->dev->tt->hub->devnum; | |
2324 | if (urb->dev->tt->multi) | |
2325 | qh->h_addr_reg |= 0x80; | |
550a7375 FB |
2326 | } |
2327 | } | |
2328 | } | |
2329 | ||
2330 | /* invariant: hep->hcpriv is null OR the qh that's already scheduled. | |
2331 | * until we get real dma queues (with an entry for each urb/buffer), | |
2332 | * we only have work to do in the former case. | |
2333 | */ | |
2334 | spin_lock_irqsave(&musb->lock, flags); | |
3067779b | 2335 | if (hep->hcpriv || !next_urb(qh)) { |
550a7375 FB |
2336 | /* some concurrent activity submitted another urb to hep... |
2337 | * odd, rare, error prone, but legal. | |
2338 | */ | |
2339 | kfree(qh); | |
714bc5ef | 2340 | qh = NULL; |
550a7375 FB |
2341 | ret = 0; |
2342 | } else | |
2343 | ret = musb_schedule(musb, qh, | |
2344 | epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK); | |
2345 | ||
2346 | if (ret == 0) { | |
2347 | urb->hcpriv = qh; | |
2348 | /* FIXME set urb->start_frame for iso/intr, it's tested in | |
2349 | * musb_start_urb(), but otherwise only konicawc cares ... | |
2350 | */ | |
2351 | } | |
2352 | spin_unlock_irqrestore(&musb->lock, flags); | |
2353 | ||
2354 | done: | |
2355 | if (ret != 0) { | |
2492e674 | 2356 | spin_lock_irqsave(&musb->lock, flags); |
550a7375 | 2357 | usb_hcd_unlink_urb_from_ep(hcd, urb); |
2492e674 | 2358 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 FB |
2359 | kfree(qh); |
2360 | } | |
2361 | return ret; | |
2362 | } | |
2363 | ||
2364 | ||
2365 | /* | |
2366 | * abort a transfer that's at the head of a hardware queue. | |
2367 | * called with controller locked, irqs blocked | |
2368 | * that hardware queue advances to the next transfer, unless prevented | |
2369 | */ | |
81ec4e4a | 2370 | static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh) |
550a7375 FB |
2371 | { |
2372 | struct musb_hw_ep *ep = qh->hw_ep; | |
5c8a86e1 | 2373 | struct musb *musb = ep->musb; |
550a7375 FB |
2374 | void __iomem *epio = ep->regs; |
2375 | unsigned hw_end = ep->epnum; | |
2376 | void __iomem *regs = ep->musb->mregs; | |
81ec4e4a | 2377 | int is_in = usb_pipein(urb->pipe); |
550a7375 | 2378 | int status = 0; |
81ec4e4a | 2379 | u16 csr; |
6def85a3 | 2380 | struct dma_channel *dma = NULL; |
550a7375 FB |
2381 | |
2382 | musb_ep_select(regs, hw_end); | |
2383 | ||
2384 | if (is_dma_capable()) { | |
550a7375 FB |
2385 | dma = is_in ? ep->rx_channel : ep->tx_channel; |
2386 | if (dma) { | |
2387 | status = ep->musb->dma_controller->channel_abort(dma); | |
b99d3659 | 2388 | musb_dbg(musb, "abort %cX%d DMA for urb %p --> %d", |
550a7375 FB |
2389 | is_in ? 'R' : 'T', ep->epnum, |
2390 | urb, status); | |
2391 | urb->actual_length += dma->actual_len; | |
2392 | } | |
2393 | } | |
2394 | ||
2395 | /* turn off DMA requests, discard state, stop polling ... */ | |
692933b2 | 2396 | if (ep->epnum && is_in) { |
550a7375 FB |
2397 | /* giveback saves bulk toggle */ |
2398 | csr = musb_h_flush_rxfifo(ep, 0); | |
2399 | ||
6def85a3 BL |
2400 | /* clear the endpoint's irq status here to avoid bogus irqs */ |
2401 | if (is_dma_capable() && dma) | |
2402 | musb_platform_clear_ep_rxintr(musb, ep->epnum); | |
78322c1a | 2403 | } else if (ep->epnum) { |
550a7375 FB |
2404 | musb_h_tx_flush_fifo(ep); |
2405 | csr = musb_readw(epio, MUSB_TXCSR); | |
2406 | csr &= ~(MUSB_TXCSR_AUTOSET | |
2407 | | MUSB_TXCSR_DMAENAB | |
2408 | | MUSB_TXCSR_H_RXSTALL | |
2409 | | MUSB_TXCSR_H_NAKTIMEOUT | |
2410 | | MUSB_TXCSR_H_ERROR | |
2411 | | MUSB_TXCSR_TXPKTRDY); | |
2412 | musb_writew(epio, MUSB_TXCSR, csr); | |
2413 | /* REVISIT may need to clear FLUSHFIFO ... */ | |
2414 | musb_writew(epio, MUSB_TXCSR, csr); | |
2415 | /* flush cpu writebuffer */ | |
2416 | csr = musb_readw(epio, MUSB_TXCSR); | |
78322c1a DB |
2417 | } else { |
2418 | musb_h_ep0_flush_fifo(ep); | |
550a7375 FB |
2419 | } |
2420 | if (status == 0) | |
2421 | musb_advance_schedule(ep->musb, urb, ep, is_in); | |
2422 | return status; | |
2423 | } | |
2424 | ||
2425 | static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) | |
2426 | { | |
2427 | struct musb *musb = hcd_to_musb(hcd); | |
2428 | struct musb_qh *qh; | |
550a7375 | 2429 | unsigned long flags; |
22a0d6f1 | 2430 | int is_in = usb_pipein(urb->pipe); |
550a7375 FB |
2431 | int ret; |
2432 | ||
19ca682e | 2433 | trace_musb_urb_deq(musb, urb); |
550a7375 FB |
2434 | |
2435 | spin_lock_irqsave(&musb->lock, flags); | |
2436 | ret = usb_hcd_check_unlink_urb(hcd, urb, status); | |
2437 | if (ret) | |
2438 | goto done; | |
2439 | ||
2440 | qh = urb->hcpriv; | |
2441 | if (!qh) | |
2442 | goto done; | |
2443 | ||
22a0d6f1 SS |
2444 | /* |
2445 | * Any URB not actively programmed into endpoint hardware can be | |
a2fd814e | 2446 | * immediately given back; that's any URB not at the head of an |
550a7375 | 2447 | * endpoint queue, unless someday we get real DMA queues. And even |
a2fd814e | 2448 | * if it's at the head, it might not be known to the hardware... |
550a7375 | 2449 | * |
22a0d6f1 | 2450 | * Otherwise abort current transfer, pending DMA, etc.; urb->status |
550a7375 FB |
2451 | * has already been updated. This is a synchronous abort; it'd be |
2452 | * OK to hold off until after some IRQ, though. | |
22a0d6f1 SS |
2453 | * |
2454 | * NOTE: qh is invalid unless !list_empty(&hep->urb_list) | |
550a7375 | 2455 | */ |
22a0d6f1 SS |
2456 | if (!qh->is_ready |
2457 | || urb->urb_list.prev != &qh->hep->urb_list | |
2458 | || musb_ep_get_qh(qh->hw_ep, is_in) != qh) { | |
550a7375 FB |
2459 | int ready = qh->is_ready; |
2460 | ||
550a7375 | 2461 | qh->is_ready = 0; |
c9cd06b3 | 2462 | musb_giveback(musb, urb, 0); |
550a7375 | 2463 | qh->is_ready = ready; |
a2fd814e SS |
2464 | |
2465 | /* If nothing else (usually musb_giveback) is using it | |
2466 | * and its URB list has emptied, recycle this qh. | |
2467 | */ | |
2468 | if (ready && list_empty(&qh->hep->urb_list)) { | |
2469 | qh->hep->hcpriv = NULL; | |
2470 | list_del(&qh->ring); | |
2471 | kfree(qh); | |
2472 | } | |
550a7375 | 2473 | } else |
81ec4e4a | 2474 | ret = musb_cleanup_urb(urb, qh); |
550a7375 FB |
2475 | done: |
2476 | spin_unlock_irqrestore(&musb->lock, flags); | |
2477 | return ret; | |
2478 | } | |
2479 | ||
2480 | /* disable an endpoint */ | |
2481 | static void | |
2482 | musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep) | |
2483 | { | |
22a0d6f1 | 2484 | u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN; |
550a7375 FB |
2485 | unsigned long flags; |
2486 | struct musb *musb = hcd_to_musb(hcd); | |
dc61d238 SS |
2487 | struct musb_qh *qh; |
2488 | struct urb *urb; | |
550a7375 | 2489 | |
550a7375 FB |
2490 | spin_lock_irqsave(&musb->lock, flags); |
2491 | ||
dc61d238 SS |
2492 | qh = hep->hcpriv; |
2493 | if (qh == NULL) | |
2494 | goto exit; | |
2495 | ||
22a0d6f1 | 2496 | /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */ |
550a7375 | 2497 | |
22a0d6f1 | 2498 | /* Kick the first URB off the hardware, if needed */ |
550a7375 | 2499 | qh->is_ready = 0; |
22a0d6f1 | 2500 | if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) { |
550a7375 FB |
2501 | urb = next_urb(qh); |
2502 | ||
2503 | /* make software (then hardware) stop ASAP */ | |
2504 | if (!urb->unlinked) | |
2505 | urb->status = -ESHUTDOWN; | |
2506 | ||
2507 | /* cleanup */ | |
81ec4e4a | 2508 | musb_cleanup_urb(urb, qh); |
550a7375 | 2509 | |
dc61d238 SS |
2510 | /* Then nuke all the others ... and advance the |
2511 | * queue on hw_ep (e.g. bulk ring) when we're done. | |
2512 | */ | |
2513 | while (!list_empty(&hep->urb_list)) { | |
2514 | urb = next_urb(qh); | |
2515 | urb->status = -ESHUTDOWN; | |
2516 | musb_advance_schedule(musb, urb, qh->hw_ep, is_in); | |
2517 | } | |
2518 | } else { | |
2519 | /* Just empty the queue; the hardware is busy with | |
2520 | * other transfers, and since !qh->is_ready nothing | |
2521 | * will activate any of these as it advances. | |
2522 | */ | |
2523 | while (!list_empty(&hep->urb_list)) | |
c9cd06b3 | 2524 | musb_giveback(musb, next_urb(qh), -ESHUTDOWN); |
550a7375 | 2525 | |
dc61d238 SS |
2526 | hep->hcpriv = NULL; |
2527 | list_del(&qh->ring); | |
2528 | kfree(qh); | |
2529 | } | |
2530 | exit: | |
550a7375 FB |
2531 | spin_unlock_irqrestore(&musb->lock, flags); |
2532 | } | |
2533 | ||
2534 | static int musb_h_get_frame_number(struct usb_hcd *hcd) | |
2535 | { | |
2536 | struct musb *musb = hcd_to_musb(hcd); | |
2537 | ||
2538 | return musb_readw(musb->mregs, MUSB_FRAME); | |
2539 | } | |
2540 | ||
2541 | static int musb_h_start(struct usb_hcd *hcd) | |
2542 | { | |
2543 | struct musb *musb = hcd_to_musb(hcd); | |
2544 | ||
2545 | /* NOTE: musb_start() is called when the hub driver turns | |
2546 | * on port power, or when (OTG) peripheral starts. | |
2547 | */ | |
2548 | hcd->state = HC_STATE_RUNNING; | |
2549 | musb->port1_status = 0; | |
2550 | return 0; | |
2551 | } | |
2552 | ||
2553 | static void musb_h_stop(struct usb_hcd *hcd) | |
2554 | { | |
2555 | musb_stop(hcd_to_musb(hcd)); | |
2556 | hcd->state = HC_STATE_HALT; | |
2557 | } | |
2558 | ||
2559 | static int musb_bus_suspend(struct usb_hcd *hcd) | |
2560 | { | |
2561 | struct musb *musb = hcd_to_musb(hcd); | |
89368d3d | 2562 | u8 devctl; |
550a7375 | 2563 | |
94f72136 DM |
2564 | musb_port_suspend(musb, true); |
2565 | ||
89368d3d | 2566 | if (!is_host_active(musb)) |
550a7375 FB |
2567 | return 0; |
2568 | ||
e47d9254 | 2569 | switch (musb->xceiv->otg->state) { |
89368d3d DB |
2570 | case OTG_STATE_A_SUSPEND: |
2571 | return 0; | |
2572 | case OTG_STATE_A_WAIT_VRISE: | |
2573 | /* ID could be grounded even if there's no device | |
2574 | * on the other end of the cable. NOTE that the | |
2575 | * A_WAIT_VRISE timers are messy with MUSB... | |
2576 | */ | |
2577 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
2578 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
e47d9254 | 2579 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON; |
89368d3d DB |
2580 | break; |
2581 | default: | |
2582 | break; | |
2583 | } | |
2584 | ||
2585 | if (musb->is_active) { | |
2586 | WARNING("trying to suspend as %s while active\n", | |
e47d9254 | 2587 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
2588 | return -EBUSY; |
2589 | } else | |
2590 | return 0; | |
2591 | } | |
2592 | ||
2593 | static int musb_bus_resume(struct usb_hcd *hcd) | |
2594 | { | |
869c5978 DM |
2595 | struct musb *musb = hcd_to_musb(hcd); |
2596 | ||
2597 | if (musb->config && | |
2598 | musb->config->host_port_deassert_reset_at_resume) | |
2599 | musb_port_reset(musb, false); | |
2600 | ||
550a7375 FB |
2601 | return 0; |
2602 | } | |
2603 | ||
8408fd1d RB |
2604 | #ifndef CONFIG_MUSB_PIO_ONLY |
2605 | ||
2606 | #define MUSB_USB_DMA_ALIGN 4 | |
2607 | ||
2608 | struct musb_temp_buffer { | |
2609 | void *kmalloc_ptr; | |
2610 | void *old_xfer_buffer; | |
2611 | u8 data[0]; | |
2612 | }; | |
2613 | ||
2614 | static void musb_free_temp_buffer(struct urb *urb) | |
2615 | { | |
2616 | enum dma_data_direction dir; | |
2617 | struct musb_temp_buffer *temp; | |
d72348fb | 2618 | size_t length; |
8408fd1d RB |
2619 | |
2620 | if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) | |
2621 | return; | |
2622 | ||
2623 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
2624 | ||
2625 | temp = container_of(urb->transfer_buffer, struct musb_temp_buffer, | |
2626 | data); | |
2627 | ||
2628 | if (dir == DMA_FROM_DEVICE) { | |
d72348fb JH |
2629 | if (usb_pipeisoc(urb->pipe)) |
2630 | length = urb->transfer_buffer_length; | |
2631 | else | |
2632 | length = urb->actual_length; | |
2633 | ||
2634 | memcpy(temp->old_xfer_buffer, temp->data, length); | |
8408fd1d RB |
2635 | } |
2636 | urb->transfer_buffer = temp->old_xfer_buffer; | |
2637 | kfree(temp->kmalloc_ptr); | |
2638 | ||
2639 | urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; | |
2640 | } | |
2641 | ||
2642 | static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags) | |
2643 | { | |
2644 | enum dma_data_direction dir; | |
2645 | struct musb_temp_buffer *temp; | |
2646 | void *kmalloc_ptr; | |
2647 | size_t kmalloc_size; | |
2648 | ||
2649 | if (urb->num_sgs || urb->sg || | |
2650 | urb->transfer_buffer_length == 0 || | |
2651 | !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1))) | |
2652 | return 0; | |
2653 | ||
2654 | dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
2655 | ||
2656 | /* Allocate a buffer with enough padding for alignment */ | |
2657 | kmalloc_size = urb->transfer_buffer_length + | |
2658 | sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1; | |
2659 | ||
2660 | kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); | |
2661 | if (!kmalloc_ptr) | |
2662 | return -ENOMEM; | |
2663 | ||
2664 | /* Position our struct temp_buffer such that data is aligned */ | |
2665 | temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN); | |
2666 | ||
2667 | ||
2668 | temp->kmalloc_ptr = kmalloc_ptr; | |
2669 | temp->old_xfer_buffer = urb->transfer_buffer; | |
2670 | if (dir == DMA_TO_DEVICE) | |
2671 | memcpy(temp->data, urb->transfer_buffer, | |
2672 | urb->transfer_buffer_length); | |
2673 | urb->transfer_buffer = temp->data; | |
2674 | ||
2675 | urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; | |
2676 | ||
2677 | return 0; | |
2678 | } | |
2679 | ||
2680 | static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, | |
2681 | gfp_t mem_flags) | |
2682 | { | |
2683 | struct musb *musb = hcd_to_musb(hcd); | |
2684 | int ret; | |
2685 | ||
2686 | /* | |
2687 | * The DMA engine in RTL1.8 and above cannot handle | |
2688 | * DMA addresses that are not aligned to a 4 byte boundary. | |
2689 | * For such engine implemented (un)map_urb_for_dma hooks. | |
2690 | * Do not use these hooks for RTL<1.8 | |
2691 | */ | |
2692 | if (musb->hwvers < MUSB_HWVERS_1800) | |
2693 | return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
2694 | ||
2695 | ret = musb_alloc_temp_buffer(urb, mem_flags); | |
2696 | if (ret) | |
2697 | return ret; | |
2698 | ||
2699 | ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); | |
2700 | if (ret) | |
2701 | musb_free_temp_buffer(urb); | |
2702 | ||
2703 | return ret; | |
2704 | } | |
2705 | ||
2706 | static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) | |
2707 | { | |
2708 | struct musb *musb = hcd_to_musb(hcd); | |
2709 | ||
2710 | usb_hcd_unmap_urb_for_dma(hcd, urb); | |
2711 | ||
2712 | /* Do not use this hook for RTL<1.8 (see description above) */ | |
2713 | if (musb->hwvers < MUSB_HWVERS_1800) | |
2714 | return; | |
2715 | ||
2716 | musb_free_temp_buffer(urb); | |
2717 | } | |
2718 | #endif /* !CONFIG_MUSB_PIO_ONLY */ | |
2719 | ||
74c2e936 | 2720 | static const struct hc_driver musb_hc_driver = { |
550a7375 FB |
2721 | .description = "musb-hcd", |
2722 | .product_desc = "MUSB HDRC host driver", | |
74c2e936 | 2723 | .hcd_priv_size = sizeof(struct musb *), |
f551e135 | 2724 | .flags = HCD_USB2 | HCD_MEMORY, |
550a7375 FB |
2725 | |
2726 | /* not using irq handler or reset hooks from usbcore, since | |
2727 | * those must be shared with peripheral code for OTG configs | |
2728 | */ | |
2729 | ||
2730 | .start = musb_h_start, | |
2731 | .stop = musb_h_stop, | |
2732 | ||
2733 | .get_frame_number = musb_h_get_frame_number, | |
2734 | ||
2735 | .urb_enqueue = musb_urb_enqueue, | |
2736 | .urb_dequeue = musb_urb_dequeue, | |
2737 | .endpoint_disable = musb_h_disable, | |
2738 | ||
8408fd1d RB |
2739 | #ifndef CONFIG_MUSB_PIO_ONLY |
2740 | .map_urb_for_dma = musb_map_urb_for_dma, | |
2741 | .unmap_urb_for_dma = musb_unmap_urb_for_dma, | |
2742 | #endif | |
2743 | ||
550a7375 FB |
2744 | .hub_status_data = musb_hub_status_data, |
2745 | .hub_control = musb_hub_control, | |
2746 | .bus_suspend = musb_bus_suspend, | |
2747 | .bus_resume = musb_bus_resume, | |
2748 | /* .start_port_reset = NULL, */ | |
2749 | /* .hub_irq_enable = NULL, */ | |
2750 | }; | |
0b3eba44 | 2751 | |
74c2e936 DM |
2752 | int musb_host_alloc(struct musb *musb) |
2753 | { | |
2754 | struct device *dev = musb->controller; | |
2755 | ||
2756 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
2757 | musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); | |
2758 | if (!musb->hcd) | |
2759 | return -EINVAL; | |
2760 | ||
2761 | *musb->hcd->hcd_priv = (unsigned long) musb; | |
2762 | musb->hcd->self.uses_pio_for_control = 1; | |
2763 | musb->hcd->uses_new_polling = 1; | |
2764 | musb->hcd->has_tt = 1; | |
2765 | ||
2766 | return 0; | |
2767 | } | |
2768 | ||
2769 | void musb_host_cleanup(struct musb *musb) | |
2770 | { | |
90474288 SAS |
2771 | if (musb->port_mode == MUSB_PORT_MODE_GADGET) |
2772 | return; | |
74c2e936 | 2773 | usb_remove_hcd(musb->hcd); |
74c2e936 DM |
2774 | } |
2775 | ||
2776 | void musb_host_free(struct musb *musb) | |
2777 | { | |
2778 | usb_put_hcd(musb->hcd); | |
2779 | } | |
2780 | ||
2cc65fea DM |
2781 | int musb_host_setup(struct musb *musb, int power_budget) |
2782 | { | |
2783 | int ret; | |
2784 | struct usb_hcd *hcd = musb->hcd; | |
2785 | ||
3c50ffef TL |
2786 | if (musb->port_mode == MUSB_PORT_MODE_HOST) { |
2787 | MUSB_HST_MODE(musb); | |
2788 | musb->xceiv->otg->default_a = 1; | |
2789 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; | |
2790 | } | |
2cc65fea DM |
2791 | otg_set_host(musb->xceiv->otg, &hcd->self); |
2792 | hcd->self.otg_port = 1; | |
2793 | musb->xceiv->otg->host = &hcd->self; | |
2794 | hcd->power_budget = 2 * (power_budget ? : 250); | |
2795 | ||
2796 | ret = usb_add_hcd(hcd, 0, 0); | |
2797 | if (ret < 0) | |
2798 | return ret; | |
2799 | ||
3c9740a1 | 2800 | device_wakeup_enable(hcd->self.controller); |
2cc65fea DM |
2801 | return 0; |
2802 | } | |
2803 | ||
0b3eba44 DM |
2804 | void musb_host_resume_root_hub(struct musb *musb) |
2805 | { | |
74c2e936 | 2806 | usb_hcd_resume_root_hub(musb->hcd); |
0b3eba44 DM |
2807 | } |
2808 | ||
2809 | void musb_host_poke_root_hub(struct musb *musb) | |
2810 | { | |
2811 | MUSB_HST_MODE(musb); | |
74c2e936 DM |
2812 | if (musb->hcd->status_urb) |
2813 | usb_hcd_poll_rh_status(musb->hcd); | |
0b3eba44 | 2814 | else |
74c2e936 | 2815 | usb_hcd_resume_root_hub(musb->hcd); |
0b3eba44 | 2816 | } |