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usb: musb: host: Issue a memory barrier before starting DMA
[linux-2.6-block.git] / drivers / usb / musb / musb_gadget_ep0.c
CommitLineData
550a7375
FB		 1/*
2 * MUSB OTG peripheral driver ep0 handling
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
a5073b52 7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
550a7375
FB		 8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/timer.h>
39#include <linux/spinlock.h>
40#include <linux/init.h>
41#include <linux/device.h>
42#include <linux/interrupt.h>
43
44#include "musb_core.h"
45
46/* ep0 is always musb->endpoints[0].ep_in */
47#define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
48
49/*
50 * locking note: we use only the controller lock, for simpler correctness.
51 * It's always held with IRQs blocked.
52 *
53 * It protects the ep0 request queue as well as ep0_state, not just the
54 * controller and indexed registers. And that lock stays held unless it
55 * needs to be dropped to allow reentering this driver ... like upcalls to
56 * the gadget driver, or adjusting endpoint halt status.
57 */
58
59static char *decode_ep0stage(u8 stage)
60{
61 switch (stage) {
a5073b52
SS		 62 case MUSB_EP0_STAGE_IDLE: return "idle";
63 case MUSB_EP0_STAGE_SETUP: return "setup";
550a7375
FB		 64 case MUSB_EP0_STAGE_TX: return "in";
65 case MUSB_EP0_STAGE_RX: return "out";
66 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
67 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
68 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
69 default: return "?";
70 }
71}
72
73/* handle a standard GET_STATUS request
74 * Context: caller holds controller lock
75 */
76static int service_tx_status_request(
77 struct musb *musb,
78 const struct usb_ctrlrequest *ctrlrequest)
79{
80 void __iomem *mbase = musb->mregs;
81 int handled = 1;
82 u8 result[2], epnum = 0;
83 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
84
85 result[1] = 0;
86
87 switch (recip) {
88 case USB_RECIP_DEVICE:
89 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
90 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
91#ifdef CONFIG_USB_MUSB_OTG
92 if (musb->g.is_otg) {
93 result[0] |= musb->g.b_hnp_enable
94 << USB_DEVICE_B_HNP_ENABLE;
95 result[0] |= musb->g.a_alt_hnp_support
96 << USB_DEVICE_A_ALT_HNP_SUPPORT;
97 result[0] |= musb->g.a_hnp_support
98 << USB_DEVICE_A_HNP_SUPPORT;
99 }
100#endif
101 break;
102
103 case USB_RECIP_INTERFACE:
104 result[0] = 0;
105 break;
106
107 case USB_RECIP_ENDPOINT: {
108 int is_in;
109 struct musb_ep *ep;
110 u16 tmp;
111 void __iomem *regs;
112
113 epnum = (u8) ctrlrequest->wIndex;
114 if (!epnum) {
115 result[0] = 0;
116 break;
117 }
118
119 is_in = epnum & USB_DIR_IN;
120 if (is_in) {
121 epnum &= 0x0f;
122 ep = &musb->endpoints[epnum].ep_in;
123 } else {
124 ep = &musb->endpoints[epnum].ep_out;
125 }
126 regs = musb->endpoints[epnum].regs;
127
128 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
129 handled = -EINVAL;
130 break;
131 }
132
133 musb_ep_select(mbase, epnum);
134 if (is_in)
135 tmp = musb_readw(regs, MUSB_TXCSR)
136 & MUSB_TXCSR_P_SENDSTALL;
137 else
138 tmp = musb_readw(regs, MUSB_RXCSR)
139 & MUSB_RXCSR_P_SENDSTALL;
140 musb_ep_select(mbase, 0);
141
142 result[0] = tmp ? 1 : 0;
143 } break;
144
145 default:
146 /* class, vendor, etc ... delegate */
147 handled = 0;
148 break;
149 }
150
151 /* fill up the fifo; caller updates csr0 */
152 if (handled > 0) {
153 u16 len = le16_to_cpu(ctrlrequest->wLength);
154
155 if (len > 2)
156 len = 2;
157 musb_write_fifo(&musb->endpoints[0], len, result);
158 }
159
160 return handled;
161}
162
163/*
164 * handle a control-IN request, the end0 buffer contains the current request
165 * that is supposed to be a standard control request. Assumes the fifo to
166 * be at least 2 bytes long.
167 *
168 * @return 0 if the request was NOT HANDLED,
169 * < 0 when error
170 * > 0 when the request is processed
171 *
172 * Context: caller holds controller lock
173 */
174static int
175service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
176{
177 int handled = 0; /* not handled */
178
179 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
180 == USB_TYPE_STANDARD) {
181 switch (ctrlrequest->bRequest) {
182 case USB_REQ_GET_STATUS:
183 handled = service_tx_status_request(musb,
184 ctrlrequest);
185 break;
186
187 /* case USB_REQ_SYNC_FRAME: */
188
189 default:
190 break;
191 }
192 }
193 return handled;
194}
195
196/*
197 * Context: caller holds controller lock
198 */
199static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
200{
201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
550a7375
FB		 202}
203
204/*
205 * Tries to start B-device HNP negotiation if enabled via sysfs
206 */
207static inline void musb_try_b_hnp_enable(struct musb *musb)
208{
209 void __iomem *mbase = musb->mregs;
210 u8 devctl;
211
212 DBG(1, "HNP: Setting HR\n");
213 devctl = musb_readb(mbase, MUSB_DEVCTL);
214 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
215}
216
217/*
218 * Handle all control requests with no DATA stage, including standard
219 * requests such as:
220 * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
221 * always delegated to the gadget driver
222 * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
223 * always handled here, except for class/vendor/... features
224 *
225 * Context: caller holds controller lock
226 */
227static int
228service_zero_data_request(struct musb *musb,
229 struct usb_ctrlrequest *ctrlrequest)
230__releases(musb->lock)
231__acquires(musb->lock)
232{
233 int handled = -EINVAL;
234 void __iomem *mbase = musb->mregs;
235 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
236
237 /* the gadget driver handles everything except what we MUST handle */
238 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
239 == USB_TYPE_STANDARD) {
240 switch (ctrlrequest->bRequest) {
241 case USB_REQ_SET_ADDRESS:
242 /* change it after the status stage */
243 musb->set_address = true;
244 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
245 handled = 1;
246 break;
247
248 case USB_REQ_CLEAR_FEATURE:
249 switch (recip) {
250 case USB_RECIP_DEVICE:
251 if (ctrlrequest->wValue
252 != USB_DEVICE_REMOTE_WAKEUP)
253 break;
254 musb->may_wakeup = 0;
255 handled = 1;
256 break;
257 case USB_RECIP_INTERFACE:
258 break;
259 case USB_RECIP_ENDPOINT:{
46034dca
SS		 260 const u8 epnum =
261 ctrlrequest->wIndex & 0x0f;
262 struct musb_ep *musb_ep;
263 struct musb_hw_ep *ep;
264 void __iomem *regs;
265 int is_in;
266 u16 csr;
550a7375 267
46034dca
SS		 268 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
269 ctrlrequest->wValue != USB_ENDPOINT_HALT)
550a7375
FB		 270 break;
271
46034dca
SS		 272 ep = musb->endpoints + epnum;
273 regs = ep->regs;
274 is_in = ctrlrequest->wIndex & USB_DIR_IN;
275 if (is_in)
276 musb_ep = &ep->ep_in;
550a7375 277 else
46034dca 278 musb_ep = &ep->ep_out;
550a7375
FB		 279 if (!musb_ep->desc)
280 break;
281
47e97605
SS		 282 handled = 1;
283 /* Ignore request if endpoint is wedged */
284 if (musb_ep->wedged)
285 break;
286
46034dca
SS		 287 musb_ep_select(mbase, epnum);
288 if (is_in) {
289 csr = musb_readw(regs, MUSB_TXCSR);
290 csr |= MUSB_TXCSR_CLRDATATOG |
291 MUSB_TXCSR_P_WZC_BITS;
292 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
293 MUSB_TXCSR_P_SENTSTALL |
294 MUSB_TXCSR_TXPKTRDY);
295 musb_writew(regs, MUSB_TXCSR, csr);
296 } else {
297 csr = musb_readw(regs, MUSB_RXCSR);
298 csr |= MUSB_RXCSR_CLRDATATOG |
299 MUSB_RXCSR_P_WZC_BITS;
300 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
301 MUSB_RXCSR_P_SENTSTALL);
302 musb_writew(regs, MUSB_RXCSR, csr);
303 }
550a7375
FB		 304
305 /* select ep0 again */
306 musb_ep_select(mbase, 0);
550a7375
FB		 307 } break;
308 default:
309 /* class, vendor, etc ... delegate */
310 handled = 0;
311 break;
312 }
313 break;
314
315 case USB_REQ_SET_FEATURE:
316 switch (recip) {
317 case USB_RECIP_DEVICE:
318 handled = 1;
319 switch (ctrlrequest->wValue) {
320 case USB_DEVICE_REMOTE_WAKEUP:
321 musb->may_wakeup = 1;
322 break;
323 case USB_DEVICE_TEST_MODE:
324 if (musb->g.speed != USB_SPEED_HIGH)
325 goto stall;
326 if (ctrlrequest->wIndex & 0xff)
327 goto stall;
328
329 switch (ctrlrequest->wIndex >> 8) {
330 case 1:
331 pr_debug("TEST_J\n");
332 /* TEST_J */
333 musb->test_mode_nr =
334 MUSB_TEST_J;
335 break;
336 case 2:
337 /* TEST_K */
338 pr_debug("TEST_K\n");
339 musb->test_mode_nr =
340 MUSB_TEST_K;
341 break;
342 case 3:
343 /* TEST_SE0_NAK */
344 pr_debug("TEST_SE0_NAK\n");
345 musb->test_mode_nr =
346 MUSB_TEST_SE0_NAK;
347 break;
348 case 4:
349 /* TEST_PACKET */
350 pr_debug("TEST_PACKET\n");
351 musb->test_mode_nr =
352 MUSB_TEST_PACKET;
353 break;
ca4b2532
FB		 354
355 case 0xc0:
356 /* TEST_FORCE_HS */
357 pr_debug("TEST_FORCE_HS\n");
358 musb->test_mode_nr =
359 MUSB_TEST_FORCE_HS;
360 break;
361 case 0xc1:
362 /* TEST_FORCE_FS */
363 pr_debug("TEST_FORCE_FS\n");
364 musb->test_mode_nr =
365 MUSB_TEST_FORCE_FS;
366 break;
367 case 0xc2:
368 /* TEST_FIFO_ACCESS */
369 pr_debug("TEST_FIFO_ACCESS\n");
370 musb->test_mode_nr =
371 MUSB_TEST_FIFO_ACCESS;
372 break;
373 case 0xc3:
374 /* TEST_FORCE_HOST */
375 pr_debug("TEST_FORCE_HOST\n");
376 musb->test_mode_nr =
377 MUSB_TEST_FORCE_HOST;
378 break;
550a7375
FB		 379 default:
380 goto stall;
381 }
382
383 /* enter test mode after irq */
384 if (handled > 0)
385 musb->test_mode = true;
386 break;
387#ifdef CONFIG_USB_MUSB_OTG
388 case USB_DEVICE_B_HNP_ENABLE:
389 if (!musb->g.is_otg)
390 goto stall;
391 musb->g.b_hnp_enable = 1;
392 musb_try_b_hnp_enable(musb);
393 break;
394 case USB_DEVICE_A_HNP_SUPPORT:
395 if (!musb->g.is_otg)
396 goto stall;
397 musb->g.a_hnp_support = 1;
398 break;
399 case USB_DEVICE_A_ALT_HNP_SUPPORT:
400 if (!musb->g.is_otg)
401 goto stall;
402 musb->g.a_alt_hnp_support = 1;
403 break;
404#endif
d0390d92 405 case USB_DEVICE_DEBUG_MODE:
406 handled = 0;
407 break;
550a7375
FB		 408stall:
409 default:
410 handled = -EINVAL;
411 break;
412 }
413 break;
414
415 case USB_RECIP_INTERFACE:
416 break;
417
418 case USB_RECIP_ENDPOINT:{
419 const u8 epnum =
420 ctrlrequest->wIndex & 0x0f;
421 struct musb_ep *musb_ep;
422 struct musb_hw_ep *ep;
423 void __iomem *regs;
424 int is_in;
425 u16 csr;
426
46034dca
SS		 427 if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
428 ctrlrequest->wValue != USB_ENDPOINT_HALT)
550a7375
FB		 429 break;
430
431 ep = musb->endpoints + epnum;
432 regs = ep->regs;
433 is_in = ctrlrequest->wIndex & USB_DIR_IN;
434 if (is_in)
435 musb_ep = &ep->ep_in;
436 else
437 musb_ep = &ep->ep_out;
438 if (!musb_ep->desc)
439 break;
440
441 musb_ep_select(mbase, epnum);
442 if (is_in) {
46034dca 443 csr = musb_readw(regs, MUSB_TXCSR);
550a7375
FB		 444 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
445 csr |= MUSB_TXCSR_FLUSHFIFO;
446 csr |= MUSB_TXCSR_P_SENDSTALL
447 | MUSB_TXCSR_CLRDATATOG
448 | MUSB_TXCSR_P_WZC_BITS;
46034dca 449 musb_writew(regs, MUSB_TXCSR, csr);
550a7375 450 } else {
46034dca 451 csr = musb_readw(regs, MUSB_RXCSR);
550a7375
FB		 452 csr |= MUSB_RXCSR_P_SENDSTALL
453 | MUSB_RXCSR_FLUSHFIFO
454 | MUSB_RXCSR_CLRDATATOG
f01b017d 455 | MUSB_RXCSR_P_WZC_BITS;
46034dca 456 musb_writew(regs, MUSB_RXCSR, csr);
550a7375
FB		 457 }
458
459 /* select ep0 again */
460 musb_ep_select(mbase, 0);
461 handled = 1;
462 } break;
463
464 default:
465 /* class, vendor, etc ... delegate */
466 handled = 0;
467 break;
468 }
469 break;
470 default:
471 /* delegate SET_CONFIGURATION, etc */
472 handled = 0;
473 }
474 } else
475 handled = 0;
476 return handled;
477}
478
479/* we have an ep0out data packet
480 * Context: caller holds controller lock
481 */
482static void ep0_rxstate(struct musb *musb)
483{
484 void __iomem *regs = musb->control_ep->regs;
485 struct usb_request *req;
64ca44a6 486 u16 count, csr;
550a7375
FB		 487
488 req = next_ep0_request(musb);
489
490 /* read packet and ack; or stall because of gadget driver bug:
491 * should have provided the rx buffer before setup() returned.
492 */
493 if (req) {
494 void *buf = req->buf + req->actual;
495 unsigned len = req->length - req->actual;
496
497 /* read the buffer */
64ca44a6
BW		 498 count = musb_readb(regs, MUSB_COUNT0);
499 if (count > len) {
550a7375 500 req->status = -EOVERFLOW;
64ca44a6 501 count = len;
550a7375 502 }
64ca44a6
BW		 503 musb_read_fifo(&musb->endpoints[0], count, buf);
504 req->actual += count;
505 csr = MUSB_CSR0_P_SVDRXPKTRDY;
506 if (count < 64 || req->actual == req->length) {
550a7375 507 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
64ca44a6 508 csr |= MUSB_CSR0_P_DATAEND;
550a7375
FB		 509 } else
510 req = NULL;
511 } else
64ca44a6 512 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
550a7375
FB		 513
514
515 /* Completion handler may choose to stall, e.g. because the
516 * message just received holds invalid data.
517 */
518 if (req) {
64ca44a6 519 musb->ackpend = csr;
550a7375
FB		 520 musb_g_ep0_giveback(musb, req);
521 if (!musb->ackpend)
522 return;
523 musb->ackpend = 0;
524 }
fb85d991 525 musb_ep_select(musb->mregs, 0);
64ca44a6 526 musb_writew(regs, MUSB_CSR0, csr);
550a7375
FB		 527}
528
529/*
530 * transmitting to the host (IN), this code might be called from IRQ
531 * and from kernel thread.
532 *
533 * Context: caller holds controller lock
534 */
535static void ep0_txstate(struct musb *musb)
536{
537 void __iomem *regs = musb->control_ep->regs;
538 struct usb_request *request = next_ep0_request(musb);
539 u16 csr = MUSB_CSR0_TXPKTRDY;
540 u8 *fifo_src;
541 u8 fifo_count;
542
543 if (!request) {
544 /* WARN_ON(1); */
545 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
546 return;
547 }
548
549 /* load the data */
550 fifo_src = (u8 *) request->buf + request->actual;
551 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
552 request->length - request->actual);
553 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
554 request->actual += fifo_count;
555
556 /* update the flags */
557 if (fifo_count < MUSB_MAX_END0_PACKET
5542bc2a
DG		 558 || (request->actual == request->length
559 && !request->zero)) {
550a7375
FB		 560 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
561 csr |= MUSB_CSR0_P_DATAEND;
562 } else
563 request = NULL;
564
565 /* report completions as soon as the fifo's loaded; there's no
566 * win in waiting till this last packet gets acked. (other than
567 * very precise fault reporting, needed by USB TMC; possible with
568 * this hardware, but not usable from portable gadget drivers.)
569 */
570 if (request) {
571 musb->ackpend = csr;
572 musb_g_ep0_giveback(musb, request);
573 if (!musb->ackpend)
574 return;
575 musb->ackpend = 0;
576 }
577
578 /* send it out, triggering a "txpktrdy cleared" irq */
fb85d991 579 musb_ep_select(musb->mregs, 0);
550a7375
FB		 580 musb_writew(regs, MUSB_CSR0, csr);
581}
582
583/*
584 * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
585 * Fields are left in USB byte-order.
586 *
587 * Context: caller holds controller lock.
588 */
589static void
590musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
591{
592 struct usb_request *r;
593 void __iomem *regs = musb->control_ep->regs;
594
595 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
596
597 /* NOTE: earlier 2.6 versions changed setup packets to host
598 * order, but now USB packets always stay in USB byte order.
599 */
600 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
601 req->bRequestType,
602 req->bRequest,
603 le16_to_cpu(req->wValue),
604 le16_to_cpu(req->wIndex),
605 le16_to_cpu(req->wLength));
606
607 /* clean up any leftover transfers */
608 r = next_ep0_request(musb);
609 if (r)
610 musb_g_ep0_giveback(musb, r);
611
612 /* For zero-data requests we want to delay the STATUS stage to
613 * avoid SETUPEND errors. If we read data (OUT), delay accepting
614 * packets until there's a buffer to store them in.
615 *
616 * If we write data, the controller acts happier if we enable
617 * the TX FIFO right away, and give the controller a moment
618 * to switch modes...
619 */
620 musb->set_address = false;
621 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
622 if (req->wLength == 0) {
623 if (req->bRequestType & USB_DIR_IN)
624 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
625 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
626 } else if (req->bRequestType & USB_DIR_IN) {
627 musb->ep0_state = MUSB_EP0_STAGE_TX;
628 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
629 while ((musb_readw(regs, MUSB_CSR0)
630 & MUSB_CSR0_RXPKTRDY) != 0)
631 cpu_relax();
632 musb->ackpend = 0;
633 } else
634 musb->ep0_state = MUSB_EP0_STAGE_RX;
635}
636
637static int
638forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
639__releases(musb->lock)
640__acquires(musb->lock)
641{
642 int retval;
643 if (!musb->gadget_driver)
644 return -EOPNOTSUPP;
645 spin_unlock(&musb->lock);
646 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
647 spin_lock(&musb->lock);
648 return retval;
649}
650
651/*
652 * Handle peripheral ep0 interrupt
653 *
654 * Context: irq handler; we won't re-enter the driver that way.
655 */
656irqreturn_t musb_g_ep0_irq(struct musb *musb)
657{
658 u16 csr;
659 u16 len;
660 void __iomem *mbase = musb->mregs;
661 void __iomem *regs = musb->endpoints[0].regs;
662 irqreturn_t retval = IRQ_NONE;
663
664 musb_ep_select(mbase, 0); /* select ep0 */
665 csr = musb_readw(regs, MUSB_CSR0);
666 len = musb_readb(regs, MUSB_COUNT0);
667
668 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
669 csr, len,
670 musb_readb(mbase, MUSB_FADDR),
671 decode_ep0stage(musb->ep0_state));
672
673 /* I sent a stall.. need to acknowledge it now.. */
674 if (csr & MUSB_CSR0_P_SENTSTALL) {
675 musb_writew(regs, MUSB_CSR0,
676 csr & ~MUSB_CSR0_P_SENTSTALL);
677 retval = IRQ_HANDLED;
a5073b52 678 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
550a7375
FB		 679 csr = musb_readw(regs, MUSB_CSR0);
680 }
681
682 /* request ended "early" */
683 if (csr & MUSB_CSR0_P_SETUPEND) {
684 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
685 retval = IRQ_HANDLED;
a5073b52
SS		 686 /* Transition into the early status phase */
687 switch (musb->ep0_state) {
688 case MUSB_EP0_STAGE_TX:
689 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
690 break;
691 case MUSB_EP0_STAGE_RX:
692 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
693 break;
694 default:
17be5c5f 695 ERR("SetupEnd came in a wrong ep0stage %s\n",
a5073b52
SS		 696 decode_ep0stage(musb->ep0_state));
697 }
550a7375
FB		 698 csr = musb_readw(regs, MUSB_CSR0);
699 /* NOTE: request may need completion */
700 }
701
702 /* docs from Mentor only describe tx, rx, and idle/setup states.
703 * we need to handle nuances around status stages, and also the
704 * case where status and setup stages come back-to-back ...
705 */
706 switch (musb->ep0_state) {
707
708 case MUSB_EP0_STAGE_TX:
709 /* irq on clearing txpktrdy */
710 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
711 ep0_txstate(musb);
712 retval = IRQ_HANDLED;
713 }
714 break;
715
716 case MUSB_EP0_STAGE_RX:
717 /* irq on set rxpktrdy */
718 if (csr & MUSB_CSR0_RXPKTRDY) {
719 ep0_rxstate(musb);
720 retval = IRQ_HANDLED;
721 }
722 break;
723
724 case MUSB_EP0_STAGE_STATUSIN:
725 /* end of sequence #2 (OUT/RX state) or #3 (no data) */
726
727 /* update address (if needed) only @ the end of the
728 * status phase per usb spec, which also guarantees
729 * we get 10 msec to receive this irq... until this
730 * is done we won't see the next packet.
731 */
732 if (musb->set_address) {
733 musb->set_address = false;
734 musb_writeb(mbase, MUSB_FADDR, musb->address);
735 }
736
737 /* enter test mode if needed (exit by reset) */
738 else if (musb->test_mode) {
739 DBG(1, "entering TESTMODE\n");
740
741 if (MUSB_TEST_PACKET == musb->test_mode_nr)
742 musb_load_testpacket(musb);
743
744 musb_writeb(mbase, MUSB_TESTMODE,
745 musb->test_mode_nr);
746 }
747 /* FALLTHROUGH */
748
749 case MUSB_EP0_STAGE_STATUSOUT:
750 /* end of sequence #1: write to host (TX state) */
751 {
752 struct usb_request *req;
753
754 req = next_ep0_request(musb);
755 if (req)
756 musb_g_ep0_giveback(musb, req);
757 }
a5073b52
SS		 758
759 /*
760 * In case when several interrupts can get coalesced,
761 * check to see if we've already received a SETUP packet...
762 */
763 if (csr & MUSB_CSR0_RXPKTRDY)
764 goto setup;
765
766 retval = IRQ_HANDLED;
767 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
768 break;
769
770 case MUSB_EP0_STAGE_IDLE:
771 /*
772 * This state is typically (but not always) indiscernible
773 * from the status states since the corresponding interrupts
774 * tend to happen within too little period of time (with only
775 * a zero-length packet in between) and so get coalesced...
776 */
550a7375
FB		 777 retval = IRQ_HANDLED;
778 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
779 /* FALLTHROUGH */
780
781 case MUSB_EP0_STAGE_SETUP:
a5073b52 782setup:
550a7375
FB		 783 if (csr & MUSB_CSR0_RXPKTRDY) {
784 struct usb_ctrlrequest setup;
785 int handled = 0;
786
787 if (len != 8) {
788 ERR("SETUP packet len %d != 8 ?\n", len);
789 break;
790 }
791 musb_read_setup(musb, &setup);
792 retval = IRQ_HANDLED;
793
794 /* sometimes the RESET won't be reported */
795 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
796 u8 power;
797
798 printk(KERN_NOTICE "%s: peripheral reset "
799 "irq lost!\n",
800 musb_driver_name);
801 power = musb_readb(mbase, MUSB_POWER);
802 musb->g.speed = (power & MUSB_POWER_HSMODE)
803 ? USB_SPEED_HIGH : USB_SPEED_FULL;
804
805 }
806
807 switch (musb->ep0_state) {
808
809 /* sequence #3 (no data stage), includes requests
810 * we can't forward (notably SET_ADDRESS and the
811 * device/endpoint feature set/clear operations)
812 * plus SET_CONFIGURATION and others we must
813 */
814 case MUSB_EP0_STAGE_ACKWAIT:
815 handled = service_zero_data_request(
816 musb, &setup);
817
17be5c5f
SS		 818 /*
819 * We're expecting no data in any case, so
820 * always set the DATAEND bit -- doing this
821 * here helps avoid SetupEnd interrupt coming
822 * in the idle stage when we're stalling...
823 */
824 musb->ackpend |= MUSB_CSR0_P_DATAEND;
825
550a7375 826 /* status stage might be immediate */
17be5c5f 827 if (handled > 0)
550a7375
FB		 828 musb->ep0_state =
829 MUSB_EP0_STAGE_STATUSIN;
550a7375
FB		 830 break;
831
832 /* sequence #1 (IN to host), includes GET_STATUS
833 * requests that we can't forward, GET_DESCRIPTOR
834 * and others that we must
835 */
836 case MUSB_EP0_STAGE_TX:
837 handled = service_in_request(musb, &setup);
838 if (handled > 0) {
839 musb->ackpend = MUSB_CSR0_TXPKTRDY
840 | MUSB_CSR0_P_DATAEND;
841 musb->ep0_state =
842 MUSB_EP0_STAGE_STATUSOUT;
843 }
844 break;
845
846 /* sequence #2 (OUT from host), always forward */
847 default: /* MUSB_EP0_STAGE_RX */
848 break;
849 }
850
851 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
852 handled, csr,
853 decode_ep0stage(musb->ep0_state));
854
855 /* unless we need to delegate this to the gadget
856 * driver, we know how to wrap this up: csr0 has
857 * not yet been written.
858 */
859 if (handled < 0)
860 goto stall;
861 else if (handled > 0)
862 goto finish;
863
864 handled = forward_to_driver(musb, &setup);
865 if (handled < 0) {
866 musb_ep_select(mbase, 0);
867stall:
868 DBG(3, "stall (%d)\n", handled);
869 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
a5073b52 870 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
550a7375
FB		 871finish:
872 musb_writew(regs, MUSB_CSR0,
873 musb->ackpend);
874 musb->ackpend = 0;
875 }
876 }
877 break;
878
879 case MUSB_EP0_STAGE_ACKWAIT:
880 /* This should not happen. But happens with tusb6010 with
881 * g_file_storage and high speed. Do nothing.
882 */
883 retval = IRQ_HANDLED;
884 break;
885
886 default:
887 /* "can't happen" */
888 WARN_ON(1);
889 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
a5073b52 890 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
550a7375
FB		 891 break;
892 }
893
894 return retval;
895}
896
897
898static int
899musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
900{
901 /* always enabled */
902 return -EINVAL;
903}
904
905static int musb_g_ep0_disable(struct usb_ep *e)
906{
907 /* always enabled */
908 return -EINVAL;
909}
910
911static int
912musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
913{
914 struct musb_ep *ep;
915 struct musb_request *req;
916 struct musb *musb;
917 int status;
918 unsigned long lockflags;
919 void __iomem *regs;
920
921 if (!e || !r)
922 return -EINVAL;
923
924 ep = to_musb_ep(e);
925 musb = ep->musb;
926 regs = musb->control_ep->regs;
927
928 req = to_musb_request(r);
929 req->musb = musb;
930 req->request.actual = 0;
931 req->request.status = -EINPROGRESS;
932 req->tx = ep->is_in;
933
934 spin_lock_irqsave(&musb->lock, lockflags);
935
936 if (!list_empty(&ep->req_list)) {
937 status = -EBUSY;
938 goto cleanup;
939 }
940
941 switch (musb->ep0_state) {
942 case MUSB_EP0_STAGE_RX: /* control-OUT data */
943 case MUSB_EP0_STAGE_TX: /* control-IN data */
944 case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
945 status = 0;
946 break;
947 default:
948 DBG(1, "ep0 request queued in state %d\n",
949 musb->ep0_state);
950 status = -EINVAL;
951 goto cleanup;
952 }
953
954 /* add request to the list */
955 list_add_tail(&(req->request.list), &(ep->req_list));
956
957 DBG(3, "queue to %s (%s), length=%d\n",
958 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
959 req->request.length);
960
961 musb_ep_select(musb->mregs, 0);
962
963 /* sequence #1, IN ... start writing the data */
964 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
965 ep0_txstate(musb);
966
967 /* sequence #3, no-data ... issue IN status */
968 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
969 if (req->request.length)
970 status = -EINVAL;
971 else {
972 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
973 musb_writew(regs, MUSB_CSR0,
974 musb->ackpend | MUSB_CSR0_P_DATAEND);
975 musb->ackpend = 0;
976 musb_g_ep0_giveback(ep->musb, r);
977 }
978
979 /* else for sequence #2 (OUT), caller provides a buffer
980 * before the next packet arrives. deferred responses
981 * (after SETUP is acked) are racey.
982 */
983 } else if (musb->ackpend) {
984 musb_writew(regs, MUSB_CSR0, musb->ackpend);
985 musb->ackpend = 0;
986 }
987
988cleanup:
989 spin_unlock_irqrestore(&musb->lock, lockflags);
990 return status;
991}
992
993static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
994{
995 /* we just won't support this */
996 return -EINVAL;
997}
998
999static int musb_g_ep0_halt(struct usb_ep *e, int value)
1000{
1001 struct musb_ep *ep;
1002 struct musb *musb;
1003 void __iomem *base, *regs;
1004 unsigned long flags;
1005 int status;
1006 u16 csr;
1007
1008 if (!e || !value)
1009 return -EINVAL;
1010
1011 ep = to_musb_ep(e);
1012 musb = ep->musb;
1013 base = musb->mregs;
1014 regs = musb->control_ep->regs;
1015 status = 0;
1016
1017 spin_lock_irqsave(&musb->lock, flags);
1018
1019 if (!list_empty(&ep->req_list)) {
1020 status = -EBUSY;
1021 goto cleanup;
1022 }
1023
1024 musb_ep_select(base, 0);
1025 csr = musb->ackpend;
1026
1027 switch (musb->ep0_state) {
1028
1029 /* Stalls are usually issued after parsing SETUP packet, either
1030 * directly in irq context from setup() or else later.
1031 */
1032 case MUSB_EP0_STAGE_TX: /* control-IN data */
1033 case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
1034 case MUSB_EP0_STAGE_RX: /* control-OUT data */
1035 csr = musb_readw(regs, MUSB_CSR0);
1036 /* FALLTHROUGH */
1037
1038 /* It's also OK to issue stalls during callbacks when a non-empty
1039 * DATA stage buffer has been read (or even written).
1040 */
1041 case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
1042 case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
1043
1044 csr |= MUSB_CSR0_P_SENDSTALL;
1045 musb_writew(regs, MUSB_CSR0, csr);
a5073b52 1046 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
550a7375
FB		 1047 musb->ackpend = 0;
1048 break;
1049 default:
1050 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
1051 status = -EINVAL;
1052 }
1053
1054cleanup:
1055 spin_unlock_irqrestore(&musb->lock, flags);
1056 return status;
1057}
1058
1059const struct usb_ep_ops musb_g_ep0_ops = {
1060 .enable = musb_g_ep0_enable,
1061 .disable = musb_g_ep0_disable,
1062 .alloc_request = musb_alloc_request,
1063 .free_request = musb_free_request,
1064 .queue = musb_g_ep0_queue,
1065 .dequeue = musb_g_ep0_dequeue,
1066 .set_halt = musb_g_ep0_halt,
1067};
Linux 6.x block layer and io_uring tree(s)