Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver peripheral support | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
cea83241 | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
550a7375 FB |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
21 | * 02110-1301 USA | |
22 | * | |
23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/list.h> | |
38 | #include <linux/timer.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/smp.h> | |
41 | #include <linux/spinlock.h> | |
42 | #include <linux/delay.h> | |
550a7375 | 43 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
550a7375 FB |
45 | |
46 | #include "musb_core.h" | |
47 | ||
48 | ||
550a7375 FB |
49 | /* ----------------------------------------------------------------------- */ |
50 | ||
c65bfa62 MYK |
51 | #define is_buffer_mapped(req) (is_dma_capable() && \ |
52 | (req->map_state != UN_MAPPED)) | |
53 | ||
92d2711f HK |
54 | /* Maps the buffer to dma */ |
55 | ||
56 | static inline void map_dma_buffer(struct musb_request *request, | |
c65bfa62 | 57 | struct musb *musb, struct musb_ep *musb_ep) |
92d2711f | 58 | { |
5f5761cb MYK |
59 | int compatible = true; |
60 | struct dma_controller *dma = musb->dma_controller; | |
61 | ||
c65bfa62 MYK |
62 | request->map_state = UN_MAPPED; |
63 | ||
64 | if (!is_dma_capable() || !musb_ep->dma) | |
65 | return; | |
66 | ||
5f5761cb MYK |
67 | /* Check if DMA engine can handle this request. |
68 | * DMA code must reject the USB request explicitly. | |
69 | * Default behaviour is to map the request. | |
70 | */ | |
71 | if (dma->is_compatible) | |
72 | compatible = dma->is_compatible(musb_ep->dma, | |
73 | musb_ep->packet_sz, request->request.buf, | |
74 | request->request.length); | |
75 | if (!compatible) | |
76 | return; | |
77 | ||
92d2711f | 78 | if (request->request.dma == DMA_ADDR_INVALID) { |
7b360f42 SAS |
79 | dma_addr_t dma_addr; |
80 | int ret; | |
81 | ||
82 | dma_addr = dma_map_single( | |
92d2711f HK |
83 | musb->controller, |
84 | request->request.buf, | |
85 | request->request.length, | |
86 | request->tx | |
87 | ? DMA_TO_DEVICE | |
88 | : DMA_FROM_DEVICE); | |
7b360f42 SAS |
89 | ret = dma_mapping_error(musb->controller, dma_addr); |
90 | if (ret) | |
91 | return; | |
92 | ||
93 | request->request.dma = dma_addr; | |
c65bfa62 | 94 | request->map_state = MUSB_MAPPED; |
92d2711f HK |
95 | } else { |
96 | dma_sync_single_for_device(musb->controller, | |
97 | request->request.dma, | |
98 | request->request.length, | |
99 | request->tx | |
100 | ? DMA_TO_DEVICE | |
101 | : DMA_FROM_DEVICE); | |
c65bfa62 | 102 | request->map_state = PRE_MAPPED; |
92d2711f HK |
103 | } |
104 | } | |
105 | ||
106 | /* Unmap the buffer from dma and maps it back to cpu */ | |
107 | static inline void unmap_dma_buffer(struct musb_request *request, | |
108 | struct musb *musb) | |
109 | { | |
06d9db72 KVA |
110 | struct musb_ep *musb_ep = request->ep; |
111 | ||
112 | if (!is_buffer_mapped(request) || !musb_ep->dma) | |
c65bfa62 MYK |
113 | return; |
114 | ||
92d2711f | 115 | if (request->request.dma == DMA_ADDR_INVALID) { |
5c8a86e1 FB |
116 | dev_vdbg(musb->controller, |
117 | "not unmapping a never mapped buffer\n"); | |
92d2711f HK |
118 | return; |
119 | } | |
c65bfa62 | 120 | if (request->map_state == MUSB_MAPPED) { |
92d2711f HK |
121 | dma_unmap_single(musb->controller, |
122 | request->request.dma, | |
123 | request->request.length, | |
124 | request->tx | |
125 | ? DMA_TO_DEVICE | |
126 | : DMA_FROM_DEVICE); | |
127 | request->request.dma = DMA_ADDR_INVALID; | |
c65bfa62 | 128 | } else { /* PRE_MAPPED */ |
92d2711f HK |
129 | dma_sync_single_for_cpu(musb->controller, |
130 | request->request.dma, | |
131 | request->request.length, | |
132 | request->tx | |
133 | ? DMA_TO_DEVICE | |
134 | : DMA_FROM_DEVICE); | |
92d2711f | 135 | } |
c65bfa62 | 136 | request->map_state = UN_MAPPED; |
92d2711f HK |
137 | } |
138 | ||
550a7375 FB |
139 | /* |
140 | * Immediately complete a request. | |
141 | * | |
142 | * @param request the request to complete | |
143 | * @param status the status to complete the request with | |
144 | * Context: controller locked, IRQs blocked. | |
145 | */ | |
146 | void musb_g_giveback( | |
147 | struct musb_ep *ep, | |
148 | struct usb_request *request, | |
149 | int status) | |
150 | __releases(ep->musb->lock) | |
151 | __acquires(ep->musb->lock) | |
152 | { | |
153 | struct musb_request *req; | |
154 | struct musb *musb; | |
155 | int busy = ep->busy; | |
156 | ||
157 | req = to_musb_request(request); | |
158 | ||
ad1adb89 | 159 | list_del(&req->list); |
550a7375 FB |
160 | if (req->request.status == -EINPROGRESS) |
161 | req->request.status = status; | |
162 | musb = req->musb; | |
163 | ||
164 | ep->busy = 1; | |
165 | spin_unlock(&musb->lock); | |
06d9db72 KVA |
166 | |
167 | if (!dma_mapping_error(&musb->g.dev, request->dma)) | |
168 | unmap_dma_buffer(req, musb); | |
169 | ||
550a7375 | 170 | if (request->status == 0) |
5c8a86e1 | 171 | dev_dbg(musb->controller, "%s done request %p, %d/%d\n", |
550a7375 FB |
172 | ep->end_point.name, request, |
173 | req->request.actual, req->request.length); | |
174 | else | |
5c8a86e1 | 175 | dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n", |
550a7375 FB |
176 | ep->end_point.name, request, |
177 | req->request.actual, req->request.length, | |
178 | request->status); | |
179 | req->request.complete(&req->ep->end_point, &req->request); | |
180 | spin_lock(&musb->lock); | |
181 | ep->busy = busy; | |
182 | } | |
183 | ||
184 | /* ----------------------------------------------------------------------- */ | |
185 | ||
186 | /* | |
187 | * Abort requests queued to an endpoint using the status. Synchronous. | |
188 | * caller locked controller and blocked irqs, and selected this ep. | |
189 | */ | |
190 | static void nuke(struct musb_ep *ep, const int status) | |
191 | { | |
5c8a86e1 | 192 | struct musb *musb = ep->musb; |
550a7375 FB |
193 | struct musb_request *req = NULL; |
194 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; | |
195 | ||
196 | ep->busy = 1; | |
197 | ||
198 | if (is_dma_capable() && ep->dma) { | |
199 | struct dma_controller *c = ep->musb->dma_controller; | |
200 | int value; | |
b6e434a5 | 201 | |
550a7375 | 202 | if (ep->is_in) { |
b6e434a5 SS |
203 | /* |
204 | * The programming guide says that we must not clear | |
205 | * the DMAMODE bit before DMAENAB, so we only | |
206 | * clear it in the second write... | |
207 | */ | |
550a7375 | 208 | musb_writew(epio, MUSB_TXCSR, |
b6e434a5 | 209 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
550a7375 FB |
210 | musb_writew(epio, MUSB_TXCSR, |
211 | 0 | MUSB_TXCSR_FLUSHFIFO); | |
212 | } else { | |
213 | musb_writew(epio, MUSB_RXCSR, | |
214 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
215 | musb_writew(epio, MUSB_RXCSR, | |
216 | 0 | MUSB_RXCSR_FLUSHFIFO); | |
217 | } | |
218 | ||
219 | value = c->channel_abort(ep->dma); | |
5c8a86e1 FB |
220 | dev_dbg(musb->controller, "%s: abort DMA --> %d\n", |
221 | ep->name, value); | |
550a7375 FB |
222 | c->channel_release(ep->dma); |
223 | ep->dma = NULL; | |
224 | } | |
225 | ||
ad1adb89 FB |
226 | while (!list_empty(&ep->req_list)) { |
227 | req = list_first_entry(&ep->req_list, struct musb_request, list); | |
550a7375 FB |
228 | musb_g_giveback(ep, &req->request, status); |
229 | } | |
230 | } | |
231 | ||
232 | /* ----------------------------------------------------------------------- */ | |
233 | ||
234 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ | |
235 | ||
236 | /* | |
237 | * This assumes the separate CPPI engine is responding to DMA requests | |
238 | * from the usb core ... sequenced a bit differently from mentor dma. | |
239 | */ | |
240 | ||
241 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) | |
242 | { | |
243 | if (can_bulk_split(musb, ep->type)) | |
244 | return ep->hw_ep->max_packet_sz_tx; | |
245 | else | |
246 | return ep->packet_sz; | |
247 | } | |
248 | ||
550a7375 FB |
249 | /* |
250 | * An endpoint is transmitting data. This can be called either from | |
251 | * the IRQ routine or from ep.queue() to kickstart a request on an | |
252 | * endpoint. | |
253 | * | |
254 | * Context: controller locked, IRQs blocked, endpoint selected | |
255 | */ | |
256 | static void txstate(struct musb *musb, struct musb_request *req) | |
257 | { | |
258 | u8 epnum = req->epnum; | |
259 | struct musb_ep *musb_ep; | |
260 | void __iomem *epio = musb->endpoints[epnum].regs; | |
261 | struct usb_request *request; | |
262 | u16 fifo_count = 0, csr; | |
263 | int use_dma = 0; | |
264 | ||
265 | musb_ep = req->ep; | |
266 | ||
abf710e6 VP |
267 | /* Check if EP is disabled */ |
268 | if (!musb_ep->desc) { | |
269 | dev_dbg(musb->controller, "ep:%s disabled - ignore request\n", | |
270 | musb_ep->end_point.name); | |
271 | return; | |
272 | } | |
273 | ||
550a7375 FB |
274 | /* we shouldn't get here while DMA is active ... but we do ... */ |
275 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 276 | dev_dbg(musb->controller, "dma pending...\n"); |
550a7375 FB |
277 | return; |
278 | } | |
279 | ||
280 | /* read TXCSR before */ | |
281 | csr = musb_readw(epio, MUSB_TXCSR); | |
282 | ||
283 | request = &req->request; | |
284 | fifo_count = min(max_ep_writesize(musb, musb_ep), | |
285 | (int)(request->length - request->actual)); | |
286 | ||
287 | if (csr & MUSB_TXCSR_TXPKTRDY) { | |
5c8a86e1 | 288 | dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n", |
550a7375 FB |
289 | musb_ep->end_point.name, csr); |
290 | return; | |
291 | } | |
292 | ||
293 | if (csr & MUSB_TXCSR_P_SENDSTALL) { | |
5c8a86e1 | 294 | dev_dbg(musb->controller, "%s stalling, txcsr %03x\n", |
550a7375 FB |
295 | musb_ep->end_point.name, csr); |
296 | return; | |
297 | } | |
298 | ||
5c8a86e1 | 299 | dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", |
550a7375 FB |
300 | epnum, musb_ep->packet_sz, fifo_count, |
301 | csr); | |
302 | ||
303 | #ifndef CONFIG_MUSB_PIO_ONLY | |
c65bfa62 | 304 | if (is_buffer_mapped(req)) { |
550a7375 | 305 | struct dma_controller *c = musb->dma_controller; |
66af83dd ML |
306 | size_t request_size; |
307 | ||
308 | /* setup DMA, then program endpoint CSR */ | |
309 | request_size = min_t(size_t, request->length - request->actual, | |
310 | musb_ep->dma->max_len); | |
550a7375 | 311 | |
d17d535f | 312 | use_dma = (request->dma != DMA_ADDR_INVALID && request_size); |
550a7375 FB |
313 | |
314 | /* MUSB_TXCSR_P_ISO is still set correctly */ | |
315 | ||
a48ff906 | 316 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
550a7375 | 317 | { |
d1043a26 | 318 | if (request_size < musb_ep->packet_sz) |
550a7375 FB |
319 | musb_ep->dma->desired_mode = 0; |
320 | else | |
321 | musb_ep->dma->desired_mode = 1; | |
322 | ||
323 | use_dma = use_dma && c->channel_program( | |
324 | musb_ep->dma, musb_ep->packet_sz, | |
325 | musb_ep->dma->desired_mode, | |
796a83fa | 326 | request->dma + request->actual, request_size); |
550a7375 FB |
327 | if (use_dma) { |
328 | if (musb_ep->dma->desired_mode == 0) { | |
b6e434a5 SS |
329 | /* |
330 | * We must not clear the DMAMODE bit | |
331 | * before the DMAENAB bit -- and the | |
332 | * latter doesn't always get cleared | |
333 | * before we get here... | |
334 | */ | |
335 | csr &= ~(MUSB_TXCSR_AUTOSET | |
336 | | MUSB_TXCSR_DMAENAB); | |
337 | musb_writew(epio, MUSB_TXCSR, csr | |
338 | | MUSB_TXCSR_P_WZC_BITS); | |
339 | csr &= ~MUSB_TXCSR_DMAMODE; | |
550a7375 FB |
340 | csr |= (MUSB_TXCSR_DMAENAB | |
341 | MUSB_TXCSR_MODE); | |
342 | /* against programming guide */ | |
f11d893d ML |
343 | } else { |
344 | csr |= (MUSB_TXCSR_DMAENAB | |
550a7375 FB |
345 | | MUSB_TXCSR_DMAMODE |
346 | | MUSB_TXCSR_MODE); | |
bb3a2ef2 | 347 | /* |
348 | * Enable Autoset according to table | |
349 | * below | |
350 | * bulk_split hb_mult Autoset_Enable | |
351 | * 0 0 Yes(Normal) | |
352 | * 0 >0 No(High BW ISO) | |
353 | * 1 0 Yes(HS bulk) | |
354 | * 1 >0 Yes(FS bulk) | |
355 | */ | |
356 | if (!musb_ep->hb_mult || | |
357 | (musb_ep->hb_mult && | |
358 | can_bulk_split(musb, | |
359 | musb_ep->type))) | |
f11d893d ML |
360 | csr |= MUSB_TXCSR_AUTOSET; |
361 | } | |
550a7375 | 362 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
f11d893d | 363 | |
550a7375 FB |
364 | musb_writew(epio, MUSB_TXCSR, csr); |
365 | } | |
366 | } | |
367 | ||
550a7375 | 368 | #endif |
fc525751 SAS |
369 | if (is_cppi_enabled()) { |
370 | /* program endpoint CSR first, then setup DMA */ | |
371 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
372 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | | |
373 | MUSB_TXCSR_MODE; | |
374 | musb_writew(epio, MUSB_TXCSR, (MUSB_TXCSR_P_WZC_BITS & | |
375 | ~MUSB_TXCSR_P_UNDERRUN) | csr); | |
376 | ||
377 | /* ensure writebuffer is empty */ | |
378 | csr = musb_readw(epio, MUSB_TXCSR); | |
379 | ||
380 | /* | |
381 | * NOTE host side sets DMAENAB later than this; both are | |
382 | * OK since the transfer dma glue (between CPPI and | |
383 | * Mentor fifos) just tells CPPI it could start. Data | |
384 | * only moves to the USB TX fifo when both fifos are | |
385 | * ready. | |
386 | */ | |
387 | /* | |
388 | * "mode" is irrelevant here; handle terminating ZLPs | |
389 | * like PIO does, since the hardware RNDIS mode seems | |
390 | * unreliable except for the | |
391 | * last-packet-is-already-short case. | |
392 | */ | |
393 | use_dma = use_dma && c->channel_program( | |
394 | musb_ep->dma, musb_ep->packet_sz, | |
395 | 0, | |
396 | request->dma + request->actual, | |
397 | request_size); | |
398 | if (!use_dma) { | |
399 | c->channel_release(musb_ep->dma); | |
400 | musb_ep->dma = NULL; | |
401 | csr &= ~MUSB_TXCSR_DMAENAB; | |
402 | musb_writew(epio, MUSB_TXCSR, csr); | |
403 | /* invariant: prequest->buf is non-null */ | |
404 | } | |
405 | } else if (tusb_dma_omap()) | |
406 | use_dma = use_dma && c->channel_program( | |
407 | musb_ep->dma, musb_ep->packet_sz, | |
408 | request->zero, | |
409 | request->dma + request->actual, | |
410 | request_size); | |
550a7375 FB |
411 | } |
412 | #endif | |
413 | ||
414 | if (!use_dma) { | |
92d2711f HK |
415 | /* |
416 | * Unmap the dma buffer back to cpu if dma channel | |
417 | * programming fails | |
418 | */ | |
c65bfa62 | 419 | unmap_dma_buffer(req, musb); |
92d2711f | 420 | |
550a7375 FB |
421 | musb_write_fifo(musb_ep->hw_ep, fifo_count, |
422 | (u8 *) (request->buf + request->actual)); | |
423 | request->actual += fifo_count; | |
424 | csr |= MUSB_TXCSR_TXPKTRDY; | |
425 | csr &= ~MUSB_TXCSR_P_UNDERRUN; | |
426 | musb_writew(epio, MUSB_TXCSR, csr); | |
427 | } | |
428 | ||
429 | /* host may already have the data when this message shows... */ | |
5c8a86e1 | 430 | dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", |
550a7375 FB |
431 | musb_ep->end_point.name, use_dma ? "dma" : "pio", |
432 | request->actual, request->length, | |
433 | musb_readw(epio, MUSB_TXCSR), | |
434 | fifo_count, | |
435 | musb_readw(epio, MUSB_TXMAXP)); | |
436 | } | |
437 | ||
438 | /* | |
439 | * FIFO state update (e.g. data ready). | |
440 | * Called from IRQ, with controller locked. | |
441 | */ | |
442 | void musb_g_tx(struct musb *musb, u8 epnum) | |
443 | { | |
444 | u16 csr; | |
ad1adb89 | 445 | struct musb_request *req; |
550a7375 FB |
446 | struct usb_request *request; |
447 | u8 __iomem *mbase = musb->mregs; | |
448 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; | |
449 | void __iomem *epio = musb->endpoints[epnum].regs; | |
450 | struct dma_channel *dma; | |
451 | ||
452 | musb_ep_select(mbase, epnum); | |
ad1adb89 FB |
453 | req = next_request(musb_ep); |
454 | request = &req->request; | |
550a7375 FB |
455 | |
456 | csr = musb_readw(epio, MUSB_TXCSR); | |
5c8a86e1 | 457 | dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); |
550a7375 FB |
458 | |
459 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
7723de7e SS |
460 | |
461 | /* | |
462 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX | |
463 | * probably rates reporting as a host error. | |
464 | */ | |
465 | if (csr & MUSB_TXCSR_P_SENTSTALL) { | |
466 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
467 | csr &= ~MUSB_TXCSR_P_SENTSTALL; | |
468 | musb_writew(epio, MUSB_TXCSR, csr); | |
469 | return; | |
470 | } | |
471 | ||
472 | if (csr & MUSB_TXCSR_P_UNDERRUN) { | |
473 | /* We NAKed, no big deal... little reason to care. */ | |
474 | csr |= MUSB_TXCSR_P_WZC_BITS; | |
475 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); | |
476 | musb_writew(epio, MUSB_TXCSR, csr); | |
5c8a86e1 FB |
477 | dev_vdbg(musb->controller, "underrun on ep%d, req %p\n", |
478 | epnum, request); | |
7723de7e SS |
479 | } |
480 | ||
481 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
482 | /* | |
483 | * SHOULD NOT HAPPEN... has with CPPI though, after | |
484 | * changing SENDSTALL (and other cases); harmless? | |
550a7375 | 485 | */ |
5c8a86e1 | 486 | dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name); |
7723de7e SS |
487 | return; |
488 | } | |
550a7375 | 489 | |
7723de7e SS |
490 | if (request) { |
491 | u8 is_dma = 0; | |
492 | ||
493 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { | |
494 | is_dma = 1; | |
550a7375 | 495 | csr |= MUSB_TXCSR_P_WZC_BITS; |
7723de7e | 496 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
100d4a9d | 497 | MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_AUTOSET); |
550a7375 | 498 | musb_writew(epio, MUSB_TXCSR, csr); |
7723de7e SS |
499 | /* Ensure writebuffer is empty. */ |
500 | csr = musb_readw(epio, MUSB_TXCSR); | |
501 | request->actual += musb_ep->dma->actual_len; | |
5c8a86e1 | 502 | dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n", |
7723de7e | 503 | epnum, csr, musb_ep->dma->actual_len, request); |
550a7375 FB |
504 | } |
505 | ||
e7379aaa ML |
506 | /* |
507 | * First, maybe a terminating short packet. Some DMA | |
508 | * engines might handle this by themselves. | |
509 | */ | |
510 | if ((request->zero && request->length | |
511 | && (request->length % musb_ep->packet_sz == 0) | |
512 | && (request->actual == request->length)) | |
a48ff906 | 513 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA) |
e7379aaa ML |
514 | || (is_dma && (!dma->desired_mode || |
515 | (request->actual & | |
516 | (musb_ep->packet_sz - 1)))) | |
550a7375 | 517 | #endif |
e7379aaa ML |
518 | ) { |
519 | /* | |
520 | * On DMA completion, FIFO may not be | |
521 | * available yet... | |
522 | */ | |
523 | if (csr & MUSB_TXCSR_TXPKTRDY) | |
524 | return; | |
550a7375 | 525 | |
5c8a86e1 | 526 | dev_dbg(musb->controller, "sending zero pkt\n"); |
e7379aaa ML |
527 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE |
528 | | MUSB_TXCSR_TXPKTRDY); | |
529 | request->zero = 0; | |
530 | } | |
531 | ||
532 | if (request->actual == request->length) { | |
533 | musb_g_giveback(musb_ep, request, 0); | |
39287076 SK |
534 | /* |
535 | * In the giveback function the MUSB lock is | |
536 | * released and acquired after sometime. During | |
537 | * this time period the INDEX register could get | |
538 | * changed by the gadget_queue function especially | |
539 | * on SMP systems. Reselect the INDEX to be sure | |
540 | * we are reading/modifying the right registers | |
541 | */ | |
542 | musb_ep_select(mbase, epnum); | |
ad1adb89 FB |
543 | req = musb_ep->desc ? next_request(musb_ep) : NULL; |
544 | if (!req) { | |
5c8a86e1 | 545 | dev_dbg(musb->controller, "%s idle now\n", |
e7379aaa ML |
546 | musb_ep->end_point.name); |
547 | return; | |
95962a77 | 548 | } |
550a7375 FB |
549 | } |
550 | ||
ad1adb89 | 551 | txstate(musb, req); |
7723de7e | 552 | } |
550a7375 FB |
553 | } |
554 | ||
555 | /* ------------------------------------------------------------ */ | |
556 | ||
550a7375 FB |
557 | /* |
558 | * Context: controller locked, IRQs blocked, endpoint selected | |
559 | */ | |
560 | static void rxstate(struct musb *musb, struct musb_request *req) | |
561 | { | |
550a7375 FB |
562 | const u8 epnum = req->epnum; |
563 | struct usb_request *request = &req->request; | |
bd2e74d6 | 564 | struct musb_ep *musb_ep; |
550a7375 | 565 | void __iomem *epio = musb->endpoints[epnum].regs; |
f0443afd SS |
566 | unsigned len = 0; |
567 | u16 fifo_count; | |
cea83241 | 568 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
bd2e74d6 | 569 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
0ae52d54 | 570 | u8 use_mode_1; |
bd2e74d6 ML |
571 | |
572 | if (hw_ep->is_shared_fifo) | |
573 | musb_ep = &hw_ep->ep_in; | |
574 | else | |
575 | musb_ep = &hw_ep->ep_out; | |
576 | ||
f0443afd | 577 | fifo_count = musb_ep->packet_sz; |
550a7375 | 578 | |
abf710e6 VP |
579 | /* Check if EP is disabled */ |
580 | if (!musb_ep->desc) { | |
581 | dev_dbg(musb->controller, "ep:%s disabled - ignore request\n", | |
582 | musb_ep->end_point.name); | |
583 | return; | |
584 | } | |
585 | ||
cea83241 SS |
586 | /* We shouldn't get here while DMA is active, but we do... */ |
587 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { | |
5c8a86e1 | 588 | dev_dbg(musb->controller, "DMA pending...\n"); |
cea83241 SS |
589 | return; |
590 | } | |
591 | ||
592 | if (csr & MUSB_RXCSR_P_SENDSTALL) { | |
5c8a86e1 | 593 | dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n", |
cea83241 SS |
594 | musb_ep->end_point.name, csr); |
595 | return; | |
596 | } | |
550a7375 | 597 | |
c65bfa62 | 598 | if (is_cppi_enabled() && is_buffer_mapped(req)) { |
550a7375 FB |
599 | struct dma_controller *c = musb->dma_controller; |
600 | struct dma_channel *channel = musb_ep->dma; | |
601 | ||
602 | /* NOTE: CPPI won't actually stop advancing the DMA | |
603 | * queue after short packet transfers, so this is almost | |
604 | * always going to run as IRQ-per-packet DMA so that | |
605 | * faults will be handled correctly. | |
606 | */ | |
607 | if (c->channel_program(channel, | |
608 | musb_ep->packet_sz, | |
609 | !request->short_not_ok, | |
610 | request->dma + request->actual, | |
611 | request->length - request->actual)) { | |
612 | ||
613 | /* make sure that if an rxpkt arrived after the irq, | |
614 | * the cppi engine will be ready to take it as soon | |
615 | * as DMA is enabled | |
616 | */ | |
617 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
618 | | MUSB_RXCSR_DMAMODE); | |
619 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; | |
620 | musb_writew(epio, MUSB_RXCSR, csr); | |
621 | return; | |
622 | } | |
623 | } | |
624 | ||
625 | if (csr & MUSB_RXCSR_RXPKTRDY) { | |
f0443afd | 626 | fifo_count = musb_readw(epio, MUSB_RXCOUNT); |
0ae52d54 AG |
627 | |
628 | /* | |
00a89180 FB |
629 | * Enable Mode 1 on RX transfers only when short_not_ok flag |
630 | * is set. Currently short_not_ok flag is set only from | |
631 | * file_storage and f_mass_storage drivers | |
0ae52d54 | 632 | */ |
00a89180 FB |
633 | |
634 | if (request->short_not_ok && fifo_count == musb_ep->packet_sz) | |
0ae52d54 AG |
635 | use_mode_1 = 1; |
636 | else | |
637 | use_mode_1 = 0; | |
638 | ||
550a7375 FB |
639 | if (request->actual < request->length) { |
640 | #ifdef CONFIG_USB_INVENTRA_DMA | |
c65bfa62 | 641 | if (is_buffer_mapped(req)) { |
550a7375 FB |
642 | struct dma_controller *c; |
643 | struct dma_channel *channel; | |
644 | int use_dma = 0; | |
37730ecc | 645 | unsigned int transfer_size; |
550a7375 FB |
646 | |
647 | c = musb->dma_controller; | |
648 | channel = musb_ep->dma; | |
649 | ||
00a89180 FB |
650 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in |
651 | * mode 0 only. So we do not get endpoint interrupts due to DMA | |
652 | * completion. We only get interrupts from DMA controller. | |
653 | * | |
654 | * We could operate in DMA mode 1 if we knew the size of the tranfer | |
655 | * in advance. For mass storage class, request->length = what the host | |
656 | * sends, so that'd work. But for pretty much everything else, | |
657 | * request->length is routinely more than what the host sends. For | |
658 | * most these gadgets, end of is signified either by a short packet, | |
659 | * or filling the last byte of the buffer. (Sending extra data in | |
660 | * that last pckate should trigger an overflow fault.) But in mode 1, | |
661 | * we don't get DMA completion interrupt for short packets. | |
662 | * | |
663 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), | |
664 | * to get endpoint interrupt on every DMA req, but that didn't seem | |
665 | * to work reliably. | |
666 | * | |
667 | * REVISIT an updated g_file_storage can set req->short_not_ok, which | |
668 | * then becomes usable as a runtime "use mode 1" hint... | |
669 | */ | |
670 | ||
0ae52d54 AG |
671 | /* Experimental: Mode1 works with mass storage use cases */ |
672 | if (use_mode_1) { | |
9001d80d | 673 | csr |= MUSB_RXCSR_AUTOCLEAR; |
0ae52d54 AG |
674 | musb_writew(epio, MUSB_RXCSR, csr); |
675 | csr |= MUSB_RXCSR_DMAENAB; | |
676 | musb_writew(epio, MUSB_RXCSR, csr); | |
677 | ||
678 | /* | |
679 | * this special sequence (enabling and then | |
680 | * disabling MUSB_RXCSR_DMAMODE) is required | |
681 | * to get DMAReq to activate | |
682 | */ | |
683 | musb_writew(epio, MUSB_RXCSR, | |
684 | csr | MUSB_RXCSR_DMAMODE); | |
685 | musb_writew(epio, MUSB_RXCSR, csr); | |
686 | ||
37730ecc FB |
687 | transfer_size = min_t(unsigned int, |
688 | request->length - | |
689 | request->actual, | |
660fa886 RQ |
690 | channel->max_len); |
691 | musb_ep->dma->desired_mode = 1; | |
0ae52d54 AG |
692 | } else { |
693 | if (!musb_ep->hb_mult && | |
694 | musb_ep->hw_ep->rx_double_buffered) | |
695 | csr |= MUSB_RXCSR_AUTOCLEAR; | |
696 | csr |= MUSB_RXCSR_DMAENAB; | |
697 | musb_writew(epio, MUSB_RXCSR, csr); | |
550a7375 | 698 | |
660fa886 | 699 | transfer_size = min(request->length - request->actual, |
f0443afd | 700 | (unsigned)fifo_count); |
660fa886 | 701 | musb_ep->dma->desired_mode = 0; |
550a7375 FB |
702 | } |
703 | ||
660fa886 RQ |
704 | use_dma = c->channel_program( |
705 | channel, | |
706 | musb_ep->packet_sz, | |
707 | channel->desired_mode, | |
708 | request->dma | |
709 | + request->actual, | |
710 | transfer_size); | |
711 | ||
550a7375 | 712 | if (use_dma) |
a48ff906 MYK |
713 | return; |
714 | } | |
715 | #elif defined(CONFIG_USB_UX500_DMA) | |
716 | if ((is_buffer_mapped(req)) && | |
717 | (request->actual < request->length)) { | |
718 | ||
719 | struct dma_controller *c; | |
720 | struct dma_channel *channel; | |
37730ecc | 721 | unsigned int transfer_size = 0; |
a48ff906 MYK |
722 | |
723 | c = musb->dma_controller; | |
724 | channel = musb_ep->dma; | |
725 | ||
726 | /* In case first packet is short */ | |
f0443afd SS |
727 | if (fifo_count < musb_ep->packet_sz) |
728 | transfer_size = fifo_count; | |
a48ff906 | 729 | else if (request->short_not_ok) |
37730ecc FB |
730 | transfer_size = min_t(unsigned int, |
731 | request->length - | |
a48ff906 MYK |
732 | request->actual, |
733 | channel->max_len); | |
734 | else | |
37730ecc FB |
735 | transfer_size = min_t(unsigned int, |
736 | request->length - | |
a48ff906 | 737 | request->actual, |
f0443afd | 738 | (unsigned)fifo_count); |
a48ff906 MYK |
739 | |
740 | csr &= ~MUSB_RXCSR_DMAMODE; | |
741 | csr |= (MUSB_RXCSR_DMAENAB | | |
742 | MUSB_RXCSR_AUTOCLEAR); | |
743 | ||
744 | musb_writew(epio, MUSB_RXCSR, csr); | |
745 | ||
746 | if (transfer_size <= musb_ep->packet_sz) { | |
747 | musb_ep->dma->desired_mode = 0; | |
748 | } else { | |
749 | musb_ep->dma->desired_mode = 1; | |
750 | /* Mode must be set after DMAENAB */ | |
751 | csr |= MUSB_RXCSR_DMAMODE; | |
752 | musb_writew(epio, MUSB_RXCSR, csr); | |
753 | } | |
754 | ||
755 | if (c->channel_program(channel, | |
756 | musb_ep->packet_sz, | |
757 | channel->desired_mode, | |
758 | request->dma | |
759 | + request->actual, | |
760 | transfer_size)) | |
761 | ||
550a7375 FB |
762 | return; |
763 | } | |
764 | #endif /* Mentor's DMA */ | |
765 | ||
f0443afd | 766 | len = request->length - request->actual; |
5c8a86e1 | 767 | dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", |
550a7375 | 768 | musb_ep->end_point.name, |
f0443afd | 769 | fifo_count, len, |
550a7375 FB |
770 | musb_ep->packet_sz); |
771 | ||
c2c96321 | 772 | fifo_count = min_t(unsigned, len, fifo_count); |
550a7375 FB |
773 | |
774 | #ifdef CONFIG_USB_TUSB_OMAP_DMA | |
c65bfa62 | 775 | if (tusb_dma_omap() && is_buffer_mapped(req)) { |
550a7375 FB |
776 | struct dma_controller *c = musb->dma_controller; |
777 | struct dma_channel *channel = musb_ep->dma; | |
778 | u32 dma_addr = request->dma + request->actual; | |
779 | int ret; | |
780 | ||
781 | ret = c->channel_program(channel, | |
782 | musb_ep->packet_sz, | |
783 | channel->desired_mode, | |
784 | dma_addr, | |
785 | fifo_count); | |
786 | if (ret) | |
787 | return; | |
788 | } | |
789 | #endif | |
92d2711f HK |
790 | /* |
791 | * Unmap the dma buffer back to cpu if dma channel | |
792 | * programming fails. This buffer is mapped if the | |
793 | * channel allocation is successful | |
794 | */ | |
c65bfa62 | 795 | if (is_buffer_mapped(req)) { |
92d2711f HK |
796 | unmap_dma_buffer(req, musb); |
797 | ||
e75df371 ML |
798 | /* |
799 | * Clear DMAENAB and AUTOCLEAR for the | |
92d2711f HK |
800 | * PIO mode transfer |
801 | */ | |
e75df371 | 802 | csr &= ~(MUSB_RXCSR_DMAENAB | MUSB_RXCSR_AUTOCLEAR); |
92d2711f HK |
803 | musb_writew(epio, MUSB_RXCSR, csr); |
804 | } | |
550a7375 FB |
805 | |
806 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) | |
807 | (request->buf + request->actual)); | |
808 | request->actual += fifo_count; | |
809 | ||
810 | /* REVISIT if we left anything in the fifo, flush | |
811 | * it and report -EOVERFLOW | |
812 | */ | |
813 | ||
814 | /* ack the read! */ | |
815 | csr |= MUSB_RXCSR_P_WZC_BITS; | |
816 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
817 | musb_writew(epio, MUSB_RXCSR, csr); | |
818 | } | |
819 | } | |
820 | ||
821 | /* reach the end or short packet detected */ | |
f0443afd SS |
822 | if (request->actual == request->length || |
823 | fifo_count < musb_ep->packet_sz) | |
550a7375 FB |
824 | musb_g_giveback(musb_ep, request, 0); |
825 | } | |
826 | ||
827 | /* | |
828 | * Data ready for a request; called from IRQ | |
829 | */ | |
830 | void musb_g_rx(struct musb *musb, u8 epnum) | |
831 | { | |
832 | u16 csr; | |
ad1adb89 | 833 | struct musb_request *req; |
550a7375 FB |
834 | struct usb_request *request; |
835 | void __iomem *mbase = musb->mregs; | |
bd2e74d6 | 836 | struct musb_ep *musb_ep; |
550a7375 FB |
837 | void __iomem *epio = musb->endpoints[epnum].regs; |
838 | struct dma_channel *dma; | |
bd2e74d6 ML |
839 | struct musb_hw_ep *hw_ep = &musb->endpoints[epnum]; |
840 | ||
841 | if (hw_ep->is_shared_fifo) | |
842 | musb_ep = &hw_ep->ep_in; | |
843 | else | |
844 | musb_ep = &hw_ep->ep_out; | |
550a7375 FB |
845 | |
846 | musb_ep_select(mbase, epnum); | |
847 | ||
ad1adb89 FB |
848 | req = next_request(musb_ep); |
849 | if (!req) | |
0abdc36f | 850 | return; |
550a7375 | 851 | |
ad1adb89 FB |
852 | request = &req->request; |
853 | ||
550a7375 FB |
854 | csr = musb_readw(epio, MUSB_RXCSR); |
855 | dma = is_dma_capable() ? musb_ep->dma : NULL; | |
856 | ||
5c8a86e1 | 857 | dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, |
550a7375 FB |
858 | csr, dma ? " (dma)" : "", request); |
859 | ||
860 | if (csr & MUSB_RXCSR_P_SENTSTALL) { | |
550a7375 FB |
861 | csr |= MUSB_RXCSR_P_WZC_BITS; |
862 | csr &= ~MUSB_RXCSR_P_SENTSTALL; | |
863 | musb_writew(epio, MUSB_RXCSR, csr); | |
cea83241 | 864 | return; |
550a7375 FB |
865 | } |
866 | ||
867 | if (csr & MUSB_RXCSR_P_OVERRUN) { | |
868 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ | |
869 | csr &= ~MUSB_RXCSR_P_OVERRUN; | |
870 | musb_writew(epio, MUSB_RXCSR, csr); | |
871 | ||
5c8a86e1 | 872 | dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request); |
43467868 | 873 | if (request->status == -EINPROGRESS) |
550a7375 FB |
874 | request->status = -EOVERFLOW; |
875 | } | |
876 | if (csr & MUSB_RXCSR_INCOMPRX) { | |
877 | /* REVISIT not necessarily an error */ | |
5c8a86e1 | 878 | dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name); |
550a7375 FB |
879 | } |
880 | ||
881 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { | |
882 | /* "should not happen"; likely RXPKTRDY pending for DMA */ | |
5c8a86e1 | 883 | dev_dbg(musb->controller, "%s busy, csr %04x\n", |
550a7375 | 884 | musb_ep->end_point.name, csr); |
cea83241 | 885 | return; |
550a7375 FB |
886 | } |
887 | ||
888 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { | |
889 | csr &= ~(MUSB_RXCSR_AUTOCLEAR | |
890 | | MUSB_RXCSR_DMAENAB | |
891 | | MUSB_RXCSR_DMAMODE); | |
892 | musb_writew(epio, MUSB_RXCSR, | |
893 | MUSB_RXCSR_P_WZC_BITS | csr); | |
894 | ||
895 | request->actual += musb_ep->dma->actual_len; | |
896 | ||
5c8a86e1 | 897 | dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", |
550a7375 FB |
898 | epnum, csr, |
899 | musb_readw(epio, MUSB_RXCSR), | |
900 | musb_ep->dma->actual_len, request); | |
901 | ||
a48ff906 MYK |
902 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
903 | defined(CONFIG_USB_UX500_DMA) | |
550a7375 | 904 | /* Autoclear doesn't clear RxPktRdy for short packets */ |
9001d80d | 905 | if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered) |
550a7375 FB |
906 | || (dma->actual_len |
907 | & (musb_ep->packet_sz - 1))) { | |
908 | /* ack the read! */ | |
909 | csr &= ~MUSB_RXCSR_RXPKTRDY; | |
910 | musb_writew(epio, MUSB_RXCSR, csr); | |
911 | } | |
912 | ||
913 | /* incomplete, and not short? wait for next IN packet */ | |
914 | if ((request->actual < request->length) | |
915 | && (musb_ep->dma->actual_len | |
9001d80d ML |
916 | == musb_ep->packet_sz)) { |
917 | /* In double buffer case, continue to unload fifo if | |
918 | * there is Rx packet in FIFO. | |
919 | **/ | |
920 | csr = musb_readw(epio, MUSB_RXCSR); | |
921 | if ((csr & MUSB_RXCSR_RXPKTRDY) && | |
922 | hw_ep->rx_double_buffered) | |
923 | goto exit; | |
cea83241 | 924 | return; |
9001d80d | 925 | } |
550a7375 FB |
926 | #endif |
927 | musb_g_giveback(musb_ep, request, 0); | |
39287076 SK |
928 | /* |
929 | * In the giveback function the MUSB lock is | |
930 | * released and acquired after sometime. During | |
931 | * this time period the INDEX register could get | |
932 | * changed by the gadget_queue function especially | |
933 | * on SMP systems. Reselect the INDEX to be sure | |
934 | * we are reading/modifying the right registers | |
935 | */ | |
936 | musb_ep_select(mbase, epnum); | |
550a7375 | 937 | |
ad1adb89 FB |
938 | req = next_request(musb_ep); |
939 | if (!req) | |
cea83241 | 940 | return; |
550a7375 | 941 | } |
a48ff906 MYK |
942 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \ |
943 | defined(CONFIG_USB_UX500_DMA) | |
9001d80d | 944 | exit: |
bb324b08 | 945 | #endif |
43467868 | 946 | /* Analyze request */ |
ad1adb89 | 947 | rxstate(musb, req); |
550a7375 FB |
948 | } |
949 | ||
950 | /* ------------------------------------------------------------ */ | |
951 | ||
952 | static int musb_gadget_enable(struct usb_ep *ep, | |
953 | const struct usb_endpoint_descriptor *desc) | |
954 | { | |
955 | unsigned long flags; | |
956 | struct musb_ep *musb_ep; | |
957 | struct musb_hw_ep *hw_ep; | |
958 | void __iomem *regs; | |
959 | struct musb *musb; | |
960 | void __iomem *mbase; | |
961 | u8 epnum; | |
962 | u16 csr; | |
963 | unsigned tmp; | |
964 | int status = -EINVAL; | |
965 | ||
966 | if (!ep || !desc) | |
967 | return -EINVAL; | |
968 | ||
969 | musb_ep = to_musb_ep(ep); | |
970 | hw_ep = musb_ep->hw_ep; | |
971 | regs = hw_ep->regs; | |
972 | musb = musb_ep->musb; | |
973 | mbase = musb->mregs; | |
974 | epnum = musb_ep->current_epnum; | |
975 | ||
976 | spin_lock_irqsave(&musb->lock, flags); | |
977 | ||
978 | if (musb_ep->desc) { | |
979 | status = -EBUSY; | |
980 | goto fail; | |
981 | } | |
96bcd090 | 982 | musb_ep->type = usb_endpoint_type(desc); |
550a7375 FB |
983 | |
984 | /* check direction and (later) maxpacket size against endpoint */ | |
96bcd090 | 985 | if (usb_endpoint_num(desc) != epnum) |
550a7375 FB |
986 | goto fail; |
987 | ||
988 | /* REVISIT this rules out high bandwidth periodic transfers */ | |
29cc8897 | 989 | tmp = usb_endpoint_maxp(desc); |
f11d893d ML |
990 | if (tmp & ~0x07ff) { |
991 | int ok; | |
992 | ||
993 | if (usb_endpoint_dir_in(desc)) | |
994 | ok = musb->hb_iso_tx; | |
995 | else | |
996 | ok = musb->hb_iso_rx; | |
997 | ||
998 | if (!ok) { | |
5c8a86e1 | 999 | dev_dbg(musb->controller, "no support for high bandwidth ISO\n"); |
f11d893d ML |
1000 | goto fail; |
1001 | } | |
1002 | musb_ep->hb_mult = (tmp >> 11) & 3; | |
1003 | } else { | |
1004 | musb_ep->hb_mult = 0; | |
1005 | } | |
1006 | ||
1007 | musb_ep->packet_sz = tmp & 0x7ff; | |
1008 | tmp = musb_ep->packet_sz * (musb_ep->hb_mult + 1); | |
550a7375 FB |
1009 | |
1010 | /* enable the interrupts for the endpoint, set the endpoint | |
1011 | * packet size (or fail), set the mode, clear the fifo | |
1012 | */ | |
1013 | musb_ep_select(mbase, epnum); | |
96bcd090 | 1014 | if (usb_endpoint_dir_in(desc)) { |
550a7375 FB |
1015 | |
1016 | if (hw_ep->is_shared_fifo) | |
1017 | musb_ep->is_in = 1; | |
1018 | if (!musb_ep->is_in) | |
1019 | goto fail; | |
f11d893d ML |
1020 | |
1021 | if (tmp > hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1022 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1023 | goto fail; |
f11d893d | 1024 | } |
550a7375 | 1025 | |
b18d26f6 SAS |
1026 | musb->intrtxe |= (1 << epnum); |
1027 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); | |
550a7375 FB |
1028 | |
1029 | /* REVISIT if can_bulk_split(), use by updating "tmp"; | |
1030 | * likewise high bandwidth periodic tx | |
1031 | */ | |
9f445cb2 | 1032 | /* Set TXMAXP with the FIFO size of the endpoint |
31c9909b | 1033 | * to disable double buffering mode. |
9f445cb2 | 1034 | */ |
bb3a2ef2 | 1035 | if (musb->double_buffer_not_ok) { |
06624818 | 1036 | musb_writew(regs, MUSB_TXMAXP, hw_ep->max_packet_sz_tx); |
bb3a2ef2 | 1037 | } else { |
1038 | if (can_bulk_split(musb, musb_ep->type)) | |
1039 | musb_ep->hb_mult = (hw_ep->max_packet_sz_tx / | |
1040 | musb_ep->packet_sz) - 1; | |
06624818 FB |
1041 | musb_writew(regs, MUSB_TXMAXP, musb_ep->packet_sz |
1042 | | (musb_ep->hb_mult << 11)); | |
bb3a2ef2 | 1043 | } |
550a7375 FB |
1044 | |
1045 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; | |
1046 | if (musb_readw(regs, MUSB_TXCSR) | |
1047 | & MUSB_TXCSR_FIFONOTEMPTY) | |
1048 | csr |= MUSB_TXCSR_FLUSHFIFO; | |
1049 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1050 | csr |= MUSB_TXCSR_P_ISO; | |
1051 | ||
1052 | /* set twice in case of double buffering */ | |
1053 | musb_writew(regs, MUSB_TXCSR, csr); | |
1054 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1055 | musb_writew(regs, MUSB_TXCSR, csr); | |
1056 | ||
1057 | } else { | |
550a7375 FB |
1058 | |
1059 | if (hw_ep->is_shared_fifo) | |
1060 | musb_ep->is_in = 0; | |
1061 | if (musb_ep->is_in) | |
1062 | goto fail; | |
f11d893d ML |
1063 | |
1064 | if (tmp > hw_ep->max_packet_sz_rx) { | |
5c8a86e1 | 1065 | dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n"); |
550a7375 | 1066 | goto fail; |
f11d893d | 1067 | } |
550a7375 | 1068 | |
af5ec14d SAS |
1069 | musb->intrrxe |= (1 << epnum); |
1070 | musb_writew(mbase, MUSB_INTRRXE, musb->intrrxe); | |
550a7375 FB |
1071 | |
1072 | /* REVISIT if can_bulk_combine() use by updating "tmp" | |
1073 | * likewise high bandwidth periodic rx | |
1074 | */ | |
9f445cb2 CC |
1075 | /* Set RXMAXP with the FIFO size of the endpoint |
1076 | * to disable double buffering mode. | |
1077 | */ | |
06624818 FB |
1078 | if (musb->double_buffer_not_ok) |
1079 | musb_writew(regs, MUSB_RXMAXP, hw_ep->max_packet_sz_tx); | |
1080 | else | |
1081 | musb_writew(regs, MUSB_RXMAXP, musb_ep->packet_sz | |
1082 | | (musb_ep->hb_mult << 11)); | |
550a7375 FB |
1083 | |
1084 | /* force shared fifo to OUT-only mode */ | |
1085 | if (hw_ep->is_shared_fifo) { | |
1086 | csr = musb_readw(regs, MUSB_TXCSR); | |
1087 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); | |
1088 | musb_writew(regs, MUSB_TXCSR, csr); | |
1089 | } | |
1090 | ||
1091 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; | |
1092 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) | |
1093 | csr |= MUSB_RXCSR_P_ISO; | |
1094 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) | |
1095 | csr |= MUSB_RXCSR_DISNYET; | |
1096 | ||
1097 | /* set twice in case of double buffering */ | |
1098 | musb_writew(regs, MUSB_RXCSR, csr); | |
1099 | musb_writew(regs, MUSB_RXCSR, csr); | |
1100 | } | |
1101 | ||
1102 | /* NOTE: all the I/O code _should_ work fine without DMA, in case | |
1103 | * for some reason you run out of channels here. | |
1104 | */ | |
1105 | if (is_dma_capable() && musb->dma_controller) { | |
1106 | struct dma_controller *c = musb->dma_controller; | |
1107 | ||
1108 | musb_ep->dma = c->channel_alloc(c, hw_ep, | |
1109 | (desc->bEndpointAddress & USB_DIR_IN)); | |
1110 | } else | |
1111 | musb_ep->dma = NULL; | |
1112 | ||
1113 | musb_ep->desc = desc; | |
1114 | musb_ep->busy = 0; | |
47e97605 | 1115 | musb_ep->wedged = 0; |
550a7375 FB |
1116 | status = 0; |
1117 | ||
1118 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", | |
1119 | musb_driver_name, musb_ep->end_point.name, | |
1120 | ({ char *s; switch (musb_ep->type) { | |
1121 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; | |
1122 | case USB_ENDPOINT_XFER_INT: s = "int"; break; | |
1123 | default: s = "iso"; break; | |
2b84f92b | 1124 | } s; }), |
550a7375 FB |
1125 | musb_ep->is_in ? "IN" : "OUT", |
1126 | musb_ep->dma ? "dma, " : "", | |
1127 | musb_ep->packet_sz); | |
1128 | ||
1129 | schedule_work(&musb->irq_work); | |
1130 | ||
1131 | fail: | |
1132 | spin_unlock_irqrestore(&musb->lock, flags); | |
1133 | return status; | |
1134 | } | |
1135 | ||
1136 | /* | |
1137 | * Disable an endpoint flushing all requests queued. | |
1138 | */ | |
1139 | static int musb_gadget_disable(struct usb_ep *ep) | |
1140 | { | |
1141 | unsigned long flags; | |
1142 | struct musb *musb; | |
1143 | u8 epnum; | |
1144 | struct musb_ep *musb_ep; | |
1145 | void __iomem *epio; | |
1146 | int status = 0; | |
1147 | ||
1148 | musb_ep = to_musb_ep(ep); | |
1149 | musb = musb_ep->musb; | |
1150 | epnum = musb_ep->current_epnum; | |
1151 | epio = musb->endpoints[epnum].regs; | |
1152 | ||
1153 | spin_lock_irqsave(&musb->lock, flags); | |
1154 | musb_ep_select(musb->mregs, epnum); | |
1155 | ||
1156 | /* zero the endpoint sizes */ | |
1157 | if (musb_ep->is_in) { | |
b18d26f6 SAS |
1158 | musb->intrtxe &= ~(1 << epnum); |
1159 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
550a7375 FB |
1160 | musb_writew(epio, MUSB_TXMAXP, 0); |
1161 | } else { | |
af5ec14d SAS |
1162 | musb->intrrxe &= ~(1 << epnum); |
1163 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
550a7375 FB |
1164 | musb_writew(epio, MUSB_RXMAXP, 0); |
1165 | } | |
1166 | ||
1167 | musb_ep->desc = NULL; | |
08f75bf1 | 1168 | musb_ep->end_point.desc = NULL; |
550a7375 FB |
1169 | |
1170 | /* abort all pending DMA and requests */ | |
1171 | nuke(musb_ep, -ESHUTDOWN); | |
1172 | ||
1173 | schedule_work(&musb->irq_work); | |
1174 | ||
1175 | spin_unlock_irqrestore(&(musb->lock), flags); | |
1176 | ||
5c8a86e1 | 1177 | dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name); |
550a7375 FB |
1178 | |
1179 | return status; | |
1180 | } | |
1181 | ||
1182 | /* | |
1183 | * Allocate a request for an endpoint. | |
1184 | * Reused by ep0 code. | |
1185 | */ | |
1186 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) | |
1187 | { | |
1188 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
5c8a86e1 | 1189 | struct musb *musb = musb_ep->musb; |
550a7375 FB |
1190 | struct musb_request *request = NULL; |
1191 | ||
1192 | request = kzalloc(sizeof *request, gfp_flags); | |
0607f862 | 1193 | if (!request) { |
5c8a86e1 | 1194 | dev_dbg(musb->controller, "not enough memory\n"); |
0607f862 | 1195 | return NULL; |
550a7375 FB |
1196 | } |
1197 | ||
0607f862 FB |
1198 | request->request.dma = DMA_ADDR_INVALID; |
1199 | request->epnum = musb_ep->current_epnum; | |
1200 | request->ep = musb_ep; | |
1201 | ||
550a7375 FB |
1202 | return &request->request; |
1203 | } | |
1204 | ||
1205 | /* | |
1206 | * Free a request | |
1207 | * Reused by ep0 code. | |
1208 | */ | |
1209 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) | |
1210 | { | |
1211 | kfree(to_musb_request(req)); | |
1212 | } | |
1213 | ||
1214 | static LIST_HEAD(buffers); | |
1215 | ||
1216 | struct free_record { | |
1217 | struct list_head list; | |
1218 | struct device *dev; | |
1219 | unsigned bytes; | |
1220 | dma_addr_t dma; | |
1221 | }; | |
1222 | ||
1223 | /* | |
1224 | * Context: controller locked, IRQs blocked. | |
1225 | */ | |
a666e3e6 | 1226 | void musb_ep_restart(struct musb *musb, struct musb_request *req) |
550a7375 | 1227 | { |
5c8a86e1 | 1228 | dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n", |
550a7375 FB |
1229 | req->tx ? "TX/IN" : "RX/OUT", |
1230 | &req->request, req->request.length, req->epnum); | |
1231 | ||
1232 | musb_ep_select(musb->mregs, req->epnum); | |
1233 | if (req->tx) | |
1234 | txstate(musb, req); | |
1235 | else | |
1236 | rxstate(musb, req); | |
1237 | } | |
1238 | ||
1239 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, | |
1240 | gfp_t gfp_flags) | |
1241 | { | |
1242 | struct musb_ep *musb_ep; | |
1243 | struct musb_request *request; | |
1244 | struct musb *musb; | |
1245 | int status = 0; | |
1246 | unsigned long lockflags; | |
1247 | ||
1248 | if (!ep || !req) | |
1249 | return -EINVAL; | |
1250 | if (!req->buf) | |
1251 | return -ENODATA; | |
1252 | ||
1253 | musb_ep = to_musb_ep(ep); | |
1254 | musb = musb_ep->musb; | |
1255 | ||
1256 | request = to_musb_request(req); | |
1257 | request->musb = musb; | |
1258 | ||
1259 | if (request->ep != musb_ep) | |
1260 | return -EINVAL; | |
1261 | ||
5c8a86e1 | 1262 | dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req); |
550a7375 FB |
1263 | |
1264 | /* request is mine now... */ | |
1265 | request->request.actual = 0; | |
1266 | request->request.status = -EINPROGRESS; | |
1267 | request->epnum = musb_ep->current_epnum; | |
1268 | request->tx = musb_ep->is_in; | |
1269 | ||
c65bfa62 | 1270 | map_dma_buffer(request, musb, musb_ep); |
550a7375 FB |
1271 | |
1272 | spin_lock_irqsave(&musb->lock, lockflags); | |
1273 | ||
1274 | /* don't queue if the ep is down */ | |
1275 | if (!musb_ep->desc) { | |
5c8a86e1 | 1276 | dev_dbg(musb->controller, "req %p queued to %s while ep %s\n", |
550a7375 FB |
1277 | req, ep->name, "disabled"); |
1278 | status = -ESHUTDOWN; | |
23a53d90 SAS |
1279 | unmap_dma_buffer(request, musb); |
1280 | goto unlock; | |
550a7375 FB |
1281 | } |
1282 | ||
1283 | /* add request to the list */ | |
ad1adb89 | 1284 | list_add_tail(&request->list, &musb_ep->req_list); |
550a7375 FB |
1285 | |
1286 | /* it this is the head of the queue, start i/o ... */ | |
ad1adb89 | 1287 | if (!musb_ep->busy && &request->list == musb_ep->req_list.next) |
550a7375 FB |
1288 | musb_ep_restart(musb, request); |
1289 | ||
23a53d90 | 1290 | unlock: |
550a7375 FB |
1291 | spin_unlock_irqrestore(&musb->lock, lockflags); |
1292 | return status; | |
1293 | } | |
1294 | ||
1295 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) | |
1296 | { | |
1297 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
4cbbf084 FB |
1298 | struct musb_request *req = to_musb_request(request); |
1299 | struct musb_request *r; | |
550a7375 FB |
1300 | unsigned long flags; |
1301 | int status = 0; | |
1302 | struct musb *musb = musb_ep->musb; | |
1303 | ||
1304 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) | |
1305 | return -EINVAL; | |
1306 | ||
1307 | spin_lock_irqsave(&musb->lock, flags); | |
1308 | ||
1309 | list_for_each_entry(r, &musb_ep->req_list, list) { | |
4cbbf084 | 1310 | if (r == req) |
550a7375 FB |
1311 | break; |
1312 | } | |
4cbbf084 | 1313 | if (r != req) { |
5c8a86e1 | 1314 | dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name); |
550a7375 FB |
1315 | status = -EINVAL; |
1316 | goto done; | |
1317 | } | |
1318 | ||
1319 | /* if the hardware doesn't have the request, easy ... */ | |
3d5ad13e | 1320 | if (musb_ep->req_list.next != &req->list || musb_ep->busy) |
550a7375 FB |
1321 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
1322 | ||
1323 | /* ... else abort the dma transfer ... */ | |
1324 | else if (is_dma_capable() && musb_ep->dma) { | |
1325 | struct dma_controller *c = musb->dma_controller; | |
1326 | ||
1327 | musb_ep_select(musb->mregs, musb_ep->current_epnum); | |
1328 | if (c->channel_abort) | |
1329 | status = c->channel_abort(musb_ep->dma); | |
1330 | else | |
1331 | status = -EBUSY; | |
1332 | if (status == 0) | |
1333 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1334 | } else { | |
1335 | /* NOTE: by sticking to easily tested hardware/driver states, | |
1336 | * we leave counting of in-flight packets imprecise. | |
1337 | */ | |
1338 | musb_g_giveback(musb_ep, request, -ECONNRESET); | |
1339 | } | |
1340 | ||
1341 | done: | |
1342 | spin_unlock_irqrestore(&musb->lock, flags); | |
1343 | return status; | |
1344 | } | |
1345 | ||
1346 | /* | |
1347 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any | |
1348 | * data but will queue requests. | |
1349 | * | |
1350 | * exported to ep0 code | |
1351 | */ | |
1b6c3b0f | 1352 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
550a7375 FB |
1353 | { |
1354 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1355 | u8 epnum = musb_ep->current_epnum; | |
1356 | struct musb *musb = musb_ep->musb; | |
1357 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1358 | void __iomem *mbase; | |
1359 | unsigned long flags; | |
1360 | u16 csr; | |
cea83241 | 1361 | struct musb_request *request; |
550a7375 FB |
1362 | int status = 0; |
1363 | ||
1364 | if (!ep) | |
1365 | return -EINVAL; | |
1366 | mbase = musb->mregs; | |
1367 | ||
1368 | spin_lock_irqsave(&musb->lock, flags); | |
1369 | ||
1370 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { | |
1371 | status = -EINVAL; | |
1372 | goto done; | |
1373 | } | |
1374 | ||
1375 | musb_ep_select(mbase, epnum); | |
1376 | ||
ad1adb89 | 1377 | request = next_request(musb_ep); |
cea83241 SS |
1378 | if (value) { |
1379 | if (request) { | |
5c8a86e1 | 1380 | dev_dbg(musb->controller, "request in progress, cannot halt %s\n", |
cea83241 SS |
1381 | ep->name); |
1382 | status = -EAGAIN; | |
1383 | goto done; | |
1384 | } | |
1385 | /* Cannot portably stall with non-empty FIFO */ | |
1386 | if (musb_ep->is_in) { | |
1387 | csr = musb_readw(epio, MUSB_TXCSR); | |
1388 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
5c8a86e1 | 1389 | dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name); |
cea83241 SS |
1390 | status = -EAGAIN; |
1391 | goto done; | |
1392 | } | |
550a7375 | 1393 | } |
47e97605 SS |
1394 | } else |
1395 | musb_ep->wedged = 0; | |
550a7375 FB |
1396 | |
1397 | /* set/clear the stall and toggle bits */ | |
5c8a86e1 | 1398 | dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear"); |
550a7375 FB |
1399 | if (musb_ep->is_in) { |
1400 | csr = musb_readw(epio, MUSB_TXCSR); | |
550a7375 FB |
1401 | csr |= MUSB_TXCSR_P_WZC_BITS |
1402 | | MUSB_TXCSR_CLRDATATOG; | |
1403 | if (value) | |
1404 | csr |= MUSB_TXCSR_P_SENDSTALL; | |
1405 | else | |
1406 | csr &= ~(MUSB_TXCSR_P_SENDSTALL | |
1407 | | MUSB_TXCSR_P_SENTSTALL); | |
1408 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
1409 | musb_writew(epio, MUSB_TXCSR, csr); | |
1410 | } else { | |
1411 | csr = musb_readw(epio, MUSB_RXCSR); | |
1412 | csr |= MUSB_RXCSR_P_WZC_BITS | |
1413 | | MUSB_RXCSR_FLUSHFIFO | |
1414 | | MUSB_RXCSR_CLRDATATOG; | |
1415 | if (value) | |
1416 | csr |= MUSB_RXCSR_P_SENDSTALL; | |
1417 | else | |
1418 | csr &= ~(MUSB_RXCSR_P_SENDSTALL | |
1419 | | MUSB_RXCSR_P_SENTSTALL); | |
1420 | musb_writew(epio, MUSB_RXCSR, csr); | |
1421 | } | |
1422 | ||
550a7375 FB |
1423 | /* maybe start the first request in the queue */ |
1424 | if (!musb_ep->busy && !value && request) { | |
5c8a86e1 | 1425 | dev_dbg(musb->controller, "restarting the request\n"); |
550a7375 FB |
1426 | musb_ep_restart(musb, request); |
1427 | } | |
1428 | ||
cea83241 | 1429 | done: |
550a7375 FB |
1430 | spin_unlock_irqrestore(&musb->lock, flags); |
1431 | return status; | |
1432 | } | |
1433 | ||
47e97605 SS |
1434 | /* |
1435 | * Sets the halt feature with the clear requests ignored | |
1436 | */ | |
1b6c3b0f | 1437 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
47e97605 SS |
1438 | { |
1439 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1440 | ||
1441 | if (!ep) | |
1442 | return -EINVAL; | |
1443 | ||
1444 | musb_ep->wedged = 1; | |
1445 | ||
1446 | return usb_ep_set_halt(ep); | |
1447 | } | |
1448 | ||
550a7375 FB |
1449 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
1450 | { | |
1451 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1452 | void __iomem *epio = musb_ep->hw_ep->regs; | |
1453 | int retval = -EINVAL; | |
1454 | ||
1455 | if (musb_ep->desc && !musb_ep->is_in) { | |
1456 | struct musb *musb = musb_ep->musb; | |
1457 | int epnum = musb_ep->current_epnum; | |
1458 | void __iomem *mbase = musb->mregs; | |
1459 | unsigned long flags; | |
1460 | ||
1461 | spin_lock_irqsave(&musb->lock, flags); | |
1462 | ||
1463 | musb_ep_select(mbase, epnum); | |
1464 | /* FIXME return zero unless RXPKTRDY is set */ | |
1465 | retval = musb_readw(epio, MUSB_RXCOUNT); | |
1466 | ||
1467 | spin_unlock_irqrestore(&musb->lock, flags); | |
1468 | } | |
1469 | return retval; | |
1470 | } | |
1471 | ||
1472 | static void musb_gadget_fifo_flush(struct usb_ep *ep) | |
1473 | { | |
1474 | struct musb_ep *musb_ep = to_musb_ep(ep); | |
1475 | struct musb *musb = musb_ep->musb; | |
1476 | u8 epnum = musb_ep->current_epnum; | |
1477 | void __iomem *epio = musb->endpoints[epnum].regs; | |
1478 | void __iomem *mbase; | |
1479 | unsigned long flags; | |
b18d26f6 | 1480 | u16 csr; |
550a7375 FB |
1481 | |
1482 | mbase = musb->mregs; | |
1483 | ||
1484 | spin_lock_irqsave(&musb->lock, flags); | |
1485 | musb_ep_select(mbase, (u8) epnum); | |
1486 | ||
1487 | /* disable interrupts */ | |
b18d26f6 | 1488 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe & ~(1 << epnum)); |
550a7375 FB |
1489 | |
1490 | if (musb_ep->is_in) { | |
1491 | csr = musb_readw(epio, MUSB_TXCSR); | |
1492 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { | |
1493 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; | |
4858f06e YK |
1494 | /* |
1495 | * Setting both TXPKTRDY and FLUSHFIFO makes controller | |
1496 | * to interrupt current FIFO loading, but not flushing | |
1497 | * the already loaded ones. | |
1498 | */ | |
1499 | csr &= ~MUSB_TXCSR_TXPKTRDY; | |
550a7375 FB |
1500 | musb_writew(epio, MUSB_TXCSR, csr); |
1501 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ | |
1502 | musb_writew(epio, MUSB_TXCSR, csr); | |
1503 | } | |
1504 | } else { | |
1505 | csr = musb_readw(epio, MUSB_RXCSR); | |
1506 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; | |
1507 | musb_writew(epio, MUSB_RXCSR, csr); | |
1508 | musb_writew(epio, MUSB_RXCSR, csr); | |
1509 | } | |
1510 | ||
1511 | /* re-enable interrupt */ | |
b18d26f6 | 1512 | musb_writew(mbase, MUSB_INTRTXE, musb->intrtxe); |
550a7375 FB |
1513 | spin_unlock_irqrestore(&musb->lock, flags); |
1514 | } | |
1515 | ||
1516 | static const struct usb_ep_ops musb_ep_ops = { | |
1517 | .enable = musb_gadget_enable, | |
1518 | .disable = musb_gadget_disable, | |
1519 | .alloc_request = musb_alloc_request, | |
1520 | .free_request = musb_free_request, | |
1521 | .queue = musb_gadget_queue, | |
1522 | .dequeue = musb_gadget_dequeue, | |
1523 | .set_halt = musb_gadget_set_halt, | |
47e97605 | 1524 | .set_wedge = musb_gadget_set_wedge, |
550a7375 FB |
1525 | .fifo_status = musb_gadget_fifo_status, |
1526 | .fifo_flush = musb_gadget_fifo_flush | |
1527 | }; | |
1528 | ||
1529 | /* ----------------------------------------------------------------------- */ | |
1530 | ||
1531 | static int musb_gadget_get_frame(struct usb_gadget *gadget) | |
1532 | { | |
1533 | struct musb *musb = gadget_to_musb(gadget); | |
1534 | ||
1535 | return (int)musb_readw(musb->mregs, MUSB_FRAME); | |
1536 | } | |
1537 | ||
1538 | static int musb_gadget_wakeup(struct usb_gadget *gadget) | |
1539 | { | |
1540 | struct musb *musb = gadget_to_musb(gadget); | |
1541 | void __iomem *mregs = musb->mregs; | |
1542 | unsigned long flags; | |
1543 | int status = -EINVAL; | |
1544 | u8 power, devctl; | |
1545 | int retries; | |
1546 | ||
1547 | spin_lock_irqsave(&musb->lock, flags); | |
1548 | ||
84e250ff | 1549 | switch (musb->xceiv->state) { |
550a7375 FB |
1550 | case OTG_STATE_B_PERIPHERAL: |
1551 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; | |
1552 | * that's part of the standard usb 1.1 state machine, and | |
1553 | * doesn't affect OTG transitions. | |
1554 | */ | |
1555 | if (musb->may_wakeup && musb->is_suspended) | |
1556 | break; | |
1557 | goto done; | |
1558 | case OTG_STATE_B_IDLE: | |
1559 | /* Start SRP ... OTG not required. */ | |
1560 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
5c8a86e1 | 1561 | dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl); |
550a7375 FB |
1562 | devctl |= MUSB_DEVCTL_SESSION; |
1563 | musb_writeb(mregs, MUSB_DEVCTL, devctl); | |
1564 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1565 | retries = 100; | |
1566 | while (!(devctl & MUSB_DEVCTL_SESSION)) { | |
1567 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1568 | if (retries-- < 1) | |
1569 | break; | |
1570 | } | |
1571 | retries = 10000; | |
1572 | while (devctl & MUSB_DEVCTL_SESSION) { | |
1573 | devctl = musb_readb(mregs, MUSB_DEVCTL); | |
1574 | if (retries-- < 1) | |
1575 | break; | |
1576 | } | |
1577 | ||
8620543e | 1578 | spin_unlock_irqrestore(&musb->lock, flags); |
6e13c650 | 1579 | otg_start_srp(musb->xceiv->otg); |
8620543e HH |
1580 | spin_lock_irqsave(&musb->lock, flags); |
1581 | ||
550a7375 FB |
1582 | /* Block idling for at least 1s */ |
1583 | musb_platform_try_idle(musb, | |
1584 | jiffies + msecs_to_jiffies(1 * HZ)); | |
1585 | ||
1586 | status = 0; | |
1587 | goto done; | |
1588 | default: | |
5c8a86e1 | 1589 | dev_dbg(musb->controller, "Unhandled wake: %s\n", |
42c0bf1c | 1590 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1591 | goto done; |
1592 | } | |
1593 | ||
1594 | status = 0; | |
1595 | ||
1596 | power = musb_readb(mregs, MUSB_POWER); | |
1597 | power |= MUSB_POWER_RESUME; | |
1598 | musb_writeb(mregs, MUSB_POWER, power); | |
5c8a86e1 | 1599 | dev_dbg(musb->controller, "issue wakeup\n"); |
550a7375 FB |
1600 | |
1601 | /* FIXME do this next chunk in a timer callback, no udelay */ | |
1602 | mdelay(2); | |
1603 | ||
1604 | power = musb_readb(mregs, MUSB_POWER); | |
1605 | power &= ~MUSB_POWER_RESUME; | |
1606 | musb_writeb(mregs, MUSB_POWER, power); | |
1607 | done: | |
1608 | spin_unlock_irqrestore(&musb->lock, flags); | |
1609 | return status; | |
1610 | } | |
1611 | ||
1612 | static int | |
1613 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) | |
1614 | { | |
1615 | struct musb *musb = gadget_to_musb(gadget); | |
1616 | ||
1617 | musb->is_self_powered = !!is_selfpowered; | |
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | static void musb_pullup(struct musb *musb, int is_on) | |
1622 | { | |
1623 | u8 power; | |
1624 | ||
1625 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1626 | if (is_on) | |
1627 | power |= MUSB_POWER_SOFTCONN; | |
1628 | else | |
1629 | power &= ~MUSB_POWER_SOFTCONN; | |
1630 | ||
1631 | /* FIXME if on, HdrcStart; if off, HdrcStop */ | |
1632 | ||
e71eb392 SAS |
1633 | dev_dbg(musb->controller, "gadget D+ pullup %s\n", |
1634 | is_on ? "on" : "off"); | |
550a7375 FB |
1635 | musb_writeb(musb->mregs, MUSB_POWER, power); |
1636 | } | |
1637 | ||
1638 | #if 0 | |
1639 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) | |
1640 | { | |
5c8a86e1 | 1641 | dev_dbg(musb->controller, "<= %s =>\n", __func__); |
550a7375 FB |
1642 | |
1643 | /* | |
1644 | * FIXME iff driver's softconnect flag is set (as it is during probe, | |
1645 | * though that can clear it), just musb_pullup(). | |
1646 | */ | |
1647 | ||
1648 | return -EINVAL; | |
1649 | } | |
1650 | #endif | |
1651 | ||
1652 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) | |
1653 | { | |
1654 | struct musb *musb = gadget_to_musb(gadget); | |
1655 | ||
84e250ff | 1656 | if (!musb->xceiv->set_power) |
550a7375 | 1657 | return -EOPNOTSUPP; |
b96d3b08 | 1658 | return usb_phy_set_power(musb->xceiv, mA); |
550a7375 FB |
1659 | } |
1660 | ||
1661 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) | |
1662 | { | |
1663 | struct musb *musb = gadget_to_musb(gadget); | |
1664 | unsigned long flags; | |
1665 | ||
1666 | is_on = !!is_on; | |
1667 | ||
93e098a8 JS |
1668 | pm_runtime_get_sync(musb->controller); |
1669 | ||
550a7375 FB |
1670 | /* NOTE: this assumes we are sensing vbus; we'd rather |
1671 | * not pullup unless the B-session is active. | |
1672 | */ | |
1673 | spin_lock_irqsave(&musb->lock, flags); | |
1674 | if (is_on != musb->softconnect) { | |
1675 | musb->softconnect = is_on; | |
1676 | musb_pullup(musb, is_on); | |
1677 | } | |
1678 | spin_unlock_irqrestore(&musb->lock, flags); | |
93e098a8 JS |
1679 | |
1680 | pm_runtime_put(musb->controller); | |
1681 | ||
550a7375 FB |
1682 | return 0; |
1683 | } | |
1684 | ||
e71eb392 SAS |
1685 | static int musb_gadget_start(struct usb_gadget *g, |
1686 | struct usb_gadget_driver *driver); | |
1687 | static int musb_gadget_stop(struct usb_gadget *g, | |
1688 | struct usb_gadget_driver *driver); | |
0f91349b | 1689 | |
550a7375 FB |
1690 | static const struct usb_gadget_ops musb_gadget_operations = { |
1691 | .get_frame = musb_gadget_get_frame, | |
1692 | .wakeup = musb_gadget_wakeup, | |
1693 | .set_selfpowered = musb_gadget_set_self_powered, | |
1694 | /* .vbus_session = musb_gadget_vbus_session, */ | |
1695 | .vbus_draw = musb_gadget_vbus_draw, | |
1696 | .pullup = musb_gadget_pullup, | |
e71eb392 SAS |
1697 | .udc_start = musb_gadget_start, |
1698 | .udc_stop = musb_gadget_stop, | |
550a7375 FB |
1699 | }; |
1700 | ||
1701 | /* ----------------------------------------------------------------------- */ | |
1702 | ||
1703 | /* Registration */ | |
1704 | ||
1705 | /* Only this registration code "knows" the rule (from USB standards) | |
1706 | * about there being only one external upstream port. It assumes | |
1707 | * all peripheral ports are external... | |
1708 | */ | |
550a7375 | 1709 | |
41ac7b3a | 1710 | static void |
550a7375 FB |
1711 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) |
1712 | { | |
1713 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; | |
1714 | ||
1715 | memset(ep, 0, sizeof *ep); | |
1716 | ||
1717 | ep->current_epnum = epnum; | |
1718 | ep->musb = musb; | |
1719 | ep->hw_ep = hw_ep; | |
1720 | ep->is_in = is_in; | |
1721 | ||
1722 | INIT_LIST_HEAD(&ep->req_list); | |
1723 | ||
1724 | sprintf(ep->name, "ep%d%s", epnum, | |
1725 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( | |
1726 | is_in ? "in" : "out")); | |
1727 | ep->end_point.name = ep->name; | |
1728 | INIT_LIST_HEAD(&ep->end_point.ep_list); | |
1729 | if (!epnum) { | |
e117e742 | 1730 | usb_ep_set_maxpacket_limit(&ep->end_point, 64); |
550a7375 FB |
1731 | ep->end_point.ops = &musb_g_ep0_ops; |
1732 | musb->g.ep0 = &ep->end_point; | |
1733 | } else { | |
1734 | if (is_in) | |
e117e742 | 1735 | usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_tx); |
550a7375 | 1736 | else |
e117e742 | 1737 | usb_ep_set_maxpacket_limit(&ep->end_point, hw_ep->max_packet_sz_rx); |
550a7375 FB |
1738 | ep->end_point.ops = &musb_ep_ops; |
1739 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); | |
1740 | } | |
1741 | } | |
1742 | ||
1743 | /* | |
1744 | * Initialize the endpoints exposed to peripheral drivers, with backlinks | |
1745 | * to the rest of the driver state. | |
1746 | */ | |
41ac7b3a | 1747 | static inline void musb_g_init_endpoints(struct musb *musb) |
550a7375 FB |
1748 | { |
1749 | u8 epnum; | |
1750 | struct musb_hw_ep *hw_ep; | |
1751 | unsigned count = 0; | |
1752 | ||
b595076a | 1753 | /* initialize endpoint list just once */ |
550a7375 FB |
1754 | INIT_LIST_HEAD(&(musb->g.ep_list)); |
1755 | ||
1756 | for (epnum = 0, hw_ep = musb->endpoints; | |
1757 | epnum < musb->nr_endpoints; | |
1758 | epnum++, hw_ep++) { | |
1759 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1760 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); | |
1761 | count++; | |
1762 | } else { | |
1763 | if (hw_ep->max_packet_sz_tx) { | |
1764 | init_peripheral_ep(musb, &hw_ep->ep_in, | |
1765 | epnum, 1); | |
1766 | count++; | |
1767 | } | |
1768 | if (hw_ep->max_packet_sz_rx) { | |
1769 | init_peripheral_ep(musb, &hw_ep->ep_out, | |
1770 | epnum, 0); | |
1771 | count++; | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | } | |
1776 | ||
1777 | /* called once during driver setup to initialize and link into | |
1778 | * the driver model; memory is zeroed. | |
1779 | */ | |
41ac7b3a | 1780 | int musb_gadget_setup(struct musb *musb) |
550a7375 FB |
1781 | { |
1782 | int status; | |
1783 | ||
1784 | /* REVISIT minor race: if (erroneously) setting up two | |
1785 | * musb peripherals at the same time, only the bus lock | |
1786 | * is probably held. | |
1787 | */ | |
550a7375 FB |
1788 | |
1789 | musb->g.ops = &musb_gadget_operations; | |
d327ab5b | 1790 | musb->g.max_speed = USB_SPEED_HIGH; |
550a7375 FB |
1791 | musb->g.speed = USB_SPEED_UNKNOWN; |
1792 | ||
1374a430 BL |
1793 | MUSB_DEV_MODE(musb); |
1794 | musb->xceiv->otg->default_a = 0; | |
1795 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
1796 | ||
550a7375 | 1797 | /* this "gadget" abstracts/virtualizes the controller */ |
550a7375 | 1798 | musb->g.name = musb_driver_name; |
032ec49f | 1799 | musb->g.is_otg = 1; |
550a7375 FB |
1800 | |
1801 | musb_g_init_endpoints(musb); | |
1802 | ||
1803 | musb->is_active = 0; | |
1804 | musb_platform_try_idle(musb, 0); | |
1805 | ||
0f91349b SAS |
1806 | status = usb_add_gadget_udc(musb->controller, &musb->g); |
1807 | if (status) | |
1808 | goto err; | |
1809 | ||
1810 | return 0; | |
1811 | err: | |
6193d699 | 1812 | musb->g.dev.parent = NULL; |
0f91349b | 1813 | device_unregister(&musb->g.dev); |
550a7375 FB |
1814 | return status; |
1815 | } | |
1816 | ||
1817 | void musb_gadget_cleanup(struct musb *musb) | |
1818 | { | |
90474288 SAS |
1819 | if (musb->port_mode == MUSB_PORT_MODE_HOST) |
1820 | return; | |
0f91349b | 1821 | usb_del_gadget_udc(&musb->g); |
550a7375 FB |
1822 | } |
1823 | ||
1824 | /* | |
1825 | * Register the gadget driver. Used by gadget drivers when | |
1826 | * registering themselves with the controller. | |
1827 | * | |
1828 | * -EINVAL something went wrong (not driver) | |
1829 | * -EBUSY another gadget is already using the controller | |
b595076a | 1830 | * -ENOMEM no memory to perform the operation |
550a7375 FB |
1831 | * |
1832 | * @param driver the gadget driver | |
1833 | * @return <0 if error, 0 if everything is fine | |
1834 | */ | |
e71eb392 SAS |
1835 | static int musb_gadget_start(struct usb_gadget *g, |
1836 | struct usb_gadget_driver *driver) | |
550a7375 | 1837 | { |
e71eb392 | 1838 | struct musb *musb = gadget_to_musb(g); |
d445b6da | 1839 | struct usb_otg *otg = musb->xceiv->otg; |
63eed2b5 | 1840 | unsigned long flags; |
032ec49f | 1841 | int retval = 0; |
550a7375 | 1842 | |
032ec49f FB |
1843 | if (driver->max_speed < USB_SPEED_HIGH) { |
1844 | retval = -EINVAL; | |
1845 | goto err; | |
1846 | } | |
550a7375 | 1847 | |
7acc6197 HH |
1848 | pm_runtime_get_sync(musb->controller); |
1849 | ||
5c8a86e1 | 1850 | dev_dbg(musb->controller, "registering driver %s\n", driver->function); |
550a7375 | 1851 | |
e71eb392 | 1852 | musb->softconnect = 0; |
63eed2b5 | 1853 | musb->gadget_driver = driver; |
550a7375 | 1854 | |
63eed2b5 | 1855 | spin_lock_irqsave(&musb->lock, flags); |
43e699ce | 1856 | musb->is_active = 1; |
550a7375 | 1857 | |
6e13c650 | 1858 | otg_set_peripheral(otg, &musb->g); |
63eed2b5 | 1859 | musb->xceiv->state = OTG_STATE_B_IDLE; |
63eed2b5 | 1860 | spin_unlock_irqrestore(&musb->lock, flags); |
550a7375 | 1861 | |
001dd84a SAS |
1862 | musb_start(musb); |
1863 | ||
032ec49f FB |
1864 | /* REVISIT: funcall to other code, which also |
1865 | * handles power budgeting ... this way also | |
1866 | * ensures HdrcStart is indirectly called. | |
1867 | */ | |
b65ae0f1 GI |
1868 | if (musb->xceiv->last_event == USB_EVENT_ID) |
1869 | musb_platform_set_vbus(musb, 1); | |
63eed2b5 | 1870 | |
cdefce16 JN |
1871 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
1872 | pm_runtime_put(musb->controller); | |
550a7375 | 1873 | |
63eed2b5 FB |
1874 | return 0; |
1875 | ||
032ec49f | 1876 | err: |
550a7375 FB |
1877 | return retval; |
1878 | } | |
550a7375 FB |
1879 | |
1880 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) | |
1881 | { | |
1882 | int i; | |
1883 | struct musb_hw_ep *hw_ep; | |
1884 | ||
1885 | /* don't disconnect if it's not connected */ | |
1886 | if (musb->g.speed == USB_SPEED_UNKNOWN) | |
1887 | driver = NULL; | |
1888 | else | |
1889 | musb->g.speed = USB_SPEED_UNKNOWN; | |
1890 | ||
1891 | /* deactivate the hardware */ | |
1892 | if (musb->softconnect) { | |
1893 | musb->softconnect = 0; | |
1894 | musb_pullup(musb, 0); | |
1895 | } | |
1896 | musb_stop(musb); | |
1897 | ||
1898 | /* killing any outstanding requests will quiesce the driver; | |
1899 | * then report disconnect | |
1900 | */ | |
1901 | if (driver) { | |
1902 | for (i = 0, hw_ep = musb->endpoints; | |
1903 | i < musb->nr_endpoints; | |
1904 | i++, hw_ep++) { | |
1905 | musb_ep_select(musb->mregs, i); | |
1906 | if (hw_ep->is_shared_fifo /* || !epnum */) { | |
1907 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1908 | } else { | |
1909 | if (hw_ep->max_packet_sz_tx) | |
1910 | nuke(&hw_ep->ep_in, -ESHUTDOWN); | |
1911 | if (hw_ep->max_packet_sz_rx) | |
1912 | nuke(&hw_ep->ep_out, -ESHUTDOWN); | |
1913 | } | |
1914 | } | |
550a7375 FB |
1915 | } |
1916 | } | |
1917 | ||
1918 | /* | |
1919 | * Unregister the gadget driver. Used by gadget drivers when | |
1920 | * unregistering themselves from the controller. | |
1921 | * | |
1922 | * @param driver the gadget driver to unregister | |
1923 | */ | |
e71eb392 SAS |
1924 | static int musb_gadget_stop(struct usb_gadget *g, |
1925 | struct usb_gadget_driver *driver) | |
550a7375 | 1926 | { |
e71eb392 | 1927 | struct musb *musb = gadget_to_musb(g); |
63eed2b5 | 1928 | unsigned long flags; |
550a7375 | 1929 | |
7acc6197 HH |
1930 | if (musb->xceiv->last_event == USB_EVENT_NONE) |
1931 | pm_runtime_get_sync(musb->controller); | |
1932 | ||
63eed2b5 FB |
1933 | /* |
1934 | * REVISIT always use otg_set_peripheral() here too; | |
550a7375 FB |
1935 | * this needs to shut down the OTG engine. |
1936 | */ | |
1937 | ||
1938 | spin_lock_irqsave(&musb->lock, flags); | |
1939 | ||
550a7375 | 1940 | musb_hnp_stop(musb); |
550a7375 | 1941 | |
63eed2b5 | 1942 | (void) musb_gadget_vbus_draw(&musb->g, 0); |
550a7375 | 1943 | |
63eed2b5 FB |
1944 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
1945 | stop_activity(musb, driver); | |
6e13c650 | 1946 | otg_set_peripheral(musb->xceiv->otg, NULL); |
550a7375 | 1947 | |
b130f03f MH |
1948 | dev_dbg(musb->controller, "unregistering driver %s\n", |
1949 | driver ? driver->function : "(removed)"); | |
550a7375 | 1950 | |
63eed2b5 | 1951 | musb->is_active = 0; |
e21de10c | 1952 | musb->gadget_driver = NULL; |
63eed2b5 | 1953 | musb_platform_try_idle(musb, 0); |
550a7375 FB |
1954 | spin_unlock_irqrestore(&musb->lock, flags); |
1955 | ||
032ec49f FB |
1956 | /* |
1957 | * FIXME we need to be able to register another | |
1958 | * gadget driver here and have everything work; | |
1959 | * that currently misbehaves. | |
1960 | */ | |
63eed2b5 | 1961 | |
7acc6197 HH |
1962 | pm_runtime_put(musb->controller); |
1963 | ||
63eed2b5 | 1964 | return 0; |
550a7375 | 1965 | } |
550a7375 FB |
1966 | |
1967 | /* ----------------------------------------------------------------------- */ | |
1968 | ||
1969 | /* lifecycle operations called through plat_uds.c */ | |
1970 | ||
1971 | void musb_g_resume(struct musb *musb) | |
1972 | { | |
1973 | musb->is_suspended = 0; | |
84e250ff | 1974 | switch (musb->xceiv->state) { |
550a7375 FB |
1975 | case OTG_STATE_B_IDLE: |
1976 | break; | |
1977 | case OTG_STATE_B_WAIT_ACON: | |
1978 | case OTG_STATE_B_PERIPHERAL: | |
1979 | musb->is_active = 1; | |
1980 | if (musb->gadget_driver && musb->gadget_driver->resume) { | |
1981 | spin_unlock(&musb->lock); | |
1982 | musb->gadget_driver->resume(&musb->g); | |
1983 | spin_lock(&musb->lock); | |
1984 | } | |
1985 | break; | |
1986 | default: | |
1987 | WARNING("unhandled RESUME transition (%s)\n", | |
42c0bf1c | 1988 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1989 | } |
1990 | } | |
1991 | ||
1992 | /* called when SOF packets stop for 3+ msec */ | |
1993 | void musb_g_suspend(struct musb *musb) | |
1994 | { | |
1995 | u8 devctl; | |
1996 | ||
1997 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
5c8a86e1 | 1998 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 | 1999 | |
84e250ff | 2000 | switch (musb->xceiv->state) { |
550a7375 FB |
2001 | case OTG_STATE_B_IDLE: |
2002 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
84e250ff | 2003 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
2004 | break; |
2005 | case OTG_STATE_B_PERIPHERAL: | |
2006 | musb->is_suspended = 1; | |
2007 | if (musb->gadget_driver && musb->gadget_driver->suspend) { | |
2008 | spin_unlock(&musb->lock); | |
2009 | musb->gadget_driver->suspend(&musb->g); | |
2010 | spin_lock(&musb->lock); | |
2011 | } | |
2012 | break; | |
2013 | default: | |
2014 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; | |
2015 | * A_PERIPHERAL may need care too | |
2016 | */ | |
2017 | WARNING("unhandled SUSPEND transition (%s)\n", | |
42c0bf1c | 2018 | usb_otg_state_string(musb->xceiv->state)); |
550a7375 FB |
2019 | } |
2020 | } | |
2021 | ||
2022 | /* Called during SRP */ | |
2023 | void musb_g_wakeup(struct musb *musb) | |
2024 | { | |
2025 | musb_gadget_wakeup(&musb->g); | |
2026 | } | |
2027 | ||
2028 | /* called when VBUS drops below session threshold, and in other cases */ | |
2029 | void musb_g_disconnect(struct musb *musb) | |
2030 | { | |
2031 | void __iomem *mregs = musb->mregs; | |
2032 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); | |
2033 | ||
5c8a86e1 | 2034 | dev_dbg(musb->controller, "devctl %02x\n", devctl); |
550a7375 FB |
2035 | |
2036 | /* clear HR */ | |
2037 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); | |
2038 | ||
2039 | /* don't draw vbus until new b-default session */ | |
2040 | (void) musb_gadget_vbus_draw(&musb->g, 0); | |
2041 | ||
2042 | musb->g.speed = USB_SPEED_UNKNOWN; | |
2043 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { | |
2044 | spin_unlock(&musb->lock); | |
2045 | musb->gadget_driver->disconnect(&musb->g); | |
2046 | spin_lock(&musb->lock); | |
2047 | } | |
2048 | ||
84e250ff | 2049 | switch (musb->xceiv->state) { |
550a7375 | 2050 | default: |
5c8a86e1 | 2051 | dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n", |
42c0bf1c | 2052 | usb_otg_state_string(musb->xceiv->state)); |
84e250ff | 2053 | musb->xceiv->state = OTG_STATE_A_IDLE; |
ab983f2a | 2054 | MUSB_HST_MODE(musb); |
550a7375 FB |
2055 | break; |
2056 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae | 2057 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
ab983f2a | 2058 | MUSB_HST_MODE(musb); |
550a7375 FB |
2059 | break; |
2060 | case OTG_STATE_B_WAIT_ACON: | |
2061 | case OTG_STATE_B_HOST: | |
550a7375 FB |
2062 | case OTG_STATE_B_PERIPHERAL: |
2063 | case OTG_STATE_B_IDLE: | |
84e250ff | 2064 | musb->xceiv->state = OTG_STATE_B_IDLE; |
550a7375 FB |
2065 | break; |
2066 | case OTG_STATE_B_SRP_INIT: | |
2067 | break; | |
2068 | } | |
2069 | ||
2070 | musb->is_active = 0; | |
2071 | } | |
2072 | ||
2073 | void musb_g_reset(struct musb *musb) | |
2074 | __releases(musb->lock) | |
2075 | __acquires(musb->lock) | |
2076 | { | |
2077 | void __iomem *mbase = musb->mregs; | |
2078 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); | |
2079 | u8 power; | |
2080 | ||
515ba29c | 2081 | dev_dbg(musb->controller, "<== %s driver '%s'\n", |
550a7375 FB |
2082 | (devctl & MUSB_DEVCTL_BDEVICE) |
2083 | ? "B-Device" : "A-Device", | |
550a7375 FB |
2084 | musb->gadget_driver |
2085 | ? musb->gadget_driver->driver.name | |
2086 | : NULL | |
2087 | ); | |
2088 | ||
2089 | /* report disconnect, if we didn't already (flushing EP state) */ | |
2090 | if (musb->g.speed != USB_SPEED_UNKNOWN) | |
2091 | musb_g_disconnect(musb); | |
2092 | ||
2093 | /* clear HR */ | |
2094 | else if (devctl & MUSB_DEVCTL_HR) | |
2095 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
2096 | ||
2097 | ||
2098 | /* what speed did we negotiate? */ | |
2099 | power = musb_readb(mbase, MUSB_POWER); | |
2100 | musb->g.speed = (power & MUSB_POWER_HSMODE) | |
2101 | ? USB_SPEED_HIGH : USB_SPEED_FULL; | |
2102 | ||
2103 | /* start in USB_STATE_DEFAULT */ | |
2104 | musb->is_active = 1; | |
2105 | musb->is_suspended = 0; | |
2106 | MUSB_DEV_MODE(musb); | |
2107 | musb->address = 0; | |
2108 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; | |
2109 | ||
2110 | musb->may_wakeup = 0; | |
2111 | musb->g.b_hnp_enable = 0; | |
2112 | musb->g.a_alt_hnp_support = 0; | |
2113 | musb->g.a_hnp_support = 0; | |
2114 | ||
2115 | /* Normal reset, as B-Device; | |
2116 | * or else after HNP, as A-Device | |
2117 | */ | |
2118 | if (devctl & MUSB_DEVCTL_BDEVICE) { | |
84e250ff | 2119 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 | 2120 | musb->g.is_a_peripheral = 0; |
032ec49f | 2121 | } else { |
84e250ff | 2122 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
550a7375 | 2123 | musb->g.is_a_peripheral = 1; |
032ec49f | 2124 | } |
550a7375 FB |
2125 | |
2126 | /* start with default limits on VBUS power draw */ | |
032ec49f | 2127 | (void) musb_gadget_vbus_draw(&musb->g, 8); |
550a7375 | 2128 | } |