[linux-2.6-block.git] / drivers / usb / musb / musb_cppi41.c

#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/sizes.h>
#include <linux/platform_device.h>
#include <linux/of.h>

#include "musb_core.h"

#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))

#define EP_MODE_AUTOREG_NONE		0
#define EP_MODE_AUTOREG_ALL_NEOP	1
#define EP_MODE_AUTOREG_ALWAYS		3

#define EP_MODE_DMA_TRANSPARENT		0
#define EP_MODE_DMA_RNDIS		1
#define EP_MODE_DMA_GEN_RNDIS		3

#define USB_CTRL_TX_MODE	0x70
#define USB_CTRL_RX_MODE	0x74
#define USB_CTRL_AUTOREQ	0xd0
#define USB_TDOWN		0xd8

struct cppi41_dma_channel {
	struct dma_channel channel;
	struct cppi41_dma_controller *controller;
	struct musb_hw_ep *hw_ep;
	struct dma_chan *dc;
	dma_cookie_t cookie;
	u8 port_num;
	u8 is_tx;
	u8 is_allocated;
	u8 usb_toggle;

	dma_addr_t buf_addr;
	u32 total_len;
	u32 prog_len;
	u32 transferred;
	u32 packet_sz;
};

#define MUSB_DMA_NUM_CHANNELS 15

struct cppi41_dma_controller {
	struct dma_controller controller;
	struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
	struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
	struct musb *musb;
	u32 rx_mode;
	u32 tx_mode;
	u32 auto_req;
};

static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
{
	u16 csr;
	u8 toggle;

	if (cppi41_channel->is_tx)
		return;
	if (!is_host_active(cppi41_channel->controller->musb))
		return;

	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

	cppi41_channel->usb_toggle = toggle;
}

static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
{
	u16 csr;
	u8 toggle;

	if (cppi41_channel->is_tx)
		return;
	if (!is_host_active(cppi41_channel->controller->musb))
		return;

	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;

	/*
	 * AM335x Advisory 1.0.13: Due to internal synchronisation error the
	 * data toggle may reset from DATA1 to DATA0 during receiving data from
	 * more than one endpoint.
	 */
	if (!toggle && toggle == cppi41_channel->usb_toggle) {
		csr |= MUSB_RXCSR_H_DATATOGGLE | MUSB_RXCSR_H_WR_DATATOGGLE;
		musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
		dev_dbg(cppi41_channel->controller->musb->controller,
				"Restoring DATA1 toggle.\n");
	}

	cppi41_channel->usb_toggle = toggle;
}

static void cppi41_dma_callback(void *private_data);

static void cppi41_trans_done(struct dma_channel *channel)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
	struct musb *musb = hw_ep->musb;

	if (!cppi41_channel->prog_len) {

		/* done, complete */
		cppi41_channel->channel.actual_len =
			cppi41_channel->transferred;
		cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
		musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
	} else {
		/* next iteration, reload */
		struct dma_chan *dc = cppi41_channel->dc;
		struct dma_async_tx_descriptor *dma_desc;
		enum dma_transfer_direction direction;
		u16 csr;
		u32 remain_bytes;
		void __iomem *epio = cppi41_channel->hw_ep->regs;

		cppi41_channel->buf_addr += cppi41_channel->packet_sz;

		remain_bytes = cppi41_channel->total_len;
		remain_bytes -= cppi41_channel->transferred;
		remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
		cppi41_channel->prog_len = remain_bytes;

		direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
			: DMA_DEV_TO_MEM;
		dma_desc = dmaengine_prep_slave_single(dc,
				cppi41_channel->buf_addr,
				remain_bytes,
				direction,
				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
		if (WARN_ON(!dma_desc))
			return;

		dma_desc->callback = cppi41_dma_callback;
		dma_desc->callback_param = channel;
		cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
		dma_async_issue_pending(dc);

		if (!cppi41_channel->is_tx) {
			csr = musb_readw(epio, MUSB_RXCSR);
			csr |= MUSB_RXCSR_H_REQPKT;
			musb_writew(epio, MUSB_RXCSR, csr);
		}
	}
}

static void cppi41_dma_callback(void *private_data)
{
	struct dma_channel *channel = private_data;
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
	struct musb *musb = hw_ep->musb;
	unsigned long flags;
	struct dma_tx_state txstate;
	u32 transferred;

	spin_lock_irqsave(&musb->lock, flags);

	dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
			&txstate);
	transferred = cppi41_channel->prog_len - txstate.residue;
	cppi41_channel->transferred += transferred;

	dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
		hw_ep->epnum, cppi41_channel->transferred,
		cppi41_channel->total_len);

	update_rx_toggle(cppi41_channel);

	if (cppi41_channel->transferred == cppi41_channel->total_len ||
			transferred < cppi41_channel->packet_sz)
		cppi41_channel->prog_len = 0;

	cppi41_trans_done(channel);

	spin_unlock_irqrestore(&musb->lock, flags);
}

static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
{
	unsigned shift;

	shift = (ep - 1) * 2;
	old &= ~(3 << shift);
	old |= mode << shift;
	return old;
}

static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
		unsigned mode)
{
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	u32 port;
	u32 new_mode;
	u32 old_mode;

	if (cppi41_channel->is_tx)
		old_mode = controller->tx_mode;
	else
		old_mode = controller->rx_mode;
	port = cppi41_channel->port_num;
	new_mode = update_ep_mode(port, mode, old_mode);

	if (new_mode == old_mode)
		return;
	if (cppi41_channel->is_tx) {
		controller->tx_mode = new_mode;
		musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
				new_mode);
	} else {
		controller->rx_mode = new_mode;
		musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
				new_mode);
	}
}

static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
		unsigned mode)
{
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	u32 port;
	u32 new_mode;
	u32 old_mode;

	old_mode = controller->auto_req;
	port = cppi41_channel->port_num;
	new_mode = update_ep_mode(port, mode, old_mode);

	if (new_mode == old_mode)
		return;
	controller->auto_req = new_mode;
	musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
}

static bool cppi41_configure_channel(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct dma_chan *dc = cppi41_channel->dc;
	struct dma_async_tx_descriptor *dma_desc;
	enum dma_transfer_direction direction;
	struct musb *musb = cppi41_channel->controller->musb;
	unsigned use_gen_rndis = 0;

	dev_dbg(musb->controller,
		"configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
		cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
		packet_sz, mode, (unsigned long long) dma_addr,
		len, cppi41_channel->is_tx);

	cppi41_channel->buf_addr = dma_addr;
	cppi41_channel->total_len = len;
	cppi41_channel->transferred = 0;
	cppi41_channel->packet_sz = packet_sz;

	/*
	 * Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
	 * than max packet size at a time.
	 */
	if (cppi41_channel->is_tx)
		use_gen_rndis = 1;

	if (use_gen_rndis) {
		/* RNDIS mode */
		if (len > packet_sz) {
			musb_writel(musb->ctrl_base,
				RNDIS_REG(cppi41_channel->port_num), len);
			/* gen rndis */
			cppi41_set_dma_mode(cppi41_channel,
					EP_MODE_DMA_GEN_RNDIS);

			/* auto req */
			cppi41_set_autoreq_mode(cppi41_channel,
					EP_MODE_AUTOREG_ALL_NEOP);
		} else {
			musb_writel(musb->ctrl_base,
					RNDIS_REG(cppi41_channel->port_num), 0);
			cppi41_set_dma_mode(cppi41_channel,
					EP_MODE_DMA_TRANSPARENT);
			cppi41_set_autoreq_mode(cppi41_channel,
					EP_MODE_AUTOREG_NONE);
		}
	} else {
		/* fallback mode */
		cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
		cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
		len = min_t(u32, packet_sz, len);
	}
	cppi41_channel->prog_len = len;
	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
	dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!dma_desc)
		return false;

	dma_desc->callback = cppi41_dma_callback;
	dma_desc->callback_param = channel;
	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);

	save_rx_toggle(cppi41_channel);
	dma_async_issue_pending(dc);
	return true;
}

static struct dma_channel *cppi41_dma_channel_allocate(struct dma_controller *c,
				struct musb_hw_ep *hw_ep, u8 is_tx)
{
	struct cppi41_dma_controller *controller = container_of(c,
			struct cppi41_dma_controller, controller);
	struct cppi41_dma_channel *cppi41_channel = NULL;
	u8 ch_num = hw_ep->epnum - 1;

	if (ch_num >= MUSB_DMA_NUM_CHANNELS)
		return NULL;

	if (is_tx)
		cppi41_channel = &controller->tx_channel[ch_num];
	else
		cppi41_channel = &controller->rx_channel[ch_num];

	if (!cppi41_channel->dc)
		return NULL;

	if (cppi41_channel->is_allocated)
		return NULL;

	cppi41_channel->hw_ep = hw_ep;
	cppi41_channel->is_allocated = 1;

	return &cppi41_channel->channel;
}

static void cppi41_dma_channel_release(struct dma_channel *channel)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;

	if (cppi41_channel->is_allocated) {
		cppi41_channel->is_allocated = 0;
		channel->status = MUSB_DMA_STATUS_FREE;
		channel->actual_len = 0;
	}
}

static int cppi41_dma_channel_program(struct dma_channel *channel,
				u16 packet_sz, u8 mode,
				dma_addr_t dma_addr, u32 len)
{
	int ret;

	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
		channel->status == MUSB_DMA_STATUS_BUSY);

	channel->status = MUSB_DMA_STATUS_BUSY;
	channel->actual_len = 0;
	ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
	if (!ret)
		channel->status = MUSB_DMA_STATUS_FREE;

	return ret;
}

static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
		void *buf, u32 length)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	struct musb *musb = controller->musb;

	if (is_host_active(musb)) {
		WARN_ON(1);
		return 1;
	}
	if (cppi41_channel->is_tx)
		return 1;
	/* AM335x Advisory 1.0.13. No workaround for device RX mode */
	return 0;
}

static int cppi41_dma_channel_abort(struct dma_channel *channel)
{
	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	struct musb *musb = controller->musb;
	void __iomem *epio = cppi41_channel->hw_ep->regs;
	int tdbit;
	int ret;
	unsigned is_tx;
	u16 csr;

	is_tx = cppi41_channel->is_tx;
	dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
			cppi41_channel->port_num, is_tx);

	if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
		return 0;

	if (is_tx) {
		csr = musb_readw(epio, MUSB_TXCSR);
		csr &= ~MUSB_TXCSR_DMAENAB;
		musb_writew(epio, MUSB_TXCSR, csr);
	} else {
		csr = musb_readw(epio, MUSB_RXCSR);
		csr &= ~(MUSB_RXCSR_H_REQPKT | MUSB_RXCSR_DMAENAB);
		musb_writew(epio, MUSB_RXCSR, csr);

		csr = musb_readw(epio, MUSB_RXCSR);
		if (csr & MUSB_RXCSR_RXPKTRDY) {
			csr |= MUSB_RXCSR_FLUSHFIFO;
			musb_writew(epio, MUSB_RXCSR, csr);
			musb_writew(epio, MUSB_RXCSR, csr);
		}
	}

	tdbit = 1 << cppi41_channel->port_num;
	if (is_tx)
		tdbit <<= 16;

	do {
		musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
		ret = dmaengine_terminate_all(cppi41_channel->dc);
	} while (ret == -EAGAIN);

	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);

	if (is_tx) {
		csr = musb_readw(epio, MUSB_TXCSR);
		if (csr & MUSB_TXCSR_TXPKTRDY) {
			csr |= MUSB_TXCSR_FLUSHFIFO;
			musb_writew(epio, MUSB_TXCSR, csr);
		}
	}

	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
	return 0;
}

static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
{
	struct dma_chan *dc;
	int i;

	for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
		dc = ctrl->tx_channel[i].dc;
		if (dc)
			dma_release_channel(dc);
		dc = ctrl->rx_channel[i].dc;
		if (dc)
			dma_release_channel(dc);
	}
}

static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
{
	cppi41_release_all_dma_chans(controller);
}

static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
{
	struct musb *musb = controller->musb;
	struct device *dev = musb->controller;
	struct device_node *np = dev->of_node;
	struct cppi41_dma_channel *cppi41_channel;
	int count;
	int i;
	int ret;

	count = of_property_count_strings(np, "dma-names");
	if (count < 0)
		return count;

	for (i = 0; i < count; i++) {
		struct dma_chan *dc;
		struct dma_channel *musb_dma;
		const char *str;
		unsigned is_tx;
		unsigned int port;

		ret = of_property_read_string_index(np, "dma-names", i, &str);
		if (ret)
			goto err;
		if (!strncmp(str, "tx", 2))
			is_tx = 1;
		else if (!strncmp(str, "rx", 2))
			is_tx = 0;
		else {
			dev_err(dev, "Wrong dmatype %s\n", str);
			goto err;
		}
		ret = kstrtouint(str + 2, 0, &port);
		if (ret)
			goto err;

		ret = -EINVAL;
		if (port > MUSB_DMA_NUM_CHANNELS || !port)
			goto err;
		if (is_tx)
			cppi41_channel = &controller->tx_channel[port - 1];
		else
			cppi41_channel = &controller->rx_channel[port - 1];

		cppi41_channel->controller = controller;
		cppi41_channel->port_num = port;
		cppi41_channel->is_tx = is_tx;

		musb_dma = &cppi41_channel->channel;
		musb_dma->private_data = cppi41_channel;
		musb_dma->status = MUSB_DMA_STATUS_FREE;
		musb_dma->max_len = SZ_4M;

		dc = dma_request_slave_channel(dev, str);
		if (!dc) {
			dev_err(dev, "Falied to request %s.\n", str);
			ret = -EPROBE_DEFER;
			goto err;
		}
		cppi41_channel->dc = dc;
	}
	return 0;
err:
	cppi41_release_all_dma_chans(controller);
	return ret;
}

void dma_controller_destroy(struct dma_controller *c)
{
	struct cppi41_dma_controller *controller = container_of(c,
			struct cppi41_dma_controller, controller);

	cppi41_dma_controller_stop(controller);
	kfree(controller);
}

struct dma_controller *dma_controller_create(struct musb *musb,
					void __iomem *base)
{
	struct cppi41_dma_controller *controller;
	int ret = 0;

	if (!musb->controller->of_node) {
		dev_err(musb->controller, "Need DT for the DMA engine.\n");
		return NULL;
	}

	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	if (!controller)
		goto kzalloc_fail;

	controller->musb = musb;

	controller->controller.channel_alloc = cppi41_dma_channel_allocate;
	controller->controller.channel_release = cppi41_dma_channel_release;
	controller->controller.channel_program = cppi41_dma_channel_program;
	controller->controller.channel_abort = cppi41_dma_channel_abort;
	controller->controller.is_compatible = cppi41_is_compatible;

	ret = cppi41_dma_controller_start(controller);
	if (ret)
		goto plat_get_fail;
	return &controller->controller;

plat_get_fail:
	kfree(controller);
kzalloc_fail:
	if (ret == -EPROBE_DEFER)
		return ERR_PTR(ret);
	return NULL;
}
Commit	Line	Data
9b3452d1 SAS	1	#include <linux/device.h>
	2	#include <linux/dma-mapping.h>
	3	#include <linux/dmaengine.h>
	4	#include <linux/sizes.h>
	5	#include <linux/platform_device.h>
	6	#include <linux/of.h>
	7
	8	#include "musb_core.h"
	9
	10	#define RNDIS_REG(x) (0x80 + ((x - 1) * 4))
	11
	12	#define EP_MODE_AUTOREG_NONE 0
	13	#define EP_MODE_AUTOREG_ALL_NEOP 1
	14	#define EP_MODE_AUTOREG_ALWAYS 3
	15
	16	#define EP_MODE_DMA_TRANSPARENT 0
	17	#define EP_MODE_DMA_RNDIS 1
	18	#define EP_MODE_DMA_GEN_RNDIS 3
	19
	20	#define USB_CTRL_TX_MODE 0x70
	21	#define USB_CTRL_RX_MODE 0x74
	22	#define USB_CTRL_AUTOREQ 0xd0
	23	#define USB_TDOWN 0xd8
	24
	25	struct cppi41_dma_channel {
	26	struct dma_channel channel;
	27	struct cppi41_dma_controller *controller;
	28	struct musb_hw_ep *hw_ep;
	29	struct dma_chan *dc;
	30	dma_cookie_t cookie;
	31	u8 port_num;
	32	u8 is_tx;
	33	u8 is_allocated;
	34	u8 usb_toggle;
	35
	36	dma_addr_t buf_addr;
	37	u32 total_len;
	38	u32 prog_len;
	39	u32 transferred;
	40	u32 packet_sz;
	41	};
	42
	43	#define MUSB_DMA_NUM_CHANNELS 15
	44
	45	struct cppi41_dma_controller {
	46	struct dma_controller controller;
	47	struct cppi41_dma_channel rx_channel[MUSB_DMA_NUM_CHANNELS];
	48	struct cppi41_dma_channel tx_channel[MUSB_DMA_NUM_CHANNELS];
	49	struct musb *musb;
	50	u32 rx_mode;
	51	u32 tx_mode;
	52	u32 auto_req;
	53	};
	54
	55	static void save_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
	56	{
	57	u16 csr;
	58	u8 toggle;
	59
	60	if (cppi41_channel->is_tx)
	61	return;
	62	if (!is_host_active(cppi41_channel->controller->musb))
	63	return;
	64
65	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
66	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
67
68	cppi41_channel->usb_toggle = toggle;
69	}
70
71	static void update_rx_toggle(struct cppi41_dma_channel *cppi41_channel)
72	{
73	u16 csr;
74	u8 toggle;
75
76	if (cppi41_channel->is_tx)
77	return;
78	if (!is_host_active(cppi41_channel->controller->musb))
79	return;
80
81	csr = musb_readw(cppi41_channel->hw_ep->regs, MUSB_RXCSR);
82	toggle = csr & MUSB_RXCSR_H_DATATOGGLE ? 1 : 0;
83
84	/*
85	* AM335x Advisory 1.0.13: Due to internal synchronisation error the
86	* data toggle may reset from DATA1 to DATA0 during receiving data from
87	* more than one endpoint.
88	*/
89	if (!toggle && toggle == cppi41_channel->usb_toggle) {
90	csr \|= MUSB_RXCSR_H_DATATOGGLE \| MUSB_RXCSR_H_WR_DATATOGGLE;
91	musb_writew(cppi41_channel->hw_ep->regs, MUSB_RXCSR, csr);
92	dev_dbg(cppi41_channel->controller->musb->controller,
93	"Restoring DATA1 toggle.\n");
94	}
95
96	cppi41_channel->usb_toggle = toggle;
97	}
98
d373a853 SAS	99	static void cppi41_dma_callback(void *private_data);
	100
	101	static void cppi41_trans_done(struct dma_channel *channel)
9b3452d1	102	{
9b3452d1 SAS	103	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	104	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
	105	struct musb *musb = hw_ep->musb;
9b3452d1	106
d373a853	107	if (!cppi41_channel->prog_len) {
9b3452d1 SAS	108
	109	/* done, complete */
	110	cppi41_channel->channel.actual_len =
	111	cppi41_channel->transferred;
	112	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
	113	musb_dma_completion(musb, hw_ep->epnum, cppi41_channel->is_tx);
	114	} else {
	115	/* next iteration, reload */
	116	struct dma_chan *dc = cppi41_channel->dc;
	117	struct dma_async_tx_descriptor *dma_desc;
	118	enum dma_transfer_direction direction;
	119	u16 csr;
	120	u32 remain_bytes;
	121	void __iomem *epio = cppi41_channel->hw_ep->regs;
	122
	123	cppi41_channel->buf_addr += cppi41_channel->packet_sz;
	124
	125	remain_bytes = cppi41_channel->total_len;
	126	remain_bytes -= cppi41_channel->transferred;
	127	remain_bytes = min(remain_bytes, cppi41_channel->packet_sz);
	128	cppi41_channel->prog_len = remain_bytes;
	129
	130	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV
	131	: DMA_DEV_TO_MEM;
	132	dma_desc = dmaengine_prep_slave_single(dc,
	133	cppi41_channel->buf_addr,
	134	remain_bytes,
	135	direction,
	136	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
d373a853	137	if (WARN_ON(!dma_desc))
9b3452d1 SAS	138	return;
	139
	140	dma_desc->callback = cppi41_dma_callback;
	141	dma_desc->callback_param = channel;
	142	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
	143	dma_async_issue_pending(dc);
	144
	145	if (!cppi41_channel->is_tx) {
	146	csr = musb_readw(epio, MUSB_RXCSR);
	147	csr \|= MUSB_RXCSR_H_REQPKT;
	148	musb_writew(epio, MUSB_RXCSR, csr);
	149	}
	150	}
d373a853 SAS	151	}
	152
	153	static void cppi41_dma_callback(void *private_data)
	154	{
	155	struct dma_channel *channel = private_data;
	156	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	157	struct musb_hw_ep *hw_ep = cppi41_channel->hw_ep;
	158	struct musb *musb = hw_ep->musb;
	159	unsigned long flags;
	160	struct dma_tx_state txstate;
	161	u32 transferred;
	162
	163	spin_lock_irqsave(&musb->lock, flags);
	164
	165	dmaengine_tx_status(cppi41_channel->dc, cppi41_channel->cookie,
	166	&txstate);
	167	transferred = cppi41_channel->prog_len - txstate.residue;
	168	cppi41_channel->transferred += transferred;
	169
	170	dev_dbg(musb->controller, "DMA transfer done on hw_ep=%d bytes=%d/%d\n",
	171	hw_ep->epnum, cppi41_channel->transferred,
	172	cppi41_channel->total_len);
	173
	174	update_rx_toggle(cppi41_channel);
	175
	176	if (cppi41_channel->transferred == cppi41_channel->total_len \|\|
	177	transferred < cppi41_channel->packet_sz)
	178	cppi41_channel->prog_len = 0;
	179
	180	cppi41_trans_done(channel);
	181
9b3452d1 SAS	182	spin_unlock_irqrestore(&musb->lock, flags);
	183	}
	184
	185	static u32 update_ep_mode(unsigned ep, unsigned mode, u32 old)
	186	{
	187	unsigned shift;
	188
	189	shift = (ep - 1) * 2;
	190	old &= ~(3 << shift);
	191	old \|= mode << shift;
	192	return old;
	193	}
	194
	195	static void cppi41_set_dma_mode(struct cppi41_dma_channel *cppi41_channel,
	196	unsigned mode)
	197	{
	198	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	199	u32 port;
	200	u32 new_mode;
	201	u32 old_mode;
	202
	203	if (cppi41_channel->is_tx)
	204	old_mode = controller->tx_mode;
	205	else
	206	old_mode = controller->rx_mode;
	207	port = cppi41_channel->port_num;
	208	new_mode = update_ep_mode(port, mode, old_mode);
	209
	210	if (new_mode == old_mode)
	211	return;
	212	if (cppi41_channel->is_tx) {
	213	controller->tx_mode = new_mode;
	214	musb_writel(controller->musb->ctrl_base, USB_CTRL_TX_MODE,
	215	new_mode);
	216	} else {
	217	controller->rx_mode = new_mode;
	218	musb_writel(controller->musb->ctrl_base, USB_CTRL_RX_MODE,
	219	new_mode);
	220	}
	221	}
	222
	223	static void cppi41_set_autoreq_mode(struct cppi41_dma_channel *cppi41_channel,
	224	unsigned mode)
	225	{
	226	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	227	u32 port;
	228	u32 new_mode;
	229	u32 old_mode;
	230
	231	old_mode = controller->auto_req;
	232	port = cppi41_channel->port_num;
	233	new_mode = update_ep_mode(port, mode, old_mode);
	234
	235	if (new_mode == old_mode)
	236	return;
	237	controller->auto_req = new_mode;
	238	musb_writel(controller->musb->ctrl_base, USB_CTRL_AUTOREQ, new_mode);
	239	}
	240
	241	static bool cppi41_configure_channel(struct dma_channel *channel,
	242	u16 packet_sz, u8 mode,
	243	dma_addr_t dma_addr, u32 len)
	244	{
	245	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
246	struct dma_chan *dc = cppi41_channel->dc;
247	struct dma_async_tx_descriptor *dma_desc;
248	enum dma_transfer_direction direction;
249	struct musb *musb = cppi41_channel->controller->musb;
250	unsigned use_gen_rndis = 0;
251
252	dev_dbg(musb->controller,
253	"configure ep%d/%x packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n",
254	cppi41_channel->port_num, RNDIS_REG(cppi41_channel->port_num),
255	packet_sz, mode, (unsigned long long) dma_addr,
256	len, cppi41_channel->is_tx);
257
258	cppi41_channel->buf_addr = dma_addr;
259	cppi41_channel->total_len = len;
260	cppi41_channel->transferred = 0;
261	cppi41_channel->packet_sz = packet_sz;
262
263	/*
264	* Due to AM335x' Advisory 1.0.13 we are not allowed to transfer more
265	* than max packet size at a time.
266	*/
267	if (cppi41_channel->is_tx)
268	use_gen_rndis = 1;
269
270	if (use_gen_rndis) {
271	/* RNDIS mode */
272	if (len > packet_sz) {
273	musb_writel(musb->ctrl_base,
274	RNDIS_REG(cppi41_channel->port_num), len);
275	/* gen rndis */
276	cppi41_set_dma_mode(cppi41_channel,
277	EP_MODE_DMA_GEN_RNDIS);
278
279	/* auto req */
280	cppi41_set_autoreq_mode(cppi41_channel,
281	EP_MODE_AUTOREG_ALL_NEOP);
282	} else {
283	musb_writel(musb->ctrl_base,
284	RNDIS_REG(cppi41_channel->port_num), 0);
285	cppi41_set_dma_mode(cppi41_channel,
286	EP_MODE_DMA_TRANSPARENT);
287	cppi41_set_autoreq_mode(cppi41_channel,
288	EP_MODE_AUTOREG_NONE);
289	}
290	} else {
291	/* fallback mode */
292	cppi41_set_dma_mode(cppi41_channel, EP_MODE_DMA_TRANSPARENT);
293	cppi41_set_autoreq_mode(cppi41_channel, EP_MODE_AUTOREG_NONE);
294	len = min_t(u32, packet_sz, len);
295	}
296	cppi41_channel->prog_len = len;
297	direction = cppi41_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
298	dma_desc = dmaengine_prep_slave_single(dc, dma_addr, len, direction,
299	DMA_PREP_INTERRUPT \| DMA_CTRL_ACK);
300	if (!dma_desc)
301	return false;
302
303	dma_desc->callback = cppi41_dma_callback;
304	dma_desc->callback_param = channel;
305	cppi41_channel->cookie = dma_desc->tx_submit(dma_desc);
306
307	save_rx_toggle(cppi41_channel);
308	dma_async_issue_pending(dc);
309	return true;
310	}
311
312	static struct dma_channel cppi41_dma_channel_allocate(struct dma_controller c,
313	struct musb_hw_ep *hw_ep, u8 is_tx)
314	{
315	struct cppi41_dma_controller *controller = container_of(c,
316	struct cppi41_dma_controller, controller);
317	struct cppi41_dma_channel *cppi41_channel = NULL;
318	u8 ch_num = hw_ep->epnum - 1;
319
320	if (ch_num >= MUSB_DMA_NUM_CHANNELS)
321	return NULL;
322
323	if (is_tx)
324	cppi41_channel = &controller->tx_channel[ch_num];
325	else
326	cppi41_channel = &controller->rx_channel[ch_num];
327
328	if (!cppi41_channel->dc)
329	return NULL;
330
331	if (cppi41_channel->is_allocated)
332	return NULL;
333
334	cppi41_channel->hw_ep = hw_ep;
335	cppi41_channel->is_allocated = 1;
336
337	return &cppi41_channel->channel;
338	}
339
340	static void cppi41_dma_channel_release(struct dma_channel *channel)
341	{
342	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
343
344	if (cppi41_channel->is_allocated) {
345	cppi41_channel->is_allocated = 0;
346	channel->status = MUSB_DMA_STATUS_FREE;
347	channel->actual_len = 0;
348	}
349	}
350
351	static int cppi41_dma_channel_program(struct dma_channel *channel,
352	u16 packet_sz, u8 mode,
353	dma_addr_t dma_addr, u32 len)
354	{
355	int ret;
356
357	BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN \|\|
358	channel->status == MUSB_DMA_STATUS_BUSY);
359
360	channel->status = MUSB_DMA_STATUS_BUSY;
361	channel->actual_len = 0;
362	ret = cppi41_configure_channel(channel, packet_sz, mode, dma_addr, len);
363	if (!ret)
364	channel->status = MUSB_DMA_STATUS_FREE;
365
366	return ret;
367	}
368
369	static int cppi41_is_compatible(struct dma_channel *channel, u16 maxpacket,
370	void *buf, u32 length)
371	{
372	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
373	struct cppi41_dma_controller *controller = cppi41_channel->controller;
374	struct musb *musb = controller->musb;
375
376	if (is_host_active(musb)) {
377	WARN_ON(1);
378	return 1;
379	}
13266fea SAS	380	if (cppi41_channel->is_tx)
	381	return 1;
	382	/* AM335x Advisory 1.0.13. No workaround for device RX mode */
9b3452d1 SAS	383	return 0;
	384	}
	385
	386	static int cppi41_dma_channel_abort(struct dma_channel *channel)
	387	{
	388	struct cppi41_dma_channel *cppi41_channel = channel->private_data;
	389	struct cppi41_dma_controller *controller = cppi41_channel->controller;
	390	struct musb *musb = controller->musb;
	391	void __iomem *epio = cppi41_channel->hw_ep->regs;
	392	int tdbit;
	393	int ret;
	394	unsigned is_tx;
	395	u16 csr;
	396
	397	is_tx = cppi41_channel->is_tx;
	398	dev_dbg(musb->controller, "abort channel=%d, is_tx=%d\n",
	399	cppi41_channel->port_num, is_tx);
	400
	401	if (cppi41_channel->channel.status == MUSB_DMA_STATUS_FREE)
	402	return 0;
	403
	404	if (is_tx) {
	405	csr = musb_readw(epio, MUSB_TXCSR);
	406	csr &= ~MUSB_TXCSR_DMAENAB;
	407	musb_writew(epio, MUSB_TXCSR, csr);
	408	} else {
	409	csr = musb_readw(epio, MUSB_RXCSR);
	410	csr &= ~(MUSB_RXCSR_H_REQPKT \| MUSB_RXCSR_DMAENAB);
	411	musb_writew(epio, MUSB_RXCSR, csr);
	412
	413	csr = musb_readw(epio, MUSB_RXCSR);
	414	if (csr & MUSB_RXCSR_RXPKTRDY) {
	415	csr \|= MUSB_RXCSR_FLUSHFIFO;
	416	musb_writew(epio, MUSB_RXCSR, csr);
	417	musb_writew(epio, MUSB_RXCSR, csr);
	418	}
	419	}
	420
	421	tdbit = 1 << cppi41_channel->port_num;
	422	if (is_tx)
	423	tdbit <<= 16;
	424
	425	do {
	426	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
	427	ret = dmaengine_terminate_all(cppi41_channel->dc);
	428	} while (ret == -EAGAIN);
	429
	430	musb_writel(musb->ctrl_base, USB_TDOWN, tdbit);
	431
	432	if (is_tx) {
	433	csr = musb_readw(epio, MUSB_TXCSR);
	434	if (csr & MUSB_TXCSR_TXPKTRDY) {
	435	csr \|= MUSB_TXCSR_FLUSHFIFO;
	436	musb_writew(epio, MUSB_TXCSR, csr);
	437	}
	438	}
	439
	440	cppi41_channel->channel.status = MUSB_DMA_STATUS_FREE;
	441	return 0;
	442	}
	443
	444	static void cppi41_release_all_dma_chans(struct cppi41_dma_controller *ctrl)
	445	{
	446	struct dma_chan *dc;
447	int i;
448
449	for (i = 0; i < MUSB_DMA_NUM_CHANNELS; i++) {
450	dc = ctrl->tx_channel[i].dc;
451	if (dc)
452	dma_release_channel(dc);
453	dc = ctrl->rx_channel[i].dc;
454	if (dc)
455	dma_release_channel(dc);
456	}
457	}
458
459	static void cppi41_dma_controller_stop(struct cppi41_dma_controller *controller)
460	{
461	cppi41_release_all_dma_chans(controller);
462	}
463
464	static int cppi41_dma_controller_start(struct cppi41_dma_controller *controller)
465	{
466	struct musb *musb = controller->musb;
467	struct device *dev = musb->controller;
468	struct device_node *np = dev->of_node;
469	struct cppi41_dma_channel *cppi41_channel;
470	int count;
471	int i;
472	int ret;
473
474	count = of_property_count_strings(np, "dma-names");
475	if (count < 0)
476	return count;
477
478	for (i = 0; i < count; i++) {
479	struct dma_chan *dc;
480	struct dma_channel *musb_dma;
481	const char *str;
482	unsigned is_tx;
483	unsigned int port;
484
485	ret = of_property_read_string_index(np, "dma-names", i, &str);
486	if (ret)
487	goto err;
488	if (!strncmp(str, "tx", 2))
489	is_tx = 1;
490	else if (!strncmp(str, "rx", 2))
491	is_tx = 0;
492	else {
493	dev_err(dev, "Wrong dmatype %s\n", str);
494	goto err;
495	}
496	ret = kstrtouint(str + 2, 0, &port);
497	if (ret)
498	goto err;
499
48054147	500	ret = -EINVAL;
9b3452d1 SAS	501	if (port > MUSB_DMA_NUM_CHANNELS \|\| !port)
	502	goto err;
	503	if (is_tx)
	504	cppi41_channel = &controller->tx_channel[port - 1];
	505	else
	506	cppi41_channel = &controller->rx_channel[port - 1];
	507
	508	cppi41_channel->controller = controller;
	509	cppi41_channel->port_num = port;
	510	cppi41_channel->is_tx = is_tx;
	511
	512	musb_dma = &cppi41_channel->channel;
	513	musb_dma->private_data = cppi41_channel;
	514	musb_dma->status = MUSB_DMA_STATUS_FREE;
	515	musb_dma->max_len = SZ_4M;
	516
	517	dc = dma_request_slave_channel(dev, str);
	518	if (!dc) {
	519	dev_err(dev, "Falied to request %s.\n", str);
48054147	520	ret = -EPROBE_DEFER;
9b3452d1 SAS	521	goto err;
	522	}
	523	cppi41_channel->dc = dc;
	524	}
	525	return 0;
	526	err:
	527	cppi41_release_all_dma_chans(controller);
48054147	528	return ret;
9b3452d1 SAS	529	}
	530
	531	void dma_controller_destroy(struct dma_controller *c)
	532	{
	533	struct cppi41_dma_controller *controller = container_of(c,
	534	struct cppi41_dma_controller, controller);
	535
	536	cppi41_dma_controller_stop(controller);
	537	kfree(controller);
	538	}
	539
	540	struct dma_controller dma_controller_create(struct musb musb,
	541	void __iomem *base)
	542	{
	543	struct cppi41_dma_controller *controller;
48054147	544	int ret = 0;
9b3452d1 SAS	545
	546	if (!musb->controller->of_node) {
	547	dev_err(musb->controller, "Need DT for the DMA engine.\n");
	548	return NULL;
	549	}
	550
	551	controller = kzalloc(sizeof(*controller), GFP_KERNEL);
	552	if (!controller)
	553	goto kzalloc_fail;
	554
	555	controller->musb = musb;
	556
	557	controller->controller.channel_alloc = cppi41_dma_channel_allocate;
	558	controller->controller.channel_release = cppi41_dma_channel_release;
	559	controller->controller.channel_program = cppi41_dma_channel_program;
	560	controller->controller.channel_abort = cppi41_dma_channel_abort;
	561	controller->controller.is_compatible = cppi41_is_compatible;
	562
	563	ret = cppi41_dma_controller_start(controller);
	564	if (ret)
	565	goto plat_get_fail;
	566	return &controller->controller;
	567
	568	plat_get_fail:
	569	kfree(controller);
	570	kzalloc_fail:
48054147 SAS	571	if (ret == -EPROBE_DEFER)
48054147 SAS	572	return ERR_PTR(ret);
9b3452d1 SAS	573	return NULL;
9b3452d1 SAS	574	}