Commit | Line | Data |
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550a7375 FB |
1 | /* |
2 | * MUSB OTG driver core code | |
3 | * | |
4 | * Copyright 2005 Mentor Graphics Corporation | |
5 | * Copyright (C) 2005-2006 by Texas Instruments | |
6 | * Copyright (C) 2006-2007 Nokia Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
20 | * 02110-1301 USA | |
21 | * | |
22 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED | |
23 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
24 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
25 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, | |
26 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
27 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
28 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | */ | |
34 | ||
35 | /* | |
36 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
37 | * | |
38 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
39 | * controller driver implementing the "Gadget" API; OTG support is | |
40 | * in the works. These are normal Linux-USB controller drivers which | |
41 | * use IRQs and have no dedicated thread. | |
42 | * | |
43 | * This version of the driver has only been used with products from | |
44 | * Texas Instruments. Those products integrate the Inventra logic | |
45 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
46 | * needs to be reflected in this driver. | |
47 | * | |
48 | * | |
49 | * NOTE: the original Mentor code here was pretty much a collection | |
50 | * of mechanisms that don't seem to have been fully integrated/working | |
51 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
52 | * Key open issues include: | |
53 | * | |
54 | * - Lack of host-side transaction scheduling, for all transfer types. | |
55 | * The hardware doesn't do it; instead, software must. | |
56 | * | |
57 | * This is not an issue for OTG devices that don't support external | |
58 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
59 | * "multipoint" support doesn't scale in the expected ways. That | |
60 | * includes DaVinci EVM in a common non-OTG mode. | |
61 | * | |
62 | * * Control and bulk use dedicated endpoints, and there's as | |
63 | * yet no mechanism to either (a) reclaim the hardware when | |
64 | * peripherals are NAKing, which gets complicated with bulk | |
65 | * endpoints, or (b) use more than a single bulk endpoint in | |
66 | * each direction. | |
67 | * | |
68 | * RESULT: one device may be perceived as blocking another one. | |
69 | * | |
70 | * * Interrupt and isochronous will dynamically allocate endpoint | |
71 | * hardware, but (a) there's no record keeping for bandwidth; | |
72 | * (b) in the common case that few endpoints are available, there | |
73 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
74 | * | |
75 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
76 | * some hardware configurations, no faults will be reported. | |
77 | * At the other extreme, the bandwidth capabilities which do | |
78 | * exist tend to be severely undercommitted. You can't yet hook | |
79 | * up both a keyboard and a mouse to an external USB hub. | |
80 | */ | |
81 | ||
82 | /* | |
83 | * This gets many kinds of configuration information: | |
84 | * - Kconfig for everything user-configurable | |
550a7375 FB |
85 | * - platform_device for addressing, irq, and platform_data |
86 | * - platform_data is mostly for board-specific informarion | |
c767c1c6 | 87 | * (plus recentrly, SOC or family details) |
550a7375 FB |
88 | * |
89 | * Most of the conditional compilation will (someday) vanish. | |
90 | */ | |
91 | ||
92 | #include <linux/module.h> | |
93 | #include <linux/kernel.h> | |
94 | #include <linux/sched.h> | |
95 | #include <linux/slab.h> | |
96 | #include <linux/init.h> | |
97 | #include <linux/list.h> | |
98 | #include <linux/kobject.h> | |
9303961f | 99 | #include <linux/prefetch.h> |
550a7375 FB |
100 | #include <linux/platform_device.h> |
101 | #include <linux/io.h> | |
102 | ||
550a7375 FB |
103 | #include "musb_core.h" |
104 | ||
f7f9d63e | 105 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
106 | |
107 | ||
550a7375 FB |
108 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
109 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
110 | ||
e8164f64 | 111 | #define MUSB_VERSION "6.0" |
550a7375 FB |
112 | |
113 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
114 | ||
05ac10dd | 115 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
116 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
117 | ||
118 | MODULE_DESCRIPTION(DRIVER_INFO); | |
119 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
120 | MODULE_LICENSE("GPL"); | |
121 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
122 | ||
123 | ||
124 | /*-------------------------------------------------------------------------*/ | |
125 | ||
126 | static inline struct musb *dev_to_musb(struct device *dev) | |
127 | { | |
550a7375 | 128 | return dev_get_drvdata(dev); |
550a7375 FB |
129 | } |
130 | ||
131 | /*-------------------------------------------------------------------------*/ | |
132 | ||
ffb865b1 HK |
133 | #ifndef CONFIG_BLACKFIN |
134 | static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset) | |
135 | { | |
136 | void __iomem *addr = otg->io_priv; | |
137 | int i = 0; | |
138 | u8 r; | |
139 | u8 power; | |
140 | ||
141 | /* Make sure the transceiver is not in low power mode */ | |
142 | power = musb_readb(addr, MUSB_POWER); | |
143 | power &= ~MUSB_POWER_SUSPENDM; | |
144 | musb_writeb(addr, MUSB_POWER, power); | |
145 | ||
146 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
147 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
148 | */ | |
149 | ||
150 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
151 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, | |
152 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
153 | ||
154 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
155 | & MUSB_ULPI_REG_CMPLT)) { | |
156 | i++; | |
5c8a86e1 | 157 | if (i == 10000) |
ffb865b1 | 158 | return -ETIMEDOUT; |
ffb865b1 HK |
159 | |
160 | } | |
161 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
162 | r &= ~MUSB_ULPI_REG_CMPLT; | |
163 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
164 | ||
165 | return musb_readb(addr, MUSB_ULPI_REG_DATA); | |
166 | } | |
167 | ||
168 | static int musb_ulpi_write(struct otg_transceiver *otg, | |
169 | u32 offset, u32 data) | |
170 | { | |
171 | void __iomem *addr = otg->io_priv; | |
172 | int i = 0; | |
173 | u8 r = 0; | |
174 | u8 power; | |
175 | ||
176 | /* Make sure the transceiver is not in low power mode */ | |
177 | power = musb_readb(addr, MUSB_POWER); | |
178 | power &= ~MUSB_POWER_SUSPENDM; | |
179 | musb_writeb(addr, MUSB_POWER, power); | |
180 | ||
181 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset); | |
182 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data); | |
183 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); | |
184 | ||
185 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
186 | & MUSB_ULPI_REG_CMPLT)) { | |
187 | i++; | |
5c8a86e1 | 188 | if (i == 10000) |
ffb865b1 | 189 | return -ETIMEDOUT; |
ffb865b1 HK |
190 | } |
191 | ||
192 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
193 | r &= ~MUSB_ULPI_REG_CMPLT; | |
194 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | #else | |
f2263db7 MF |
199 | #define musb_ulpi_read NULL |
200 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
201 | #endif |
202 | ||
203 | static struct otg_io_access_ops musb_ulpi_access = { | |
204 | .read = musb_ulpi_read, | |
205 | .write = musb_ulpi_write, | |
206 | }; | |
207 | ||
208 | /*-------------------------------------------------------------------------*/ | |
209 | ||
7c925546 | 210 | #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN) |
c6cf8b00 | 211 | |
550a7375 FB |
212 | /* |
213 | * Load an endpoint's FIFO | |
214 | */ | |
215 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
216 | { | |
5c8a86e1 | 217 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
218 | void __iomem *fifo = hw_ep->fifo; |
219 | ||
220 | prefetch((u8 *)src); | |
221 | ||
5c8a86e1 | 222 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
223 | 'T', hw_ep->epnum, fifo, len, src); |
224 | ||
225 | /* we can't assume unaligned reads work */ | |
226 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
227 | u16 index = 0; | |
228 | ||
229 | /* best case is 32bit-aligned source address */ | |
230 | if ((0x02 & (unsigned long) src) == 0) { | |
231 | if (len >= 4) { | |
232 | writesl(fifo, src + index, len >> 2); | |
233 | index += len & ~0x03; | |
234 | } | |
235 | if (len & 0x02) { | |
236 | musb_writew(fifo, 0, *(u16 *)&src[index]); | |
237 | index += 2; | |
238 | } | |
239 | } else { | |
240 | if (len >= 2) { | |
241 | writesw(fifo, src + index, len >> 1); | |
242 | index += len & ~0x01; | |
243 | } | |
244 | } | |
245 | if (len & 0x01) | |
246 | musb_writeb(fifo, 0, src[index]); | |
247 | } else { | |
248 | /* byte aligned */ | |
249 | writesb(fifo, src, len); | |
250 | } | |
251 | } | |
252 | ||
843bb1d0 | 253 | #if !defined(CONFIG_USB_MUSB_AM35X) |
550a7375 FB |
254 | /* |
255 | * Unload an endpoint's FIFO | |
256 | */ | |
257 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
258 | { | |
5c8a86e1 | 259 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
260 | void __iomem *fifo = hw_ep->fifo; |
261 | ||
5c8a86e1 | 262 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
263 | 'R', hw_ep->epnum, fifo, len, dst); |
264 | ||
265 | /* we can't assume unaligned writes work */ | |
266 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
267 | u16 index = 0; | |
268 | ||
269 | /* best case is 32bit-aligned destination address */ | |
270 | if ((0x02 & (unsigned long) dst) == 0) { | |
271 | if (len >= 4) { | |
272 | readsl(fifo, dst, len >> 2); | |
273 | index = len & ~0x03; | |
274 | } | |
275 | if (len & 0x02) { | |
276 | *(u16 *)&dst[index] = musb_readw(fifo, 0); | |
277 | index += 2; | |
278 | } | |
279 | } else { | |
280 | if (len >= 2) { | |
281 | readsw(fifo, dst, len >> 1); | |
282 | index = len & ~0x01; | |
283 | } | |
284 | } | |
285 | if (len & 0x01) | |
286 | dst[index] = musb_readb(fifo, 0); | |
287 | } else { | |
288 | /* byte aligned */ | |
289 | readsb(fifo, dst, len); | |
290 | } | |
291 | } | |
843bb1d0 | 292 | #endif |
550a7375 FB |
293 | |
294 | #endif /* normal PIO */ | |
295 | ||
296 | ||
297 | /*-------------------------------------------------------------------------*/ | |
298 | ||
299 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
300 | static const u8 musb_test_packet[53] = { | |
301 | /* implicit SYNC then DATA0 to start */ | |
302 | ||
303 | /* JKJKJKJK x9 */ | |
304 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
305 | /* JJKKJJKK x8 */ | |
306 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
307 | /* JJJJKKKK x8 */ | |
308 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
309 | /* JJJJJJJKKKKKKK x8 */ | |
310 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
311 | /* JJJJJJJK x8 */ | |
312 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
313 | /* JKKKKKKK x10, JK */ | |
314 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
315 | ||
316 | /* implicit CRC16 then EOP to end */ | |
317 | }; | |
318 | ||
319 | void musb_load_testpacket(struct musb *musb) | |
320 | { | |
321 | void __iomem *regs = musb->endpoints[0].regs; | |
322 | ||
323 | musb_ep_select(musb->mregs, 0); | |
324 | musb_write_fifo(musb->control_ep, | |
325 | sizeof(musb_test_packet), musb_test_packet); | |
326 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
327 | } | |
328 | ||
329 | /*-------------------------------------------------------------------------*/ | |
330 | ||
550a7375 FB |
331 | /* |
332 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
333 | */ | |
334 | void musb_otg_timer_func(unsigned long data) | |
335 | { | |
336 | struct musb *musb = (struct musb *)data; | |
337 | unsigned long flags; | |
338 | ||
339 | spin_lock_irqsave(&musb->lock, flags); | |
84e250ff | 340 | switch (musb->xceiv->state) { |
550a7375 | 341 | case OTG_STATE_B_WAIT_ACON: |
5c8a86e1 | 342 | dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n"); |
550a7375 | 343 | musb_g_disconnect(musb); |
84e250ff | 344 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
345 | musb->is_active = 0; |
346 | break; | |
ab983f2a | 347 | case OTG_STATE_A_SUSPEND: |
550a7375 | 348 | case OTG_STATE_A_WAIT_BCON: |
5c8a86e1 | 349 | dev_dbg(musb->controller, "HNP: %s timeout\n", |
3df00453 | 350 | otg_state_string(musb->xceiv->state)); |
743411b3 | 351 | musb_platform_set_vbus(musb, 0); |
ab983f2a | 352 | musb->xceiv->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
353 | break; |
354 | default: | |
5c8a86e1 | 355 | dev_dbg(musb->controller, "HNP: Unhandled mode %s\n", |
3df00453 | 356 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
357 | } |
358 | musb->ignore_disconnect = 0; | |
359 | spin_unlock_irqrestore(&musb->lock, flags); | |
360 | } | |
361 | ||
550a7375 | 362 | /* |
f7f9d63e | 363 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
364 | */ |
365 | void musb_hnp_stop(struct musb *musb) | |
366 | { | |
367 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
368 | void __iomem *mbase = musb->mregs; | |
369 | u8 reg; | |
370 | ||
5c8a86e1 | 371 | dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state)); |
ab983f2a | 372 | |
84e250ff | 373 | switch (musb->xceiv->state) { |
550a7375 | 374 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 375 | musb_g_disconnect(musb); |
5c8a86e1 | 376 | dev_dbg(musb->controller, "HNP: back to %s\n", |
3df00453 | 377 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
378 | break; |
379 | case OTG_STATE_B_HOST: | |
5c8a86e1 | 380 | dev_dbg(musb->controller, "HNP: Disabling HR\n"); |
550a7375 | 381 | hcd->self.is_b_host = 0; |
84e250ff | 382 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
383 | MUSB_DEV_MODE(musb); |
384 | reg = musb_readb(mbase, MUSB_POWER); | |
385 | reg |= MUSB_POWER_SUSPENDM; | |
386 | musb_writeb(mbase, MUSB_POWER, reg); | |
387 | /* REVISIT: Start SESSION_REQUEST here? */ | |
388 | break; | |
389 | default: | |
5c8a86e1 | 390 | dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n", |
3df00453 | 391 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
392 | } |
393 | ||
394 | /* | |
395 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
396 | * which cause occasional OPT A "Did not receive reset after connect" | |
397 | * errors. | |
398 | */ | |
749da5f8 | 399 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
400 | } |
401 | ||
550a7375 FB |
402 | /* |
403 | * Interrupt Service Routine to record USB "global" interrupts. | |
404 | * Since these do not happen often and signify things of | |
405 | * paramount importance, it seems OK to check them individually; | |
406 | * the order of the tests is specified in the manual | |
407 | * | |
408 | * @param musb instance pointer | |
409 | * @param int_usb register contents | |
410 | * @param devctl | |
411 | * @param power | |
412 | */ | |
413 | ||
550a7375 FB |
414 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
415 | u8 devctl, u8 power) | |
416 | { | |
417 | irqreturn_t handled = IRQ_NONE; | |
550a7375 | 418 | |
5c8a86e1 | 419 | dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl, |
550a7375 FB |
420 | int_usb); |
421 | ||
422 | /* in host mode, the peripheral may issue remote wakeup. | |
423 | * in peripheral mode, the host may resume the link. | |
424 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
425 | */ | |
426 | if (int_usb & MUSB_INTR_RESUME) { | |
427 | handled = IRQ_HANDLED; | |
5c8a86e1 | 428 | dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
429 | |
430 | if (devctl & MUSB_DEVCTL_HM) { | |
aa471456 FB |
431 | void __iomem *mbase = musb->mregs; |
432 | ||
84e250ff | 433 | switch (musb->xceiv->state) { |
550a7375 FB |
434 | case OTG_STATE_A_SUSPEND: |
435 | /* remote wakeup? later, GetPortStatus | |
436 | * will stop RESUME signaling | |
437 | */ | |
438 | ||
439 | if (power & MUSB_POWER_SUSPENDM) { | |
440 | /* spurious */ | |
441 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
5c8a86e1 | 442 | dev_dbg(musb->controller, "Spurious SUSPENDM\n"); |
550a7375 FB |
443 | break; |
444 | } | |
445 | ||
446 | power &= ~MUSB_POWER_SUSPENDM; | |
447 | musb_writeb(mbase, MUSB_POWER, | |
448 | power | MUSB_POWER_RESUME); | |
449 | ||
450 | musb->port1_status |= | |
451 | (USB_PORT_STAT_C_SUSPEND << 16) | |
452 | | MUSB_PORT_STAT_RESUME; | |
453 | musb->rh_timer = jiffies | |
454 | + msecs_to_jiffies(20); | |
455 | ||
84e250ff | 456 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
457 | musb->is_active = 1; |
458 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
459 | break; | |
460 | case OTG_STATE_B_WAIT_ACON: | |
84e250ff | 461 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
462 | musb->is_active = 1; |
463 | MUSB_DEV_MODE(musb); | |
464 | break; | |
465 | default: | |
466 | WARNING("bogus %s RESUME (%s)\n", | |
467 | "host", | |
3df00453 | 468 | otg_state_string(musb->xceiv->state)); |
550a7375 | 469 | } |
550a7375 | 470 | } else { |
84e250ff | 471 | switch (musb->xceiv->state) { |
550a7375 FB |
472 | case OTG_STATE_A_SUSPEND: |
473 | /* possibly DISCONNECT is upcoming */ | |
84e250ff | 474 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
475 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); |
476 | break; | |
550a7375 FB |
477 | case OTG_STATE_B_WAIT_ACON: |
478 | case OTG_STATE_B_PERIPHERAL: | |
479 | /* disconnect while suspended? we may | |
480 | * not get a disconnect irq... | |
481 | */ | |
482 | if ((devctl & MUSB_DEVCTL_VBUS) | |
483 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
484 | ) { | |
485 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
486 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
487 | break; | |
488 | } | |
489 | musb_g_resume(musb); | |
490 | break; | |
491 | case OTG_STATE_B_IDLE: | |
492 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
493 | break; | |
550a7375 FB |
494 | default: |
495 | WARNING("bogus %s RESUME (%s)\n", | |
496 | "peripheral", | |
3df00453 | 497 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
498 | } |
499 | } | |
500 | } | |
501 | ||
550a7375 FB |
502 | /* see manual for the order of the tests */ |
503 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
504 | void __iomem *mbase = musb->mregs; |
505 | ||
19aab56c HK |
506 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
507 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
5c8a86e1 | 508 | dev_dbg(musb->controller, "SessReq while on B state\n"); |
a6038ee7 HK |
509 | return IRQ_HANDLED; |
510 | } | |
511 | ||
5c8a86e1 | 512 | dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n", |
3df00453 | 513 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
514 | |
515 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
516 | * is removed) SRP. responses are time critical: | |
517 | * - turn on VBUS (with silicon-specific mechanism) | |
518 | * - go through A_WAIT_VRISE | |
519 | * - ... to A_WAIT_BCON. | |
520 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
521 | */ | |
522 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
523 | musb->ep0_stage = MUSB_EP0_START; | |
84e250ff | 524 | musb->xceiv->state = OTG_STATE_A_IDLE; |
550a7375 | 525 | MUSB_HST_MODE(musb); |
743411b3 | 526 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
527 | |
528 | handled = IRQ_HANDLED; | |
529 | } | |
530 | ||
531 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
532 | int ignore = 0; | |
533 | ||
534 | /* During connection as an A-Device, we may see a short | |
535 | * current spikes causing voltage drop, because of cable | |
536 | * and peripheral capacitance combined with vbus draw. | |
537 | * (So: less common with truly self-powered devices, where | |
538 | * vbus doesn't act like a power supply.) | |
539 | * | |
540 | * Such spikes are short; usually less than ~500 usec, max | |
541 | * of ~2 msec. That is, they're not sustained overcurrent | |
542 | * errors, though they're reported using VBUSERROR irqs. | |
543 | * | |
544 | * Workarounds: (a) hardware: use self powered devices. | |
545 | * (b) software: ignore non-repeated VBUS errors. | |
546 | * | |
547 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
548 | * make trouble here, keeping VBUS < 4.4V ? | |
549 | */ | |
84e250ff | 550 | switch (musb->xceiv->state) { |
550a7375 FB |
551 | case OTG_STATE_A_HOST: |
552 | /* recovery is dicey once we've gotten past the | |
553 | * initial stages of enumeration, but if VBUS | |
554 | * stayed ok at the other end of the link, and | |
555 | * another reset is due (at least for high speed, | |
556 | * to redo the chirp etc), it might work OK... | |
557 | */ | |
558 | case OTG_STATE_A_WAIT_BCON: | |
559 | case OTG_STATE_A_WAIT_VRISE: | |
560 | if (musb->vbuserr_retry) { | |
aa471456 FB |
561 | void __iomem *mbase = musb->mregs; |
562 | ||
550a7375 FB |
563 | musb->vbuserr_retry--; |
564 | ignore = 1; | |
565 | devctl |= MUSB_DEVCTL_SESSION; | |
566 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
567 | } else { | |
568 | musb->port1_status |= | |
749da5f8 AS |
569 | USB_PORT_STAT_OVERCURRENT |
570 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
571 | } |
572 | break; | |
573 | default: | |
574 | break; | |
575 | } | |
576 | ||
5c8a86e1 | 577 | dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", |
3df00453 | 578 | otg_state_string(musb->xceiv->state), |
550a7375 FB |
579 | devctl, |
580 | ({ char *s; | |
581 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
582 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
583 | s = "<SessEnd"; break; | |
584 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
585 | s = "<AValid"; break; | |
586 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
587 | s = "<VBusValid"; break; | |
588 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
589 | default: | |
590 | s = "VALID"; break; | |
591 | }; s; }), | |
592 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, | |
593 | musb->port1_status); | |
594 | ||
595 | /* go through A_WAIT_VFALL then start a new session */ | |
596 | if (!ignore) | |
743411b3 | 597 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
598 | handled = IRQ_HANDLED; |
599 | } | |
600 | ||
1c25fda4 | 601 | if (int_usb & MUSB_INTR_SUSPEND) { |
5c8a86e1 | 602 | dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n", |
3df00453 | 603 | otg_state_string(musb->xceiv->state), devctl, power); |
1c25fda4 AM |
604 | handled = IRQ_HANDLED; |
605 | ||
606 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
607 | case OTG_STATE_A_PERIPHERAL: |
608 | /* We also come here if the cable is removed, since | |
609 | * this silicon doesn't report ID-no-longer-grounded. | |
610 | * | |
611 | * We depend on T(a_wait_bcon) to shut us down, and | |
612 | * hope users don't do anything dicey during this | |
613 | * undesired detour through A_WAIT_BCON. | |
614 | */ | |
615 | musb_hnp_stop(musb); | |
616 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
617 | musb_root_disconnect(musb); | |
618 | musb_platform_try_idle(musb, jiffies | |
619 | + msecs_to_jiffies(musb->a_wait_bcon | |
620 | ? : OTG_TIME_A_WAIT_BCON)); | |
621 | ||
622 | break; | |
1c25fda4 AM |
623 | case OTG_STATE_B_IDLE: |
624 | if (!musb->is_active) | |
625 | break; | |
626 | case OTG_STATE_B_PERIPHERAL: | |
627 | musb_g_suspend(musb); | |
628 | musb->is_active = is_otg_enabled(musb) | |
629 | && musb->xceiv->gadget->b_hnp_enable; | |
630 | if (musb->is_active) { | |
1c25fda4 | 631 | musb->xceiv->state = OTG_STATE_B_WAIT_ACON; |
5c8a86e1 | 632 | dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n"); |
1c25fda4 AM |
633 | mod_timer(&musb->otg_timer, jiffies |
634 | + msecs_to_jiffies( | |
635 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
636 | } |
637 | break; | |
638 | case OTG_STATE_A_WAIT_BCON: | |
639 | if (musb->a_wait_bcon != 0) | |
640 | musb_platform_try_idle(musb, jiffies | |
641 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
642 | break; | |
643 | case OTG_STATE_A_HOST: | |
644 | musb->xceiv->state = OTG_STATE_A_SUSPEND; | |
645 | musb->is_active = is_otg_enabled(musb) | |
646 | && musb->xceiv->host->b_hnp_enable; | |
647 | break; | |
648 | case OTG_STATE_B_HOST: | |
649 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
5c8a86e1 | 650 | dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n"); |
1c25fda4 AM |
651 | break; |
652 | default: | |
653 | /* "should not happen" */ | |
654 | musb->is_active = 0; | |
655 | break; | |
656 | } | |
657 | } | |
658 | ||
550a7375 FB |
659 | if (int_usb & MUSB_INTR_CONNECT) { |
660 | struct usb_hcd *hcd = musb_to_hcd(musb); | |
661 | ||
662 | handled = IRQ_HANDLED; | |
663 | musb->is_active = 1; | |
664 | set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags); | |
665 | ||
666 | musb->ep0_stage = MUSB_EP0_START; | |
667 | ||
550a7375 FB |
668 | /* flush endpoints when transitioning from Device Mode */ |
669 | if (is_peripheral_active(musb)) { | |
670 | /* REVISIT HNP; just force disconnect */ | |
671 | } | |
d709d22e AKG |
672 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask); |
673 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
674 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
675 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
676 | |USB_PORT_STAT_HIGH_SPEED | |
677 | |USB_PORT_STAT_ENABLE | |
678 | ); | |
679 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
680 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
681 | ||
682 | /* high vs full speed is just a guess until after reset */ | |
683 | if (devctl & MUSB_DEVCTL_LSDEV) | |
684 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
685 | ||
550a7375 | 686 | /* indicate new connection to OTG machine */ |
84e250ff | 687 | switch (musb->xceiv->state) { |
550a7375 FB |
688 | case OTG_STATE_B_PERIPHERAL: |
689 | if (int_usb & MUSB_INTR_SUSPEND) { | |
5c8a86e1 | 690 | dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n"); |
550a7375 | 691 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 692 | goto b_host; |
550a7375 | 693 | } else |
5c8a86e1 | 694 | dev_dbg(musb->controller, "CONNECT as b_peripheral???\n"); |
550a7375 FB |
695 | break; |
696 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 697 | dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n"); |
1de00dae | 698 | b_host: |
84e250ff | 699 | musb->xceiv->state = OTG_STATE_B_HOST; |
550a7375 | 700 | hcd->self.is_b_host = 1; |
1de00dae DB |
701 | musb->ignore_disconnect = 0; |
702 | del_timer(&musb->otg_timer); | |
550a7375 FB |
703 | break; |
704 | default: | |
705 | if ((devctl & MUSB_DEVCTL_VBUS) | |
706 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
84e250ff | 707 | musb->xceiv->state = OTG_STATE_A_HOST; |
550a7375 FB |
708 | hcd->self.is_b_host = 0; |
709 | } | |
710 | break; | |
711 | } | |
1de00dae DB |
712 | |
713 | /* poke the root hub */ | |
714 | MUSB_HST_MODE(musb); | |
715 | if (hcd->status_urb) | |
716 | usb_hcd_poll_rh_status(hcd); | |
717 | else | |
718 | usb_hcd_resume_root_hub(hcd); | |
719 | ||
5c8a86e1 | 720 | dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n", |
3df00453 | 721 | otg_state_string(musb->xceiv->state), devctl); |
550a7375 | 722 | } |
550a7375 | 723 | |
1c25fda4 | 724 | if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) { |
5c8a86e1 | 725 | dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n", |
3df00453 | 726 | otg_state_string(musb->xceiv->state), |
1c25fda4 AM |
727 | MUSB_MODE(musb), devctl); |
728 | handled = IRQ_HANDLED; | |
729 | ||
730 | switch (musb->xceiv->state) { | |
1c25fda4 AM |
731 | case OTG_STATE_A_HOST: |
732 | case OTG_STATE_A_SUSPEND: | |
733 | usb_hcd_resume_root_hub(musb_to_hcd(musb)); | |
734 | musb_root_disconnect(musb); | |
735 | if (musb->a_wait_bcon != 0 && is_otg_enabled(musb)) | |
736 | musb_platform_try_idle(musb, jiffies | |
737 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
738 | break; | |
1c25fda4 AM |
739 | case OTG_STATE_B_HOST: |
740 | /* REVISIT this behaves for "real disconnect" | |
741 | * cases; make sure the other transitions from | |
742 | * from B_HOST act right too. The B_HOST code | |
743 | * in hnp_stop() is currently not used... | |
744 | */ | |
745 | musb_root_disconnect(musb); | |
746 | musb_to_hcd(musb)->self.is_b_host = 0; | |
747 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; | |
748 | MUSB_DEV_MODE(musb); | |
749 | musb_g_disconnect(musb); | |
750 | break; | |
751 | case OTG_STATE_A_PERIPHERAL: | |
752 | musb_hnp_stop(musb); | |
753 | musb_root_disconnect(musb); | |
754 | /* FALLTHROUGH */ | |
755 | case OTG_STATE_B_WAIT_ACON: | |
756 | /* FALLTHROUGH */ | |
1c25fda4 AM |
757 | case OTG_STATE_B_PERIPHERAL: |
758 | case OTG_STATE_B_IDLE: | |
759 | musb_g_disconnect(musb); | |
760 | break; | |
1c25fda4 AM |
761 | default: |
762 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
3df00453 | 763 | otg_state_string(musb->xceiv->state)); |
1c25fda4 AM |
764 | break; |
765 | } | |
766 | } | |
767 | ||
550a7375 FB |
768 | /* mentor saves a bit: bus reset and babble share the same irq. |
769 | * only host sees babble; only peripheral sees bus reset. | |
770 | */ | |
771 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 772 | handled = IRQ_HANDLED; |
550a7375 FB |
773 | if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) { |
774 | /* | |
775 | * Looks like non-HS BABBLE can be ignored, but | |
776 | * HS BABBLE is an error condition. For HS the solution | |
777 | * is to avoid babble in the first place and fix what | |
778 | * caused BABBLE. When HS BABBLE happens we can only | |
779 | * stop the session. | |
780 | */ | |
781 | if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV)) | |
5c8a86e1 | 782 | dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl); |
550a7375 FB |
783 | else { |
784 | ERR("Stopping host session -- babble\n"); | |
1c25fda4 | 785 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
550a7375 FB |
786 | } |
787 | } else if (is_peripheral_capable()) { | |
5c8a86e1 | 788 | dev_dbg(musb->controller, "BUS RESET as %s\n", |
3df00453 | 789 | otg_state_string(musb->xceiv->state)); |
84e250ff | 790 | switch (musb->xceiv->state) { |
550a7375 FB |
791 | case OTG_STATE_A_SUSPEND: |
792 | /* We need to ignore disconnect on suspend | |
793 | * otherwise tusb 2.0 won't reconnect after a | |
794 | * power cycle, which breaks otg compliance. | |
795 | */ | |
796 | musb->ignore_disconnect = 1; | |
797 | musb_g_reset(musb); | |
798 | /* FALLTHROUGH */ | |
799 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 800 | /* never use invalid T(a_wait_bcon) */ |
5c8a86e1 | 801 | dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n", |
3df00453 AG |
802 | otg_state_string(musb->xceiv->state), |
803 | TA_WAIT_BCON(musb)); | |
f7f9d63e DB |
804 | mod_timer(&musb->otg_timer, jiffies |
805 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
806 | break; |
807 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
808 | musb->ignore_disconnect = 0; |
809 | del_timer(&musb->otg_timer); | |
810 | musb_g_reset(musb); | |
550a7375 FB |
811 | break; |
812 | case OTG_STATE_B_WAIT_ACON: | |
5c8a86e1 | 813 | dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n", |
3df00453 | 814 | otg_state_string(musb->xceiv->state)); |
84e250ff | 815 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
816 | musb_g_reset(musb); |
817 | break; | |
550a7375 | 818 | case OTG_STATE_B_IDLE: |
84e250ff | 819 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
820 | /* FALLTHROUGH */ |
821 | case OTG_STATE_B_PERIPHERAL: | |
822 | musb_g_reset(musb); | |
823 | break; | |
824 | default: | |
5c8a86e1 | 825 | dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n", |
3df00453 | 826 | otg_state_string(musb->xceiv->state)); |
550a7375 FB |
827 | } |
828 | } | |
550a7375 | 829 | } |
550a7375 FB |
830 | |
831 | #if 0 | |
832 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
833 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
834 | * limits of a given frame or microframe. | |
835 | * | |
836 | * It's not needed for peripheral side, which dedicates endpoints; | |
837 | * though it _might_ use SOF irqs for other purposes. | |
838 | * | |
839 | * And it's not currently needed for host side, which also dedicates | |
840 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
841 | * to support ISO transfers yet. | |
842 | */ | |
843 | if (int_usb & MUSB_INTR_SOF) { | |
844 | void __iomem *mbase = musb->mregs; | |
845 | struct musb_hw_ep *ep; | |
846 | u8 epnum; | |
847 | u16 frame; | |
848 | ||
5c8a86e1 | 849 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
850 | handled = IRQ_HANDLED; |
851 | ||
852 | /* start any periodic Tx transfers waiting for current frame */ | |
853 | frame = musb_readw(mbase, MUSB_FRAME); | |
854 | ep = musb->endpoints; | |
855 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
856 | && (musb->epmask >= (1 << epnum)); | |
857 | epnum++, ep++) { | |
858 | /* | |
859 | * FIXME handle framecounter wraps (12 bits) | |
860 | * eliminate duplicated StartUrb logic | |
861 | */ | |
862 | if (ep->dwWaitFrame >= frame) { | |
863 | ep->dwWaitFrame = 0; | |
864 | pr_debug("SOF --> periodic TX%s on %d\n", | |
865 | ep->tx_channel ? " DMA" : "", | |
866 | epnum); | |
867 | if (!ep->tx_channel) | |
868 | musb_h_tx_start(musb, epnum); | |
869 | else | |
870 | cppi_hostdma_start(musb, epnum); | |
871 | } | |
872 | } /* end of for loop */ | |
873 | } | |
874 | #endif | |
875 | ||
1c25fda4 | 876 | schedule_work(&musb->irq_work); |
550a7375 FB |
877 | |
878 | return handled; | |
879 | } | |
880 | ||
881 | /*-------------------------------------------------------------------------*/ | |
882 | ||
883 | /* | |
884 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
885 | */ | |
886 | void musb_start(struct musb *musb) | |
887 | { | |
888 | void __iomem *regs = musb->mregs; | |
889 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
890 | ||
5c8a86e1 | 891 | dev_dbg(musb->controller, "<== devctl %02x\n", devctl); |
550a7375 FB |
892 | |
893 | /* Set INT enable registers, enable interrupts */ | |
894 | musb_writew(regs, MUSB_INTRTXE, musb->epmask); | |
895 | musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe); | |
896 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
897 | ||
898 | musb_writeb(regs, MUSB_TESTMODE, 0); | |
899 | ||
900 | /* put into basic highspeed mode and start session */ | |
901 | musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE | |
902 | | MUSB_POWER_SOFTCONN | |
903 | | MUSB_POWER_HSENAB | |
904 | /* ENSUSPEND wedges tusb */ | |
905 | /* | MUSB_POWER_ENSUSPEND */ | |
906 | ); | |
907 | ||
908 | musb->is_active = 0; | |
909 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
910 | devctl &= ~MUSB_DEVCTL_SESSION; | |
911 | ||
912 | if (is_otg_enabled(musb)) { | |
913 | /* session started after: | |
914 | * (a) ID-grounded irq, host mode; | |
915 | * (b) vbus present/connect IRQ, peripheral mode; | |
916 | * (c) peripheral initiates, using SRP | |
917 | */ | |
918 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
919 | musb->is_active = 1; | |
920 | else | |
921 | devctl |= MUSB_DEVCTL_SESSION; | |
922 | ||
923 | } else if (is_host_enabled(musb)) { | |
924 | /* assume ID pin is hard-wired to ground */ | |
925 | devctl |= MUSB_DEVCTL_SESSION; | |
926 | ||
927 | } else /* peripheral is enabled */ { | |
928 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) | |
929 | musb->is_active = 1; | |
930 | } | |
931 | musb_platform_enable(musb); | |
932 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
933 | } | |
934 | ||
935 | ||
936 | static void musb_generic_disable(struct musb *musb) | |
937 | { | |
938 | void __iomem *mbase = musb->mregs; | |
939 | u16 temp; | |
940 | ||
941 | /* disable interrupts */ | |
942 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
943 | musb_writew(mbase, MUSB_INTRTXE, 0); | |
944 | musb_writew(mbase, MUSB_INTRRXE, 0); | |
945 | ||
946 | /* off */ | |
947 | musb_writeb(mbase, MUSB_DEVCTL, 0); | |
948 | ||
949 | /* flush pending interrupts */ | |
950 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
951 | temp = musb_readw(mbase, MUSB_INTRTX); | |
952 | temp = musb_readw(mbase, MUSB_INTRRX); | |
953 | ||
954 | } | |
955 | ||
956 | /* | |
957 | * Make the HDRC stop (disable interrupts, etc.); | |
958 | * reversible by musb_start | |
959 | * called on gadget driver unregister | |
960 | * with controller locked, irqs blocked | |
961 | * acts as a NOP unless some role activated the hardware | |
962 | */ | |
963 | void musb_stop(struct musb *musb) | |
964 | { | |
965 | /* stop IRQs, timers, ... */ | |
966 | musb_platform_disable(musb); | |
967 | musb_generic_disable(musb); | |
5c8a86e1 | 968 | dev_dbg(musb->controller, "HDRC disabled\n"); |
550a7375 FB |
969 | |
970 | /* FIXME | |
971 | * - mark host and/or peripheral drivers unusable/inactive | |
972 | * - disable DMA (and enable it in HdrcStart) | |
973 | * - make sure we can musb_start() after musb_stop(); with | |
974 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
975 | * - ... | |
976 | */ | |
977 | musb_platform_try_idle(musb, 0); | |
978 | } | |
979 | ||
980 | static void musb_shutdown(struct platform_device *pdev) | |
981 | { | |
982 | struct musb *musb = dev_to_musb(&pdev->dev); | |
983 | unsigned long flags; | |
984 | ||
4f9edd2d | 985 | pm_runtime_get_sync(musb->controller); |
550a7375 FB |
986 | spin_lock_irqsave(&musb->lock, flags); |
987 | musb_platform_disable(musb); | |
988 | musb_generic_disable(musb); | |
550a7375 FB |
989 | spin_unlock_irqrestore(&musb->lock, flags); |
990 | ||
120d074c GI |
991 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) |
992 | usb_remove_hcd(musb_to_hcd(musb)); | |
993 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
994 | musb_platform_exit(musb); | |
120d074c | 995 | |
4f9edd2d | 996 | pm_runtime_put(musb->controller); |
550a7375 FB |
997 | /* FIXME power down */ |
998 | } | |
999 | ||
1000 | ||
1001 | /*-------------------------------------------------------------------------*/ | |
1002 | ||
1003 | /* | |
1004 | * The silicon either has hard-wired endpoint configurations, or else | |
1005 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1006 | * writing only the dynamic sizing is very well tested. Since we switched |
1007 | * away from compile-time hardware parameters, we can no longer rely on | |
1008 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1009 | * |
1010 | * We don't currently use dynamic fifo setup capability to do anything | |
1011 | * more than selecting one of a bunch of predefined configurations. | |
1012 | */ | |
ee34e51a FB |
1013 | #if defined(CONFIG_USB_MUSB_TUSB6010) \ |
1014 | || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \ | |
1015 | || defined(CONFIG_USB_MUSB_OMAP2PLUS) \ | |
1016 | || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \ | |
1017 | || defined(CONFIG_USB_MUSB_AM35X) \ | |
1018 | || defined(CONFIG_USB_MUSB_AM35X_MODULE) | |
550a7375 | 1019 | static ushort __initdata fifo_mode = 4; |
ee34e51a FB |
1020 | #elif defined(CONFIG_USB_MUSB_UX500) \ |
1021 | || defined(CONFIG_USB_MUSB_UX500_MODULE) | |
4bc36fd3 | 1022 | static ushort __initdata fifo_mode = 5; |
550a7375 FB |
1023 | #else |
1024 | static ushort __initdata fifo_mode = 2; | |
1025 | #endif | |
1026 | ||
1027 | /* "modprobe ... fifo_mode=1" etc */ | |
1028 | module_param(fifo_mode, ushort, 0); | |
1029 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1030 | ||
550a7375 FB |
1031 | /* |
1032 | * tables defining fifo_mode values. define more if you like. | |
1033 | * for host side, make sure both halves of ep1 are set up. | |
1034 | */ | |
1035 | ||
1036 | /* mode 0 - fits in 2KB */ | |
e6c213b2 | 1037 | static struct musb_fifo_cfg __initdata mode_0_cfg[] = { |
550a7375 FB |
1038 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1039 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1040 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1041 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1042 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1043 | }; | |
1044 | ||
1045 | /* mode 1 - fits in 4KB */ | |
e6c213b2 | 1046 | static struct musb_fifo_cfg __initdata mode_1_cfg[] = { |
550a7375 FB |
1047 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1048 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1049 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1050 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1051 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1052 | }; | |
1053 | ||
1054 | /* mode 2 - fits in 4KB */ | |
e6c213b2 | 1055 | static struct musb_fifo_cfg __initdata mode_2_cfg[] = { |
550a7375 FB |
1056 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1057 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1058 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1059 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1060 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1061 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1062 | }; | |
1063 | ||
1064 | /* mode 3 - fits in 4KB */ | |
e6c213b2 | 1065 | static struct musb_fifo_cfg __initdata mode_3_cfg[] = { |
550a7375 FB |
1066 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1067 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1068 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1069 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1070 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1071 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1072 | }; | |
1073 | ||
1074 | /* mode 4 - fits in 16KB */ | |
e6c213b2 | 1075 | static struct musb_fifo_cfg __initdata mode_4_cfg[] = { |
550a7375 FB |
1076 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1077 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1078 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1079 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1080 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1081 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1082 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1083 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1084 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1085 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1086 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1087 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1088 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1089 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1090 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1091 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1092 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1093 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1094 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1095 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1096 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1097 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1098 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1099 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1100 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1101 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1102 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1103 | }; | |
1104 | ||
3b151526 | 1105 | /* mode 5 - fits in 8KB */ |
e6c213b2 | 1106 | static struct musb_fifo_cfg __initdata mode_5_cfg[] = { |
3b151526 AKG |
1107 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1108 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1109 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1110 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1111 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1112 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1114 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1115 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1116 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1117 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1118 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1119 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1120 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1121 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1122 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1123 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1124 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1125 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1126 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1127 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1128 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1129 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1130 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1131 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1132 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1133 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1134 | }; | |
550a7375 FB |
1135 | |
1136 | /* | |
1137 | * configure a fifo; for non-shared endpoints, this may be called | |
1138 | * once for a tx fifo and once for an rx fifo. | |
1139 | * | |
1140 | * returns negative errno or offset for next fifo. | |
1141 | */ | |
1142 | static int __init | |
1143 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, | |
e6c213b2 | 1144 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1145 | { |
1146 | void __iomem *mbase = musb->mregs; | |
1147 | int size = 0; | |
1148 | u16 maxpacket = cfg->maxpacket; | |
1149 | u16 c_off = offset >> 3; | |
1150 | u8 c_size; | |
1151 | ||
1152 | /* expect hw_ep has already been zero-initialized */ | |
1153 | ||
1154 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1155 | maxpacket = 1 << size; | |
1156 | ||
1157 | c_size = size - 3; | |
1158 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1159 | if ((offset + (maxpacket << 1)) > |
1160 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1161 | return -EMSGSIZE; |
1162 | c_size |= MUSB_FIFOSZ_DPB; | |
1163 | } else { | |
ca6d1b13 | 1164 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1165 | return -EMSGSIZE; |
1166 | } | |
1167 | ||
1168 | /* configure the FIFO */ | |
1169 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1170 | ||
550a7375 FB |
1171 | /* EP0 reserved endpoint for control, bidirectional; |
1172 | * EP1 reserved for bulk, two unidirection halves. | |
1173 | */ | |
1174 | if (hw_ep->epnum == 1) | |
1175 | musb->bulk_ep = hw_ep; | |
1176 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1177 | switch (cfg->style) { |
1178 | case FIFO_TX: | |
c6cf8b00 BW |
1179 | musb_write_txfifosz(mbase, c_size); |
1180 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1181 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1182 | hw_ep->max_packet_sz_tx = maxpacket; | |
1183 | break; | |
1184 | case FIFO_RX: | |
c6cf8b00 BW |
1185 | musb_write_rxfifosz(mbase, c_size); |
1186 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1187 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1188 | hw_ep->max_packet_sz_rx = maxpacket; | |
1189 | break; | |
1190 | case FIFO_RXTX: | |
c6cf8b00 BW |
1191 | musb_write_txfifosz(mbase, c_size); |
1192 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1193 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1194 | hw_ep->max_packet_sz_rx = maxpacket; | |
1195 | ||
c6cf8b00 BW |
1196 | musb_write_rxfifosz(mbase, c_size); |
1197 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1198 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1199 | hw_ep->max_packet_sz_tx = maxpacket; | |
1200 | ||
1201 | hw_ep->is_shared_fifo = true; | |
1202 | break; | |
1203 | } | |
1204 | ||
1205 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1206 | * which happens to be ok | |
1207 | */ | |
1208 | musb->epmask |= (1 << hw_ep->epnum); | |
1209 | ||
1210 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1211 | } | |
1212 | ||
e6c213b2 | 1213 | static struct musb_fifo_cfg __initdata ep0_cfg = { |
550a7375 FB |
1214 | .style = FIFO_RXTX, .maxpacket = 64, |
1215 | }; | |
1216 | ||
1217 | static int __init ep_config_from_table(struct musb *musb) | |
1218 | { | |
e6c213b2 | 1219 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1220 | unsigned i, n; |
1221 | int offset; | |
1222 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1223 | ||
e6c213b2 FB |
1224 | if (musb->config->fifo_cfg) { |
1225 | cfg = musb->config->fifo_cfg; | |
1226 | n = musb->config->fifo_cfg_size; | |
1227 | goto done; | |
1228 | } | |
1229 | ||
550a7375 FB |
1230 | switch (fifo_mode) { |
1231 | default: | |
1232 | fifo_mode = 0; | |
1233 | /* FALLTHROUGH */ | |
1234 | case 0: | |
1235 | cfg = mode_0_cfg; | |
1236 | n = ARRAY_SIZE(mode_0_cfg); | |
1237 | break; | |
1238 | case 1: | |
1239 | cfg = mode_1_cfg; | |
1240 | n = ARRAY_SIZE(mode_1_cfg); | |
1241 | break; | |
1242 | case 2: | |
1243 | cfg = mode_2_cfg; | |
1244 | n = ARRAY_SIZE(mode_2_cfg); | |
1245 | break; | |
1246 | case 3: | |
1247 | cfg = mode_3_cfg; | |
1248 | n = ARRAY_SIZE(mode_3_cfg); | |
1249 | break; | |
1250 | case 4: | |
1251 | cfg = mode_4_cfg; | |
1252 | n = ARRAY_SIZE(mode_4_cfg); | |
1253 | break; | |
3b151526 AKG |
1254 | case 5: |
1255 | cfg = mode_5_cfg; | |
1256 | n = ARRAY_SIZE(mode_5_cfg); | |
1257 | break; | |
550a7375 FB |
1258 | } |
1259 | ||
1260 | printk(KERN_DEBUG "%s: setup fifo_mode %d\n", | |
1261 | musb_driver_name, fifo_mode); | |
1262 | ||
1263 | ||
e6c213b2 | 1264 | done: |
550a7375 FB |
1265 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1266 | /* assert(offset > 0) */ | |
1267 | ||
1268 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1269 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1270 | */ |
1271 | ||
1272 | for (i = 0; i < n; i++) { | |
1273 | u8 epn = cfg->hw_ep_num; | |
1274 | ||
ca6d1b13 | 1275 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1276 | pr_debug("%s: invalid ep %d\n", |
1277 | musb_driver_name, epn); | |
bb1c9ef1 | 1278 | return -EINVAL; |
550a7375 FB |
1279 | } |
1280 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1281 | if (offset < 0) { | |
1282 | pr_debug("%s: mem overrun, ep %d\n", | |
1283 | musb_driver_name, epn); | |
1284 | return -EINVAL; | |
1285 | } | |
1286 | epn++; | |
1287 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1288 | } | |
1289 | ||
1290 | printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n", | |
1291 | musb_driver_name, | |
ca6d1b13 FB |
1292 | n + 1, musb->config->num_eps * 2 - 1, |
1293 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1294 | |
550a7375 FB |
1295 | if (!musb->bulk_ep) { |
1296 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1297 | return -EINVAL; | |
1298 | } | |
550a7375 FB |
1299 | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | ||
1304 | /* | |
1305 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1306 | * @param musb the controller | |
1307 | */ | |
1308 | static int __init ep_config_from_hw(struct musb *musb) | |
1309 | { | |
c6cf8b00 | 1310 | u8 epnum = 0; |
550a7375 FB |
1311 | struct musb_hw_ep *hw_ep; |
1312 | void *mbase = musb->mregs; | |
c6cf8b00 | 1313 | int ret = 0; |
550a7375 | 1314 | |
5c8a86e1 | 1315 | dev_dbg(musb->controller, "<== static silicon ep config\n"); |
550a7375 FB |
1316 | |
1317 | /* FIXME pick up ep0 maxpacket size */ | |
1318 | ||
ca6d1b13 | 1319 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1320 | musb_ep_select(mbase, epnum); |
1321 | hw_ep = musb->endpoints + epnum; | |
1322 | ||
c6cf8b00 BW |
1323 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1324 | if (ret < 0) | |
550a7375 | 1325 | break; |
550a7375 FB |
1326 | |
1327 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1328 | ||
550a7375 FB |
1329 | /* pick an RX/TX endpoint for bulk */ |
1330 | if (hw_ep->max_packet_sz_tx < 512 | |
1331 | || hw_ep->max_packet_sz_rx < 512) | |
1332 | continue; | |
1333 | ||
1334 | /* REVISIT: this algorithm is lazy, we should at least | |
1335 | * try to pick a double buffered endpoint. | |
1336 | */ | |
1337 | if (musb->bulk_ep) | |
1338 | continue; | |
1339 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1340 | } |
1341 | ||
550a7375 FB |
1342 | if (!musb->bulk_ep) { |
1343 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1344 | return -EINVAL; | |
1345 | } | |
550a7375 FB |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | ||
1350 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1351 | ||
1352 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1353 | * configure endpoints, or take their config from silicon | |
1354 | */ | |
1355 | static int __init musb_core_init(u16 musb_type, struct musb *musb) | |
1356 | { | |
550a7375 FB |
1357 | u8 reg; |
1358 | char *type; | |
0ea52ff4 | 1359 | char aInfo[90], aRevision[32], aDate[12]; |
550a7375 FB |
1360 | void __iomem *mbase = musb->mregs; |
1361 | int status = 0; | |
1362 | int i; | |
1363 | ||
1364 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1365 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1366 | |
1367 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1368 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1369 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1370 | musb->dyn_fifo = true; |
1371 | } | |
550a7375 FB |
1372 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1373 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1374 | musb->bulk_combine = true; |
550a7375 FB |
1375 | } |
1376 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1377 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1378 | musb->bulk_split = true; |
550a7375 FB |
1379 | } |
1380 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1381 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1382 | musb->hb_iso_rx = true; |
550a7375 FB |
1383 | } |
1384 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1385 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1386 | musb->hb_iso_tx = true; |
550a7375 FB |
1387 | } |
1388 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1389 | strcat(aInfo, ", SoftConn"); | |
1390 | ||
1391 | printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n", | |
1392 | musb_driver_name, reg, aInfo); | |
1393 | ||
550a7375 | 1394 | aDate[0] = 0; |
550a7375 FB |
1395 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1396 | musb->is_multipoint = 1; | |
1397 | type = "M"; | |
1398 | } else { | |
1399 | musb->is_multipoint = 0; | |
1400 | type = ""; | |
550a7375 FB |
1401 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
1402 | printk(KERN_ERR | |
1403 | "%s: kernel must blacklist external hubs\n", | |
1404 | musb_driver_name); | |
550a7375 FB |
1405 | #endif |
1406 | } | |
1407 | ||
1408 | /* log release info */ | |
32c3b94e AG |
1409 | musb->hwvers = musb_read_hwvers(mbase); |
1410 | snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers), | |
1411 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1412 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1413 | printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n", |
1414 | musb_driver_name, type, aRevision, aDate); | |
1415 | ||
1416 | /* configure ep0 */ | |
c6cf8b00 | 1417 | musb_configure_ep0(musb); |
550a7375 FB |
1418 | |
1419 | /* discover endpoint configuration */ | |
1420 | musb->nr_endpoints = 1; | |
1421 | musb->epmask = 1; | |
1422 | ||
ad517e9e FB |
1423 | if (musb->dyn_fifo) |
1424 | status = ep_config_from_table(musb); | |
1425 | else | |
1426 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1427 | |
1428 | if (status < 0) | |
1429 | return status; | |
1430 | ||
1431 | /* finish init, and print endpoint config */ | |
1432 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1433 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1434 | ||
1435 | hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase; | |
7c925546 | 1436 | #ifdef CONFIG_USB_MUSB_TUSB6010 |
550a7375 FB |
1437 | hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i); |
1438 | hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i); | |
1439 | hw_ep->fifo_sync_va = | |
1440 | musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i); | |
1441 | ||
1442 | if (i == 0) | |
1443 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1444 | else | |
1445 | hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2); | |
1446 | #endif | |
1447 | ||
1448 | hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase; | |
c6cf8b00 | 1449 | hw_ep->target_regs = musb_read_target_reg_base(i, mbase); |
550a7375 FB |
1450 | hw_ep->rx_reinit = 1; |
1451 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1452 | |
1453 | if (hw_ep->max_packet_sz_tx) { | |
5c8a86e1 | 1454 | dev_dbg(musb->controller, |
550a7375 FB |
1455 | "%s: hw_ep %d%s, %smax %d\n", |
1456 | musb_driver_name, i, | |
1457 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1458 | hw_ep->tx_double_buffered | |
1459 | ? "doublebuffer, " : "", | |
1460 | hw_ep->max_packet_sz_tx); | |
1461 | } | |
1462 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
5c8a86e1 | 1463 | dev_dbg(musb->controller, |
550a7375 FB |
1464 | "%s: hw_ep %d%s, %smax %d\n", |
1465 | musb_driver_name, i, | |
1466 | "rx", | |
1467 | hw_ep->rx_double_buffered | |
1468 | ? "doublebuffer, " : "", | |
1469 | hw_ep->max_packet_sz_rx); | |
1470 | } | |
1471 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
5c8a86e1 | 1472 | dev_dbg(musb->controller, "hw_ep %d not configured\n", i); |
550a7375 FB |
1473 | } |
1474 | ||
1475 | return 0; | |
1476 | } | |
1477 | ||
1478 | /*-------------------------------------------------------------------------*/ | |
1479 | ||
59b479e0 | 1480 | #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \ |
4bc36fd3 MYK |
1481 | defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \ |
1482 | defined(CONFIG_ARCH_U5500) | |
550a7375 FB |
1483 | |
1484 | static irqreturn_t generic_interrupt(int irq, void *__hci) | |
1485 | { | |
1486 | unsigned long flags; | |
1487 | irqreturn_t retval = IRQ_NONE; | |
1488 | struct musb *musb = __hci; | |
1489 | ||
1490 | spin_lock_irqsave(&musb->lock, flags); | |
1491 | ||
1492 | musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB); | |
1493 | musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX); | |
1494 | musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX); | |
1495 | ||
1496 | if (musb->int_usb || musb->int_tx || musb->int_rx) | |
1497 | retval = musb_interrupt(musb); | |
1498 | ||
1499 | spin_unlock_irqrestore(&musb->lock, flags); | |
1500 | ||
a5073b52 | 1501 | return retval; |
550a7375 FB |
1502 | } |
1503 | ||
1504 | #else | |
1505 | #define generic_interrupt NULL | |
1506 | #endif | |
1507 | ||
1508 | /* | |
1509 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1510 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1511 | * will be assigned, and the irq will already have been acked. | |
1512 | * | |
1513 | * called in irq context with spinlock held, irqs blocked | |
1514 | */ | |
1515 | irqreturn_t musb_interrupt(struct musb *musb) | |
1516 | { | |
1517 | irqreturn_t retval = IRQ_NONE; | |
1518 | u8 devctl, power; | |
1519 | int ep_num; | |
1520 | u32 reg; | |
1521 | ||
1522 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1523 | power = musb_readb(musb->mregs, MUSB_POWER); | |
1524 | ||
5c8a86e1 | 1525 | dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n", |
550a7375 FB |
1526 | (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral", |
1527 | musb->int_usb, musb->int_tx, musb->int_rx); | |
1528 | ||
cd42fef0 FB |
1529 | if (is_otg_enabled(musb) || is_peripheral_enabled(musb)) |
1530 | if (!musb->gadget_driver) { | |
5c8a86e1 | 1531 | dev_dbg(musb->controller, "No gadget driver loaded\n"); |
cd42fef0 FB |
1532 | return IRQ_HANDLED; |
1533 | } | |
cd42fef0 | 1534 | |
550a7375 FB |
1535 | /* the core can interrupt us for multiple reasons; docs have |
1536 | * a generic interrupt flowchart to follow | |
1537 | */ | |
7d9645fd | 1538 | if (musb->int_usb) |
550a7375 FB |
1539 | retval |= musb_stage0_irq(musb, musb->int_usb, |
1540 | devctl, power); | |
1541 | ||
1542 | /* "stage 1" is handling endpoint irqs */ | |
1543 | ||
1544 | /* handle endpoint 0 first */ | |
1545 | if (musb->int_tx & 1) { | |
1546 | if (devctl & MUSB_DEVCTL_HM) | |
1547 | retval |= musb_h_ep0_irq(musb); | |
1548 | else | |
1549 | retval |= musb_g_ep0_irq(musb); | |
1550 | } | |
1551 | ||
1552 | /* RX on endpoints 1-15 */ | |
1553 | reg = musb->int_rx >> 1; | |
1554 | ep_num = 1; | |
1555 | while (reg) { | |
1556 | if (reg & 1) { | |
1557 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1558 | /* REVISIT just retval = ep->rx_irq(...) */ | |
1559 | retval = IRQ_HANDLED; | |
1560 | if (devctl & MUSB_DEVCTL_HM) { | |
1561 | if (is_host_capable()) | |
1562 | musb_host_rx(musb, ep_num); | |
1563 | } else { | |
1564 | if (is_peripheral_capable()) | |
1565 | musb_g_rx(musb, ep_num); | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | reg >>= 1; | |
1570 | ep_num++; | |
1571 | } | |
1572 | ||
1573 | /* TX on endpoints 1-15 */ | |
1574 | reg = musb->int_tx >> 1; | |
1575 | ep_num = 1; | |
1576 | while (reg) { | |
1577 | if (reg & 1) { | |
1578 | /* musb_ep_select(musb->mregs, ep_num); */ | |
1579 | /* REVISIT just retval |= ep->tx_irq(...) */ | |
1580 | retval = IRQ_HANDLED; | |
1581 | if (devctl & MUSB_DEVCTL_HM) { | |
1582 | if (is_host_capable()) | |
1583 | musb_host_tx(musb, ep_num); | |
1584 | } else { | |
1585 | if (is_peripheral_capable()) | |
1586 | musb_g_tx(musb, ep_num); | |
1587 | } | |
1588 | } | |
1589 | reg >>= 1; | |
1590 | ep_num++; | |
1591 | } | |
1592 | ||
550a7375 FB |
1593 | return retval; |
1594 | } | |
981430a1 | 1595 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1596 | |
1597 | #ifndef CONFIG_MUSB_PIO_ONLY | |
1598 | static int __initdata use_dma = 1; | |
1599 | ||
1600 | /* "modprobe ... use_dma=0" etc */ | |
1601 | module_param(use_dma, bool, 0); | |
1602 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); | |
1603 | ||
1604 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1605 | { | |
1606 | u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1607 | ||
1608 | /* called with controller lock already held */ | |
1609 | ||
1610 | if (!epnum) { | |
1611 | #ifndef CONFIG_USB_TUSB_OMAP_DMA | |
1612 | if (!is_cppi_enabled()) { | |
1613 | /* endpoint 0 */ | |
1614 | if (devctl & MUSB_DEVCTL_HM) | |
1615 | musb_h_ep0_irq(musb); | |
1616 | else | |
1617 | musb_g_ep0_irq(musb); | |
1618 | } | |
1619 | #endif | |
1620 | } else { | |
1621 | /* endpoints 1..15 */ | |
1622 | if (transmit) { | |
1623 | if (devctl & MUSB_DEVCTL_HM) { | |
1624 | if (is_host_capable()) | |
1625 | musb_host_tx(musb, epnum); | |
1626 | } else { | |
1627 | if (is_peripheral_capable()) | |
1628 | musb_g_tx(musb, epnum); | |
1629 | } | |
1630 | } else { | |
1631 | /* receive */ | |
1632 | if (devctl & MUSB_DEVCTL_HM) { | |
1633 | if (is_host_capable()) | |
1634 | musb_host_rx(musb, epnum); | |
1635 | } else { | |
1636 | if (is_peripheral_capable()) | |
1637 | musb_g_rx(musb, epnum); | |
1638 | } | |
1639 | } | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | #else | |
1644 | #define use_dma 0 | |
1645 | #endif | |
1646 | ||
1647 | /*-------------------------------------------------------------------------*/ | |
1648 | ||
1649 | #ifdef CONFIG_SYSFS | |
1650 | ||
1651 | static ssize_t | |
1652 | musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1653 | { | |
1654 | struct musb *musb = dev_to_musb(dev); | |
1655 | unsigned long flags; | |
1656 | int ret = -EINVAL; | |
1657 | ||
1658 | spin_lock_irqsave(&musb->lock, flags); | |
3df00453 | 1659 | ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state)); |
550a7375 FB |
1660 | spin_unlock_irqrestore(&musb->lock, flags); |
1661 | ||
1662 | return ret; | |
1663 | } | |
1664 | ||
1665 | static ssize_t | |
1666 | musb_mode_store(struct device *dev, struct device_attribute *attr, | |
1667 | const char *buf, size_t n) | |
1668 | { | |
1669 | struct musb *musb = dev_to_musb(dev); | |
1670 | unsigned long flags; | |
96a274d1 | 1671 | int status; |
550a7375 FB |
1672 | |
1673 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1674 | if (sysfs_streq(buf, "host")) |
1675 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1676 | else if (sysfs_streq(buf, "peripheral")) | |
1677 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1678 | else if (sysfs_streq(buf, "otg")) | |
1679 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1680 | else | |
1681 | status = -EINVAL; | |
550a7375 FB |
1682 | spin_unlock_irqrestore(&musb->lock, flags); |
1683 | ||
96a274d1 | 1684 | return (status == 0) ? n : status; |
550a7375 FB |
1685 | } |
1686 | static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store); | |
1687 | ||
1688 | static ssize_t | |
1689 | musb_vbus_store(struct device *dev, struct device_attribute *attr, | |
1690 | const char *buf, size_t n) | |
1691 | { | |
1692 | struct musb *musb = dev_to_musb(dev); | |
1693 | unsigned long flags; | |
1694 | unsigned long val; | |
1695 | ||
1696 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1697 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1698 | return -EINVAL; |
1699 | } | |
1700 | ||
1701 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1702 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1703 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
84e250ff | 1704 | if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1705 | musb->is_active = 0; |
1706 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1707 | spin_unlock_irqrestore(&musb->lock, flags); | |
1708 | ||
1709 | return n; | |
1710 | } | |
1711 | ||
1712 | static ssize_t | |
1713 | musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf) | |
1714 | { | |
1715 | struct musb *musb = dev_to_musb(dev); | |
1716 | unsigned long flags; | |
1717 | unsigned long val; | |
1718 | int vbus; | |
1719 | ||
1720 | spin_lock_irqsave(&musb->lock, flags); | |
1721 | val = musb->a_wait_bcon; | |
f7f9d63e DB |
1722 | /* FIXME get_vbus_status() is normally #defined as false... |
1723 | * and is effectively TUSB-specific. | |
1724 | */ | |
550a7375 FB |
1725 | vbus = musb_platform_get_vbus_status(musb); |
1726 | spin_unlock_irqrestore(&musb->lock, flags); | |
1727 | ||
f7f9d63e | 1728 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1729 | vbus ? "on" : "off", val); |
1730 | } | |
1731 | static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store); | |
1732 | ||
550a7375 FB |
1733 | /* Gadget drivers can't know that a host is connected so they might want |
1734 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1735 | */ | |
1736 | static ssize_t | |
1737 | musb_srp_store(struct device *dev, struct device_attribute *attr, | |
1738 | const char *buf, size_t n) | |
1739 | { | |
1740 | struct musb *musb = dev_to_musb(dev); | |
1741 | unsigned short srp; | |
1742 | ||
1743 | if (sscanf(buf, "%hu", &srp) != 1 | |
1744 | || (srp != 1)) { | |
b3b1cc3b | 1745 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1746 | return -EINVAL; |
1747 | } | |
1748 | ||
1749 | if (srp == 1) | |
1750 | musb_g_wakeup(musb); | |
1751 | ||
1752 | return n; | |
1753 | } | |
1754 | static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store); | |
1755 | ||
94375751 FB |
1756 | static struct attribute *musb_attributes[] = { |
1757 | &dev_attr_mode.attr, | |
1758 | &dev_attr_vbus.attr, | |
94375751 | 1759 | &dev_attr_srp.attr, |
94375751 FB |
1760 | NULL |
1761 | }; | |
1762 | ||
1763 | static const struct attribute_group musb_attr_group = { | |
1764 | .attrs = musb_attributes, | |
1765 | }; | |
1766 | ||
550a7375 FB |
1767 | #endif /* sysfs */ |
1768 | ||
1769 | /* Only used to provide driver mode change events */ | |
1770 | static void musb_irq_work(struct work_struct *data) | |
1771 | { | |
1772 | struct musb *musb = container_of(data, struct musb, irq_work); | |
1773 | static int old_state; | |
1774 | ||
84e250ff DB |
1775 | if (musb->xceiv->state != old_state) { |
1776 | old_state = musb->xceiv->state; | |
550a7375 FB |
1777 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1778 | } | |
1779 | } | |
1780 | ||
1781 | /* -------------------------------------------------------------------------- | |
1782 | * Init support | |
1783 | */ | |
1784 | ||
1785 | static struct musb *__init | |
ca6d1b13 FB |
1786 | allocate_instance(struct device *dev, |
1787 | struct musb_hdrc_config *config, void __iomem *mbase) | |
550a7375 FB |
1788 | { |
1789 | struct musb *musb; | |
1790 | struct musb_hw_ep *ep; | |
1791 | int epnum; | |
550a7375 FB |
1792 | struct usb_hcd *hcd; |
1793 | ||
427c4f33 | 1794 | hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev)); |
550a7375 FB |
1795 | if (!hcd) |
1796 | return NULL; | |
1797 | /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */ | |
1798 | ||
1799 | musb = hcd_to_musb(hcd); | |
1800 | INIT_LIST_HEAD(&musb->control); | |
1801 | INIT_LIST_HEAD(&musb->in_bulk); | |
1802 | INIT_LIST_HEAD(&musb->out_bulk); | |
1803 | ||
1804 | hcd->uses_new_polling = 1; | |
ec95d35a | 1805 | hcd->has_tt = 1; |
550a7375 FB |
1806 | |
1807 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; | |
f7f9d63e | 1808 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
456bb169 | 1809 | dev_set_drvdata(dev, musb); |
550a7375 FB |
1810 | musb->mregs = mbase; |
1811 | musb->ctrl_base = mbase; | |
1812 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1813 | musb->config = config; |
02582b92 | 1814 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1815 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1816 | epnum < musb->config->num_eps; |
550a7375 | 1817 | epnum++, ep++) { |
550a7375 FB |
1818 | ep->musb = musb; |
1819 | ep->epnum = epnum; | |
1820 | } | |
1821 | ||
1822 | musb->controller = dev; | |
743411b3 | 1823 | |
550a7375 FB |
1824 | return musb; |
1825 | } | |
1826 | ||
1827 | static void musb_free(struct musb *musb) | |
1828 | { | |
1829 | /* this has multiple entry modes. it handles fault cleanup after | |
1830 | * probe(), where things may be partially set up, as well as rmmod | |
1831 | * cleanup after everything's been de-activated. | |
1832 | */ | |
1833 | ||
1834 | #ifdef CONFIG_SYSFS | |
94375751 | 1835 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
1836 | #endif |
1837 | ||
550a7375 | 1838 | musb_gadget_cleanup(musb); |
550a7375 | 1839 | |
97a39896 AKG |
1840 | if (musb->nIrq >= 0) { |
1841 | if (musb->irq_wake) | |
1842 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
1843 | free_irq(musb->nIrq, musb); |
1844 | } | |
1845 | if (is_dma_capable() && musb->dma_controller) { | |
1846 | struct dma_controller *c = musb->dma_controller; | |
1847 | ||
1848 | (void) c->stop(c); | |
1849 | dma_controller_destroy(c); | |
1850 | } | |
1851 | ||
550a7375 | 1852 | kfree(musb); |
550a7375 FB |
1853 | } |
1854 | ||
1855 | /* | |
1856 | * Perform generic per-controller initialization. | |
1857 | * | |
1858 | * @pDevice: the controller (already clocked, etc) | |
1859 | * @nIrq: irq | |
1860 | * @mregs: virtual address of controller registers, | |
1861 | * not yet corrected for platform-specific offsets | |
1862 | */ | |
1863 | static int __init | |
1864 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) | |
1865 | { | |
1866 | int status; | |
1867 | struct musb *musb; | |
1868 | struct musb_hdrc_platform_data *plat = dev->platform_data; | |
1869 | ||
1870 | /* The driver might handle more features than the board; OK. | |
1871 | * Fail when the board needs a feature that's not enabled. | |
1872 | */ | |
1873 | if (!plat) { | |
1874 | dev_dbg(dev, "no platform_data?\n"); | |
34e2beb2 SS |
1875 | status = -ENODEV; |
1876 | goto fail0; | |
550a7375 | 1877 | } |
34e2beb2 | 1878 | |
550a7375 | 1879 | /* allocate */ |
ca6d1b13 | 1880 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
1881 | if (!musb) { |
1882 | status = -ENOMEM; | |
1883 | goto fail0; | |
1884 | } | |
550a7375 | 1885 | |
7acc6197 HH |
1886 | pm_runtime_use_autosuspend(musb->controller); |
1887 | pm_runtime_set_autosuspend_delay(musb->controller, 200); | |
1888 | pm_runtime_enable(musb->controller); | |
1889 | ||
550a7375 FB |
1890 | spin_lock_init(&musb->lock); |
1891 | musb->board_mode = plat->mode; | |
1892 | musb->board_set_power = plat->set_power; | |
550a7375 | 1893 | musb->min_power = plat->min_power; |
f7ec9437 | 1894 | musb->ops = plat->platform_ops; |
550a7375 | 1895 | |
84e250ff DB |
1896 | /* The musb_platform_init() call: |
1897 | * - adjusts musb->mregs and musb->isr if needed, | |
1898 | * - may initialize an integrated tranceiver | |
1899 | * - initializes musb->xceiv, usually by otg_get_transceiver() | |
84e250ff | 1900 | * - stops powering VBUS |
84e250ff DB |
1901 | * |
1902 | * There are various transciever configurations. Blackfin, | |
1903 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses | |
1904 | * external/discrete ones in various flavors (twl4030 family, | |
1905 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 FB |
1906 | */ |
1907 | musb->isr = generic_interrupt; | |
ea65df57 | 1908 | status = musb_platform_init(musb); |
550a7375 | 1909 | if (status < 0) |
03491761 | 1910 | goto fail1; |
34e2beb2 | 1911 | |
550a7375 FB |
1912 | if (!musb->isr) { |
1913 | status = -ENODEV; | |
34e2beb2 | 1914 | goto fail3; |
550a7375 FB |
1915 | } |
1916 | ||
ffb865b1 HK |
1917 | if (!musb->xceiv->io_ops) { |
1918 | musb->xceiv->io_priv = musb->mregs; | |
1919 | musb->xceiv->io_ops = &musb_ulpi_access; | |
1920 | } | |
1921 | ||
550a7375 FB |
1922 | #ifndef CONFIG_MUSB_PIO_ONLY |
1923 | if (use_dma && dev->dma_mask) { | |
1924 | struct dma_controller *c; | |
1925 | ||
1926 | c = dma_controller_create(musb, musb->mregs); | |
1927 | musb->dma_controller = c; | |
1928 | if (c) | |
1929 | (void) c->start(c); | |
1930 | } | |
1931 | #endif | |
1932 | /* ideally this would be abstracted in platform setup */ | |
1933 | if (!is_dma_capable() || !musb->dma_controller) | |
1934 | dev->dma_mask = NULL; | |
1935 | ||
1936 | /* be sure interrupts are disabled before connecting ISR */ | |
1937 | musb_platform_disable(musb); | |
1938 | musb_generic_disable(musb); | |
1939 | ||
1940 | /* setup musb parts of the core (especially endpoints) */ | |
ca6d1b13 | 1941 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
1942 | ? MUSB_CONTROLLER_MHDRC |
1943 | : MUSB_CONTROLLER_HDRC, musb); | |
1944 | if (status < 0) | |
34e2beb2 | 1945 | goto fail3; |
550a7375 | 1946 | |
f7f9d63e | 1947 | setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb); |
f7f9d63e | 1948 | |
550a7375 FB |
1949 | /* Init IRQ workqueue before request_irq */ |
1950 | INIT_WORK(&musb->irq_work, musb_irq_work); | |
1951 | ||
1952 | /* attach to the IRQ */ | |
427c4f33 | 1953 | if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) { |
550a7375 FB |
1954 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
1955 | status = -ENODEV; | |
34e2beb2 | 1956 | goto fail3; |
550a7375 FB |
1957 | } |
1958 | musb->nIrq = nIrq; | |
1959 | /* FIXME this handles wakeup irqs wrong */ | |
c48a5155 FB |
1960 | if (enable_irq_wake(nIrq) == 0) { |
1961 | musb->irq_wake = 1; | |
550a7375 | 1962 | device_init_wakeup(dev, 1); |
c48a5155 FB |
1963 | } else { |
1964 | musb->irq_wake = 0; | |
1965 | } | |
550a7375 | 1966 | |
84e250ff DB |
1967 | /* host side needs more setup */ |
1968 | if (is_host_enabled(musb)) { | |
550a7375 FB |
1969 | struct usb_hcd *hcd = musb_to_hcd(musb); |
1970 | ||
84e250ff DB |
1971 | otg_set_host(musb->xceiv, &hcd->self); |
1972 | ||
1973 | if (is_otg_enabled(musb)) | |
550a7375 | 1974 | hcd->self.otg_port = 1; |
84e250ff | 1975 | musb->xceiv->host = &hcd->self; |
550a7375 | 1976 | hcd->power_budget = 2 * (plat->power ? : 250); |
5fc4e779 AKG |
1977 | |
1978 | /* program PHY to use external vBus if required */ | |
1979 | if (plat->extvbus) { | |
adb3ee42 | 1980 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); |
5fc4e779 | 1981 | busctl |= MUSB_ULPI_USE_EXTVBUS; |
adb3ee42 | 1982 | musb_write_ulpi_buscontrol(musb->mregs, busctl); |
5fc4e779 | 1983 | } |
550a7375 | 1984 | } |
550a7375 FB |
1985 | |
1986 | /* For the host-only role, we can activate right away. | |
1987 | * (We expect the ID pin to be forcibly grounded!!) | |
1988 | * Otherwise, wait till the gadget driver hooks up. | |
1989 | */ | |
1990 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) { | |
07a8cdd2 AG |
1991 | struct usb_hcd *hcd = musb_to_hcd(musb); |
1992 | ||
550a7375 | 1993 | MUSB_HST_MODE(musb); |
84e250ff DB |
1994 | musb->xceiv->default_a = 1; |
1995 | musb->xceiv->state = OTG_STATE_A_IDLE; | |
550a7375 FB |
1996 | |
1997 | status = usb_add_hcd(musb_to_hcd(musb), -1, 0); | |
1998 | ||
07a8cdd2 | 1999 | hcd->self.uses_pio_for_control = 1; |
5c8a86e1 | 2000 | dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n", |
550a7375 FB |
2001 | "HOST", status, |
2002 | musb_readb(musb->mregs, MUSB_DEVCTL), | |
2003 | (musb_readb(musb->mregs, MUSB_DEVCTL) | |
2004 | & MUSB_DEVCTL_BDEVICE | |
2005 | ? 'B' : 'A')); | |
2006 | ||
2007 | } else /* peripheral is enabled */ { | |
2008 | MUSB_DEV_MODE(musb); | |
84e250ff DB |
2009 | musb->xceiv->default_a = 0; |
2010 | musb->xceiv->state = OTG_STATE_B_IDLE; | |
550a7375 FB |
2011 | |
2012 | status = musb_gadget_setup(musb); | |
2013 | ||
5c8a86e1 | 2014 | dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n", |
550a7375 FB |
2015 | is_otg_enabled(musb) ? "OTG" : "PERIPHERAL", |
2016 | status, | |
2017 | musb_readb(musb->mregs, MUSB_DEVCTL)); | |
2018 | ||
2019 | } | |
461972d8 | 2020 | if (status < 0) |
34e2beb2 | 2021 | goto fail3; |
550a7375 | 2022 | |
7acc6197 HH |
2023 | pm_runtime_put(musb->controller); |
2024 | ||
7f7f9e2a FB |
2025 | status = musb_init_debugfs(musb); |
2026 | if (status < 0) | |
b0f9da7e | 2027 | goto fail4; |
7f7f9e2a | 2028 | |
550a7375 | 2029 | #ifdef CONFIG_SYSFS |
94375751 | 2030 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 2031 | if (status) |
b0f9da7e | 2032 | goto fail5; |
461972d8 | 2033 | #endif |
550a7375 | 2034 | |
ab3bbfa1 FB |
2035 | dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n", |
2036 | ({char *s; | |
2037 | switch (musb->board_mode) { | |
2038 | case MUSB_HOST: s = "Host"; break; | |
2039 | case MUSB_PERIPHERAL: s = "Peripheral"; break; | |
2040 | default: s = "OTG"; break; | |
2041 | }; s; }), | |
2042 | ctrl, | |
2043 | (is_dma_capable() && musb->dma_controller) | |
2044 | ? "DMA" : "PIO", | |
2045 | musb->nIrq); | |
2046 | ||
28c2c51c | 2047 | return 0; |
550a7375 | 2048 | |
b0f9da7e FB |
2049 | fail5: |
2050 | musb_exit_debugfs(musb); | |
2051 | ||
34e2beb2 SS |
2052 | fail4: |
2053 | if (!is_otg_enabled(musb) && is_host_enabled(musb)) | |
2054 | usb_remove_hcd(musb_to_hcd(musb)); | |
2055 | else | |
2056 | musb_gadget_cleanup(musb); | |
2057 | ||
2058 | fail3: | |
2059 | if (musb->irq_wake) | |
2060 | device_init_wakeup(dev, 0); | |
550a7375 | 2061 | musb_platform_exit(musb); |
28c2c51c | 2062 | |
34e2beb2 SS |
2063 | fail1: |
2064 | dev_err(musb->controller, | |
2065 | "musb_init_controller failed with status %d\n", status); | |
2066 | ||
28c2c51c FB |
2067 | musb_free(musb); |
2068 | ||
34e2beb2 SS |
2069 | fail0: |
2070 | ||
28c2c51c FB |
2071 | return status; |
2072 | ||
550a7375 FB |
2073 | } |
2074 | ||
2075 | /*-------------------------------------------------------------------------*/ | |
2076 | ||
2077 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2078 | * bridge to a platform device; this driver then suffices. | |
2079 | */ | |
2080 | ||
2081 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2082 | static u64 *orig_dma_mask; | |
2083 | #endif | |
2084 | ||
2085 | static int __init musb_probe(struct platform_device *pdev) | |
2086 | { | |
2087 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2088 | int irq = platform_get_irq_byname(pdev, "mc"); |
da5108e1 | 2089 | int status; |
550a7375 FB |
2090 | struct resource *iomem; |
2091 | void __iomem *base; | |
2092 | ||
2093 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
541079de | 2094 | if (!iomem || irq <= 0) |
550a7375 FB |
2095 | return -ENODEV; |
2096 | ||
195e9e46 | 2097 | base = ioremap(iomem->start, resource_size(iomem)); |
550a7375 FB |
2098 | if (!base) { |
2099 | dev_err(dev, "ioremap failed\n"); | |
2100 | return -ENOMEM; | |
2101 | } | |
2102 | ||
2103 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2104 | /* clobbered by use_dma=n */ | |
2105 | orig_dma_mask = dev->dma_mask; | |
2106 | #endif | |
da5108e1 FB |
2107 | status = musb_init_controller(dev, irq, base); |
2108 | if (status < 0) | |
2109 | iounmap(base); | |
2110 | ||
2111 | return status; | |
550a7375 FB |
2112 | } |
2113 | ||
e3060b17 | 2114 | static int __exit musb_remove(struct platform_device *pdev) |
550a7375 FB |
2115 | { |
2116 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2117 | void __iomem *ctrl_base = musb->ctrl_base; | |
2118 | ||
2119 | /* this gets called on rmmod. | |
2120 | * - Host mode: host may still be active | |
2121 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2122 | * - OTG mode: both roles are deactivated (or never-activated) | |
2123 | */ | |
7acc6197 | 2124 | pm_runtime_get_sync(musb->controller); |
7f7f9e2a | 2125 | musb_exit_debugfs(musb); |
550a7375 | 2126 | musb_shutdown(pdev); |
461972d8 | 2127 | |
7acc6197 | 2128 | pm_runtime_put(musb->controller); |
550a7375 FB |
2129 | musb_free(musb); |
2130 | iounmap(ctrl_base); | |
2131 | device_init_wakeup(&pdev->dev, 0); | |
2132 | #ifndef CONFIG_MUSB_PIO_ONLY | |
2133 | pdev->dev.dma_mask = orig_dma_mask; | |
2134 | #endif | |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | #ifdef CONFIG_PM | |
2139 | ||
3c8a5fcc | 2140 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2141 | { |
2142 | int i; | |
2143 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2144 | void __iomem *epio; |
4f712e01 AKG |
2145 | |
2146 | if (is_host_enabled(musb)) { | |
7421107b FB |
2147 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2148 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2149 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
4f712e01 | 2150 | } |
7421107b FB |
2151 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
2152 | musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE); | |
2153 | musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE); | |
2154 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); | |
2155 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2156 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2157 | |
ae9b2ad2 | 2158 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2159 | struct musb_hw_ep *hw_ep; |
2160 | ||
2161 | hw_ep = &musb->endpoints[i]; | |
2162 | if (!hw_ep) | |
2163 | continue; | |
2164 | ||
2165 | epio = hw_ep->regs; | |
2166 | if (!epio) | |
2167 | continue; | |
2168 | ||
7421107b | 2169 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2170 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2171 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2172 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2173 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2174 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2175 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2176 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2177 | |
2178 | if (musb->dyn_fifo) { | |
7421107b | 2179 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2180 | musb_read_txfifoadd(musb_base); |
7421107b | 2181 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2182 | musb_read_rxfifoadd(musb_base); |
7421107b | 2183 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2184 | musb_read_txfifosz(musb_base); |
7421107b | 2185 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2186 | musb_read_rxfifosz(musb_base); |
2187 | } | |
2188 | if (is_host_enabled(musb)) { | |
7421107b | 2189 | musb->context.index_regs[i].txtype = |
ae9b2ad2 | 2190 | musb_readb(epio, MUSB_TXTYPE); |
7421107b | 2191 | musb->context.index_regs[i].txinterval = |
ae9b2ad2 | 2192 | musb_readb(epio, MUSB_TXINTERVAL); |
7421107b | 2193 | musb->context.index_regs[i].rxtype = |
ae9b2ad2 | 2194 | musb_readb(epio, MUSB_RXTYPE); |
7421107b | 2195 | musb->context.index_regs[i].rxinterval = |
ae9b2ad2 | 2196 | musb_readb(epio, MUSB_RXINTERVAL); |
4f712e01 | 2197 | |
7421107b | 2198 | musb->context.index_regs[i].txfunaddr = |
4f712e01 | 2199 | musb_read_txfunaddr(musb_base, i); |
7421107b | 2200 | musb->context.index_regs[i].txhubaddr = |
4f712e01 | 2201 | musb_read_txhubaddr(musb_base, i); |
7421107b | 2202 | musb->context.index_regs[i].txhubport = |
4f712e01 AKG |
2203 | musb_read_txhubport(musb_base, i); |
2204 | ||
7421107b | 2205 | musb->context.index_regs[i].rxfunaddr = |
4f712e01 | 2206 | musb_read_rxfunaddr(musb_base, i); |
7421107b | 2207 | musb->context.index_regs[i].rxhubaddr = |
4f712e01 | 2208 | musb_read_rxhubaddr(musb_base, i); |
7421107b | 2209 | musb->context.index_regs[i].rxhubport = |
4f712e01 AKG |
2210 | musb_read_rxhubport(musb_base, i); |
2211 | } | |
2212 | } | |
4f712e01 AKG |
2213 | } |
2214 | ||
3c8a5fcc | 2215 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2216 | { |
2217 | int i; | |
2218 | void __iomem *musb_base = musb->mregs; | |
2219 | void __iomem *ep_target_regs; | |
ae9b2ad2 | 2220 | void __iomem *epio; |
4f712e01 | 2221 | |
4f712e01 | 2222 | if (is_host_enabled(musb)) { |
7421107b FB |
2223 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2224 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2225 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
4f712e01 | 2226 | } |
7421107b FB |
2227 | musb_writeb(musb_base, MUSB_POWER, musb->context.power); |
2228 | musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe); | |
2229 | musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe); | |
2230 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); | |
2231 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2232 | |
ae9b2ad2 | 2233 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2234 | struct musb_hw_ep *hw_ep; |
2235 | ||
2236 | hw_ep = &musb->endpoints[i]; | |
2237 | if (!hw_ep) | |
2238 | continue; | |
2239 | ||
2240 | epio = hw_ep->regs; | |
2241 | if (!epio) | |
2242 | continue; | |
2243 | ||
ae9b2ad2 | 2244 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2245 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2246 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2247 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2248 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2249 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2250 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2251 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2252 | |
2253 | if (musb->dyn_fifo) { | |
2254 | musb_write_txfifosz(musb_base, | |
7421107b | 2255 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2256 | musb_write_rxfifosz(musb_base, |
7421107b | 2257 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2258 | musb_write_txfifoadd(musb_base, |
7421107b | 2259 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2260 | musb_write_rxfifoadd(musb_base, |
7421107b | 2261 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2262 | } |
2263 | ||
2264 | if (is_host_enabled(musb)) { | |
ae9b2ad2 | 2265 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2266 | musb->context.index_regs[i].txtype); |
ae9b2ad2 | 2267 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2268 | musb->context.index_regs[i].txinterval); |
ae9b2ad2 | 2269 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2270 | musb->context.index_regs[i].rxtype); |
ae9b2ad2 | 2271 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2272 | |
7421107b | 2273 | musb->context.index_regs[i].rxinterval); |
4f712e01 | 2274 | musb_write_txfunaddr(musb_base, i, |
7421107b | 2275 | musb->context.index_regs[i].txfunaddr); |
4f712e01 | 2276 | musb_write_txhubaddr(musb_base, i, |
7421107b | 2277 | musb->context.index_regs[i].txhubaddr); |
4f712e01 | 2278 | musb_write_txhubport(musb_base, i, |
7421107b | 2279 | musb->context.index_regs[i].txhubport); |
4f712e01 AKG |
2280 | |
2281 | ep_target_regs = | |
2282 | musb_read_target_reg_base(i, musb_base); | |
2283 | ||
2284 | musb_write_rxfunaddr(ep_target_regs, | |
7421107b | 2285 | musb->context.index_regs[i].rxfunaddr); |
4f712e01 | 2286 | musb_write_rxhubaddr(ep_target_regs, |
7421107b | 2287 | musb->context.index_regs[i].rxhubaddr); |
4f712e01 | 2288 | musb_write_rxhubport(ep_target_regs, |
7421107b | 2289 | musb->context.index_regs[i].rxhubport); |
4f712e01 AKG |
2290 | } |
2291 | } | |
4f712e01 AKG |
2292 | } |
2293 | ||
48fea965 | 2294 | static int musb_suspend(struct device *dev) |
550a7375 | 2295 | { |
48fea965 | 2296 | struct platform_device *pdev = to_platform_device(dev); |
550a7375 FB |
2297 | unsigned long flags; |
2298 | struct musb *musb = dev_to_musb(&pdev->dev); | |
2299 | ||
550a7375 FB |
2300 | spin_lock_irqsave(&musb->lock, flags); |
2301 | ||
2302 | if (is_peripheral_active(musb)) { | |
2303 | /* FIXME force disconnect unless we know USB will wake | |
2304 | * the system up quickly enough to respond ... | |
2305 | */ | |
2306 | } else if (is_host_active(musb)) { | |
2307 | /* we know all the children are suspended; sometimes | |
2308 | * they will even be wakeup-enabled. | |
2309 | */ | |
2310 | } | |
2311 | ||
4f712e01 AKG |
2312 | musb_save_context(musb); |
2313 | ||
550a7375 FB |
2314 | spin_unlock_irqrestore(&musb->lock, flags); |
2315 | return 0; | |
2316 | } | |
2317 | ||
48fea965 | 2318 | static int musb_resume_noirq(struct device *dev) |
550a7375 | 2319 | { |
48fea965 | 2320 | struct platform_device *pdev = to_platform_device(dev); |
550a7375 FB |
2321 | struct musb *musb = dev_to_musb(&pdev->dev); |
2322 | ||
4f712e01 AKG |
2323 | musb_restore_context(musb); |
2324 | ||
550a7375 | 2325 | /* for static cmos like DaVinci, register values were preserved |
0ec8fd70 KK |
2326 | * unless for some reason the whole soc powered down or the USB |
2327 | * module got reset through the PSC (vs just being disabled). | |
550a7375 | 2328 | */ |
550a7375 FB |
2329 | return 0; |
2330 | } | |
2331 | ||
7acc6197 HH |
2332 | static int musb_runtime_suspend(struct device *dev) |
2333 | { | |
2334 | struct musb *musb = dev_to_musb(dev); | |
2335 | ||
2336 | musb_save_context(musb); | |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | static int musb_runtime_resume(struct device *dev) | |
2342 | { | |
2343 | struct musb *musb = dev_to_musb(dev); | |
2344 | static int first = 1; | |
2345 | ||
2346 | /* | |
2347 | * When pm_runtime_get_sync called for the first time in driver | |
2348 | * init, some of the structure is still not initialized which is | |
2349 | * used in restore function. But clock needs to be | |
2350 | * enabled before any register access, so | |
2351 | * pm_runtime_get_sync has to be called. | |
2352 | * Also context restore without save does not make | |
2353 | * any sense | |
2354 | */ | |
2355 | if (!first) | |
2356 | musb_restore_context(musb); | |
2357 | first = 0; | |
2358 | ||
2359 | return 0; | |
2360 | } | |
2361 | ||
47145210 | 2362 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 MD |
2363 | .suspend = musb_suspend, |
2364 | .resume_noirq = musb_resume_noirq, | |
7acc6197 HH |
2365 | .runtime_suspend = musb_runtime_suspend, |
2366 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2367 | }; |
2368 | ||
2369 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2370 | #else |
48fea965 | 2371 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2372 | #endif |
2373 | ||
2374 | static struct platform_driver musb_driver = { | |
2375 | .driver = { | |
2376 | .name = (char *)musb_driver_name, | |
2377 | .bus = &platform_bus_type, | |
2378 | .owner = THIS_MODULE, | |
48fea965 | 2379 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2380 | }, |
e3060b17 | 2381 | .remove = __exit_p(musb_remove), |
550a7375 | 2382 | .shutdown = musb_shutdown, |
550a7375 FB |
2383 | }; |
2384 | ||
2385 | /*-------------------------------------------------------------------------*/ | |
2386 | ||
2387 | static int __init musb_init(void) | |
2388 | { | |
550a7375 FB |
2389 | if (usb_disabled()) |
2390 | return 0; | |
550a7375 FB |
2391 | |
2392 | pr_info("%s: version " MUSB_VERSION ", " | |
550a7375 | 2393 | "?dma?" |
550a7375 | 2394 | ", " |
62285963 | 2395 | "otg (peripheral+host)", |
5c8a86e1 | 2396 | musb_driver_name); |
550a7375 FB |
2397 | return platform_driver_probe(&musb_driver, musb_probe); |
2398 | } | |
2399 | ||
34f32c97 DB |
2400 | /* make us init after usbcore and i2c (transceivers, regulators, etc) |
2401 | * and before usb gadget and host-side drivers start to register | |
550a7375 | 2402 | */ |
34f32c97 | 2403 | fs_initcall(musb_init); |
550a7375 FB |
2404 | |
2405 | static void __exit musb_cleanup(void) | |
2406 | { | |
2407 | platform_driver_unregister(&musb_driver); | |
2408 | } | |
2409 | module_exit(musb_cleanup); |