Commit | Line | Data |
---|---|---|
5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
550a7375 FB |
2 | /* |
3 | * MUSB OTG driver core code | |
4 | * | |
5 | * Copyright 2005 Mentor Graphics Corporation | |
6 | * Copyright (C) 2005-2006 by Texas Instruments | |
7 | * Copyright (C) 2006-2007 Nokia Corporation | |
550a7375 FB |
8 | */ |
9 | ||
10 | /* | |
11 | * Inventra (Multipoint) Dual-Role Controller Driver for Linux. | |
12 | * | |
13 | * This consists of a Host Controller Driver (HCD) and a peripheral | |
14 | * controller driver implementing the "Gadget" API; OTG support is | |
15 | * in the works. These are normal Linux-USB controller drivers which | |
16 | * use IRQs and have no dedicated thread. | |
17 | * | |
18 | * This version of the driver has only been used with products from | |
19 | * Texas Instruments. Those products integrate the Inventra logic | |
20 | * with other DMA, IRQ, and bus modules, as well as other logic that | |
21 | * needs to be reflected in this driver. | |
22 | * | |
23 | * | |
24 | * NOTE: the original Mentor code here was pretty much a collection | |
25 | * of mechanisms that don't seem to have been fully integrated/working | |
26 | * for *any* Linux kernel version. This version aims at Linux 2.6.now, | |
27 | * Key open issues include: | |
28 | * | |
29 | * - Lack of host-side transaction scheduling, for all transfer types. | |
30 | * The hardware doesn't do it; instead, software must. | |
31 | * | |
32 | * This is not an issue for OTG devices that don't support external | |
33 | * hubs, but for more "normal" USB hosts it's a user issue that the | |
34 | * "multipoint" support doesn't scale in the expected ways. That | |
35 | * includes DaVinci EVM in a common non-OTG mode. | |
36 | * | |
37 | * * Control and bulk use dedicated endpoints, and there's as | |
38 | * yet no mechanism to either (a) reclaim the hardware when | |
39 | * peripherals are NAKing, which gets complicated with bulk | |
40 | * endpoints, or (b) use more than a single bulk endpoint in | |
41 | * each direction. | |
42 | * | |
43 | * RESULT: one device may be perceived as blocking another one. | |
44 | * | |
45 | * * Interrupt and isochronous will dynamically allocate endpoint | |
46 | * hardware, but (a) there's no record keeping for bandwidth; | |
47 | * (b) in the common case that few endpoints are available, there | |
48 | * is no mechanism to reuse endpoints to talk to multiple devices. | |
49 | * | |
50 | * RESULT: At one extreme, bandwidth can be overcommitted in | |
51 | * some hardware configurations, no faults will be reported. | |
52 | * At the other extreme, the bandwidth capabilities which do | |
53 | * exist tend to be severely undercommitted. You can't yet hook | |
54 | * up both a keyboard and a mouse to an external USB hub. | |
55 | */ | |
56 | ||
57 | /* | |
58 | * This gets many kinds of configuration information: | |
59 | * - Kconfig for everything user-configurable | |
550a7375 | 60 | * - platform_device for addressing, irq, and platform_data |
5ae477b0 | 61 | * - platform_data is mostly for board-specific information |
c767c1c6 | 62 | * (plus recentrly, SOC or family details) |
550a7375 FB |
63 | * |
64 | * Most of the conditional compilation will (someday) vanish. | |
65 | */ | |
66 | ||
67 | #include <linux/module.h> | |
68 | #include <linux/kernel.h> | |
69 | #include <linux/sched.h> | |
70 | #include <linux/slab.h> | |
550a7375 FB |
71 | #include <linux/list.h> |
72 | #include <linux/kobject.h> | |
9303961f | 73 | #include <linux/prefetch.h> |
550a7375 FB |
74 | #include <linux/platform_device.h> |
75 | #include <linux/io.h> | |
8d2421e6 | 76 | #include <linux/dma-mapping.h> |
309be239 | 77 | #include <linux/usb.h> |
830fc64c | 78 | #include <linux/usb/of.h> |
550a7375 | 79 | |
550a7375 | 80 | #include "musb_core.h" |
c74173fd | 81 | #include "musb_trace.h" |
550a7375 | 82 | |
f7f9d63e | 83 | #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON) |
550a7375 FB |
84 | |
85 | ||
550a7375 FB |
86 | #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia" |
87 | #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver" | |
88 | ||
e8164f64 | 89 | #define MUSB_VERSION "6.0" |
550a7375 FB |
90 | |
91 | #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION | |
92 | ||
05ac10dd | 93 | #define MUSB_DRIVER_NAME "musb-hdrc" |
550a7375 FB |
94 | const char musb_driver_name[] = MUSB_DRIVER_NAME; |
95 | ||
96 | MODULE_DESCRIPTION(DRIVER_INFO); | |
97 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
98 | MODULE_LICENSE("GPL"); | |
99 | MODULE_ALIAS("platform:" MUSB_DRIVER_NAME); | |
100 | ||
101 | ||
102 | /*-------------------------------------------------------------------------*/ | |
103 | ||
104 | static inline struct musb *dev_to_musb(struct device *dev) | |
105 | { | |
550a7375 | 106 | return dev_get_drvdata(dev); |
550a7375 FB |
107 | } |
108 | ||
830fc64c PK |
109 | enum musb_mode musb_get_mode(struct device *dev) |
110 | { | |
111 | enum usb_dr_mode mode; | |
112 | ||
113 | mode = usb_get_dr_mode(dev); | |
114 | switch (mode) { | |
115 | case USB_DR_MODE_HOST: | |
116 | return MUSB_HOST; | |
117 | case USB_DR_MODE_PERIPHERAL: | |
118 | return MUSB_PERIPHERAL; | |
119 | case USB_DR_MODE_OTG: | |
120 | case USB_DR_MODE_UNKNOWN: | |
121 | default: | |
122 | return MUSB_OTG; | |
123 | } | |
124 | } | |
125 | EXPORT_SYMBOL_GPL(musb_get_mode); | |
126 | ||
550a7375 FB |
127 | /*-------------------------------------------------------------------------*/ |
128 | ||
ffb865b1 | 129 | #ifndef CONFIG_BLACKFIN |
705e63d2 | 130 | static int musb_ulpi_read(struct usb_phy *phy, u32 reg) |
ffb865b1 | 131 | { |
b96d3b08 | 132 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
133 | int i = 0; |
134 | u8 r; | |
135 | u8 power; | |
bf070bc1 GI |
136 | int ret; |
137 | ||
138 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
139 | |
140 | /* Make sure the transceiver is not in low power mode */ | |
141 | power = musb_readb(addr, MUSB_POWER); | |
142 | power &= ~MUSB_POWER_SUSPENDM; | |
143 | musb_writeb(addr, MUSB_POWER, power); | |
144 | ||
145 | /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the | |
146 | * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM. | |
147 | */ | |
148 | ||
705e63d2 | 149 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); |
ffb865b1 HK |
150 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, |
151 | MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR); | |
152 | ||
153 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
154 | & MUSB_ULPI_REG_CMPLT)) { | |
155 | i++; | |
bf070bc1 GI |
156 | if (i == 10000) { |
157 | ret = -ETIMEDOUT; | |
158 | goto out; | |
159 | } | |
ffb865b1 HK |
160 | |
161 | } | |
162 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
163 | r &= ~MUSB_ULPI_REG_CMPLT; | |
164 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
165 | ||
bf070bc1 GI |
166 | ret = musb_readb(addr, MUSB_ULPI_REG_DATA); |
167 | ||
168 | out: | |
169 | pm_runtime_put(phy->io_dev); | |
170 | ||
171 | return ret; | |
ffb865b1 HK |
172 | } |
173 | ||
705e63d2 | 174 | static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg) |
ffb865b1 | 175 | { |
b96d3b08 | 176 | void __iomem *addr = phy->io_priv; |
ffb865b1 HK |
177 | int i = 0; |
178 | u8 r = 0; | |
179 | u8 power; | |
bf070bc1 GI |
180 | int ret = 0; |
181 | ||
182 | pm_runtime_get_sync(phy->io_dev); | |
ffb865b1 HK |
183 | |
184 | /* Make sure the transceiver is not in low power mode */ | |
185 | power = musb_readb(addr, MUSB_POWER); | |
186 | power &= ~MUSB_POWER_SUSPENDM; | |
187 | musb_writeb(addr, MUSB_POWER, power); | |
188 | ||
705e63d2 UKK |
189 | musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg); |
190 | musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val); | |
ffb865b1 HK |
191 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ); |
192 | ||
193 | while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL) | |
194 | & MUSB_ULPI_REG_CMPLT)) { | |
195 | i++; | |
bf070bc1 GI |
196 | if (i == 10000) { |
197 | ret = -ETIMEDOUT; | |
198 | goto out; | |
199 | } | |
ffb865b1 HK |
200 | } |
201 | ||
202 | r = musb_readb(addr, MUSB_ULPI_REG_CONTROL); | |
203 | r &= ~MUSB_ULPI_REG_CMPLT; | |
204 | musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r); | |
205 | ||
bf070bc1 GI |
206 | out: |
207 | pm_runtime_put(phy->io_dev); | |
208 | ||
209 | return ret; | |
ffb865b1 HK |
210 | } |
211 | #else | |
f2263db7 MF |
212 | #define musb_ulpi_read NULL |
213 | #define musb_ulpi_write NULL | |
ffb865b1 HK |
214 | #endif |
215 | ||
b96d3b08 | 216 | static struct usb_phy_io_ops musb_ulpi_access = { |
ffb865b1 HK |
217 | .read = musb_ulpi_read, |
218 | .write = musb_ulpi_write, | |
219 | }; | |
220 | ||
221 | /*-------------------------------------------------------------------------*/ | |
222 | ||
1b40fc57 TL |
223 | static u32 musb_default_fifo_offset(u8 epnum) |
224 | { | |
225 | return 0x20 + (epnum * 4); | |
226 | } | |
227 | ||
d026e9c7 TL |
228 | /* "flat" mapping: each endpoint has its own i/o address */ |
229 | static void musb_flat_ep_select(void __iomem *mbase, u8 epnum) | |
230 | { | |
231 | } | |
232 | ||
233 | static u32 musb_flat_ep_offset(u8 epnum, u16 offset) | |
234 | { | |
235 | return 0x100 + (0x10 * epnum) + offset; | |
236 | } | |
237 | ||
238 | /* "indexed" mapping: INDEX register controls register bank select */ | |
239 | static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum) | |
240 | { | |
241 | musb_writeb(mbase, MUSB_INDEX, epnum); | |
242 | } | |
243 | ||
244 | static u32 musb_indexed_ep_offset(u8 epnum, u16 offset) | |
245 | { | |
246 | return 0x10 + offset; | |
247 | } | |
248 | ||
6cc2af6d HG |
249 | static u32 musb_default_busctl_offset(u8 epnum, u16 offset) |
250 | { | |
251 | return 0x80 + (0x08 * epnum) + offset; | |
252 | } | |
253 | ||
1b40fc57 TL |
254 | static u8 musb_default_readb(const void __iomem *addr, unsigned offset) |
255 | { | |
c74173fd BL |
256 | u8 data = __raw_readb(addr + offset); |
257 | ||
258 | trace_musb_readb(__builtin_return_address(0), addr, offset, data); | |
259 | return data; | |
1b40fc57 TL |
260 | } |
261 | ||
262 | static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data) | |
263 | { | |
c74173fd | 264 | trace_musb_writeb(__builtin_return_address(0), addr, offset, data); |
1b40fc57 TL |
265 | __raw_writeb(data, addr + offset); |
266 | } | |
267 | ||
268 | static u16 musb_default_readw(const void __iomem *addr, unsigned offset) | |
269 | { | |
c74173fd BL |
270 | u16 data = __raw_readw(addr + offset); |
271 | ||
272 | trace_musb_readw(__builtin_return_address(0), addr, offset, data); | |
273 | return data; | |
1b40fc57 TL |
274 | } |
275 | ||
276 | static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data) | |
277 | { | |
c74173fd | 278 | trace_musb_writew(__builtin_return_address(0), addr, offset, data); |
1b40fc57 TL |
279 | __raw_writew(data, addr + offset); |
280 | } | |
281 | ||
282 | static u32 musb_default_readl(const void __iomem *addr, unsigned offset) | |
283 | { | |
c74173fd BL |
284 | u32 data = __raw_readl(addr + offset); |
285 | ||
286 | trace_musb_readl(__builtin_return_address(0), addr, offset, data); | |
287 | return data; | |
1b40fc57 TL |
288 | } |
289 | ||
290 | static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data) | |
291 | { | |
c74173fd | 292 | trace_musb_writel(__builtin_return_address(0), addr, offset, data); |
1b40fc57 TL |
293 | __raw_writel(data, addr + offset); |
294 | } | |
c6cf8b00 | 295 | |
550a7375 FB |
296 | /* |
297 | * Load an endpoint's FIFO | |
298 | */ | |
1b40fc57 TL |
299 | static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len, |
300 | const u8 *src) | |
550a7375 | 301 | { |
5c8a86e1 | 302 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
303 | void __iomem *fifo = hw_ep->fifo; |
304 | ||
603fe2b2 AKG |
305 | if (unlikely(len == 0)) |
306 | return; | |
307 | ||
550a7375 FB |
308 | prefetch((u8 *)src); |
309 | ||
5c8a86e1 | 310 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
311 | 'T', hw_ep->epnum, fifo, len, src); |
312 | ||
313 | /* we can't assume unaligned reads work */ | |
314 | if (likely((0x01 & (unsigned long) src) == 0)) { | |
315 | u16 index = 0; | |
316 | ||
317 | /* best case is 32bit-aligned source address */ | |
318 | if ((0x02 & (unsigned long) src) == 0) { | |
319 | if (len >= 4) { | |
2bf0a8f6 | 320 | iowrite32_rep(fifo, src + index, len >> 2); |
550a7375 FB |
321 | index += len & ~0x03; |
322 | } | |
323 | if (len & 0x02) { | |
be780381 | 324 | __raw_writew(*(u16 *)&src[index], fifo); |
550a7375 FB |
325 | index += 2; |
326 | } | |
327 | } else { | |
328 | if (len >= 2) { | |
2bf0a8f6 | 329 | iowrite16_rep(fifo, src + index, len >> 1); |
550a7375 FB |
330 | index += len & ~0x01; |
331 | } | |
332 | } | |
333 | if (len & 0x01) | |
be780381 | 334 | __raw_writeb(src[index], fifo); |
550a7375 FB |
335 | } else { |
336 | /* byte aligned */ | |
2bf0a8f6 | 337 | iowrite8_rep(fifo, src, len); |
550a7375 FB |
338 | } |
339 | } | |
340 | ||
341 | /* | |
342 | * Unload an endpoint's FIFO | |
343 | */ | |
1b40fc57 | 344 | static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) |
550a7375 | 345 | { |
5c8a86e1 | 346 | struct musb *musb = hw_ep->musb; |
550a7375 FB |
347 | void __iomem *fifo = hw_ep->fifo; |
348 | ||
603fe2b2 AKG |
349 | if (unlikely(len == 0)) |
350 | return; | |
351 | ||
5c8a86e1 | 352 | dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n", |
550a7375 FB |
353 | 'R', hw_ep->epnum, fifo, len, dst); |
354 | ||
355 | /* we can't assume unaligned writes work */ | |
356 | if (likely((0x01 & (unsigned long) dst) == 0)) { | |
357 | u16 index = 0; | |
358 | ||
359 | /* best case is 32bit-aligned destination address */ | |
360 | if ((0x02 & (unsigned long) dst) == 0) { | |
361 | if (len >= 4) { | |
2bf0a8f6 | 362 | ioread32_rep(fifo, dst, len >> 2); |
550a7375 FB |
363 | index = len & ~0x03; |
364 | } | |
365 | if (len & 0x02) { | |
be780381 | 366 | *(u16 *)&dst[index] = __raw_readw(fifo); |
550a7375 FB |
367 | index += 2; |
368 | } | |
369 | } else { | |
370 | if (len >= 2) { | |
2bf0a8f6 | 371 | ioread16_rep(fifo, dst, len >> 1); |
550a7375 FB |
372 | index = len & ~0x01; |
373 | } | |
374 | } | |
375 | if (len & 0x01) | |
be780381 | 376 | dst[index] = __raw_readb(fifo); |
550a7375 FB |
377 | } else { |
378 | /* byte aligned */ | |
2bf0a8f6 | 379 | ioread8_rep(fifo, dst, len); |
550a7375 FB |
380 | } |
381 | } | |
382 | ||
1b40fc57 TL |
383 | /* |
384 | * Old style IO functions | |
385 | */ | |
386 | u8 (*musb_readb)(const void __iomem *addr, unsigned offset); | |
387 | EXPORT_SYMBOL_GPL(musb_readb); | |
388 | ||
389 | void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data); | |
390 | EXPORT_SYMBOL_GPL(musb_writeb); | |
550a7375 | 391 | |
1b40fc57 TL |
392 | u16 (*musb_readw)(const void __iomem *addr, unsigned offset); |
393 | EXPORT_SYMBOL_GPL(musb_readw); | |
394 | ||
395 | void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data); | |
396 | EXPORT_SYMBOL_GPL(musb_writew); | |
397 | ||
398 | u32 (*musb_readl)(const void __iomem *addr, unsigned offset); | |
399 | EXPORT_SYMBOL_GPL(musb_readl); | |
400 | ||
401 | void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data); | |
402 | EXPORT_SYMBOL_GPL(musb_writel); | |
403 | ||
7f6283ed TL |
404 | #ifndef CONFIG_MUSB_PIO_ONLY |
405 | struct dma_controller * | |
406 | (*musb_dma_controller_create)(struct musb *musb, void __iomem *base); | |
407 | EXPORT_SYMBOL(musb_dma_controller_create); | |
408 | ||
409 | void (*musb_dma_controller_destroy)(struct dma_controller *c); | |
410 | EXPORT_SYMBOL(musb_dma_controller_destroy); | |
411 | #endif | |
412 | ||
1b40fc57 TL |
413 | /* |
414 | * New style IO functions | |
415 | */ | |
416 | void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst) | |
417 | { | |
418 | return hw_ep->musb->io.read_fifo(hw_ep, len, dst); | |
419 | } | |
420 | ||
421 | void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src) | |
422 | { | |
423 | return hw_ep->musb->io.write_fifo(hw_ep, len, src); | |
424 | } | |
550a7375 FB |
425 | |
426 | /*-------------------------------------------------------------------------*/ | |
427 | ||
428 | /* for high speed test mode; see USB 2.0 spec 7.1.20 */ | |
429 | static const u8 musb_test_packet[53] = { | |
430 | /* implicit SYNC then DATA0 to start */ | |
431 | ||
432 | /* JKJKJKJK x9 */ | |
433 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
434 | /* JJKKJJKK x8 */ | |
435 | 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, | |
436 | /* JJJJKKKK x8 */ | |
437 | 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, | |
438 | /* JJJJJJJKKKKKKK x8 */ | |
439 | 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, | |
440 | /* JJJJJJJK x8 */ | |
441 | 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, | |
442 | /* JKKKKKKK x10, JK */ | |
443 | 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e | |
444 | ||
445 | /* implicit CRC16 then EOP to end */ | |
446 | }; | |
447 | ||
448 | void musb_load_testpacket(struct musb *musb) | |
449 | { | |
450 | void __iomem *regs = musb->endpoints[0].regs; | |
451 | ||
452 | musb_ep_select(musb->mregs, 0); | |
453 | musb_write_fifo(musb->control_ep, | |
454 | sizeof(musb_test_packet), musb_test_packet); | |
455 | musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY); | |
456 | } | |
457 | ||
458 | /*-------------------------------------------------------------------------*/ | |
459 | ||
550a7375 FB |
460 | /* |
461 | * Handles OTG hnp timeouts, such as b_ase0_brst | |
462 | */ | |
05678497 | 463 | static void musb_otg_timer_func(struct timer_list *t) |
550a7375 | 464 | { |
05678497 | 465 | struct musb *musb = from_timer(musb, t, otg_timer); |
550a7375 FB |
466 | unsigned long flags; |
467 | ||
468 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 469 | switch (musb->xceiv->otg->state) { |
550a7375 | 470 | case OTG_STATE_B_WAIT_ACON: |
b99d3659 BL |
471 | musb_dbg(musb, |
472 | "HNP: b_wait_acon timeout; back to b_peripheral"); | |
550a7375 | 473 | musb_g_disconnect(musb); |
e47d9254 | 474 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
475 | musb->is_active = 0; |
476 | break; | |
ab983f2a | 477 | case OTG_STATE_A_SUSPEND: |
550a7375 | 478 | case OTG_STATE_A_WAIT_BCON: |
b99d3659 | 479 | musb_dbg(musb, "HNP: %s timeout", |
e47d9254 | 480 | usb_otg_state_string(musb->xceiv->otg->state)); |
743411b3 | 481 | musb_platform_set_vbus(musb, 0); |
e47d9254 | 482 | musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL; |
550a7375 FB |
483 | break; |
484 | default: | |
b99d3659 | 485 | musb_dbg(musb, "HNP: Unhandled mode %s", |
e47d9254 | 486 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 | 487 | } |
550a7375 FB |
488 | spin_unlock_irqrestore(&musb->lock, flags); |
489 | } | |
490 | ||
550a7375 | 491 | /* |
f7f9d63e | 492 | * Stops the HNP transition. Caller must take care of locking. |
550a7375 FB |
493 | */ |
494 | void musb_hnp_stop(struct musb *musb) | |
495 | { | |
8b125df5 | 496 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
497 | void __iomem *mbase = musb->mregs; |
498 | u8 reg; | |
499 | ||
b99d3659 | 500 | musb_dbg(musb, "HNP: stop from %s", |
e47d9254 | 501 | usb_otg_state_string(musb->xceiv->otg->state)); |
ab983f2a | 502 | |
e47d9254 | 503 | switch (musb->xceiv->otg->state) { |
550a7375 | 504 | case OTG_STATE_A_PERIPHERAL: |
550a7375 | 505 | musb_g_disconnect(musb); |
b99d3659 | 506 | musb_dbg(musb, "HNP: back to %s", |
e47d9254 | 507 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
508 | break; |
509 | case OTG_STATE_B_HOST: | |
b99d3659 | 510 | musb_dbg(musb, "HNP: Disabling HR"); |
74c2e936 DM |
511 | if (hcd) |
512 | hcd->self.is_b_host = 0; | |
e47d9254 | 513 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
514 | MUSB_DEV_MODE(musb); |
515 | reg = musb_readb(mbase, MUSB_POWER); | |
516 | reg |= MUSB_POWER_SUSPENDM; | |
517 | musb_writeb(mbase, MUSB_POWER, reg); | |
518 | /* REVISIT: Start SESSION_REQUEST here? */ | |
519 | break; | |
520 | default: | |
b99d3659 | 521 | musb_dbg(musb, "HNP: Stopping in unknown state %s", |
e47d9254 | 522 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
523 | } |
524 | ||
525 | /* | |
526 | * When returning to A state after HNP, avoid hub_port_rebounce(), | |
527 | * which cause occasional OPT A "Did not receive reset after connect" | |
528 | * errors. | |
529 | */ | |
749da5f8 | 530 | musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16); |
550a7375 FB |
531 | } |
532 | ||
83b8f5b8 | 533 | static void musb_recover_from_babble(struct musb *musb); |
e1eb3eb8 | 534 | |
550a7375 FB |
535 | /* |
536 | * Interrupt Service Routine to record USB "global" interrupts. | |
537 | * Since these do not happen often and signify things of | |
538 | * paramount importance, it seems OK to check them individually; | |
539 | * the order of the tests is specified in the manual | |
540 | * | |
541 | * @param musb instance pointer | |
542 | * @param int_usb register contents | |
543 | * @param devctl | |
544 | * @param power | |
545 | */ | |
546 | ||
550a7375 | 547 | static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb, |
b11e94d0 | 548 | u8 devctl) |
550a7375 FB |
549 | { |
550 | irqreturn_t handled = IRQ_NONE; | |
550a7375 | 551 | |
b99d3659 | 552 | musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb); |
550a7375 FB |
553 | |
554 | /* in host mode, the peripheral may issue remote wakeup. | |
555 | * in peripheral mode, the host may resume the link. | |
556 | * spurious RESUME irqs happen too, paired with SUSPEND. | |
557 | */ | |
558 | if (int_usb & MUSB_INTR_RESUME) { | |
559 | handled = IRQ_HANDLED; | |
b99d3659 | 560 | musb_dbg(musb, "RESUME (%s)", |
0acff6b8 | 561 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
562 | |
563 | if (devctl & MUSB_DEVCTL_HM) { | |
e47d9254 | 564 | switch (musb->xceiv->otg->state) { |
550a7375 | 565 | case OTG_STATE_A_SUSPEND: |
65322797 | 566 | /* remote wakeup? */ |
550a7375 FB |
567 | musb->port1_status |= |
568 | (USB_PORT_STAT_C_SUSPEND << 16) | |
569 | | MUSB_PORT_STAT_RESUME; | |
30d361bf | 570 | musb->rh_timer = jiffies |
309be239 | 571 | + msecs_to_jiffies(USB_RESUME_TIMEOUT); |
e47d9254 | 572 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
550a7375 | 573 | musb->is_active = 1; |
9298b4aa | 574 | musb_host_resume_root_hub(musb); |
407788b5 TL |
575 | schedule_delayed_work(&musb->finish_resume_work, |
576 | msecs_to_jiffies(USB_RESUME_TIMEOUT)); | |
550a7375 FB |
577 | break; |
578 | case OTG_STATE_B_WAIT_ACON: | |
e47d9254 | 579 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
580 | musb->is_active = 1; |
581 | MUSB_DEV_MODE(musb); | |
582 | break; | |
583 | default: | |
584 | WARNING("bogus %s RESUME (%s)\n", | |
585 | "host", | |
e47d9254 | 586 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 | 587 | } |
550a7375 | 588 | } else { |
e47d9254 | 589 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
590 | case OTG_STATE_A_SUSPEND: |
591 | /* possibly DISCONNECT is upcoming */ | |
e47d9254 | 592 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
0b3eba44 | 593 | musb_host_resume_root_hub(musb); |
550a7375 | 594 | break; |
550a7375 FB |
595 | case OTG_STATE_B_WAIT_ACON: |
596 | case OTG_STATE_B_PERIPHERAL: | |
597 | /* disconnect while suspended? we may | |
598 | * not get a disconnect irq... | |
599 | */ | |
600 | if ((devctl & MUSB_DEVCTL_VBUS) | |
601 | != (3 << MUSB_DEVCTL_VBUS_SHIFT) | |
602 | ) { | |
603 | musb->int_usb |= MUSB_INTR_DISCONNECT; | |
604 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
605 | break; | |
606 | } | |
607 | musb_g_resume(musb); | |
608 | break; | |
609 | case OTG_STATE_B_IDLE: | |
610 | musb->int_usb &= ~MUSB_INTR_SUSPEND; | |
611 | break; | |
550a7375 FB |
612 | default: |
613 | WARNING("bogus %s RESUME (%s)\n", | |
614 | "peripheral", | |
e47d9254 | 615 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
616 | } |
617 | } | |
618 | } | |
619 | ||
550a7375 FB |
620 | /* see manual for the order of the tests */ |
621 | if (int_usb & MUSB_INTR_SESSREQ) { | |
aa471456 FB |
622 | void __iomem *mbase = musb->mregs; |
623 | ||
19aab56c HK |
624 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS |
625 | && (devctl & MUSB_DEVCTL_BDEVICE)) { | |
b99d3659 | 626 | musb_dbg(musb, "SessReq while on B state"); |
a6038ee7 HK |
627 | return IRQ_HANDLED; |
628 | } | |
629 | ||
b99d3659 | 630 | musb_dbg(musb, "SESSION_REQUEST (%s)", |
e47d9254 | 631 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
632 | |
633 | /* IRQ arrives from ID pin sense or (later, if VBUS power | |
634 | * is removed) SRP. responses are time critical: | |
635 | * - turn on VBUS (with silicon-specific mechanism) | |
636 | * - go through A_WAIT_VRISE | |
637 | * - ... to A_WAIT_BCON. | |
638 | * a_wait_vrise_tmout triggers VBUS_ERROR transitions | |
639 | */ | |
640 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); | |
641 | musb->ep0_stage = MUSB_EP0_START; | |
e47d9254 | 642 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
550a7375 | 643 | MUSB_HST_MODE(musb); |
743411b3 | 644 | musb_platform_set_vbus(musb, 1); |
550a7375 FB |
645 | |
646 | handled = IRQ_HANDLED; | |
647 | } | |
648 | ||
649 | if (int_usb & MUSB_INTR_VBUSERROR) { | |
650 | int ignore = 0; | |
651 | ||
652 | /* During connection as an A-Device, we may see a short | |
653 | * current spikes causing voltage drop, because of cable | |
654 | * and peripheral capacitance combined with vbus draw. | |
655 | * (So: less common with truly self-powered devices, where | |
656 | * vbus doesn't act like a power supply.) | |
657 | * | |
658 | * Such spikes are short; usually less than ~500 usec, max | |
659 | * of ~2 msec. That is, they're not sustained overcurrent | |
660 | * errors, though they're reported using VBUSERROR irqs. | |
661 | * | |
662 | * Workarounds: (a) hardware: use self powered devices. | |
663 | * (b) software: ignore non-repeated VBUS errors. | |
664 | * | |
665 | * REVISIT: do delays from lots of DEBUG_KERNEL checks | |
666 | * make trouble here, keeping VBUS < 4.4V ? | |
667 | */ | |
e47d9254 | 668 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
669 | case OTG_STATE_A_HOST: |
670 | /* recovery is dicey once we've gotten past the | |
671 | * initial stages of enumeration, but if VBUS | |
672 | * stayed ok at the other end of the link, and | |
673 | * another reset is due (at least for high speed, | |
674 | * to redo the chirp etc), it might work OK... | |
675 | */ | |
676 | case OTG_STATE_A_WAIT_BCON: | |
677 | case OTG_STATE_A_WAIT_VRISE: | |
678 | if (musb->vbuserr_retry) { | |
aa471456 FB |
679 | void __iomem *mbase = musb->mregs; |
680 | ||
550a7375 FB |
681 | musb->vbuserr_retry--; |
682 | ignore = 1; | |
683 | devctl |= MUSB_DEVCTL_SESSION; | |
684 | musb_writeb(mbase, MUSB_DEVCTL, devctl); | |
685 | } else { | |
686 | musb->port1_status |= | |
749da5f8 AS |
687 | USB_PORT_STAT_OVERCURRENT |
688 | | (USB_PORT_STAT_C_OVERCURRENT << 16); | |
550a7375 FB |
689 | } |
690 | break; | |
691 | default: | |
692 | break; | |
693 | } | |
694 | ||
54485116 GI |
695 | dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller, |
696 | "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n", | |
e47d9254 | 697 | usb_otg_state_string(musb->xceiv->otg->state), |
550a7375 FB |
698 | devctl, |
699 | ({ char *s; | |
700 | switch (devctl & MUSB_DEVCTL_VBUS) { | |
701 | case 0 << MUSB_DEVCTL_VBUS_SHIFT: | |
702 | s = "<SessEnd"; break; | |
703 | case 1 << MUSB_DEVCTL_VBUS_SHIFT: | |
704 | s = "<AValid"; break; | |
705 | case 2 << MUSB_DEVCTL_VBUS_SHIFT: | |
706 | s = "<VBusValid"; break; | |
707 | /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */ | |
708 | default: | |
709 | s = "VALID"; break; | |
2b84f92b | 710 | } s; }), |
550a7375 FB |
711 | VBUSERR_RETRY_COUNT - musb->vbuserr_retry, |
712 | musb->port1_status); | |
713 | ||
714 | /* go through A_WAIT_VFALL then start a new session */ | |
715 | if (!ignore) | |
743411b3 | 716 | musb_platform_set_vbus(musb, 0); |
550a7375 FB |
717 | handled = IRQ_HANDLED; |
718 | } | |
719 | ||
1c25fda4 | 720 | if (int_usb & MUSB_INTR_SUSPEND) { |
b99d3659 | 721 | musb_dbg(musb, "SUSPEND (%s) devctl %02x", |
e47d9254 | 722 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
1c25fda4 AM |
723 | handled = IRQ_HANDLED; |
724 | ||
e47d9254 | 725 | switch (musb->xceiv->otg->state) { |
1c25fda4 AM |
726 | case OTG_STATE_A_PERIPHERAL: |
727 | /* We also come here if the cable is removed, since | |
728 | * this silicon doesn't report ID-no-longer-grounded. | |
729 | * | |
730 | * We depend on T(a_wait_bcon) to shut us down, and | |
731 | * hope users don't do anything dicey during this | |
732 | * undesired detour through A_WAIT_BCON. | |
733 | */ | |
734 | musb_hnp_stop(musb); | |
0b3eba44 | 735 | musb_host_resume_root_hub(musb); |
1c25fda4 AM |
736 | musb_root_disconnect(musb); |
737 | musb_platform_try_idle(musb, jiffies | |
738 | + msecs_to_jiffies(musb->a_wait_bcon | |
739 | ? : OTG_TIME_A_WAIT_BCON)); | |
740 | ||
741 | break; | |
1c25fda4 AM |
742 | case OTG_STATE_B_IDLE: |
743 | if (!musb->is_active) | |
744 | break; | |
0c636364 | 745 | /* fall through */ |
1c25fda4 AM |
746 | case OTG_STATE_B_PERIPHERAL: |
747 | musb_g_suspend(musb); | |
eee3f15d | 748 | musb->is_active = musb->g.b_hnp_enable; |
1c25fda4 | 749 | if (musb->is_active) { |
e47d9254 | 750 | musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON; |
b99d3659 | 751 | musb_dbg(musb, "HNP: Setting timer for b_ase0_brst"); |
1c25fda4 AM |
752 | mod_timer(&musb->otg_timer, jiffies |
753 | + msecs_to_jiffies( | |
754 | OTG_TIME_B_ASE0_BRST)); | |
1c25fda4 AM |
755 | } |
756 | break; | |
757 | case OTG_STATE_A_WAIT_BCON: | |
758 | if (musb->a_wait_bcon != 0) | |
759 | musb_platform_try_idle(musb, jiffies | |
760 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
761 | break; | |
762 | case OTG_STATE_A_HOST: | |
e47d9254 | 763 | musb->xceiv->otg->state = OTG_STATE_A_SUSPEND; |
eee3f15d | 764 | musb->is_active = musb->hcd->self.b_hnp_enable; |
1c25fda4 AM |
765 | break; |
766 | case OTG_STATE_B_HOST: | |
767 | /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */ | |
b99d3659 | 768 | musb_dbg(musb, "REVISIT: SUSPEND as B_HOST"); |
1c25fda4 AM |
769 | break; |
770 | default: | |
771 | /* "should not happen" */ | |
772 | musb->is_active = 0; | |
773 | break; | |
774 | } | |
775 | } | |
776 | ||
550a7375 | 777 | if (int_usb & MUSB_INTR_CONNECT) { |
8b125df5 | 778 | struct usb_hcd *hcd = musb->hcd; |
550a7375 FB |
779 | |
780 | handled = IRQ_HANDLED; | |
781 | musb->is_active = 1; | |
550a7375 FB |
782 | |
783 | musb->ep0_stage = MUSB_EP0_START; | |
784 | ||
b18d26f6 SAS |
785 | musb->intrtxe = musb->epmask; |
786 | musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe); | |
af5ec14d SAS |
787 | musb->intrrxe = musb->epmask & 0xfffe; |
788 | musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe); | |
d709d22e | 789 | musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7); |
550a7375 FB |
790 | musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED |
791 | |USB_PORT_STAT_HIGH_SPEED | |
792 | |USB_PORT_STAT_ENABLE | |
793 | ); | |
794 | musb->port1_status |= USB_PORT_STAT_CONNECTION | |
795 | |(USB_PORT_STAT_C_CONNECTION << 16); | |
796 | ||
797 | /* high vs full speed is just a guess until after reset */ | |
798 | if (devctl & MUSB_DEVCTL_LSDEV) | |
799 | musb->port1_status |= USB_PORT_STAT_LOW_SPEED; | |
800 | ||
550a7375 | 801 | /* indicate new connection to OTG machine */ |
e47d9254 | 802 | switch (musb->xceiv->otg->state) { |
550a7375 FB |
803 | case OTG_STATE_B_PERIPHERAL: |
804 | if (int_usb & MUSB_INTR_SUSPEND) { | |
b99d3659 | 805 | musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host"); |
550a7375 | 806 | int_usb &= ~MUSB_INTR_SUSPEND; |
1de00dae | 807 | goto b_host; |
550a7375 | 808 | } else |
b99d3659 | 809 | musb_dbg(musb, "CONNECT as b_peripheral???"); |
550a7375 FB |
810 | break; |
811 | case OTG_STATE_B_WAIT_ACON: | |
b99d3659 | 812 | musb_dbg(musb, "HNP: CONNECT, now b_host"); |
1de00dae | 813 | b_host: |
e47d9254 | 814 | musb->xceiv->otg->state = OTG_STATE_B_HOST; |
74c2e936 DM |
815 | if (musb->hcd) |
816 | musb->hcd->self.is_b_host = 1; | |
1de00dae | 817 | del_timer(&musb->otg_timer); |
550a7375 FB |
818 | break; |
819 | default: | |
820 | if ((devctl & MUSB_DEVCTL_VBUS) | |
821 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) { | |
e47d9254 | 822 | musb->xceiv->otg->state = OTG_STATE_A_HOST; |
0b3eba44 DM |
823 | if (hcd) |
824 | hcd->self.is_b_host = 0; | |
550a7375 FB |
825 | } |
826 | break; | |
827 | } | |
1de00dae | 828 | |
0b3eba44 | 829 | musb_host_poke_root_hub(musb); |
1de00dae | 830 | |
b99d3659 | 831 | musb_dbg(musb, "CONNECT (%s) devctl %02x", |
e47d9254 | 832 | usb_otg_state_string(musb->xceiv->otg->state), devctl); |
550a7375 | 833 | } |
550a7375 | 834 | |
6d349671 | 835 | if (int_usb & MUSB_INTR_DISCONNECT) { |
b99d3659 | 836 | musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x", |
e47d9254 | 837 | usb_otg_state_string(musb->xceiv->otg->state), |
1c25fda4 AM |
838 | MUSB_MODE(musb), devctl); |
839 | handled = IRQ_HANDLED; | |
840 | ||
e47d9254 | 841 | switch (musb->xceiv->otg->state) { |
1c25fda4 AM |
842 | case OTG_STATE_A_HOST: |
843 | case OTG_STATE_A_SUSPEND: | |
0b3eba44 | 844 | musb_host_resume_root_hub(musb); |
1c25fda4 | 845 | musb_root_disconnect(musb); |
032ec49f | 846 | if (musb->a_wait_bcon != 0) |
1c25fda4 AM |
847 | musb_platform_try_idle(musb, jiffies |
848 | + msecs_to_jiffies(musb->a_wait_bcon)); | |
849 | break; | |
1c25fda4 AM |
850 | case OTG_STATE_B_HOST: |
851 | /* REVISIT this behaves for "real disconnect" | |
852 | * cases; make sure the other transitions from | |
853 | * from B_HOST act right too. The B_HOST code | |
854 | * in hnp_stop() is currently not used... | |
855 | */ | |
856 | musb_root_disconnect(musb); | |
74c2e936 DM |
857 | if (musb->hcd) |
858 | musb->hcd->self.is_b_host = 0; | |
e47d9254 | 859 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
1c25fda4 AM |
860 | MUSB_DEV_MODE(musb); |
861 | musb_g_disconnect(musb); | |
862 | break; | |
863 | case OTG_STATE_A_PERIPHERAL: | |
864 | musb_hnp_stop(musb); | |
865 | musb_root_disconnect(musb); | |
866 | /* FALLTHROUGH */ | |
867 | case OTG_STATE_B_WAIT_ACON: | |
868 | /* FALLTHROUGH */ | |
1c25fda4 AM |
869 | case OTG_STATE_B_PERIPHERAL: |
870 | case OTG_STATE_B_IDLE: | |
871 | musb_g_disconnect(musb); | |
872 | break; | |
1c25fda4 AM |
873 | default: |
874 | WARNING("unhandled DISCONNECT transition (%s)\n", | |
e47d9254 | 875 | usb_otg_state_string(musb->xceiv->otg->state)); |
1c25fda4 AM |
876 | break; |
877 | } | |
878 | } | |
879 | ||
550a7375 FB |
880 | /* mentor saves a bit: bus reset and babble share the same irq. |
881 | * only host sees babble; only peripheral sees bus reset. | |
882 | */ | |
883 | if (int_usb & MUSB_INTR_RESET) { | |
1c25fda4 | 884 | handled = IRQ_HANDLED; |
445ef615 | 885 | if (is_host_active(musb)) { |
550a7375 | 886 | /* |
34754dec | 887 | * When BABBLE happens what we can depends on which |
28378d5e FB |
888 | * platform MUSB is running, because some platforms |
889 | * implemented proprietary means for 'recovering' from | |
890 | * Babble conditions. One such platform is AM335x. In | |
34754dec FB |
891 | * most cases, however, the only thing we can do is |
892 | * drop the session. | |
550a7375 | 893 | */ |
34754dec | 894 | dev_err(musb->controller, "Babble\n"); |
445ef615 | 895 | musb_recover_from_babble(musb); |
a04d46d0 | 896 | } else { |
b99d3659 | 897 | musb_dbg(musb, "BUS RESET as %s", |
e47d9254 AT |
898 | usb_otg_state_string(musb->xceiv->otg->state)); |
899 | switch (musb->xceiv->otg->state) { | |
550a7375 | 900 | case OTG_STATE_A_SUSPEND: |
550a7375 FB |
901 | musb_g_reset(musb); |
902 | /* FALLTHROUGH */ | |
903 | case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */ | |
f7f9d63e | 904 | /* never use invalid T(a_wait_bcon) */ |
b99d3659 | 905 | musb_dbg(musb, "HNP: in %s, %d msec timeout", |
e47d9254 | 906 | usb_otg_state_string(musb->xceiv->otg->state), |
3df00453 | 907 | TA_WAIT_BCON(musb)); |
f7f9d63e DB |
908 | mod_timer(&musb->otg_timer, jiffies |
909 | + msecs_to_jiffies(TA_WAIT_BCON(musb))); | |
550a7375 FB |
910 | break; |
911 | case OTG_STATE_A_PERIPHERAL: | |
1de00dae DB |
912 | del_timer(&musb->otg_timer); |
913 | musb_g_reset(musb); | |
550a7375 FB |
914 | break; |
915 | case OTG_STATE_B_WAIT_ACON: | |
b99d3659 | 916 | musb_dbg(musb, "HNP: RESET (%s), to b_peripheral", |
e47d9254 AT |
917 | usb_otg_state_string(musb->xceiv->otg->state)); |
918 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; | |
550a7375 FB |
919 | musb_g_reset(musb); |
920 | break; | |
550a7375 | 921 | case OTG_STATE_B_IDLE: |
e47d9254 | 922 | musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL; |
550a7375 FB |
923 | /* FALLTHROUGH */ |
924 | case OTG_STATE_B_PERIPHERAL: | |
925 | musb_g_reset(musb); | |
926 | break; | |
927 | default: | |
b99d3659 | 928 | musb_dbg(musb, "Unhandled BUS RESET as %s", |
e47d9254 | 929 | usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
930 | } |
931 | } | |
550a7375 | 932 | } |
550a7375 FB |
933 | |
934 | #if 0 | |
935 | /* REVISIT ... this would be for multiplexing periodic endpoints, or | |
936 | * supporting transfer phasing to prevent exceeding ISO bandwidth | |
937 | * limits of a given frame or microframe. | |
938 | * | |
939 | * It's not needed for peripheral side, which dedicates endpoints; | |
940 | * though it _might_ use SOF irqs for other purposes. | |
941 | * | |
942 | * And it's not currently needed for host side, which also dedicates | |
943 | * endpoints, relies on TX/RX interval registers, and isn't claimed | |
944 | * to support ISO transfers yet. | |
945 | */ | |
946 | if (int_usb & MUSB_INTR_SOF) { | |
947 | void __iomem *mbase = musb->mregs; | |
948 | struct musb_hw_ep *ep; | |
949 | u8 epnum; | |
950 | u16 frame; | |
951 | ||
5c8a86e1 | 952 | dev_dbg(musb->controller, "START_OF_FRAME\n"); |
550a7375 FB |
953 | handled = IRQ_HANDLED; |
954 | ||
955 | /* start any periodic Tx transfers waiting for current frame */ | |
956 | frame = musb_readw(mbase, MUSB_FRAME); | |
957 | ep = musb->endpoints; | |
958 | for (epnum = 1; (epnum < musb->nr_endpoints) | |
959 | && (musb->epmask >= (1 << epnum)); | |
960 | epnum++, ep++) { | |
961 | /* | |
962 | * FIXME handle framecounter wraps (12 bits) | |
963 | * eliminate duplicated StartUrb logic | |
964 | */ | |
965 | if (ep->dwWaitFrame >= frame) { | |
966 | ep->dwWaitFrame = 0; | |
967 | pr_debug("SOF --> periodic TX%s on %d\n", | |
968 | ep->tx_channel ? " DMA" : "", | |
969 | epnum); | |
970 | if (!ep->tx_channel) | |
971 | musb_h_tx_start(musb, epnum); | |
972 | else | |
973 | cppi_hostdma_start(musb, epnum); | |
974 | } | |
975 | } /* end of for loop */ | |
976 | } | |
977 | #endif | |
978 | ||
2bff3916 | 979 | schedule_delayed_work(&musb->irq_work, 0); |
550a7375 FB |
980 | |
981 | return handled; | |
982 | } | |
983 | ||
984 | /*-------------------------------------------------------------------------*/ | |
985 | ||
e1eb3eb8 | 986 | static void musb_disable_interrupts(struct musb *musb) |
550a7375 FB |
987 | { |
988 | void __iomem *mbase = musb->mregs; | |
989 | u16 temp; | |
990 | ||
991 | /* disable interrupts */ | |
992 | musb_writeb(mbase, MUSB_INTRUSBE, 0); | |
b18d26f6 | 993 | musb->intrtxe = 0; |
550a7375 | 994 | musb_writew(mbase, MUSB_INTRTXE, 0); |
af5ec14d | 995 | musb->intrrxe = 0; |
550a7375 FB |
996 | musb_writew(mbase, MUSB_INTRRXE, 0); |
997 | ||
550a7375 FB |
998 | /* flush pending interrupts */ |
999 | temp = musb_readb(mbase, MUSB_INTRUSB); | |
1000 | temp = musb_readw(mbase, MUSB_INTRTX); | |
1001 | temp = musb_readw(mbase, MUSB_INTRRX); | |
e1eb3eb8 FB |
1002 | } |
1003 | ||
1004 | static void musb_enable_interrupts(struct musb *musb) | |
1005 | { | |
1006 | void __iomem *regs = musb->mregs; | |
1007 | ||
1008 | /* Set INT enable registers, enable interrupts */ | |
1009 | musb->intrtxe = musb->epmask; | |
1010 | musb_writew(regs, MUSB_INTRTXE, musb->intrtxe); | |
1011 | musb->intrrxe = musb->epmask & 0xfffe; | |
1012 | musb_writew(regs, MUSB_INTRRXE, musb->intrrxe); | |
1013 | musb_writeb(regs, MUSB_INTRUSBE, 0xf7); | |
550a7375 FB |
1014 | |
1015 | } | |
1016 | ||
001dd84a SAS |
1017 | /* |
1018 | * Program the HDRC to start (enable interrupts, dma, etc.). | |
1019 | */ | |
1020 | void musb_start(struct musb *musb) | |
1021 | { | |
1022 | void __iomem *regs = musb->mregs; | |
1023 | u8 devctl = musb_readb(regs, MUSB_DEVCTL); | |
9b753764 | 1024 | u8 power; |
001dd84a | 1025 | |
b99d3659 | 1026 | musb_dbg(musb, "<== devctl %02x", devctl); |
001dd84a | 1027 | |
e1eb3eb8 | 1028 | musb_enable_interrupts(musb); |
001dd84a SAS |
1029 | musb_writeb(regs, MUSB_TESTMODE, 0); |
1030 | ||
9b753764 BL |
1031 | power = MUSB_POWER_ISOUPDATE; |
1032 | /* | |
1033 | * treating UNKNOWN as unspecified maximum speed, in which case | |
1034 | * we will default to high-speed. | |
1035 | */ | |
1036 | if (musb->config->maximum_speed == USB_SPEED_HIGH || | |
1037 | musb->config->maximum_speed == USB_SPEED_UNKNOWN) | |
1038 | power |= MUSB_POWER_HSENAB; | |
1039 | musb_writeb(regs, MUSB_POWER, power); | |
001dd84a SAS |
1040 | |
1041 | musb->is_active = 0; | |
1042 | devctl = musb_readb(regs, MUSB_DEVCTL); | |
1043 | devctl &= ~MUSB_DEVCTL_SESSION; | |
1044 | ||
1045 | /* session started after: | |
1046 | * (a) ID-grounded irq, host mode; | |
1047 | * (b) vbus present/connect IRQ, peripheral mode; | |
1048 | * (c) peripheral initiates, using SRP | |
1049 | */ | |
1050 | if (musb->port_mode != MUSB_PORT_MODE_HOST && | |
40af177e | 1051 | musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON && |
001dd84a SAS |
1052 | (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) { |
1053 | musb->is_active = 1; | |
1054 | } else { | |
1055 | devctl |= MUSB_DEVCTL_SESSION; | |
1056 | } | |
1057 | ||
1058 | musb_platform_enable(musb); | |
1059 | musb_writeb(regs, MUSB_DEVCTL, devctl); | |
1060 | } | |
1061 | ||
550a7375 FB |
1062 | /* |
1063 | * Make the HDRC stop (disable interrupts, etc.); | |
1064 | * reversible by musb_start | |
1065 | * called on gadget driver unregister | |
1066 | * with controller locked, irqs blocked | |
1067 | * acts as a NOP unless some role activated the hardware | |
1068 | */ | |
1069 | void musb_stop(struct musb *musb) | |
1070 | { | |
1071 | /* stop IRQs, timers, ... */ | |
1072 | musb_platform_disable(musb); | |
e945953d BL |
1073 | musb_disable_interrupts(musb); |
1074 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
550a7375 FB |
1075 | |
1076 | /* FIXME | |
1077 | * - mark host and/or peripheral drivers unusable/inactive | |
1078 | * - disable DMA (and enable it in HdrcStart) | |
1079 | * - make sure we can musb_start() after musb_stop(); with | |
1080 | * OTG mode, gadget driver module rmmod/modprobe cycles that | |
1081 | * - ... | |
1082 | */ | |
1083 | musb_platform_try_idle(musb, 0); | |
1084 | } | |
1085 | ||
550a7375 FB |
1086 | /*-------------------------------------------------------------------------*/ |
1087 | ||
1088 | /* | |
1089 | * The silicon either has hard-wired endpoint configurations, or else | |
1090 | * "dynamic fifo" sizing. The driver has support for both, though at this | |
c767c1c6 DB |
1091 | * writing only the dynamic sizing is very well tested. Since we switched |
1092 | * away from compile-time hardware parameters, we can no longer rely on | |
1093 | * dead code elimination to leave only the relevant one in the object file. | |
550a7375 FB |
1094 | * |
1095 | * We don't currently use dynamic fifo setup capability to do anything | |
1096 | * more than selecting one of a bunch of predefined configurations. | |
1097 | */ | |
8a77f05a | 1098 | static ushort fifo_mode; |
550a7375 FB |
1099 | |
1100 | /* "modprobe ... fifo_mode=1" etc */ | |
1101 | module_param(fifo_mode, ushort, 0); | |
1102 | MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration"); | |
1103 | ||
550a7375 FB |
1104 | /* |
1105 | * tables defining fifo_mode values. define more if you like. | |
1106 | * for host side, make sure both halves of ep1 are set up. | |
1107 | */ | |
1108 | ||
1109 | /* mode 0 - fits in 2KB */ | |
d3608b6d | 1110 | static struct musb_fifo_cfg mode_0_cfg[] = { |
550a7375 FB |
1111 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1112 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1113 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1114 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1115 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1116 | }; | |
1117 | ||
1118 | /* mode 1 - fits in 4KB */ | |
d3608b6d | 1119 | static struct musb_fifo_cfg mode_1_cfg[] = { |
550a7375 FB |
1120 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1121 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1122 | { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1123 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1124 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1125 | }; | |
1126 | ||
1127 | /* mode 2 - fits in 4KB */ | |
d3608b6d | 1128 | static struct musb_fifo_cfg mode_2_cfg[] = { |
550a7375 FB |
1129 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1130 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1131 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1132 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
55aad53f BL |
1133 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, }, |
1134 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
550a7375 FB |
1135 | }; |
1136 | ||
1137 | /* mode 3 - fits in 4KB */ | |
d3608b6d | 1138 | static struct musb_fifo_cfg mode_3_cfg[] = { |
550a7375 FB |
1139 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, }, |
1140 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, }, | |
1141 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1142 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1143 | { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1144 | { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, }, | |
1145 | }; | |
1146 | ||
1147 | /* mode 4 - fits in 16KB */ | |
d3608b6d | 1148 | static struct musb_fifo_cfg mode_4_cfg[] = { |
550a7375 FB |
1149 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1150 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1151 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1152 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1153 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1154 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1155 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1156 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1157 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1158 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1159 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, }, | |
1160 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, }, | |
1161 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, }, | |
1162 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, }, | |
1163 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, }, | |
1164 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, }, | |
1165 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, }, | |
1166 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, }, | |
a483d706 AKG |
1167 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, }, |
1168 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, }, | |
1169 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, }, | |
1170 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, }, | |
1171 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, }, | |
1172 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, }, | |
1173 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, }, | |
550a7375 FB |
1174 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, |
1175 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1176 | }; | |
1177 | ||
3b151526 | 1178 | /* mode 5 - fits in 8KB */ |
d3608b6d | 1179 | static struct musb_fifo_cfg mode_5_cfg[] = { |
3b151526 AKG |
1180 | { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, }, |
1181 | { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, }, | |
1182 | { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, }, | |
1183 | { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, }, | |
1184 | { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, }, | |
1185 | { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, }, | |
1186 | { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, }, | |
1187 | { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, }, | |
1188 | { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, }, | |
1189 | { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, }, | |
1190 | { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, }, | |
1191 | { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, }, | |
1192 | { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, }, | |
1193 | { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, }, | |
1194 | { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, }, | |
1195 | { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, }, | |
1196 | { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, }, | |
1197 | { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, }, | |
1198 | { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, }, | |
1199 | { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, }, | |
1200 | { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, }, | |
1201 | { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, }, | |
1202 | { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, }, | |
1203 | { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, }, | |
1204 | { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, }, | |
1205 | { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1206 | { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, }, | |
1207 | }; | |
550a7375 FB |
1208 | |
1209 | /* | |
1210 | * configure a fifo; for non-shared endpoints, this may be called | |
1211 | * once for a tx fifo and once for an rx fifo. | |
1212 | * | |
1213 | * returns negative errno or offset for next fifo. | |
1214 | */ | |
41ac7b3a | 1215 | static int |
550a7375 | 1216 | fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep, |
e6c213b2 | 1217 | const struct musb_fifo_cfg *cfg, u16 offset) |
550a7375 FB |
1218 | { |
1219 | void __iomem *mbase = musb->mregs; | |
1220 | int size = 0; | |
1221 | u16 maxpacket = cfg->maxpacket; | |
1222 | u16 c_off = offset >> 3; | |
1223 | u8 c_size; | |
1224 | ||
1225 | /* expect hw_ep has already been zero-initialized */ | |
1226 | ||
1227 | size = ffs(max(maxpacket, (u16) 8)) - 1; | |
1228 | maxpacket = 1 << size; | |
1229 | ||
1230 | c_size = size - 3; | |
1231 | if (cfg->mode == BUF_DOUBLE) { | |
ca6d1b13 FB |
1232 | if ((offset + (maxpacket << 1)) > |
1233 | (1 << (musb->config->ram_bits + 2))) | |
550a7375 FB |
1234 | return -EMSGSIZE; |
1235 | c_size |= MUSB_FIFOSZ_DPB; | |
1236 | } else { | |
ca6d1b13 | 1237 | if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2))) |
550a7375 FB |
1238 | return -EMSGSIZE; |
1239 | } | |
1240 | ||
1241 | /* configure the FIFO */ | |
1242 | musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum); | |
1243 | ||
550a7375 | 1244 | /* EP0 reserved endpoint for control, bidirectional; |
5ae477b0 | 1245 | * EP1 reserved for bulk, two unidirectional halves. |
550a7375 FB |
1246 | */ |
1247 | if (hw_ep->epnum == 1) | |
1248 | musb->bulk_ep = hw_ep; | |
1249 | /* REVISIT error check: be sure ep0 can both rx and tx ... */ | |
550a7375 FB |
1250 | switch (cfg->style) { |
1251 | case FIFO_TX: | |
c6cf8b00 BW |
1252 | musb_write_txfifosz(mbase, c_size); |
1253 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1254 | hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1255 | hw_ep->max_packet_sz_tx = maxpacket; | |
1256 | break; | |
1257 | case FIFO_RX: | |
c6cf8b00 BW |
1258 | musb_write_rxfifosz(mbase, c_size); |
1259 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1260 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1261 | hw_ep->max_packet_sz_rx = maxpacket; | |
1262 | break; | |
1263 | case FIFO_RXTX: | |
c6cf8b00 BW |
1264 | musb_write_txfifosz(mbase, c_size); |
1265 | musb_write_txfifoadd(mbase, c_off); | |
550a7375 FB |
1266 | hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB); |
1267 | hw_ep->max_packet_sz_rx = maxpacket; | |
1268 | ||
c6cf8b00 BW |
1269 | musb_write_rxfifosz(mbase, c_size); |
1270 | musb_write_rxfifoadd(mbase, c_off); | |
550a7375 FB |
1271 | hw_ep->tx_double_buffered = hw_ep->rx_double_buffered; |
1272 | hw_ep->max_packet_sz_tx = maxpacket; | |
1273 | ||
1274 | hw_ep->is_shared_fifo = true; | |
1275 | break; | |
1276 | } | |
1277 | ||
1278 | /* NOTE rx and tx endpoint irqs aren't managed separately, | |
1279 | * which happens to be ok | |
1280 | */ | |
1281 | musb->epmask |= (1 << hw_ep->epnum); | |
1282 | ||
1283 | return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0)); | |
1284 | } | |
1285 | ||
d3608b6d | 1286 | static struct musb_fifo_cfg ep0_cfg = { |
550a7375 FB |
1287 | .style = FIFO_RXTX, .maxpacket = 64, |
1288 | }; | |
1289 | ||
41ac7b3a | 1290 | static int ep_config_from_table(struct musb *musb) |
550a7375 | 1291 | { |
e6c213b2 | 1292 | const struct musb_fifo_cfg *cfg; |
550a7375 FB |
1293 | unsigned i, n; |
1294 | int offset; | |
1295 | struct musb_hw_ep *hw_ep = musb->endpoints; | |
1296 | ||
e6c213b2 FB |
1297 | if (musb->config->fifo_cfg) { |
1298 | cfg = musb->config->fifo_cfg; | |
1299 | n = musb->config->fifo_cfg_size; | |
1300 | goto done; | |
1301 | } | |
1302 | ||
550a7375 FB |
1303 | switch (fifo_mode) { |
1304 | default: | |
1305 | fifo_mode = 0; | |
1306 | /* FALLTHROUGH */ | |
1307 | case 0: | |
1308 | cfg = mode_0_cfg; | |
1309 | n = ARRAY_SIZE(mode_0_cfg); | |
1310 | break; | |
1311 | case 1: | |
1312 | cfg = mode_1_cfg; | |
1313 | n = ARRAY_SIZE(mode_1_cfg); | |
1314 | break; | |
1315 | case 2: | |
1316 | cfg = mode_2_cfg; | |
1317 | n = ARRAY_SIZE(mode_2_cfg); | |
1318 | break; | |
1319 | case 3: | |
1320 | cfg = mode_3_cfg; | |
1321 | n = ARRAY_SIZE(mode_3_cfg); | |
1322 | break; | |
1323 | case 4: | |
1324 | cfg = mode_4_cfg; | |
1325 | n = ARRAY_SIZE(mode_4_cfg); | |
1326 | break; | |
3b151526 AKG |
1327 | case 5: |
1328 | cfg = mode_5_cfg; | |
1329 | n = ARRAY_SIZE(mode_5_cfg); | |
1330 | break; | |
550a7375 FB |
1331 | } |
1332 | ||
3ff4b573 | 1333 | pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode); |
550a7375 FB |
1334 | |
1335 | ||
e6c213b2 | 1336 | done: |
550a7375 FB |
1337 | offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0); |
1338 | /* assert(offset > 0) */ | |
1339 | ||
1340 | /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would | |
ca6d1b13 | 1341 | * be better than static musb->config->num_eps and DYN_FIFO_SIZE... |
550a7375 FB |
1342 | */ |
1343 | ||
1344 | for (i = 0; i < n; i++) { | |
1345 | u8 epn = cfg->hw_ep_num; | |
1346 | ||
ca6d1b13 | 1347 | if (epn >= musb->config->num_eps) { |
550a7375 FB |
1348 | pr_debug("%s: invalid ep %d\n", |
1349 | musb_driver_name, epn); | |
bb1c9ef1 | 1350 | return -EINVAL; |
550a7375 FB |
1351 | } |
1352 | offset = fifo_setup(musb, hw_ep + epn, cfg++, offset); | |
1353 | if (offset < 0) { | |
1354 | pr_debug("%s: mem overrun, ep %d\n", | |
1355 | musb_driver_name, epn); | |
f69dfa1f | 1356 | return offset; |
550a7375 FB |
1357 | } |
1358 | epn++; | |
1359 | musb->nr_endpoints = max(epn, musb->nr_endpoints); | |
1360 | } | |
1361 | ||
3ff4b573 | 1362 | pr_debug("%s: %d/%d max ep, %d/%d memory\n", |
550a7375 | 1363 | musb_driver_name, |
ca6d1b13 FB |
1364 | n + 1, musb->config->num_eps * 2 - 1, |
1365 | offset, (1 << (musb->config->ram_bits + 2))); | |
550a7375 | 1366 | |
550a7375 FB |
1367 | if (!musb->bulk_ep) { |
1368 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1369 | return -EINVAL; | |
1370 | } | |
550a7375 FB |
1371 | |
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | ||
1376 | /* | |
1377 | * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false | |
1378 | * @param musb the controller | |
1379 | */ | |
41ac7b3a | 1380 | static int ep_config_from_hw(struct musb *musb) |
550a7375 | 1381 | { |
c6cf8b00 | 1382 | u8 epnum = 0; |
550a7375 | 1383 | struct musb_hw_ep *hw_ep; |
a156544b | 1384 | void __iomem *mbase = musb->mregs; |
c6cf8b00 | 1385 | int ret = 0; |
550a7375 | 1386 | |
b99d3659 | 1387 | musb_dbg(musb, "<== static silicon ep config"); |
550a7375 FB |
1388 | |
1389 | /* FIXME pick up ep0 maxpacket size */ | |
1390 | ||
ca6d1b13 | 1391 | for (epnum = 1; epnum < musb->config->num_eps; epnum++) { |
550a7375 FB |
1392 | musb_ep_select(mbase, epnum); |
1393 | hw_ep = musb->endpoints + epnum; | |
1394 | ||
c6cf8b00 BW |
1395 | ret = musb_read_fifosize(musb, hw_ep, epnum); |
1396 | if (ret < 0) | |
550a7375 | 1397 | break; |
550a7375 FB |
1398 | |
1399 | /* FIXME set up hw_ep->{rx,tx}_double_buffered */ | |
1400 | ||
550a7375 FB |
1401 | /* pick an RX/TX endpoint for bulk */ |
1402 | if (hw_ep->max_packet_sz_tx < 512 | |
1403 | || hw_ep->max_packet_sz_rx < 512) | |
1404 | continue; | |
1405 | ||
1406 | /* REVISIT: this algorithm is lazy, we should at least | |
1407 | * try to pick a double buffered endpoint. | |
1408 | */ | |
1409 | if (musb->bulk_ep) | |
1410 | continue; | |
1411 | musb->bulk_ep = hw_ep; | |
550a7375 FB |
1412 | } |
1413 | ||
550a7375 FB |
1414 | if (!musb->bulk_ep) { |
1415 | pr_debug("%s: missing bulk\n", musb_driver_name); | |
1416 | return -EINVAL; | |
1417 | } | |
550a7375 FB |
1418 | |
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, }; | |
1423 | ||
1424 | /* Initialize MUSB (M)HDRC part of the USB hardware subsystem; | |
1425 | * configure endpoints, or take their config from silicon | |
1426 | */ | |
41ac7b3a | 1427 | static int musb_core_init(u16 musb_type, struct musb *musb) |
550a7375 | 1428 | { |
550a7375 FB |
1429 | u8 reg; |
1430 | char *type; | |
21b031fb | 1431 | char aInfo[90]; |
550a7375 FB |
1432 | void __iomem *mbase = musb->mregs; |
1433 | int status = 0; | |
1434 | int i; | |
1435 | ||
1436 | /* log core options (read using indexed model) */ | |
c6cf8b00 | 1437 | reg = musb_read_configdata(mbase); |
550a7375 FB |
1438 | |
1439 | strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8"); | |
51bf0d0e | 1440 | if (reg & MUSB_CONFIGDATA_DYNFIFO) { |
550a7375 | 1441 | strcat(aInfo, ", dyn FIFOs"); |
51bf0d0e AKG |
1442 | musb->dyn_fifo = true; |
1443 | } | |
550a7375 FB |
1444 | if (reg & MUSB_CONFIGDATA_MPRXE) { |
1445 | strcat(aInfo, ", bulk combine"); | |
550a7375 | 1446 | musb->bulk_combine = true; |
550a7375 FB |
1447 | } |
1448 | if (reg & MUSB_CONFIGDATA_MPTXE) { | |
1449 | strcat(aInfo, ", bulk split"); | |
550a7375 | 1450 | musb->bulk_split = true; |
550a7375 FB |
1451 | } |
1452 | if (reg & MUSB_CONFIGDATA_HBRXE) { | |
1453 | strcat(aInfo, ", HB-ISO Rx"); | |
a483d706 | 1454 | musb->hb_iso_rx = true; |
550a7375 FB |
1455 | } |
1456 | if (reg & MUSB_CONFIGDATA_HBTXE) { | |
1457 | strcat(aInfo, ", HB-ISO Tx"); | |
a483d706 | 1458 | musb->hb_iso_tx = true; |
550a7375 FB |
1459 | } |
1460 | if (reg & MUSB_CONFIGDATA_SOFTCONE) | |
1461 | strcat(aInfo, ", SoftConn"); | |
1462 | ||
3ff4b573 | 1463 | pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo); |
550a7375 | 1464 | |
550a7375 FB |
1465 | if (MUSB_CONTROLLER_MHDRC == musb_type) { |
1466 | musb->is_multipoint = 1; | |
1467 | type = "M"; | |
1468 | } else { | |
1469 | musb->is_multipoint = 0; | |
1470 | type = ""; | |
550a7375 | 1471 | #ifndef CONFIG_USB_OTG_BLACKLIST_HUB |
3ff4b573 RV |
1472 | pr_err("%s: kernel must blacklist external hubs\n", |
1473 | musb_driver_name); | |
550a7375 FB |
1474 | #endif |
1475 | } | |
1476 | ||
1477 | /* log release info */ | |
32c3b94e | 1478 | musb->hwvers = musb_read_hwvers(mbase); |
21b031fb RV |
1479 | pr_debug("%s: %sHDRC RTL version %d.%d%s\n", |
1480 | musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers), | |
1481 | MUSB_HWVERS_MINOR(musb->hwvers), | |
1482 | (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : ""); | |
550a7375 FB |
1483 | |
1484 | /* configure ep0 */ | |
c6cf8b00 | 1485 | musb_configure_ep0(musb); |
550a7375 FB |
1486 | |
1487 | /* discover endpoint configuration */ | |
1488 | musb->nr_endpoints = 1; | |
1489 | musb->epmask = 1; | |
1490 | ||
ad517e9e FB |
1491 | if (musb->dyn_fifo) |
1492 | status = ep_config_from_table(musb); | |
1493 | else | |
1494 | status = ep_config_from_hw(musb); | |
550a7375 FB |
1495 | |
1496 | if (status < 0) | |
1497 | return status; | |
1498 | ||
1499 | /* finish init, and print endpoint config */ | |
1500 | for (i = 0; i < musb->nr_endpoints; i++) { | |
1501 | struct musb_hw_ep *hw_ep = musb->endpoints + i; | |
1502 | ||
1b40fc57 | 1503 | hw_ep->fifo = musb->io.fifo_offset(i) + mbase; |
ebf39920 | 1504 | #if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010) |
1b40fc57 TL |
1505 | if (musb->io.quirks & MUSB_IN_TUSB) { |
1506 | hw_ep->fifo_async = musb->async + 0x400 + | |
1507 | musb->io.fifo_offset(i); | |
1508 | hw_ep->fifo_sync = musb->sync + 0x400 + | |
1509 | musb->io.fifo_offset(i); | |
1510 | hw_ep->fifo_sync_va = | |
1511 | musb->sync_va + 0x400 + musb->io.fifo_offset(i); | |
1512 | ||
1513 | if (i == 0) | |
1514 | hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF; | |
1515 | else | |
1516 | hw_ep->conf = mbase + 0x400 + | |
1517 | (((i - 1) & 0xf) << 2); | |
1518 | } | |
550a7375 FB |
1519 | #endif |
1520 | ||
d026e9c7 | 1521 | hw_ep->regs = musb->io.ep_offset(i, 0) + mbase; |
550a7375 FB |
1522 | hw_ep->rx_reinit = 1; |
1523 | hw_ep->tx_reinit = 1; | |
550a7375 FB |
1524 | |
1525 | if (hw_ep->max_packet_sz_tx) { | |
b99d3659 | 1526 | musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", |
550a7375 FB |
1527 | musb_driver_name, i, |
1528 | hw_ep->is_shared_fifo ? "shared" : "tx", | |
1529 | hw_ep->tx_double_buffered | |
1530 | ? "doublebuffer, " : "", | |
1531 | hw_ep->max_packet_sz_tx); | |
1532 | } | |
1533 | if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) { | |
b99d3659 | 1534 | musb_dbg(musb, "%s: hw_ep %d%s, %smax %d", |
550a7375 FB |
1535 | musb_driver_name, i, |
1536 | "rx", | |
1537 | hw_ep->rx_double_buffered | |
1538 | ? "doublebuffer, " : "", | |
1539 | hw_ep->max_packet_sz_rx); | |
1540 | } | |
1541 | if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx)) | |
b99d3659 | 1542 | musb_dbg(musb, "hw_ep %d not configured", i); |
550a7375 FB |
1543 | } |
1544 | ||
1545 | return 0; | |
1546 | } | |
1547 | ||
1548 | /*-------------------------------------------------------------------------*/ | |
1549 | ||
550a7375 FB |
1550 | /* |
1551 | * handle all the irqs defined by the HDRC core. for now we expect: other | |
1552 | * irq sources (phy, dma, etc) will be handled first, musb->int_* values | |
1553 | * will be assigned, and the irq will already have been acked. | |
1554 | * | |
1555 | * called in irq context with spinlock held, irqs blocked | |
1556 | */ | |
1557 | irqreturn_t musb_interrupt(struct musb *musb) | |
1558 | { | |
1559 | irqreturn_t retval = IRQ_NONE; | |
31a0ede0 FB |
1560 | unsigned long status; |
1561 | unsigned long epnum; | |
b11e94d0 | 1562 | u8 devctl; |
31a0ede0 FB |
1563 | |
1564 | if (!musb->int_usb && !musb->int_tx && !musb->int_rx) | |
1565 | return IRQ_NONE; | |
550a7375 FB |
1566 | |
1567 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
550a7375 | 1568 | |
cfb9a1bc | 1569 | trace_musb_isr(musb); |
550a7375 | 1570 | |
e3c93e1a FB |
1571 | /** |
1572 | * According to Mentor Graphics' documentation, flowchart on page 98, | |
1573 | * IRQ should be handled as follows: | |
1574 | * | |
1575 | * . Resume IRQ | |
1576 | * . Session Request IRQ | |
1577 | * . VBUS Error IRQ | |
1578 | * . Suspend IRQ | |
1579 | * . Connect IRQ | |
1580 | * . Disconnect IRQ | |
1581 | * . Reset/Babble IRQ | |
1582 | * . SOF IRQ (we're not using this one) | |
1583 | * . Endpoint 0 IRQ | |
1584 | * . TX Endpoints | |
1585 | * . RX Endpoints | |
1586 | * | |
1587 | * We will be following that flowchart in order to avoid any problems | |
1588 | * that might arise with internal Finite State Machine. | |
550a7375 | 1589 | */ |
e3c93e1a | 1590 | |
7d9645fd | 1591 | if (musb->int_usb) |
31a0ede0 | 1592 | retval |= musb_stage0_irq(musb, musb->int_usb, devctl); |
550a7375 | 1593 | |
550a7375 | 1594 | if (musb->int_tx & 1) { |
c03da38d | 1595 | if (is_host_active(musb)) |
550a7375 FB |
1596 | retval |= musb_h_ep0_irq(musb); |
1597 | else | |
1598 | retval |= musb_g_ep0_irq(musb); | |
31a0ede0 FB |
1599 | |
1600 | /* we have just handled endpoint 0 IRQ, clear it */ | |
1601 | musb->int_tx &= ~BIT(0); | |
550a7375 FB |
1602 | } |
1603 | ||
31a0ede0 FB |
1604 | status = musb->int_tx; |
1605 | ||
1606 | for_each_set_bit(epnum, &status, 16) { | |
1607 | retval = IRQ_HANDLED; | |
1608 | if (is_host_active(musb)) | |
1609 | musb_host_tx(musb, epnum); | |
1610 | else | |
1611 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1612 | } |
1613 | ||
31a0ede0 | 1614 | status = musb->int_rx; |
e3c93e1a | 1615 | |
31a0ede0 FB |
1616 | for_each_set_bit(epnum, &status, 16) { |
1617 | retval = IRQ_HANDLED; | |
1618 | if (is_host_active(musb)) | |
1619 | musb_host_rx(musb, epnum); | |
1620 | else | |
1621 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1622 | } |
1623 | ||
550a7375 FB |
1624 | return retval; |
1625 | } | |
981430a1 | 1626 | EXPORT_SYMBOL_GPL(musb_interrupt); |
550a7375 FB |
1627 | |
1628 | #ifndef CONFIG_MUSB_PIO_ONLY | |
d3608b6d | 1629 | static bool use_dma = 1; |
550a7375 FB |
1630 | |
1631 | /* "modprobe ... use_dma=0" etc */ | |
51676c8d | 1632 | module_param(use_dma, bool, 0644); |
550a7375 FB |
1633 | MODULE_PARM_DESC(use_dma, "enable/disable use of DMA"); |
1634 | ||
1635 | void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit) | |
1636 | { | |
550a7375 FB |
1637 | /* called with controller lock already held */ |
1638 | ||
1639 | if (!epnum) { | |
f8e9f34f | 1640 | if (!is_cppi_enabled(musb)) { |
550a7375 | 1641 | /* endpoint 0 */ |
c03da38d | 1642 | if (is_host_active(musb)) |
550a7375 FB |
1643 | musb_h_ep0_irq(musb); |
1644 | else | |
1645 | musb_g_ep0_irq(musb); | |
1646 | } | |
550a7375 FB |
1647 | } else { |
1648 | /* endpoints 1..15 */ | |
1649 | if (transmit) { | |
c03da38d | 1650 | if (is_host_active(musb)) |
a04d46d0 FB |
1651 | musb_host_tx(musb, epnum); |
1652 | else | |
1653 | musb_g_tx(musb, epnum); | |
550a7375 FB |
1654 | } else { |
1655 | /* receive */ | |
c03da38d | 1656 | if (is_host_active(musb)) |
a04d46d0 FB |
1657 | musb_host_rx(musb, epnum); |
1658 | else | |
1659 | musb_g_rx(musb, epnum); | |
550a7375 FB |
1660 | } |
1661 | } | |
1662 | } | |
9a35f876 | 1663 | EXPORT_SYMBOL_GPL(musb_dma_completion); |
550a7375 FB |
1664 | |
1665 | #else | |
1666 | #define use_dma 0 | |
1667 | #endif | |
1668 | ||
12b7db2b | 1669 | static int (*musb_phy_callback)(enum musb_vbus_id_status status); |
8055555f TL |
1670 | |
1671 | /* | |
1672 | * musb_mailbox - optional phy notifier function | |
1673 | * @status phy state change | |
1674 | * | |
1675 | * Optionally gets called from the USB PHY. Note that the USB PHY must be | |
1676 | * disabled at the point the phy_callback is registered or unregistered. | |
1677 | */ | |
12b7db2b | 1678 | int musb_mailbox(enum musb_vbus_id_status status) |
8055555f TL |
1679 | { |
1680 | if (musb_phy_callback) | |
12b7db2b | 1681 | return musb_phy_callback(status); |
8055555f | 1682 | |
12b7db2b | 1683 | return -ENODEV; |
8055555f TL |
1684 | }; |
1685 | EXPORT_SYMBOL_GPL(musb_mailbox); | |
1686 | ||
550a7375 FB |
1687 | /*-------------------------------------------------------------------------*/ |
1688 | ||
550a7375 | 1689 | static ssize_t |
ed5bd7a4 | 1690 | mode_show(struct device *dev, struct device_attribute *attr, char *buf) |
550a7375 FB |
1691 | { |
1692 | struct musb *musb = dev_to_musb(dev); | |
1693 | unsigned long flags; | |
1694 | int ret = -EINVAL; | |
1695 | ||
1696 | spin_lock_irqsave(&musb->lock, flags); | |
e47d9254 | 1697 | ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state)); |
550a7375 FB |
1698 | spin_unlock_irqrestore(&musb->lock, flags); |
1699 | ||
1700 | return ret; | |
1701 | } | |
1702 | ||
1703 | static ssize_t | |
ed5bd7a4 | 1704 | mode_store(struct device *dev, struct device_attribute *attr, |
550a7375 FB |
1705 | const char *buf, size_t n) |
1706 | { | |
1707 | struct musb *musb = dev_to_musb(dev); | |
1708 | unsigned long flags; | |
96a274d1 | 1709 | int status; |
550a7375 FB |
1710 | |
1711 | spin_lock_irqsave(&musb->lock, flags); | |
96a274d1 DB |
1712 | if (sysfs_streq(buf, "host")) |
1713 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
1714 | else if (sysfs_streq(buf, "peripheral")) | |
1715 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
1716 | else if (sysfs_streq(buf, "otg")) | |
1717 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
1718 | else | |
1719 | status = -EINVAL; | |
550a7375 FB |
1720 | spin_unlock_irqrestore(&musb->lock, flags); |
1721 | ||
96a274d1 | 1722 | return (status == 0) ? n : status; |
550a7375 | 1723 | } |
ed5bd7a4 | 1724 | static DEVICE_ATTR_RW(mode); |
550a7375 FB |
1725 | |
1726 | static ssize_t | |
ed5bd7a4 | 1727 | vbus_store(struct device *dev, struct device_attribute *attr, |
550a7375 FB |
1728 | const char *buf, size_t n) |
1729 | { | |
1730 | struct musb *musb = dev_to_musb(dev); | |
1731 | unsigned long flags; | |
1732 | unsigned long val; | |
1733 | ||
1734 | if (sscanf(buf, "%lu", &val) < 1) { | |
b3b1cc3b | 1735 | dev_err(dev, "Invalid VBUS timeout ms value\n"); |
550a7375 FB |
1736 | return -EINVAL; |
1737 | } | |
1738 | ||
1739 | spin_lock_irqsave(&musb->lock, flags); | |
f7f9d63e DB |
1740 | /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */ |
1741 | musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ; | |
e47d9254 | 1742 | if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) |
550a7375 FB |
1743 | musb->is_active = 0; |
1744 | musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val)); | |
1745 | spin_unlock_irqrestore(&musb->lock, flags); | |
1746 | ||
1747 | return n; | |
1748 | } | |
1749 | ||
1750 | static ssize_t | |
ed5bd7a4 | 1751 | vbus_show(struct device *dev, struct device_attribute *attr, char *buf) |
550a7375 FB |
1752 | { |
1753 | struct musb *musb = dev_to_musb(dev); | |
1754 | unsigned long flags; | |
1755 | unsigned long val; | |
1756 | int vbus; | |
3bbafac8 | 1757 | u8 devctl; |
550a7375 FB |
1758 | |
1759 | spin_lock_irqsave(&musb->lock, flags); | |
1760 | val = musb->a_wait_bcon; | |
1761 | vbus = musb_platform_get_vbus_status(musb); | |
3bbafac8 RA |
1762 | if (vbus < 0) { |
1763 | /* Use default MUSB method by means of DEVCTL register */ | |
1764 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1765 | if ((devctl & MUSB_DEVCTL_VBUS) | |
1766 | == (3 << MUSB_DEVCTL_VBUS_SHIFT)) | |
1767 | vbus = 1; | |
1768 | else | |
1769 | vbus = 0; | |
1770 | } | |
550a7375 FB |
1771 | spin_unlock_irqrestore(&musb->lock, flags); |
1772 | ||
f7f9d63e | 1773 | return sprintf(buf, "Vbus %s, timeout %lu msec\n", |
550a7375 FB |
1774 | vbus ? "on" : "off", val); |
1775 | } | |
ed5bd7a4 | 1776 | static DEVICE_ATTR_RW(vbus); |
550a7375 | 1777 | |
550a7375 FB |
1778 | /* Gadget drivers can't know that a host is connected so they might want |
1779 | * to start SRP, but users can. This allows userspace to trigger SRP. | |
1780 | */ | |
6e4294d0 | 1781 | static ssize_t srp_store(struct device *dev, struct device_attribute *attr, |
550a7375 FB |
1782 | const char *buf, size_t n) |
1783 | { | |
1784 | struct musb *musb = dev_to_musb(dev); | |
1785 | unsigned short srp; | |
1786 | ||
1787 | if (sscanf(buf, "%hu", &srp) != 1 | |
1788 | || (srp != 1)) { | |
b3b1cc3b | 1789 | dev_err(dev, "SRP: Value must be 1\n"); |
550a7375 FB |
1790 | return -EINVAL; |
1791 | } | |
1792 | ||
1793 | if (srp == 1) | |
1794 | musb_g_wakeup(musb); | |
1795 | ||
1796 | return n; | |
1797 | } | |
6e4294d0 | 1798 | static DEVICE_ATTR_WO(srp); |
550a7375 | 1799 | |
94375751 FB |
1800 | static struct attribute *musb_attributes[] = { |
1801 | &dev_attr_mode.attr, | |
1802 | &dev_attr_vbus.attr, | |
94375751 | 1803 | &dev_attr_srp.attr, |
94375751 FB |
1804 | NULL |
1805 | }; | |
1806 | ||
1807 | static const struct attribute_group musb_attr_group = { | |
1808 | .attrs = musb_attributes, | |
1809 | }; | |
1810 | ||
467d5c98 TL |
1811 | #define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \ |
1812 | (2 << MUSB_DEVCTL_VBUS_SHIFT) | \ | |
1813 | MUSB_DEVCTL_SESSION) | |
1814 | #define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \ | |
1815 | MUSB_DEVCTL_SESSION) | |
1816 | ||
1817 | /* | |
1818 | * Check the musb devctl session bit to determine if we want to | |
1819 | * allow PM runtime for the device. In general, we want to keep things | |
1820 | * active when the session bit is set except after host disconnect. | |
1821 | * | |
1822 | * Only called from musb_irq_work. If this ever needs to get called | |
1823 | * elsewhere, proper locking must be implemented for musb->session. | |
1824 | */ | |
1825 | static void musb_pm_runtime_check_session(struct musb *musb) | |
1826 | { | |
1827 | u8 devctl, s; | |
1828 | int error; | |
1829 | ||
1830 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1831 | ||
1832 | /* Handle session status quirks first */ | |
1833 | s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV | | |
1834 | MUSB_DEVCTL_HR; | |
1835 | switch (devctl & ~s) { | |
1836 | case MUSB_QUIRK_B_INVALID_VBUS_91: | |
0c3aae9b | 1837 | if (musb->quirk_retries && !musb->flush_irq_work) { |
2b9a8c40 | 1838 | musb_dbg(musb, |
2bff3916 TL |
1839 | "Poll devctl on invalid vbus, assume no session"); |
1840 | schedule_delayed_work(&musb->irq_work, | |
1841 | msecs_to_jiffies(1000)); | |
4f190e0b | 1842 | musb->quirk_retries--; |
2b9a8c40 TL |
1843 | return; |
1844 | } | |
eff0b85e | 1845 | /* fall through */ |
467d5c98 | 1846 | case MUSB_QUIRK_A_DISCONNECT_19: |
0c3aae9b | 1847 | if (musb->quirk_retries && !musb->flush_irq_work) { |
2bff3916 TL |
1848 | musb_dbg(musb, |
1849 | "Poll devctl on possible host mode disconnect"); | |
1850 | schedule_delayed_work(&musb->irq_work, | |
1851 | msecs_to_jiffies(1000)); | |
4f190e0b | 1852 | musb->quirk_retries--; |
2bff3916 TL |
1853 | return; |
1854 | } | |
467d5c98 TL |
1855 | if (!musb->session) |
1856 | break; | |
1857 | musb_dbg(musb, "Allow PM on possible host mode disconnect"); | |
1858 | pm_runtime_mark_last_busy(musb->controller); | |
1859 | pm_runtime_put_autosuspend(musb->controller); | |
1860 | musb->session = false; | |
1861 | return; | |
1862 | default: | |
1863 | break; | |
1864 | } | |
1865 | ||
1866 | /* No need to do anything if session has not changed */ | |
1867 | s = devctl & MUSB_DEVCTL_SESSION; | |
1868 | if (s == musb->session) | |
1869 | return; | |
1870 | ||
1871 | /* Block PM or allow PM? */ | |
1872 | if (s) { | |
1873 | musb_dbg(musb, "Block PM on active session: %02x", devctl); | |
1874 | error = pm_runtime_get_sync(musb->controller); | |
1875 | if (error < 0) | |
1876 | dev_err(musb->controller, "Could not enable: %i\n", | |
1877 | error); | |
2bff3916 | 1878 | musb->quirk_retries = 3; |
467d5c98 TL |
1879 | } else { |
1880 | musb_dbg(musb, "Allow PM with no session: %02x", devctl); | |
1881 | pm_runtime_mark_last_busy(musb->controller); | |
1882 | pm_runtime_put_autosuspend(musb->controller); | |
1883 | } | |
1884 | ||
1885 | musb->session = s; | |
1886 | } | |
1887 | ||
550a7375 FB |
1888 | /* Only used to provide driver mode change events */ |
1889 | static void musb_irq_work(struct work_struct *data) | |
1890 | { | |
2bff3916 | 1891 | struct musb *musb = container_of(data, struct musb, irq_work.work); |
3ba7b779 TL |
1892 | int error; |
1893 | ||
1894 | error = pm_runtime_get_sync(musb->controller); | |
1895 | if (error < 0) { | |
1896 | dev_err(musb->controller, "Could not enable: %i\n", error); | |
1897 | ||
1898 | return; | |
1899 | } | |
550a7375 | 1900 | |
467d5c98 TL |
1901 | musb_pm_runtime_check_session(musb); |
1902 | ||
e47d9254 AT |
1903 | if (musb->xceiv->otg->state != musb->xceiv_old_state) { |
1904 | musb->xceiv_old_state = musb->xceiv->otg->state; | |
550a7375 FB |
1905 | sysfs_notify(&musb->controller->kobj, NULL, "mode"); |
1906 | } | |
3ba7b779 TL |
1907 | |
1908 | pm_runtime_mark_last_busy(musb->controller); | |
1909 | pm_runtime_put_autosuspend(musb->controller); | |
550a7375 FB |
1910 | } |
1911 | ||
83b8f5b8 | 1912 | static void musb_recover_from_babble(struct musb *musb) |
ca88fc2e | 1913 | { |
b4dc38fd FB |
1914 | int ret; |
1915 | u8 devctl; | |
ca88fc2e | 1916 | |
0244336f FB |
1917 | musb_disable_interrupts(musb); |
1918 | ||
83b8f5b8 FB |
1919 | /* |
1920 | * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give | |
1921 | * it some slack and wait for 10us. | |
1922 | */ | |
1923 | udelay(10); | |
1924 | ||
b28a6432 | 1925 | ret = musb_platform_recover(musb); |
ba7ee8bb FB |
1926 | if (ret) { |
1927 | musb_enable_interrupts(musb); | |
d871c622 | 1928 | return; |
ba7ee8bb | 1929 | } |
ca88fc2e | 1930 | |
b4dc38fd FB |
1931 | /* drop session bit */ |
1932 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); | |
1933 | devctl &= ~MUSB_DEVCTL_SESSION; | |
1934 | musb_writeb(musb->mregs, MUSB_DEVCTL, devctl); | |
ca88fc2e | 1935 | |
b4dc38fd FB |
1936 | /* tell usbcore about it */ |
1937 | musb_root_disconnect(musb); | |
ca88fc2e DM |
1938 | |
1939 | /* | |
d871c622 GC |
1940 | * When a babble condition occurs, the musb controller |
1941 | * removes the session bit and the endpoint config is lost. | |
ca88fc2e DM |
1942 | */ |
1943 | if (musb->dyn_fifo) | |
b4dc38fd | 1944 | ret = ep_config_from_table(musb); |
ca88fc2e | 1945 | else |
b4dc38fd | 1946 | ret = ep_config_from_hw(musb); |
ca88fc2e | 1947 | |
b4dc38fd FB |
1948 | /* restart session */ |
1949 | if (ret == 0) | |
ca88fc2e DM |
1950 | musb_start(musb); |
1951 | } | |
1952 | ||
550a7375 FB |
1953 | /* -------------------------------------------------------------------------- |
1954 | * Init support | |
1955 | */ | |
1956 | ||
41ac7b3a | 1957 | static struct musb *allocate_instance(struct device *dev, |
ead22caf | 1958 | const struct musb_hdrc_config *config, void __iomem *mbase) |
550a7375 FB |
1959 | { |
1960 | struct musb *musb; | |
1961 | struct musb_hw_ep *ep; | |
1962 | int epnum; | |
74c2e936 | 1963 | int ret; |
550a7375 | 1964 | |
74c2e936 DM |
1965 | musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL); |
1966 | if (!musb) | |
550a7375 | 1967 | return NULL; |
550a7375 | 1968 | |
550a7375 FB |
1969 | INIT_LIST_HEAD(&musb->control); |
1970 | INIT_LIST_HEAD(&musb->in_bulk); | |
1971 | INIT_LIST_HEAD(&musb->out_bulk); | |
ea2f35c0 | 1972 | INIT_LIST_HEAD(&musb->pending_list); |
550a7375 | 1973 | |
550a7375 | 1974 | musb->vbuserr_retry = VBUSERR_RETRY_COUNT; |
f7f9d63e | 1975 | musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON; |
550a7375 FB |
1976 | musb->mregs = mbase; |
1977 | musb->ctrl_base = mbase; | |
1978 | musb->nIrq = -ENODEV; | |
ca6d1b13 | 1979 | musb->config = config; |
02582b92 | 1980 | BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS); |
550a7375 | 1981 | for (epnum = 0, ep = musb->endpoints; |
ca6d1b13 | 1982 | epnum < musb->config->num_eps; |
550a7375 | 1983 | epnum++, ep++) { |
550a7375 FB |
1984 | ep->musb = musb; |
1985 | ep->epnum = epnum; | |
1986 | } | |
1987 | ||
1988 | musb->controller = dev; | |
743411b3 | 1989 | |
74c2e936 DM |
1990 | ret = musb_host_alloc(musb); |
1991 | if (ret < 0) | |
1992 | goto err_free; | |
1993 | ||
1994 | dev_set_drvdata(dev, musb); | |
1995 | ||
550a7375 | 1996 | return musb; |
74c2e936 DM |
1997 | |
1998 | err_free: | |
1999 | return NULL; | |
550a7375 FB |
2000 | } |
2001 | ||
2002 | static void musb_free(struct musb *musb) | |
2003 | { | |
2004 | /* this has multiple entry modes. it handles fault cleanup after | |
2005 | * probe(), where things may be partially set up, as well as rmmod | |
2006 | * cleanup after everything's been de-activated. | |
2007 | */ | |
2008 | ||
2009 | #ifdef CONFIG_SYSFS | |
94375751 | 2010 | sysfs_remove_group(&musb->controller->kobj, &musb_attr_group); |
550a7375 FB |
2011 | #endif |
2012 | ||
97a39896 AKG |
2013 | if (musb->nIrq >= 0) { |
2014 | if (musb->irq_wake) | |
2015 | disable_irq_wake(musb->nIrq); | |
550a7375 FB |
2016 | free_irq(musb->nIrq, musb); |
2017 | } | |
550a7375 | 2018 | |
74c2e936 | 2019 | musb_host_free(musb); |
550a7375 FB |
2020 | } |
2021 | ||
ea2f35c0 TL |
2022 | struct musb_pending_work { |
2023 | int (*callback)(struct musb *musb, void *data); | |
2024 | void *data; | |
2025 | struct list_head node; | |
2026 | }; | |
2027 | ||
c8bd2ac3 | 2028 | #ifdef CONFIG_PM |
ea2f35c0 TL |
2029 | /* |
2030 | * Called from musb_runtime_resume(), musb_resume(), and | |
2031 | * musb_queue_resume_work(). Callers must take musb->lock. | |
2032 | */ | |
2033 | static int musb_run_resume_work(struct musb *musb) | |
2034 | { | |
2035 | struct musb_pending_work *w, *_w; | |
2036 | unsigned long flags; | |
2037 | int error = 0; | |
2038 | ||
2039 | spin_lock_irqsave(&musb->list_lock, flags); | |
2040 | list_for_each_entry_safe(w, _w, &musb->pending_list, node) { | |
2041 | if (w->callback) { | |
2042 | error = w->callback(musb, w->data); | |
2043 | if (error < 0) { | |
2044 | dev_err(musb->controller, | |
2045 | "resume callback %p failed: %i\n", | |
2046 | w->callback, error); | |
2047 | } | |
2048 | } | |
2049 | list_del(&w->node); | |
2050 | devm_kfree(musb->controller, w); | |
2051 | } | |
2052 | spin_unlock_irqrestore(&musb->list_lock, flags); | |
2053 | ||
2054 | return error; | |
2055 | } | |
c8bd2ac3 | 2056 | #endif |
ea2f35c0 TL |
2057 | |
2058 | /* | |
2059 | * Called to run work if device is active or else queue the work to happen | |
2060 | * on resume. Caller must take musb->lock and must hold an RPM reference. | |
2061 | * | |
2062 | * Note that we cowardly refuse queuing work after musb PM runtime | |
2063 | * resume is done calling musb_run_resume_work() and return -EINPROGRESS | |
2064 | * instead. | |
2065 | */ | |
2066 | int musb_queue_resume_work(struct musb *musb, | |
2067 | int (*callback)(struct musb *musb, void *data), | |
2068 | void *data) | |
2069 | { | |
2070 | struct musb_pending_work *w; | |
2071 | unsigned long flags; | |
2072 | int error; | |
2073 | ||
2074 | if (WARN_ON(!callback)) | |
2075 | return -EINVAL; | |
2076 | ||
2077 | if (pm_runtime_active(musb->controller)) | |
2078 | return callback(musb, data); | |
2079 | ||
2080 | w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC); | |
2081 | if (!w) | |
2082 | return -ENOMEM; | |
2083 | ||
2084 | w->callback = callback; | |
2085 | w->data = data; | |
2086 | spin_lock_irqsave(&musb->list_lock, flags); | |
2087 | if (musb->is_runtime_suspended) { | |
2088 | list_add_tail(&w->node, &musb->pending_list); | |
2089 | error = 0; | |
2090 | } else { | |
2091 | dev_err(musb->controller, "could not add resume work %p\n", | |
2092 | callback); | |
2093 | devm_kfree(musb->controller, w); | |
2094 | error = -EINPROGRESS; | |
2095 | } | |
2096 | spin_unlock_irqrestore(&musb->list_lock, flags); | |
2097 | ||
2098 | return error; | |
2099 | } | |
2100 | EXPORT_SYMBOL_GPL(musb_queue_resume_work); | |
2101 | ||
8ed1fb79 DM |
2102 | static void musb_deassert_reset(struct work_struct *work) |
2103 | { | |
2104 | struct musb *musb; | |
2105 | unsigned long flags; | |
2106 | ||
2107 | musb = container_of(work, struct musb, deassert_reset_work.work); | |
2108 | ||
2109 | spin_lock_irqsave(&musb->lock, flags); | |
2110 | ||
2111 | if (musb->port1_status & USB_PORT_STAT_RESET) | |
2112 | musb_port_reset(musb, false); | |
2113 | ||
2114 | spin_unlock_irqrestore(&musb->lock, flags); | |
2115 | } | |
2116 | ||
550a7375 FB |
2117 | /* |
2118 | * Perform generic per-controller initialization. | |
2119 | * | |
28dd924a SS |
2120 | * @dev: the controller (already clocked, etc) |
2121 | * @nIrq: IRQ number | |
2122 | * @ctrl: virtual address of controller registers, | |
550a7375 FB |
2123 | * not yet corrected for platform-specific offsets |
2124 | */ | |
41ac7b3a | 2125 | static int |
550a7375 FB |
2126 | musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl) |
2127 | { | |
2128 | int status; | |
2129 | struct musb *musb; | |
c1a7d67c | 2130 | struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); |
550a7375 FB |
2131 | |
2132 | /* The driver might handle more features than the board; OK. | |
2133 | * Fail when the board needs a feature that's not enabled. | |
2134 | */ | |
2135 | if (!plat) { | |
b99d3659 | 2136 | dev_err(dev, "no platform_data?\n"); |
34e2beb2 SS |
2137 | status = -ENODEV; |
2138 | goto fail0; | |
550a7375 | 2139 | } |
34e2beb2 | 2140 | |
550a7375 | 2141 | /* allocate */ |
ca6d1b13 | 2142 | musb = allocate_instance(dev, plat->config, ctrl); |
34e2beb2 SS |
2143 | if (!musb) { |
2144 | status = -ENOMEM; | |
2145 | goto fail0; | |
2146 | } | |
550a7375 FB |
2147 | |
2148 | spin_lock_init(&musb->lock); | |
ea2f35c0 | 2149 | spin_lock_init(&musb->list_lock); |
550a7375 | 2150 | musb->board_set_power = plat->set_power; |
550a7375 | 2151 | musb->min_power = plat->min_power; |
f7ec9437 | 2152 | musb->ops = plat->platform_ops; |
9ad96e69 | 2153 | musb->port_mode = plat->mode; |
550a7375 | 2154 | |
1b40fc57 TL |
2155 | /* |
2156 | * Initialize the default IO functions. At least omap2430 needs | |
2157 | * these early. We initialize the platform specific IO functions | |
2158 | * later on. | |
2159 | */ | |
2160 | musb_readb = musb_default_readb; | |
2161 | musb_writeb = musb_default_writeb; | |
2162 | musb_readw = musb_default_readw; | |
2163 | musb_writew = musb_default_writew; | |
2164 | musb_readl = musb_default_readl; | |
2165 | musb_writel = musb_default_writel; | |
2166 | ||
84e250ff | 2167 | /* The musb_platform_init() call: |
baef653a PDS |
2168 | * - adjusts musb->mregs |
2169 | * - sets the musb->isr | |
5ae477b0 | 2170 | * - may initialize an integrated transceiver |
721002ec | 2171 | * - initializes musb->xceiv, usually by otg_get_phy() |
84e250ff | 2172 | * - stops powering VBUS |
84e250ff | 2173 | * |
7c9d440e | 2174 | * There are various transceiver configurations. Blackfin, |
84e250ff DB |
2175 | * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses |
2176 | * external/discrete ones in various flavors (twl4030 family, | |
2177 | * isp1504, non-OTG, etc) mostly hooking up through ULPI. | |
550a7375 | 2178 | */ |
ea65df57 | 2179 | status = musb_platform_init(musb); |
550a7375 | 2180 | if (status < 0) |
03491761 | 2181 | goto fail1; |
34e2beb2 | 2182 | |
550a7375 FB |
2183 | if (!musb->isr) { |
2184 | status = -ENODEV; | |
c04352a5 | 2185 | goto fail2; |
550a7375 FB |
2186 | } |
2187 | ||
1b40fc57 TL |
2188 | if (musb->ops->quirks) |
2189 | musb->io.quirks = musb->ops->quirks; | |
2190 | ||
da96cfc1 | 2191 | /* Most devices use indexed offset or flat offset */ |
d026e9c7 TL |
2192 | if (musb->io.quirks & MUSB_INDEXED_EP) { |
2193 | musb->io.ep_offset = musb_indexed_ep_offset; | |
2194 | musb->io.ep_select = musb_indexed_ep_select; | |
2195 | } else { | |
2196 | musb->io.ep_offset = musb_flat_ep_offset; | |
2197 | musb->io.ep_select = musb_flat_ep_select; | |
2198 | } | |
2199 | ||
1fa07c37 PU |
2200 | if (musb->io.quirks & MUSB_G_NO_SKB_RESERVE) |
2201 | musb->g.quirk_avoids_skb_reserve = 1; | |
2202 | ||
da96cfc1 BH |
2203 | /* At least tusb6010 has its own offsets */ |
2204 | if (musb->ops->ep_offset) | |
2205 | musb->io.ep_offset = musb->ops->ep_offset; | |
2206 | if (musb->ops->ep_select) | |
2207 | musb->io.ep_select = musb->ops->ep_select; | |
2208 | ||
8a77f05a TL |
2209 | if (musb->ops->fifo_mode) |
2210 | fifo_mode = musb->ops->fifo_mode; | |
2211 | else | |
2212 | fifo_mode = 4; | |
2213 | ||
1b40fc57 TL |
2214 | if (musb->ops->fifo_offset) |
2215 | musb->io.fifo_offset = musb->ops->fifo_offset; | |
2216 | else | |
2217 | musb->io.fifo_offset = musb_default_fifo_offset; | |
2218 | ||
6cc2af6d HG |
2219 | if (musb->ops->busctl_offset) |
2220 | musb->io.busctl_offset = musb->ops->busctl_offset; | |
2221 | else | |
2222 | musb->io.busctl_offset = musb_default_busctl_offset; | |
2223 | ||
1b40fc57 TL |
2224 | if (musb->ops->readb) |
2225 | musb_readb = musb->ops->readb; | |
2226 | if (musb->ops->writeb) | |
2227 | musb_writeb = musb->ops->writeb; | |
2228 | if (musb->ops->readw) | |
2229 | musb_readw = musb->ops->readw; | |
2230 | if (musb->ops->writew) | |
2231 | musb_writew = musb->ops->writew; | |
2232 | if (musb->ops->readl) | |
2233 | musb_readl = musb->ops->readl; | |
2234 | if (musb->ops->writel) | |
2235 | musb_writel = musb->ops->writel; | |
2236 | ||
7f6283ed TL |
2237 | #ifndef CONFIG_MUSB_PIO_ONLY |
2238 | if (!musb->ops->dma_init || !musb->ops->dma_exit) { | |
2239 | dev_err(dev, "DMA controller not set\n"); | |
7d32cdef | 2240 | status = -ENODEV; |
7f6283ed TL |
2241 | goto fail2; |
2242 | } | |
2243 | musb_dma_controller_create = musb->ops->dma_init; | |
2244 | musb_dma_controller_destroy = musb->ops->dma_exit; | |
2245 | #endif | |
2246 | ||
1b40fc57 TL |
2247 | if (musb->ops->read_fifo) |
2248 | musb->io.read_fifo = musb->ops->read_fifo; | |
2249 | else | |
2250 | musb->io.read_fifo = musb_default_read_fifo; | |
2251 | ||
2252 | if (musb->ops->write_fifo) | |
2253 | musb->io.write_fifo = musb->ops->write_fifo; | |
2254 | else | |
2255 | musb->io.write_fifo = musb_default_write_fifo; | |
2256 | ||
ffb865b1 | 2257 | if (!musb->xceiv->io_ops) { |
bf070bc1 | 2258 | musb->xceiv->io_dev = musb->controller; |
ffb865b1 HK |
2259 | musb->xceiv->io_priv = musb->mregs; |
2260 | musb->xceiv->io_ops = &musb_ulpi_access; | |
2261 | } | |
2262 | ||
8055555f TL |
2263 | if (musb->ops->phy_callback) |
2264 | musb_phy_callback = musb->ops->phy_callback; | |
2265 | ||
f730f205 TL |
2266 | /* |
2267 | * We need musb_read/write functions initialized for PM. | |
2268 | * Note that at least 2430 glue needs autosuspend delay | |
2269 | * somewhere above 300 ms for the hardware to idle properly | |
2270 | * after disconnecting the cable in host mode. Let's use | |
2271 | * 500 ms for some margin. | |
2272 | */ | |
2273 | pm_runtime_use_autosuspend(musb->controller); | |
2274 | pm_runtime_set_autosuspend_delay(musb->controller, 500); | |
2275 | pm_runtime_enable(musb->controller); | |
c04352a5 GI |
2276 | pm_runtime_get_sync(musb->controller); |
2277 | ||
39cee200 UKK |
2278 | status = usb_phy_init(musb->xceiv); |
2279 | if (status < 0) | |
2280 | goto err_usb_phy_init; | |
2281 | ||
48054147 | 2282 | if (use_dma && dev->dma_mask) { |
7f6283ed TL |
2283 | musb->dma_controller = |
2284 | musb_dma_controller_create(musb, musb->mregs); | |
48054147 SAS |
2285 | if (IS_ERR(musb->dma_controller)) { |
2286 | status = PTR_ERR(musb->dma_controller); | |
2287 | goto fail2_5; | |
2288 | } | |
2289 | } | |
550a7375 FB |
2290 | |
2291 | /* be sure interrupts are disabled before connecting ISR */ | |
2292 | musb_platform_disable(musb); | |
e945953d BL |
2293 | musb_disable_interrupts(musb); |
2294 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
550a7375 | 2295 | |
66fadea5 | 2296 | /* Init IRQ workqueue before request_irq */ |
2bff3916 | 2297 | INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work); |
8ed1fb79 DM |
2298 | INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset); |
2299 | INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume); | |
66fadea5 | 2300 | |
550a7375 | 2301 | /* setup musb parts of the core (especially endpoints) */ |
ca6d1b13 | 2302 | status = musb_core_init(plat->config->multipoint |
550a7375 FB |
2303 | ? MUSB_CONTROLLER_MHDRC |
2304 | : MUSB_CONTROLLER_HDRC, musb); | |
2305 | if (status < 0) | |
34e2beb2 | 2306 | goto fail3; |
550a7375 | 2307 | |
05678497 | 2308 | timer_setup(&musb->otg_timer, musb_otg_timer_func, 0); |
f7f9d63e | 2309 | |
550a7375 | 2310 | /* attach to the IRQ */ |
aa2fb886 | 2311 | if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) { |
550a7375 FB |
2312 | dev_err(dev, "request_irq %d failed!\n", nIrq); |
2313 | status = -ENODEV; | |
34e2beb2 | 2314 | goto fail3; |
550a7375 FB |
2315 | } |
2316 | musb->nIrq = nIrq; | |
032ec49f | 2317 | /* FIXME this handles wakeup irqs wrong */ |
c48a5155 FB |
2318 | if (enable_irq_wake(nIrq) == 0) { |
2319 | musb->irq_wake = 1; | |
550a7375 | 2320 | device_init_wakeup(dev, 1); |
c48a5155 FB |
2321 | } else { |
2322 | musb->irq_wake = 0; | |
2323 | } | |
550a7375 | 2324 | |
032ec49f FB |
2325 | /* program PHY to use external vBus if required */ |
2326 | if (plat->extvbus) { | |
2327 | u8 busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
2328 | busctl |= MUSB_ULPI_USE_EXTVBUS; | |
2329 | musb_write_ulpi_buscontrol(musb->mregs, busctl); | |
550a7375 | 2330 | } |
550a7375 | 2331 | |
e5615112 GI |
2332 | if (musb->xceiv->otg->default_a) { |
2333 | MUSB_HST_MODE(musb); | |
e47d9254 | 2334 | musb->xceiv->otg->state = OTG_STATE_A_IDLE; |
e5615112 GI |
2335 | } else { |
2336 | MUSB_DEV_MODE(musb); | |
e47d9254 | 2337 | musb->xceiv->otg->state = OTG_STATE_B_IDLE; |
e5615112 | 2338 | } |
550a7375 | 2339 | |
6c5f6a6f DM |
2340 | switch (musb->port_mode) { |
2341 | case MUSB_PORT_MODE_HOST: | |
2342 | status = musb_host_setup(musb, plat->power); | |
2df6761e FB |
2343 | if (status < 0) |
2344 | goto fail3; | |
2345 | status = musb_platform_set_mode(musb, MUSB_HOST); | |
6c5f6a6f DM |
2346 | break; |
2347 | case MUSB_PORT_MODE_GADGET: | |
2348 | status = musb_gadget_setup(musb); | |
2df6761e FB |
2349 | if (status < 0) |
2350 | goto fail3; | |
2351 | status = musb_platform_set_mode(musb, MUSB_PERIPHERAL); | |
6c5f6a6f DM |
2352 | break; |
2353 | case MUSB_PORT_MODE_DUAL_ROLE: | |
2354 | status = musb_host_setup(musb, plat->power); | |
2355 | if (status < 0) | |
2356 | goto fail3; | |
2357 | status = musb_gadget_setup(musb); | |
2df6761e | 2358 | if (status) { |
0d2dd7ea | 2359 | musb_host_cleanup(musb); |
2df6761e FB |
2360 | goto fail3; |
2361 | } | |
2362 | status = musb_platform_set_mode(musb, MUSB_OTG); | |
6c5f6a6f DM |
2363 | break; |
2364 | default: | |
2365 | dev_err(dev, "unsupported port mode %d\n", musb->port_mode); | |
2366 | break; | |
2367 | } | |
550a7375 | 2368 | |
461972d8 | 2369 | if (status < 0) |
34e2beb2 | 2370 | goto fail3; |
550a7375 | 2371 | |
7f7f9e2a FB |
2372 | status = musb_init_debugfs(musb); |
2373 | if (status < 0) | |
b0f9da7e | 2374 | goto fail4; |
7f7f9e2a | 2375 | |
94375751 | 2376 | status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group); |
28c2c51c | 2377 | if (status) |
b0f9da7e | 2378 | goto fail5; |
550a7375 | 2379 | |
c723bd6e | 2380 | musb->is_initialized = 1; |
7099dbc5 TL |
2381 | pm_runtime_mark_last_busy(musb->controller); |
2382 | pm_runtime_put_autosuspend(musb->controller); | |
c04352a5 | 2383 | |
28c2c51c | 2384 | return 0; |
550a7375 | 2385 | |
b0f9da7e FB |
2386 | fail5: |
2387 | musb_exit_debugfs(musb); | |
2388 | ||
34e2beb2 | 2389 | fail4: |
032ec49f | 2390 | musb_gadget_cleanup(musb); |
0d2dd7ea | 2391 | musb_host_cleanup(musb); |
34e2beb2 SS |
2392 | |
2393 | fail3: | |
2bff3916 | 2394 | cancel_delayed_work_sync(&musb->irq_work); |
8ed1fb79 DM |
2395 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2396 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
f3ce4d5b | 2397 | if (musb->dma_controller) |
7f6283ed | 2398 | musb_dma_controller_destroy(musb->dma_controller); |
39cee200 | 2399 | |
48054147 | 2400 | fail2_5: |
39cee200 UKK |
2401 | usb_phy_shutdown(musb->xceiv); |
2402 | ||
2403 | err_usb_phy_init: | |
7099dbc5 | 2404 | pm_runtime_dont_use_autosuspend(musb->controller); |
c04352a5 | 2405 | pm_runtime_put_sync(musb->controller); |
f730f205 | 2406 | pm_runtime_disable(musb->controller); |
c04352a5 GI |
2407 | |
2408 | fail2: | |
34e2beb2 SS |
2409 | if (musb->irq_wake) |
2410 | device_init_wakeup(dev, 0); | |
550a7375 | 2411 | musb_platform_exit(musb); |
28c2c51c | 2412 | |
34e2beb2 | 2413 | fail1: |
3df08dc7 LM |
2414 | if (status != -EPROBE_DEFER) |
2415 | dev_err(musb->controller, | |
2416 | "%s failed with status %d\n", __func__, status); | |
34e2beb2 | 2417 | |
28c2c51c FB |
2418 | musb_free(musb); |
2419 | ||
34e2beb2 SS |
2420 | fail0: |
2421 | ||
28c2c51c FB |
2422 | return status; |
2423 | ||
550a7375 FB |
2424 | } |
2425 | ||
2426 | /*-------------------------------------------------------------------------*/ | |
2427 | ||
2428 | /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just | |
2429 | * bridge to a platform device; this driver then suffices. | |
2430 | */ | |
41ac7b3a | 2431 | static int musb_probe(struct platform_device *pdev) |
550a7375 FB |
2432 | { |
2433 | struct device *dev = &pdev->dev; | |
fcf173e4 | 2434 | int irq = platform_get_irq_byname(pdev, "mc"); |
550a7375 FB |
2435 | struct resource *iomem; |
2436 | void __iomem *base; | |
2437 | ||
1f79b26c | 2438 | if (irq <= 0) |
550a7375 FB |
2439 | return -ENODEV; |
2440 | ||
1f79b26c | 2441 | iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b42f7f30 FB |
2442 | base = devm_ioremap_resource(dev, iomem); |
2443 | if (IS_ERR(base)) | |
2444 | return PTR_ERR(base); | |
550a7375 | 2445 | |
b42f7f30 | 2446 | return musb_init_controller(dev, irq, base); |
550a7375 FB |
2447 | } |
2448 | ||
fb4e98ab | 2449 | static int musb_remove(struct platform_device *pdev) |
550a7375 | 2450 | { |
8d2421e6 AKG |
2451 | struct device *dev = &pdev->dev; |
2452 | struct musb *musb = dev_to_musb(dev); | |
302f6802 | 2453 | unsigned long flags; |
550a7375 FB |
2454 | |
2455 | /* this gets called on rmmod. | |
2456 | * - Host mode: host may still be active | |
2457 | * - Peripheral mode: peripheral is deactivated (or never-activated) | |
2458 | * - OTG mode: both roles are deactivated (or never-activated) | |
2459 | */ | |
7f7f9e2a | 2460 | musb_exit_debugfs(musb); |
302f6802 | 2461 | |
2bff3916 | 2462 | cancel_delayed_work_sync(&musb->irq_work); |
f730f205 TL |
2463 | cancel_delayed_work_sync(&musb->finish_resume_work); |
2464 | cancel_delayed_work_sync(&musb->deassert_reset_work); | |
302f6802 TL |
2465 | pm_runtime_get_sync(musb->controller); |
2466 | musb_host_cleanup(musb); | |
2467 | musb_gadget_cleanup(musb); | |
e945953d | 2468 | |
302f6802 | 2469 | musb_platform_disable(musb); |
bc1e2154 | 2470 | spin_lock_irqsave(&musb->lock, flags); |
e945953d | 2471 | musb_disable_interrupts(musb); |
302f6802 | 2472 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); |
e945953d BL |
2473 | spin_unlock_irqrestore(&musb->lock, flags); |
2474 | ||
f730f205 TL |
2475 | pm_runtime_dont_use_autosuspend(musb->controller); |
2476 | pm_runtime_put_sync(musb->controller); | |
2477 | pm_runtime_disable(musb->controller); | |
302f6802 | 2478 | musb_platform_exit(musb); |
8055555f | 2479 | musb_phy_callback = NULL; |
8d1aad74 | 2480 | if (musb->dma_controller) |
7f6283ed | 2481 | musb_dma_controller_destroy(musb->dma_controller); |
39cee200 | 2482 | usb_phy_shutdown(musb->xceiv); |
550a7375 | 2483 | musb_free(musb); |
8d2421e6 | 2484 | device_init_wakeup(dev, 0); |
550a7375 FB |
2485 | return 0; |
2486 | } | |
2487 | ||
2488 | #ifdef CONFIG_PM | |
2489 | ||
3c8a5fcc | 2490 | static void musb_save_context(struct musb *musb) |
4f712e01 AKG |
2491 | { |
2492 | int i; | |
2493 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2494 | void __iomem *epio; |
4f712e01 | 2495 | |
032ec49f FB |
2496 | musb->context.frame = musb_readw(musb_base, MUSB_FRAME); |
2497 | musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE); | |
2498 | musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs); | |
7421107b | 2499 | musb->context.power = musb_readb(musb_base, MUSB_POWER); |
7421107b FB |
2500 | musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE); |
2501 | musb->context.index = musb_readb(musb_base, MUSB_INDEX); | |
2502 | musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL); | |
4f712e01 | 2503 | |
ae9b2ad2 | 2504 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2505 | struct musb_hw_ep *hw_ep; |
2506 | ||
2507 | hw_ep = &musb->endpoints[i]; | |
2508 | if (!hw_ep) | |
2509 | continue; | |
2510 | ||
2511 | epio = hw_ep->regs; | |
2512 | if (!epio) | |
2513 | continue; | |
2514 | ||
ea737554 | 2515 | musb_writeb(musb_base, MUSB_INDEX, i); |
7421107b | 2516 | musb->context.index_regs[i].txmaxp = |
ae9b2ad2 | 2517 | musb_readw(epio, MUSB_TXMAXP); |
7421107b | 2518 | musb->context.index_regs[i].txcsr = |
ae9b2ad2 | 2519 | musb_readw(epio, MUSB_TXCSR); |
7421107b | 2520 | musb->context.index_regs[i].rxmaxp = |
ae9b2ad2 | 2521 | musb_readw(epio, MUSB_RXMAXP); |
7421107b | 2522 | musb->context.index_regs[i].rxcsr = |
ae9b2ad2 | 2523 | musb_readw(epio, MUSB_RXCSR); |
4f712e01 AKG |
2524 | |
2525 | if (musb->dyn_fifo) { | |
7421107b | 2526 | musb->context.index_regs[i].txfifoadd = |
4f712e01 | 2527 | musb_read_txfifoadd(musb_base); |
7421107b | 2528 | musb->context.index_regs[i].rxfifoadd = |
4f712e01 | 2529 | musb_read_rxfifoadd(musb_base); |
7421107b | 2530 | musb->context.index_regs[i].txfifosz = |
4f712e01 | 2531 | musb_read_txfifosz(musb_base); |
7421107b | 2532 | musb->context.index_regs[i].rxfifosz = |
4f712e01 AKG |
2533 | musb_read_rxfifosz(musb_base); |
2534 | } | |
032ec49f FB |
2535 | |
2536 | musb->context.index_regs[i].txtype = | |
2537 | musb_readb(epio, MUSB_TXTYPE); | |
2538 | musb->context.index_regs[i].txinterval = | |
2539 | musb_readb(epio, MUSB_TXINTERVAL); | |
2540 | musb->context.index_regs[i].rxtype = | |
2541 | musb_readb(epio, MUSB_RXTYPE); | |
2542 | musb->context.index_regs[i].rxinterval = | |
2543 | musb_readb(epio, MUSB_RXINTERVAL); | |
2544 | ||
2545 | musb->context.index_regs[i].txfunaddr = | |
6cc2af6d | 2546 | musb_read_txfunaddr(musb, i); |
032ec49f | 2547 | musb->context.index_regs[i].txhubaddr = |
6cc2af6d | 2548 | musb_read_txhubaddr(musb, i); |
032ec49f | 2549 | musb->context.index_regs[i].txhubport = |
6cc2af6d | 2550 | musb_read_txhubport(musb, i); |
032ec49f FB |
2551 | |
2552 | musb->context.index_regs[i].rxfunaddr = | |
6cc2af6d | 2553 | musb_read_rxfunaddr(musb, i); |
032ec49f | 2554 | musb->context.index_regs[i].rxhubaddr = |
6cc2af6d | 2555 | musb_read_rxhubaddr(musb, i); |
032ec49f | 2556 | musb->context.index_regs[i].rxhubport = |
6cc2af6d | 2557 | musb_read_rxhubport(musb, i); |
4f712e01 | 2558 | } |
4f712e01 AKG |
2559 | } |
2560 | ||
3c8a5fcc | 2561 | static void musb_restore_context(struct musb *musb) |
4f712e01 AKG |
2562 | { |
2563 | int i; | |
2564 | void __iomem *musb_base = musb->mregs; | |
ae9b2ad2 | 2565 | void __iomem *epio; |
33f8d75f | 2566 | u8 power; |
4f712e01 | 2567 | |
032ec49f FB |
2568 | musb_writew(musb_base, MUSB_FRAME, musb->context.frame); |
2569 | musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode); | |
2570 | musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl); | |
33f8d75f RQ |
2571 | |
2572 | /* Don't affect SUSPENDM/RESUME bits in POWER reg */ | |
2573 | power = musb_readb(musb_base, MUSB_POWER); | |
2574 | power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME; | |
2575 | musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME); | |
2576 | power |= musb->context.power; | |
2577 | musb_writeb(musb_base, MUSB_POWER, power); | |
2578 | ||
b18d26f6 | 2579 | musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe); |
af5ec14d | 2580 | musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe); |
7421107b | 2581 | musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe); |
84ac5d11 BL |
2582 | if (musb->context.devctl & MUSB_DEVCTL_SESSION) |
2583 | musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl); | |
4f712e01 | 2584 | |
ae9b2ad2 | 2585 | for (i = 0; i < musb->config->num_eps; ++i) { |
e4e5b136 FB |
2586 | struct musb_hw_ep *hw_ep; |
2587 | ||
2588 | hw_ep = &musb->endpoints[i]; | |
2589 | if (!hw_ep) | |
2590 | continue; | |
2591 | ||
2592 | epio = hw_ep->regs; | |
2593 | if (!epio) | |
2594 | continue; | |
2595 | ||
ea737554 | 2596 | musb_writeb(musb_base, MUSB_INDEX, i); |
ae9b2ad2 | 2597 | musb_writew(epio, MUSB_TXMAXP, |
7421107b | 2598 | musb->context.index_regs[i].txmaxp); |
ae9b2ad2 | 2599 | musb_writew(epio, MUSB_TXCSR, |
7421107b | 2600 | musb->context.index_regs[i].txcsr); |
ae9b2ad2 | 2601 | musb_writew(epio, MUSB_RXMAXP, |
7421107b | 2602 | musb->context.index_regs[i].rxmaxp); |
ae9b2ad2 | 2603 | musb_writew(epio, MUSB_RXCSR, |
7421107b | 2604 | musb->context.index_regs[i].rxcsr); |
4f712e01 AKG |
2605 | |
2606 | if (musb->dyn_fifo) { | |
2607 | musb_write_txfifosz(musb_base, | |
7421107b | 2608 | musb->context.index_regs[i].txfifosz); |
4f712e01 | 2609 | musb_write_rxfifosz(musb_base, |
7421107b | 2610 | musb->context.index_regs[i].rxfifosz); |
4f712e01 | 2611 | musb_write_txfifoadd(musb_base, |
7421107b | 2612 | musb->context.index_regs[i].txfifoadd); |
4f712e01 | 2613 | musb_write_rxfifoadd(musb_base, |
7421107b | 2614 | musb->context.index_regs[i].rxfifoadd); |
4f712e01 AKG |
2615 | } |
2616 | ||
032ec49f | 2617 | musb_writeb(epio, MUSB_TXTYPE, |
7421107b | 2618 | musb->context.index_regs[i].txtype); |
032ec49f | 2619 | musb_writeb(epio, MUSB_TXINTERVAL, |
7421107b | 2620 | musb->context.index_regs[i].txinterval); |
032ec49f | 2621 | musb_writeb(epio, MUSB_RXTYPE, |
7421107b | 2622 | musb->context.index_regs[i].rxtype); |
032ec49f | 2623 | musb_writeb(epio, MUSB_RXINTERVAL, |
4f712e01 | 2624 | |
032ec49f | 2625 | musb->context.index_regs[i].rxinterval); |
6cc2af6d | 2626 | musb_write_txfunaddr(musb, i, |
7421107b | 2627 | musb->context.index_regs[i].txfunaddr); |
6cc2af6d | 2628 | musb_write_txhubaddr(musb, i, |
7421107b | 2629 | musb->context.index_regs[i].txhubaddr); |
6cc2af6d | 2630 | musb_write_txhubport(musb, i, |
7421107b | 2631 | musb->context.index_regs[i].txhubport); |
4f712e01 | 2632 | |
6cc2af6d | 2633 | musb_write_rxfunaddr(musb, i, |
7421107b | 2634 | musb->context.index_regs[i].rxfunaddr); |
6cc2af6d | 2635 | musb_write_rxhubaddr(musb, i, |
7421107b | 2636 | musb->context.index_regs[i].rxhubaddr); |
6cc2af6d | 2637 | musb_write_rxhubport(musb, i, |
7421107b | 2638 | musb->context.index_regs[i].rxhubport); |
4f712e01 | 2639 | } |
3c5fec75 | 2640 | musb_writeb(musb_base, MUSB_INDEX, musb->context.index); |
4f712e01 AKG |
2641 | } |
2642 | ||
48fea965 | 2643 | static int musb_suspend(struct device *dev) |
550a7375 | 2644 | { |
8220796d | 2645 | struct musb *musb = dev_to_musb(dev); |
550a7375 | 2646 | unsigned long flags; |
082df8be JH |
2647 | int ret; |
2648 | ||
2649 | ret = pm_runtime_get_sync(dev); | |
2650 | if (ret < 0) { | |
2651 | pm_runtime_put_noidle(dev); | |
2652 | return ret; | |
2653 | } | |
550a7375 | 2654 | |
6fc6f4b8 | 2655 | musb_platform_disable(musb); |
e945953d | 2656 | musb_disable_interrupts(musb); |
0c3aae9b JH |
2657 | |
2658 | musb->flush_irq_work = true; | |
2659 | while (flush_delayed_work(&musb->irq_work)) | |
2660 | ; | |
2661 | musb->flush_irq_work = false; | |
2662 | ||
a926ed11 AB |
2663 | if (!(musb->io.quirks & MUSB_PRESERVE_SESSION)) |
2664 | musb_writeb(musb->mregs, MUSB_DEVCTL, 0); | |
0c3aae9b | 2665 | |
ea2f35c0 | 2666 | WARN_ON(!list_empty(&musb->pending_list)); |
6fc6f4b8 | 2667 | |
550a7375 FB |
2668 | spin_lock_irqsave(&musb->lock, flags); |
2669 | ||
2670 | if (is_peripheral_active(musb)) { | |
2671 | /* FIXME force disconnect unless we know USB will wake | |
2672 | * the system up quickly enough to respond ... | |
2673 | */ | |
2674 | } else if (is_host_active(musb)) { | |
2675 | /* we know all the children are suspended; sometimes | |
2676 | * they will even be wakeup-enabled. | |
2677 | */ | |
2678 | } | |
2679 | ||
c338412b DM |
2680 | musb_save_context(musb); |
2681 | ||
550a7375 FB |
2682 | spin_unlock_irqrestore(&musb->lock, flags); |
2683 | return 0; | |
2684 | } | |
2685 | ||
3e87d9a3 | 2686 | static int musb_resume(struct device *dev) |
550a7375 | 2687 | { |
ea2f35c0 TL |
2688 | struct musb *musb = dev_to_musb(dev); |
2689 | unsigned long flags; | |
2690 | int error; | |
2691 | u8 devctl; | |
2692 | u8 mask; | |
c338412b DM |
2693 | |
2694 | /* | |
2695 | * For static cmos like DaVinci, register values were preserved | |
0ec8fd70 KK |
2696 | * unless for some reason the whole soc powered down or the USB |
2697 | * module got reset through the PSC (vs just being disabled). | |
c338412b DM |
2698 | * |
2699 | * For the DSPS glue layer though, a full register restore has to | |
2700 | * be done. As it shouldn't harm other platforms, we do it | |
2701 | * unconditionally. | |
550a7375 | 2702 | */ |
c338412b DM |
2703 | |
2704 | musb_restore_context(musb); | |
2705 | ||
b87fd2f7 SAS |
2706 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
2707 | mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV; | |
2708 | if ((devctl & mask) != (musb->context.devctl & mask)) | |
2709 | musb->port1_status = 0; | |
a1fc1920 | 2710 | |
17539f2f AK |
2711 | musb_enable_interrupts(musb); |
2712 | musb_platform_enable(musb); | |
6fc6f4b8 | 2713 | |
ea2f35c0 TL |
2714 | spin_lock_irqsave(&musb->lock, flags); |
2715 | error = musb_run_resume_work(musb); | |
2716 | if (error) | |
2717 | dev_err(musb->controller, "resume work failed with %i\n", | |
2718 | error); | |
2719 | spin_unlock_irqrestore(&musb->lock, flags); | |
2720 | ||
082df8be JH |
2721 | pm_runtime_mark_last_busy(dev); |
2722 | pm_runtime_put_autosuspend(dev); | |
2723 | ||
550a7375 FB |
2724 | return 0; |
2725 | } | |
2726 | ||
7acc6197 HH |
2727 | static int musb_runtime_suspend(struct device *dev) |
2728 | { | |
2729 | struct musb *musb = dev_to_musb(dev); | |
2730 | ||
2731 | musb_save_context(musb); | |
ea2f35c0 | 2732 | musb->is_runtime_suspended = 1; |
7acc6197 HH |
2733 | |
2734 | return 0; | |
2735 | } | |
2736 | ||
2737 | static int musb_runtime_resume(struct device *dev) | |
2738 | { | |
ea2f35c0 TL |
2739 | struct musb *musb = dev_to_musb(dev); |
2740 | unsigned long flags; | |
2741 | int error; | |
7acc6197 HH |
2742 | |
2743 | /* | |
2744 | * When pm_runtime_get_sync called for the first time in driver | |
2745 | * init, some of the structure is still not initialized which is | |
2746 | * used in restore function. But clock needs to be | |
2747 | * enabled before any register access, so | |
2748 | * pm_runtime_get_sync has to be called. | |
2749 | * Also context restore without save does not make | |
2750 | * any sense | |
2751 | */ | |
c723bd6e TL |
2752 | if (!musb->is_initialized) |
2753 | return 0; | |
2754 | ||
2755 | musb_restore_context(musb); | |
7acc6197 | 2756 | |
ea2f35c0 TL |
2757 | spin_lock_irqsave(&musb->lock, flags); |
2758 | error = musb_run_resume_work(musb); | |
2759 | if (error) | |
2760 | dev_err(musb->controller, "resume work failed with %i\n", | |
2761 | error); | |
2762 | musb->is_runtime_suspended = 0; | |
2763 | spin_unlock_irqrestore(&musb->lock, flags); | |
2764 | ||
7acc6197 HH |
2765 | return 0; |
2766 | } | |
2767 | ||
47145210 | 2768 | static const struct dev_pm_ops musb_dev_pm_ops = { |
48fea965 | 2769 | .suspend = musb_suspend, |
3e87d9a3 | 2770 | .resume = musb_resume, |
7acc6197 HH |
2771 | .runtime_suspend = musb_runtime_suspend, |
2772 | .runtime_resume = musb_runtime_resume, | |
48fea965 MD |
2773 | }; |
2774 | ||
2775 | #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops) | |
550a7375 | 2776 | #else |
48fea965 | 2777 | #define MUSB_DEV_PM_OPS NULL |
550a7375 FB |
2778 | #endif |
2779 | ||
2780 | static struct platform_driver musb_driver = { | |
2781 | .driver = { | |
2782 | .name = (char *)musb_driver_name, | |
2783 | .bus = &platform_bus_type, | |
48fea965 | 2784 | .pm = MUSB_DEV_PM_OPS, |
550a7375 | 2785 | }, |
e9e8c85e | 2786 | .probe = musb_probe, |
7690417d | 2787 | .remove = musb_remove, |
550a7375 FB |
2788 | }; |
2789 | ||
89f836a8 | 2790 | module_platform_driver(musb_driver); |